text: #!/usr/bin/env python3
  
  #
  # This file is part of LiteX-Boards.
  #
  # Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
  # SPDX-License-Identifier: BSD-2-Clause
  
  import os
  import argparse
  
  from migen import *
  from migen.genlib.resetsync import AsyncResetSynchronizer
  
  from litex.build.io import DDROutput
  
  from litex_boards.platforms import de1soc
  
  from litex.soc.cores.clock import CycloneVPLL
  from litex.soc.integration.soc_core import *
  from litex.soc.integration.builder import *
  from litex.soc.cores.led import LedChaser
  
  from litedram.modules import IS42S16320
  from litedram.phy import GENSDRPHY
  
  # CRG ----------------------------------------------------------------------------------------------
  
  class _CRG(Module):
      def __init__(self, platform, sys_clk_freq):
          self.rst = Signal()
          self.clock_domains.cd_sys    = ClockDomain()
          self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
  
          # # #
  
          # Clk / Rst
          clk50 = platform.request("clk50")
  
          # PLL
          self.submodules.pll = pll = CycloneVPLL(speedgrade="-C6")
          self.comb += pll.reset.eq(self.rst)
          pll.register_clkin(clk50, 50e6)
          pll.create_clkout(self.cd_sys,    sys_clk_freq)
          pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
  
          # SDRAM clock
          self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
  
  # BaseSoC ------------------------------------------------------------------------------------------
  
  class BaseSoC(SoCCore):
      def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, **kwargs):
          platform = de1soc.Platform()
  
          # SoCCore ----------------------------------------------------------------------------------
          SoCCore.__init__(self, platform, sys_clk_freq,
              ident = "LiteX SoC on DE1-SoC",
              **kwargs)
  
          # CRG --------------------------------------------------------------------------------------
          self.submodules.crg = _CRG(platform, sys_clk_freq)
  
          # SDR SDRAM --------------------------------------------------------------------------------
          if not self.integrated_main_ram_size:
              self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
              self.add_sdram("sdram",
                  phy           = self.sdrphy,
                  module        = IS42S16320(sys_clk_freq, "1:1"),
                  l2_cache_size = kwargs.get("l2_size", 8192)
              )
  
          # Leds -------------------------------------------------------------------------------------
          if with_led_chaser:
              self.submodules.leds = LedChaser(
                  pads         = platform.request_all("user_led"),
                  sys_clk_freq = sys_clk_freq)
  
  # Build --------------------------------------------------------------------------------------------
  
  def main():
      parser = argparse.ArgumentParser(description="LiteX SoC on DE1-SoC")
      parser.add_argument("--build",        action="store_true", help="Build bitstream.")
      parser.add_argument("--load",         action="store_true", help="Load bitstream.")
      parser.add_argument("--sys-clk-freq", default=50e6,        help="System clock frequency.")
      builder_args(parser)
      soc_core_args(parser)
      args = parser.parse_args()
  
      soc = BaseSoC(
          sys_clk_freq = int(float(args.sys_clk_freq)),
          **soc_core_argdict(args)
      )
      builder = Builder(soc, **builder_argdict(args))
      builder.build(run=args.build)
  
      if args.load:
          prog = soc.platform.create_programmer()
          prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
  
  if __name__ == "__main__":
      main()
  