text: // ==============================================================
  // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
  // Version: 2015.2
  // Copyright (C) 2015 Xilinx Inc. All rights reserved.
  // 
  // ==============================================================
  
  #ifndef __duc_imf3_c_1_1_H__
  #define __duc_imf3_c_1_1_H__
  
  
  #include <systemc>
  using namespace sc_core;
  using namespace sc_dt;
  
  
  
  
  #include <iostream>
  #include <fstream>
  
  struct duc_imf3_c_1_1_ram : public sc_core::sc_module {
  
    static const unsigned DataWidth = 1;
    static const unsigned AddressRange = 6;
    static const unsigned AddressWidth = 3;
  
  //latency = 1
  //input_reg = 1
  //output_reg = 0
  sc_core::sc_in <sc_lv<AddressWidth> > address0;
  sc_core::sc_in <sc_logic> ce0;
  sc_core::sc_out <sc_lv<DataWidth> > q0;
  sc_core::sc_in<sc_logic> reset;
  sc_core::sc_in<bool> clk;
  
  
  sc_lv<DataWidth> ram[AddressRange];
  
  
     SC_CTOR(duc_imf3_c_1_1_ram) {
          ram[0] = "0b0";
          ram[1] = "0b0";
          ram[2] = "0b0";
          ram[3] = "0b1";
          ram[4] = "0b0";
          ram[5] = "0b0";
  
  
  SC_METHOD(prc_write_0);
    sensitive<<clk.pos();
     }
  
  
  void prc_write_0()
  {
      if (ce0.read() == sc_dt::Log_1) 
      {
              if(address0.read().is_01() && address0.read().to_uint()<AddressRange)
                q0 = ram[address0.read().to_uint()];
              else
                q0 = sc_lv<DataWidth>();
      }
  }
  
  
  }; //endmodule
  
  
  SC_MODULE(duc_imf3_c_1_1) {
  
  
  static const unsigned DataWidth = 1;
  static const unsigned AddressRange = 6;
  static const unsigned AddressWidth = 3;
  
  sc_core::sc_in <sc_lv<AddressWidth> > address0;
  sc_core::sc_in<sc_logic> ce0;
  sc_core::sc_out <sc_lv<DataWidth> > q0;
  sc_core::sc_in<sc_logic> reset;
  sc_core::sc_in<bool> clk;
  
  
  duc_imf3_c_1_1_ram* meminst;
  
  
  SC_CTOR(duc_imf3_c_1_1) {
  meminst = new duc_imf3_c_1_1_ram("duc_imf3_c_1_1_ram");
  meminst->address0(address0);
  meminst->ce0(ce0);
  meminst->q0(q0);
  
  meminst->reset(reset);
  meminst->clk(clk);
  }
  ~duc_imf3_c_1_1() {
      delete meminst;
  }
  
  
  };//endmodule
  #endif
  