text: /*
  ** ###################################################################
  **     Processors:          MKW21Z256VHT4
  **                          MKW21Z512VHT4
  **
  **     Compilers:           Keil ARM C/C++ Compiler
  **                          GNU C Compiler
  **                          IAR ANSI C/C++ Compiler for ARM
  **
  **     Reference manual:    MKW41Z512RM Rev. 0.1, 04/2016
  **     Version:             rev. 1.0, 2015-09-23
  **     Build:               b160720
  **
  **     Abstract:
  **         Provides a system configuration function and a global variable that
  **         contains the system frequency. It configures the device and initializes
  **         the oscillator (PLL) that is part of the microcontroller device.
  **
  **     Copyright (c) 2016 Freescale Semiconductor, Inc.
  **     All rights reserved.
  **
  **     Redistribution and use in source and binary forms, with or without modification,
  **     are permitted provided that the following conditions are met:
  **
  **     o Redistributions of source code must retain the above copyright notice, this list
  **       of conditions and the following disclaimer.
  **
  **     o Redistributions in binary form must reproduce the above copyright notice, this
  **       list of conditions and the following disclaimer in the documentation and/or
  **       other materials provided with the distribution.
  **
  **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  **       contributors may be used to endorse or promote products derived from this
  **       software without specific prior written permission.
  **
  **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  **
  **     http:                 www.freescale.com
  **     mail:                 support@freescale.com
  **
  **     Revisions:
  **     - rev. 1.0 (2015-09-23)
  **         Initial version.
  **
  ** ###################################################################
  */
  
  /*!
   * @file MKW21Z4
   * @version 1.0
   * @date 2015-09-23
   * @brief Device specific configuration file for MKW21Z4 (implementation file)
   *
   * Provides a system configuration function and a global variable that contains
   * the system frequency. It configures the device and initializes the oscillator
   * (PLL) that is part of the microcontroller device.
   */
  
  #include <stdint.h>
  #include "fsl_device_registers.h"
  
  
  
  /* ----------------------------------------------------------------------------
     -- Core clock
     ---------------------------------------------------------------------------- */
  
  uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
  
  /* ----------------------------------------------------------------------------
     -- SystemInit()
     ---------------------------------------------------------------------------- */
  
  void SystemInit (void) {
  
  #if (DISABLE_WDOG)
    /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
    SIM->COPC = (uint32_t)0x00u;
  #endif /* (DISABLE_WDOG) */
  
  }
  
  /* ----------------------------------------------------------------------------
     -- SystemCoreClockUpdate()
     ---------------------------------------------------------------------------- */
  
  void SystemCoreClockUpdate (void) {
  
    uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
    uint16_t Divider;
  
    if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
      /* FLL is selected */
      if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
        /* External reference clock is selected */
        if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) {
          MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
        } else {
          MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
        }
        if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
          switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
          case 0x38U:
            Divider = 1536U;
            break;
          case 0x30U:
            Divider = 1280U;
            break;
          default:
            Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
            break;
          }
        } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
          Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
        }
        MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
      } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
        MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
      } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
      /* Select correct multiplier to calculate the MCG output clock  */
      switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
        case 0x00U:
          MCGOUTClock *= 640U;
          break;
        case 0x20U:
          MCGOUTClock *= 1280U;
          break;
        case 0x40U:
          MCGOUTClock *= 1920U;
          break;
        case 0x60U:
          MCGOUTClock *= 2560U;
          break;
        case 0x80U:
          MCGOUTClock *= 732U;
          break;
        case 0xA0U:
          MCGOUTClock *= 1464U;
          break;
        case 0xC0U:
          MCGOUTClock *= 2197U;
          break;
        case 0xE0U:
          MCGOUTClock *= 2929U;
          break;
        default:
          break;
      }
    } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
      /* Internal reference clock is selected */
      if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
        MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
      } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
        Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
        MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
      } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
    } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
      /* External reference clock is selected */
      if((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x00U) {
        MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
      } else {
        MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
      }
    } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
      /* Reserved value */
      return;
    } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
    SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
  
  }
  