text: from __future__ import absolute_import
  from __future__ import print_function
  import sys
  import os
  
  # the next line can be removed after installation
  sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
      os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
  
  from veriloggen import *
  import veriloggen.thread as vthread
  
  
  def mkLed():
      m = Module('blinkled')
      clk = m.Input('CLK')
      rst = m.Input('RST')
      led = m.OutputReg('LED', 8, initval=0)
      count = m.Reg('count', 8, initval=0)
  
      def countup():
          times = 20
          inc = 1
          count.value = 0
          for i in range(times):
              count.value += inc
              print("count = %d" % count)
  
      def blink(times, inc=1):
          th_countup.run()
          led.value = 0
          for i in range(times):
              led.value += inc
              print("  led = %d" % led)
  
      th_countup = vthread.Thread(m, 'th_countup', clk, rst, countup)
      th_blink = vthread.Thread(m, 'th_blink', clk, rst, blink)
  
      fsm = th_blink.start(10)
  
      return m
  
  
  def mkTest():
      m = Module('test')
  
      # target instance
      led = mkLed()
  
      # copy paras and ports
      params = m.copy_params(led)
      ports = m.copy_sim_ports(led)
  
      clk = ports['CLK']
      rst = ports['RST']
  
      uut = m.Instance(led, 'uut',
                       params=m.connect_params(led),
                       ports=m.connect_ports(led))
  
      # simulation.setup_waveform(m, uut)
      simulation.setup_clock(m, clk, hperiod=5)
      init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
  
      init.add(
          Delay(10000),
          Systask('finish'),
      )
  
      return m
  
  
  if __name__ == '__main__':
      test = mkTest()
      verilog = test.to_verilog('tmp.v')
      print(verilog)
  
      sim = simulation.Simulator(test)
      rslt = sim.run()
      print(rslt)
  