text: # ======================================================================
  # Copyright TOTAL / CERFACS / LIRMM (02/2020)
  # Contributor: Adrien Suau (<adrien.suau@cerfacs.fr>
  #                           <adrien.suau@lirmm.fr>)
  #              Siyuan Niu  (<siyuan.niu@lirmm.fr>)
  # This software is governed by the CeCILL-B license under French law and
  # abiding  by the  rules of  distribution of free software. You can use,
  # modify  and/or  redistribute  the  software  under  the  terms  of the
  # CeCILL-B license as circulated by CEA, CNRS and INRIA at the following
  # URL "http://www.cecill.info".
  #
  # As a counterpart to the access to  the source code and rights to copy,
  # modify and  redistribute granted  by the  license, users  are provided
  # only with a limited warranty and  the software's author, the holder of
  # the economic rights,  and the  successive licensors  have only limited
  # liability.
  #
  # In this respect, the user's attention is drawn to the risks associated
  # with loading,  using, modifying and/or  developing or reproducing  the
  # software by the user in light of its specific status of free software,
  # that  may mean  that it  is complicated  to manipulate,  and that also
  # therefore  means that  it is reserved for  developers and  experienced
  # professionals having in-depth  computer knowledge. Users are therefore
  # encouraged  to load and  test  the software's  suitability as  regards
  # their  requirements  in  conditions  enabling  the  security  of their
  # systems  and/or  data to be  ensured and,  more generally,  to use and
  # operate it in the same conditions as regards security.
  #
  # The fact that you  are presently reading this  means that you have had
  # knowledge of the CeCILL-B license and that you accept its terms.
  # ======================================================================
  
  import logging
  
  import networkx as nx
  
  logging.basicConfig()
  logging.root.setLevel(logging.WARNING)
  
  
  class HardwareArchitecture(nx.DiGraph):
      def __init__(self, incoming_graph_data=None, **kwargs):
          super().__init__(incoming_graph_data, **kwargs)
          self._qubit_number = 0
  
      def add_qubit(self, **qubit_data) -> int:
          self.add_node(self._qubit_number, **qubit_data)
          self._qubit_number += 1
          return self._qubit_number
  
      def add_link(self, qubit1: int, qubit2: int, **link_data):
          self.add_edge(qubit1, qubit2, **link_data)
  
      @property
      def qubit_number(self):
          return self._qubit_number
  