text: /*
   * Copyright (c) 2021, NXP
   *
   * SPDX-License-Identifier: Apache-2.0
   */
  
  #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_
  #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_
  
  /* Peripheral:
   *   range: 0 - 0xFF, starting from 0
   *
   * Instance:
   *   range: 0 - 0xFF, starting from 0
   */
  #define IMX_CCM_PERIPHERAL_MASK 0xFF00UL
  #define IMX_CCM_INSTANCE_MASK   0xFFUL
  
  #define IMX_CCM_CORESYS_CLK		0
  #define IMX_CCM_PLATFORM_CLK	0x1UL
  #define IMX_CCM_BUS_CLK			0x2UL
  /* LPUART */
  #define IMX_CCM_LPUART_CLK		0x300UL
  #define IMX_CCM_LPUART1_CLK		0x300UL
  #define IMX_CCM_LPUART2_CLK		0x301UL
  #define IMX_CCM_LPUART3_CLK		0x302UL
  #define IMX_CCM_LPUART4_CLK		0x303UL
  #define IMX_CCM_LPUART5_CLK		0x304UL
  #define IMX_CCM_LPUART6_CLK		0x305UL
  #define IMX_CCM_LPUART7_CLK		0x306UL
  #define IMX_CCM_LPUART8_CLK		0x307UL
  #define IMX_CCM_LPUART9_CLK		0x308UL
  #define IMX_CCM_LPUART10_CLK	0x309UL
  #define IMX_CCM_LPUART11_CLK	0x30aUL
  #define IMX_CCM_LPUART12_CLK	0x30bUL
  
  /* LPI2C */
  #define IMX_CCM_LPI2C_CLK		0x400UL
  #define IMX_CCM_LPI2C1_CLK		0x400UL
  #define IMX_CCM_LPI2C2_CLK		0x401UL
  #define IMX_CCM_LPI2C3_CLK		0x402UL
  #define IMX_CCM_LPI2C4_CLK		0x403UL
  #define IMX_CCM_LPI2C5_CLK		0x404UL
  #define IMX_CCM_LPI2C6_CLK		0x405UL
  
  /* LPSPI */
  #define IMX_CCM_LPSPI_CLK		0x500UL
  #define IMX_CCM_LPSPI1_CLK		0x500UL
  #define IMX_CCM_LPSPI2_CLK		0x501UL
  #define IMX_CCM_LPSPI3_CLK		0x502UL
  #define IMX_CCM_LPSPI4_CLK		0x503UL
  #define IMX_CCM_LPSPI5_CLK		0x504UL
  #define IMX_CCM_LPSPI6_CLK		0x505UL
  
  /* USDHC */
  #define IMX_CCM_USDHC1_CLK		0x600UL
  #define IMX_CCM_USDHC2_CLK		0x601UL
  
  /* DMA  */
  #define IMX_CCM_EDMA_CLK        0x700UL
  #define IMX_CCM_EDMA_LPSR_CLK   0x701UL
  
  /* CAN */
  #define IMX_CCM_CAN_CLK		    0x900UL
  #define IMX_CCM_CAN1_CLK		0x900UL
  #define IMX_CCM_CAN2_CLK		0x901UL
  #define IMX_CCM_CAN3_CLK		0x902UL
  
  /* GPT */
  #define IMX_CCM_GPT_CLK		    0x1000UL
  #define IMX_CCM_GPT1_CLK		0x1000UL
  #define IMX_CCM_GPT2_CLK		0x1001UL
  #define IMX_CCM_GPT3_CLK		0x1002UL
  #define IMX_CCM_GPT4_CLK		0x1003UL
  #define IMX_CCM_GPT5_CLK		0x1004UL
  #define IMX_CCM_GPT6_CLK		0x1005UL
  
  #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ */
  