text: DECL|ACMP0_BASE|macro|ACMP0_BASE
  DECL|ACMP0_IRQn|enumerator|ACMP0_IRQn = 13, /*!< 13 EFR32 ACMP0 Interrupt */
  DECL|ACMP0|macro|ACMP0
  DECL|ACMP1_BASE|macro|ACMP1_BASE
  DECL|ACMP1|macro|ACMP1
  DECL|ACMP_COUNT|macro|ACMP_COUNT
  DECL|ACMP_OFFSET|macro|ACMP_OFFSET
  DECL|ACMP_PRESENT|macro|ACMP_PRESENT
  DECL|ADC0_BASE|macro|ADC0_BASE
  DECL|ADC0_IRQn|enumerator|ADC0_IRQn = 14, /*!< 14 EFR32 ADC0 Interrupt */
  DECL|ADC0|macro|ADC0
  DECL|ADC_COUNT|macro|ADC_COUNT
  DECL|ADC_OFFSET|macro|ADC_OFFSET
  DECL|ADC_PRESENT|macro|ADC_PRESENT
  DECL|AFACHAN_MAX|macro|AFACHAN_MAX
  DECL|AFCHANLOC_MAX|macro|AFCHANLOC_MAX
  DECL|AFCHAN_MAX|macro|AFCHAN_MAX
  DECL|BITBAND_PER_BASE|macro|BITBAND_PER_BASE
  DECL|BITBAND_RAM_BASE|macro|BITBAND_RAM_BASE
  DECL|BOOTLOADER_COUNT|macro|BOOTLOADER_COUNT
  DECL|BOOTLOADER_PRESENT|macro|BOOTLOADER_PRESENT
  DECL|BusFault_IRQn|enumerator|BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
  DECL|CMU_BASE|macro|CMU_BASE
  DECL|CMU_COUNT|macro|CMU_COUNT
  DECL|CMU_IRQn|enumerator|CMU_IRQn = 23, /*!< 23 EFR32 CMU Interrupt */
  DECL|CMU_PRESENT|macro|CMU_PRESENT
  DECL|CMU_UNLOCK_CODE|macro|CMU_UNLOCK_CODE
  DECL|CMU|macro|CMU
  DECL|CRYOTIMER_BASE|macro|CRYOTIMER_BASE
  DECL|CRYOTIMER_COUNT|macro|CRYOTIMER_COUNT
  DECL|CRYOTIMER_IRQn|enumerator|CRYOTIMER_IRQn = 31, /*!< 31 EFR32 CRYOTIMER Interrupt */
  DECL|CRYOTIMER_PRESENT|macro|CRYOTIMER_PRESENT
  DECL|CRYOTIMER|macro|CRYOTIMER
  DECL|CRYPTO_BASE|macro|CRYPTO_BASE
  DECL|CRYPTO_BITCLR_MEM_BASE|macro|CRYPTO_BITCLR_MEM_BASE
  DECL|CRYPTO_BITCLR_MEM_BITS|macro|CRYPTO_BITCLR_MEM_BITS
  DECL|CRYPTO_BITCLR_MEM_END|macro|CRYPTO_BITCLR_MEM_END
  DECL|CRYPTO_BITCLR_MEM_SIZE|macro|CRYPTO_BITCLR_MEM_SIZE
  DECL|CRYPTO_BITSET_MEM_BASE|macro|CRYPTO_BITSET_MEM_BASE
  DECL|CRYPTO_BITSET_MEM_BITS|macro|CRYPTO_BITSET_MEM_BITS
  DECL|CRYPTO_BITSET_MEM_END|macro|CRYPTO_BITSET_MEM_END
  DECL|CRYPTO_BITSET_MEM_SIZE|macro|CRYPTO_BITSET_MEM_SIZE
  DECL|CRYPTO_COUNT|macro|CRYPTO_COUNT
  DECL|CRYPTO_IRQn|enumerator|CRYPTO_IRQn = 25, /*!< 25 EFR32 CRYPTO Interrupt */
  DECL|CRYPTO_MEM_BASE|macro|CRYPTO_MEM_BASE
  DECL|CRYPTO_MEM_BITS|macro|CRYPTO_MEM_BITS
  DECL|CRYPTO_MEM_END|macro|CRYPTO_MEM_END
  DECL|CRYPTO_MEM_SIZE|macro|CRYPTO_MEM_SIZE
  DECL|CRYPTO_PRESENT|macro|CRYPTO_PRESENT
  DECL|CRYPTO|macro|CRYPTO
  DECL|DEVINFO_BASE|macro|DEVINFO_BASE
  DECL|DEVINFO|macro|DEVINFO
  DECL|DMA_CHAN_COUNT|macro|DMA_CHAN_COUNT
  DECL|DebugMonitor_IRQn|enumerator|DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
  DECL|EFR32FG1P131F256GM48_H|macro|EFR32FG1P131F256GM48_H
  DECL|EFR32FG1P131F256GM48|macro|EFR32FG1P131F256GM48
  DECL|EMU_BASE|macro|EMU_BASE
  DECL|EMU_COUNT|macro|EMU_COUNT
  DECL|EMU_IRQn|enumerator|EMU_IRQn = 0, /*!< 0 EFR32 EMU Interrupt */
  DECL|EMU_PRESENT|macro|EMU_PRESENT
  DECL|EMU_UNLOCK_CODE|macro|EMU_UNLOCK_CODE
  DECL|EMU|macro|EMU
  DECL|EXT_IRQ_COUNT|macro|EXT_IRQ_COUNT
  DECL|FLASH_BASE|macro|FLASH_BASE
  DECL|FLASH_MEM_BASE|macro|FLASH_MEM_BASE
  DECL|FLASH_MEM_BITS|macro|FLASH_MEM_BITS
  DECL|FLASH_MEM_END|macro|FLASH_MEM_END
  DECL|FLASH_MEM_SIZE|macro|FLASH_MEM_SIZE
  DECL|FLASH_PAGE_SIZE|macro|FLASH_PAGE_SIZE
  DECL|FLASH_SIZE|macro|FLASH_SIZE
  DECL|FPUEH_BASE|macro|FPUEH_BASE
  DECL|FPUEH_COUNT|macro|FPUEH_COUNT
  DECL|FPUEH_IRQn|enumerator|FPUEH_IRQn = 33, /*!< 33 EFR32 FPUEH Interrupt */
  DECL|FPUEH_PRESENT|macro|FPUEH_PRESENT
  DECL|FPUEH|macro|FPUEH
  DECL|GPCRC_BASE|macro|GPCRC_BASE
  DECL|GPCRC_COUNT|macro|GPCRC_COUNT
  DECL|GPCRC_PRESENT|macro|GPCRC_PRESENT
  DECL|GPCRC|macro|GPCRC
  DECL|GPIO_BASE|macro|GPIO_BASE
  DECL|GPIO_COUNT|macro|GPIO_COUNT
  DECL|GPIO_EVEN_IRQn|enumerator|GPIO_EVEN_IRQn = 9, /*!< 9 EFR32 GPIO_EVEN Interrupt */
  DECL|GPIO_ODD_IRQn|enumerator|GPIO_ODD_IRQn = 17, /*!< 17 EFR32 GPIO_ODD Interrupt */
  DECL|GPIO_PRESENT|macro|GPIO_PRESENT
  DECL|GPIO_UNLOCK_CODE|macro|GPIO_UNLOCK_CODE
  DECL|GPIO|macro|GPIO
  DECL|HardFault_IRQn|enumerator|HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
  DECL|I2C0_BASE|macro|I2C0_BASE
  DECL|I2C0_IRQn|enumerator|I2C0_IRQn = 16, /*!< 16 EFR32 I2C0 Interrupt */
  DECL|I2C0|macro|I2C0
  DECL|I2C_COUNT|macro|I2C_COUNT
  DECL|I2C_OFFSET|macro|I2C_OFFSET
  DECL|I2C_PRESENT|macro|I2C_PRESENT
  DECL|IDAC0_BASE|macro|IDAC0_BASE
  DECL|IDAC0_IRQn|enumerator|IDAC0_IRQn = 15, /*!< 15 EFR32 IDAC0 Interrupt */
  DECL|IDAC0|macro|IDAC0
  DECL|IDAC_COUNT|macro|IDAC_COUNT
  DECL|IDAC_OFFSET|macro|IDAC_OFFSET
  DECL|IDAC_PRESENT|macro|IDAC_PRESENT
  DECL|IRQn_Type|typedef|} IRQn_Type;
  DECL|IRQn|enum|typedef enum IRQn
  DECL|LDMA_BASE|macro|LDMA_BASE
  DECL|LDMA_COUNT|macro|LDMA_COUNT
  DECL|LDMA_IRQn|enumerator|LDMA_IRQn = 8, /*!< 8 EFR32 LDMA Interrupt */
  DECL|LDMA_PRESENT|macro|LDMA_PRESENT
  DECL|LDMA|macro|LDMA
  DECL|LETIMER0_BASE|macro|LETIMER0_BASE
  DECL|LETIMER0_IRQn|enumerator|LETIMER0_IRQn = 26, /*!< 26 EFR32 LETIMER0 Interrupt */
  DECL|LETIMER0|macro|LETIMER0
  DECL|LETIMER_COUNT|macro|LETIMER_COUNT
  DECL|LETIMER_OFFSET|macro|LETIMER_OFFSET
  DECL|LETIMER_PRESENT|macro|LETIMER_PRESENT
  DECL|LEUART0_BASE|macro|LEUART0_BASE
  DECL|LEUART0_IRQn|enumerator|LEUART0_IRQn = 21, /*!< 21 EFR32 LEUART0 Interrupt */
  DECL|LEUART0|macro|LEUART0
  DECL|LEUART_COUNT|macro|LEUART_COUNT
  DECL|LEUART_OFFSET|macro|LEUART_OFFSET
  DECL|LEUART_PRESENT|macro|LEUART_PRESENT
  DECL|LOCKBITS_BASE|macro|LOCKBITS_BASE
  DECL|MSC_BASE|macro|MSC_BASE
  DECL|MSC_COUNT|macro|MSC_COUNT
  DECL|MSC_IRQn|enumerator|MSC_IRQn = 24, /*!< 24 EFR32 MSC Interrupt */
  DECL|MSC_PRESENT|macro|MSC_PRESENT
  DECL|MSC_UNLOCK_CODE|macro|MSC_UNLOCK_CODE
  DECL|MSC|macro|MSC
  DECL|MemoryManagement_IRQn|enumerator|MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
  DECL|NonMaskableInt_IRQn|enumerator|NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
  DECL|PART_NUMBER|macro|PART_NUMBER
  DECL|PCNT0_BASE|macro|PCNT0_BASE
  DECL|PCNT0_IRQn|enumerator|PCNT0_IRQn = 22, /*!< 22 EFR32 PCNT0 Interrupt */
  DECL|PCNT0|macro|PCNT0
  DECL|PCNT_COUNT|macro|PCNT_COUNT
  DECL|PCNT_OFFSET|macro|PCNT_OFFSET
  DECL|PCNT_PRESENT|macro|PCNT_PRESENT
  DECL|PER_BITCLR_MEM_BASE|macro|PER_BITCLR_MEM_BASE
  DECL|PER_BITCLR_MEM_BITS|macro|PER_BITCLR_MEM_BITS
  DECL|PER_BITCLR_MEM_END|macro|PER_BITCLR_MEM_END
  DECL|PER_BITCLR_MEM_SIZE|macro|PER_BITCLR_MEM_SIZE
  DECL|PER_BITSET_MEM_BASE|macro|PER_BITSET_MEM_BASE
  DECL|PER_BITSET_MEM_BITS|macro|PER_BITSET_MEM_BITS
  DECL|PER_BITSET_MEM_END|macro|PER_BITSET_MEM_END
  DECL|PER_BITSET_MEM_SIZE|macro|PER_BITSET_MEM_SIZE
  DECL|PER_MEM_BASE|macro|PER_MEM_BASE
  DECL|PER_MEM_BITS|macro|PER_MEM_BITS
  DECL|PER_MEM_END|macro|PER_MEM_END
  DECL|PER_MEM_SIZE|macro|PER_MEM_SIZE
  DECL|PRS_BASE|macro|PRS_BASE
  DECL|PRS_CHAN_COUNT|macro|PRS_CHAN_COUNT
  DECL|PRS_COUNT|macro|PRS_COUNT
  DECL|PRS_PRESENT|macro|PRS_PRESENT
  DECL|PRS|macro|PRS
  DECL|PendSV_IRQn|enumerator|PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
  DECL|RAM_CODE_MEM_BASE|macro|RAM_CODE_MEM_BASE
  DECL|RAM_CODE_MEM_BITS|macro|RAM_CODE_MEM_BITS
  DECL|RAM_CODE_MEM_END|macro|RAM_CODE_MEM_END
  DECL|RAM_CODE_MEM_SIZE|macro|RAM_CODE_MEM_SIZE
  DECL|RAM_MEM_BASE|macro|RAM_MEM_BASE
  DECL|RAM_MEM_BITS|macro|RAM_MEM_BITS
  DECL|RAM_MEM_END|macro|RAM_MEM_END
  DECL|RAM_MEM_SIZE|macro|RAM_MEM_SIZE
  DECL|RMU_BASE|macro|RMU_BASE
  DECL|RMU_COUNT|macro|RMU_COUNT
  DECL|RMU_PRESENT|macro|RMU_PRESENT
  DECL|RMU_UNLOCK_CODE|macro|RMU_UNLOCK_CODE
  DECL|RMU|macro|RMU
  DECL|ROMTABLE_BASE|macro|ROMTABLE_BASE
  DECL|ROMTABLE|macro|ROMTABLE
  DECL|RTCC_BASE|macro|RTCC_BASE
  DECL|RTCC_COUNT|macro|RTCC_COUNT
  DECL|RTCC_IRQn|enumerator|RTCC_IRQn = 29, /*!< 29 EFR32 RTCC Interrupt */
  DECL|RTCC_PRESENT|macro|RTCC_PRESENT
  DECL|RTCC_UNLOCK_CODE|macro|RTCC_UNLOCK_CODE
  DECL|RTCC|macro|RTCC
  DECL|SET_BIT_FIELD|macro|SET_BIT_FIELD
  DECL|SRAM_BASE|macro|SRAM_BASE
  DECL|SRAM_SIZE|macro|SRAM_SIZE
  DECL|SVCall_IRQn|enumerator|SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
  DECL|SysTick_IRQn|enumerator|SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
  DECL|TIMER0_BASE|macro|TIMER0_BASE
  DECL|TIMER0_IRQn|enumerator|TIMER0_IRQn = 10, /*!< 10 EFR32 TIMER0 Interrupt */
  DECL|TIMER0|macro|TIMER0
  DECL|TIMER1_BASE|macro|TIMER1_BASE
  DECL|TIMER1_IRQn|enumerator|TIMER1_IRQn = 18, /*!< 18 EFR32 TIMER1 Interrupt */
  DECL|TIMER1|macro|TIMER1
  DECL|TIMER_COUNT|macro|TIMER_COUNT
  DECL|TIMER_OFFSET|macro|TIMER_OFFSET
  DECL|TIMER_PRESENT|macro|TIMER_PRESENT
  DECL|TIMER_UNLOCK_CODE|macro|TIMER_UNLOCK_CODE
  DECL|USART0_BASE|macro|USART0_BASE
  DECL|USART0_RX_IRQn|enumerator|USART0_RX_IRQn = 11, /*!< 11 EFR32 USART0_RX Interrupt */
  DECL|USART0_TX_IRQn|enumerator|USART0_TX_IRQn = 12, /*!< 12 EFR32 USART0_TX Interrupt */
  DECL|USART0|macro|USART0
  DECL|USART1_BASE|macro|USART1_BASE
  DECL|USART1_RX_IRQn|enumerator|USART1_RX_IRQn = 19, /*!< 19 EFR32 USART1_RX Interrupt */
  DECL|USART1_TX_IRQn|enumerator|USART1_TX_IRQn = 20, /*!< 20 EFR32 USART1_TX Interrupt */
  DECL|USART1|macro|USART1
  DECL|USART_COUNT|macro|USART_COUNT
  DECL|USART_OFFSET|macro|USART_OFFSET
  DECL|USART_PRESENT|macro|USART_PRESENT
  DECL|USERDATA_BASE|macro|USERDATA_BASE
  DECL|UsageFault_IRQn|enumerator|UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
  DECL|WDOG0_BASE|macro|WDOG0_BASE
  DECL|WDOG0_IRQn|enumerator|WDOG0_IRQn = 2, /*!< 2 EFR32 WDOG0 Interrupt */
  DECL|WDOG0|macro|WDOG0
  DECL|WDOG_COUNT|macro|WDOG_COUNT
  DECL|WDOG_OFFSET|macro|WDOG_OFFSET
  DECL|WDOG_PRESENT|macro|WDOG_PRESENT
  DECL|_EFR32_FLEX_FAMILY|macro|_EFR32_FLEX_FAMILY
  DECL|_EFR_DEVICE|macro|_EFR_DEVICE
  DECL|_SILICON_LABS_32B_PLATFORM_2_GEN_1|macro|_SILICON_LABS_32B_PLATFORM_2_GEN_1
  DECL|_SILICON_LABS_32B_PLATFORM_2_GEN|macro|_SILICON_LABS_32B_PLATFORM_2_GEN
  DECL|_SILICON_LABS_32B_PLATFORM_2|macro|_SILICON_LABS_32B_PLATFORM_2
  DECL|_SILICON_LABS_32B_PLATFORM|macro|_SILICON_LABS_32B_PLATFORM
  DECL|_SILICON_LABS_32B_SERIES_1_CONFIG_1|macro|_SILICON_LABS_32B_SERIES_1_CONFIG_1
  DECL|_SILICON_LABS_32B_SERIES_1_CONFIG|macro|_SILICON_LABS_32B_SERIES_1_CONFIG
  DECL|_SILICON_LABS_32B_SERIES_1|macro|_SILICON_LABS_32B_SERIES_1
  DECL|_SILICON_LABS_32B_SERIES|macro|_SILICON_LABS_32B_SERIES
  DECL|_SILICON_LABS_EFR32_RADIO_2G4HZ|macro|_SILICON_LABS_EFR32_RADIO_2G4HZ
  DECL|_SILICON_LABS_EFR32_RADIO_DUALBAND|macro|_SILICON_LABS_EFR32_RADIO_DUALBAND
  DECL|_SILICON_LABS_EFR32_RADIO_SUBGHZ|macro|_SILICON_LABS_EFR32_RADIO_SUBGHZ
  DECL|_SILICON_LABS_EFR32_RADIO_TYPE|macro|_SILICON_LABS_EFR32_RADIO_TYPE
  DECL|_SILICON_LABS_GECKO_INTERNAL_SDID_80|macro|_SILICON_LABS_GECKO_INTERNAL_SDID_80
  DECL|_SILICON_LABS_GECKO_INTERNAL_SDID|macro|_SILICON_LABS_GECKO_INTERNAL_SDID
  DECL|__CM4_REV|macro|__CM4_REV
  DECL|__FPU_PRESENT|macro|__FPU_PRESENT
  DECL|__MPU_PRESENT|macro|__MPU_PRESENT
  DECL|__NVIC_PRIO_BITS|macro|__NVIC_PRIO_BITS
  DECL|__VTOR_PRESENT|macro|__VTOR_PRESENT
  DECL|__Vendor_SysTickConfig|macro|__Vendor_SysTickConfig
  