text: #!/usr/bin/env python3
  
  # Copyright (c) 2019 Michael Betz <michibetz@gmail.com>
  # Copyright (c) 2020 Fei Gao <feig@princeton.edu>
  # Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
  # SPDX-License-Identifier: BSD-2-Clause
  
  import os
  import argparse
  
  from migen import *
  
  from litex_boards.platforms import vc707
  
  from litex.soc.cores.clock import *
  from litex.soc.integration.soc_core import *
  from litex.soc.integration.builder import *
  from litex.soc.cores.led import LedChaser
  
  from litedram.modules import MT8JTF12864
  from litedram.phy import s7ddrphy
  
  
  from litepcie.phy.s7pciephy import S7PCIEPHY
  from litepcie.software import generate_litepcie_software
  
  # CRG ----------------------------------------------------------------------------------------------
  
  class _CRG(Module):
      def __init__(self, platform, sys_clk_freq):
          self.rst = Signal()
          self.clock_domains.cd_sys    = ClockDomain()
          self.clock_domains.cd_sys4x  = ClockDomain(reset_less=True)
          self.clock_domains.cd_idelay = ClockDomain()
  
          # # #
  
          self.submodules.pll = pll = S7MMCM(speedgrade=-2)
          self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst)
          pll.register_clkin(platform.request("clk200"), 200e6)
          pll.create_clkout(self.cd_sys,    sys_clk_freq)
          pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
          pll.create_clkout(self.cd_idelay, 200e6)
          platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
  
          self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
  
  # BaseSoC ------------------------------------------------------------------------------------------
  
  class BaseSoC(SoCCore):
      def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, with_pcie=False, **kwargs):
          platform = vc707.Platform()
  
          # SoCCore ----------------------------------------------------------------------------------
          SoCCore.__init__(self, platform, sys_clk_freq,
              ident = "LiteX SoC on VC707",
              **kwargs)
  
          # CRG --------------------------------------------------------------------------------------
          self.submodules.crg = _CRG(platform, sys_clk_freq)
  
          # DDR3 SDRAM -------------------------------------------------------------------------------
          if not self.integrated_main_ram_size:
              self.submodules.ddrphy = s7ddrphy.V7DDRPHY(platform.request("ddram"),
                  memtype      = "DDR3",
                  nphases      = 4,
                  sys_clk_freq = sys_clk_freq)
              self.add_sdram("sdram",
                  phy           = self.ddrphy,
                  module        = MT8JTF12864(sys_clk_freq, "1:4"),
                  l2_cache_size = kwargs.get("l2_size", 8192)
              )
  
          # PCIe -------------------------------------------------------------------------------------
          if with_pcie:
              self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
                  data_width = 128,
                  bar0_size  = 0x20000)
              self.add_pcie(phy=self.pcie_phy, ndmas=1)
  
          # Leds -------------------------------------------------------------------------------------
          if with_led_chaser:
              self.submodules.leds = LedChaser(
                  pads         = platform.request_all("user_led"),
                  sys_clk_freq = sys_clk_freq)
  
  # Build --------------------------------------------------------------------------------------------
  
  def main():
      parser = argparse.ArgumentParser(description="LiteX SoC on VC707")
      parser.add_argument("--build",        action="store_true", help="Build bitstream.")
      parser.add_argument("--load",         action="store_true", help="Load bitstream.")
      parser.add_argument("--sys-clk-freq", default=125e6,       help="System clock frequency.")
      parser.add_argument("--with-pcie",    action="store_true", help="Enable PCIe support.")
      parser.add_argument("--driver",       action="store_true", help="Generate PCIe driver.")
      builder_args(parser)
      soc_core_args(parser)
      args = parser.parse_args()
  
      soc = BaseSoC(
          sys_clk_freq = int(float(args.sys_clk_freq)),
          with_pcie_   = args.with_pcie,
          **soc_core_argdict(args)
      )
      builder = Builder(soc, **builder_argdict(args))
      builder.build(run=args.build)
  
      if args.driver:
          generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
  
      if args.load:
          prog = soc.platform.create_programmer()
          prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
  
  if __name__ == "__main__":
      main()
  