text: /**************************************************************************//**
   * @file     main.c
   * @version  V3.00
   * @brief
   *           Configure SPI0 as Slave mode and demonstrate how to communicate with an off-chip SPI Master device with FIFO mode. 
   *           This sample code needs to work with SPI_MasterFifoMode sample code.
   * @note
   * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
   ******************************************************************************/
  #include <stdio.h>
  #include "NuMicro.h"
  
  #define TEST_COUNT 16
  
  uint32_t g_au32SourceData[TEST_COUNT];
  uint32_t g_au32DestinationData[TEST_COUNT];
  volatile uint32_t g_u32TxDataCount;
  volatile uint32_t g_u32RxDataCount;
  
  /* Function prototype declaration */
  void SYS_Init(void);
  void SPI_Init(void);
  
  /* ------------- */
  /* Main function */
  /* ------------- */
  int main(void)
  {
      volatile uint32_t u32TxDataCount, u32RxDataCount;
  
      /* Unlock protected registers */
      SYS_UnlockReg();
      /* Init system, IP clock and multi-function I/O. */
      SYS_Init();
      /* Lock protected registers */
      SYS_LockReg();
  
      /* Configure UART0: 115200, 8-bit word, no parity bit, 1 stop bit. */
      UART_Open(UART0, 115200);
  
      /* Init SPI */
      SPI_Init();
  
      printf("\n\n");
      printf("+-----------------------------------------------------+\n");
      printf("|           SPI Slave Mode Sample Code                |\n");
      printf("+-----------------------------------------------------+\n");
      printf("\n");
      printf("Configure SPI0 as a slave.\n");
      printf("Bit length of a transaction: 32\n");
      printf("The I/O connection for SPI0:\n");
      printf("    SPI0_SS0 (PC.0)\n    SPI0_CLK (PC.1)\n");
      printf("    SPI0_MISO0 (PC.2)\n    SPI0_MOSI0 (PC.3)\n\n");
      printf("SPI controller will enable FIFO mode and transfer %d data to a off-chip master device.\n", TEST_COUNT);
      printf("In the meanwhile the SPI controller will receive %d data from the off-chip master device.\n", TEST_COUNT);
      printf("After the transfer is done, the %d received data will be printed out.\n", TEST_COUNT);
  
      for(u32TxDataCount = 0; u32TxDataCount < TEST_COUNT; u32TxDataCount++)
      {
          /* Write the initial value to source buffer */
          g_au32SourceData[u32TxDataCount] = 0x00AA0000 + u32TxDataCount;
          /* Clear destination buffer */
          g_au32DestinationData[u32TxDataCount] = 0;
      }
  
      u32TxDataCount = 0;
      u32RxDataCount = 0;
      printf("Press any key if the master device configuration is ready.\n");
      getchar();
      printf("\n");
  
      /* Set TX FIFO threshold and enable FIFO mode. */
      SPI_EnableFIFO(SPI0, 4, 4);
      
      /* Access TX and RX FIFO */
      while(u32RxDataCount < TEST_COUNT)
      {
          /* Check TX FULL flag and TX data count */
          if((SPI_GET_TX_FIFO_FULL_FLAG(SPI0) == 0) && (u32TxDataCount < TEST_COUNT))
              SPI_WRITE_TX(SPI0, g_au32SourceData[u32TxDataCount++]); /* Write to TX FIFO */
          /* Check RX EMPTY flag */
          if(SPI_GET_RX_FIFO_EMPTY_FLAG(SPI0) == 0)
              g_au32DestinationData[u32RxDataCount++] = SPI_READ_RX(SPI0); /* Read RX FIFO */
      }
  
      /* Print the received data */
      printf("Received data:\n");
      for(u32RxDataCount = 0; u32RxDataCount < TEST_COUNT; u32RxDataCount++)
      {
          printf("%d:\t0x%X\n", u32RxDataCount, g_au32DestinationData[u32RxDataCount]);
      }
      printf("The data transfer was done.\n");
  
      printf("\n\nExit SPI driver sample code.\n");
  
      /* Reset SPI0 */
      SPI_Close(SPI0);
      while(1);
  }
  
  void SYS_Init(void)
  {
      /*---------------------------------------------------------------------------------------------------------*/
      /* Init System Clock                                                                                       */
      /*---------------------------------------------------------------------------------------------------------*/
      /* Enable Internal RC 22.1184 MHz clock */
      CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
  
      /* Waiting for Internal RC clock ready */
      CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
      
      /* Enable external 12 MHz XTAL */
      CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);
  
      /* Waiting for clock ready */
      CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk);
  
      /* Set core clock rate as 72 MHz from PLL */
      CLK_SetCoreClock(72000000);
  
      /* Select HXT as the clock source of UART0 */
      CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));
  
      /* Select HCLK as the clock source of SPI0 */
      CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL1_SPI0_S_HCLK, MODULE_NoMsk);
  
      /* Enable UART peripheral clock */
      CLK_EnableModuleClock(UART0_MODULE);
      /* Enable SPI0 peripheral clock */
      CLK_EnableModuleClock(SPI0_MODULE);
  
      /* Update System Core Clock */
      /* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CyclesPerUs automatically. */
      SystemCoreClockUpdate();
  
      /*---------------------------------------------------------------------------------------------------------*/
      /* Init I/O Multi-function                                                                                 */
      /*---------------------------------------------------------------------------------------------------------*/
      /* Set PB multi-function pins for UART0 RXD and TXD */
      SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk);
      SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD);
  
      /* Setup SPI0 multi-function pins */
      SYS->GPC_MFP &= ~(SYS_GPC_MFP_PC0_Msk | SYS_GPC_MFP_PC1_Msk | SYS_GPC_MFP_PC2_Msk | SYS_GPC_MFP_PC3_Msk);
      SYS->GPC_MFP |= SYS_GPC_MFP_PC0_SPI0_SS0 | SYS_GPC_MFP_PC1_SPI0_CLK | SYS_GPC_MFP_PC2_SPI0_MISO0 | SYS_GPC_MFP_PC3_SPI0_MOSI0;
      SYS->ALT_MFP &= ~(SYS_ALT_MFP_PC0_Msk | SYS_ALT_MFP_PC1_Msk | SYS_ALT_MFP_PC2_Msk | SYS_ALT_MFP_PC3_Msk);
      SYS->ALT_MFP |= SYS_ALT_MFP_PC0_SPI0_SS0 | SYS_ALT_MFP_PC1_SPI0_CLK | SYS_ALT_MFP_PC2_SPI0_MISO0 | SYS_ALT_MFP_PC3_SPI0_MOSI0;
  }
  
  void SPI_Init(void)
  {
      /*---------------------------------------------------------------------------------------------------------*/
      /* Init SPI                                                                                                */
      /*---------------------------------------------------------------------------------------------------------*/
      /* Configure as a slave, clock idle low, 32-bit transaction, drive output on falling clock edge and latch input on rising edge. */
      /* Configure SPI0 as a low level active device. */
      SPI_Open(SPI0, SPI_SLAVE, SPI_MODE_0, 32, NULL);
  }
  
  /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
  
  