text: #!/usr/bin/env python3
  
  #
  # This file is part of LiteX-Boards.
  #
  # Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>,
  # Copyright (c) 2020 Staf Verhaegen <staf@fibraservi.eu>
  # SPDX-License-Identifier: BSD-2-Clause
  
  import os
  import argparse
  
  from migen import *
  
  from litex_boards.platforms import arty_s7
  from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
  
  from litex.soc.cores.clock import *
  from litex.soc.integration.soc_core import *
  from litex.soc.integration.builder import *
  from litex.soc.cores.led import LedChaser
  
  from litedram.modules import MT41K128M16
  from litedram.phy import s7ddrphy
  
  # CRG ----------------------------------------------------------------------------------------------
  
  class _CRG(Module):
      def __init__(self, platform, sys_clk_freq):
          self.rst = Signal()
          self.clock_domains.cd_sys       = ClockDomain()
          self.clock_domains.cd_sys2x     = ClockDomain(reset_less=True)
          self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
          self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
          self.clock_domains.cd_idelay    = ClockDomain()
  
          # # #
  
          self.submodules.pll = pll = S7PLL(speedgrade=-1)
          self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst)
          pll.register_clkin(platform.request("clk100"), 100e6)
          pll.create_clkout(self.cd_sys,       sys_clk_freq)
          pll.create_clkout(self.cd_sys2x,     2*sys_clk_freq)
          pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
          pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
          pll.create_clkout(self.cd_idelay,    200e6)
          platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
  
          self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
  
  # BaseSoC ------------------------------------------------------------------------------------------
  
  class BaseSoC(SoCCore):
      def __init__(self, variant="s7-50", sys_clk_freq=int(100e6), with_spi_flash=False, with_led_chaser=True, **kwargs):
          platform = arty_s7.Platform(variant=variant)
  
          # SoCCore ----------------------------------------------------------------------------------
          SoCCore.__init__(self, platform, sys_clk_freq,
              ident          = "LiteX SoC on Arty S7",
              ident_version  = True,
              **kwargs)
  
          # CRG --------------------------------------------------------------------------------------
          self.submodules.crg = _CRG(platform, sys_clk_freq)
  
          # DDR3 SDRAM -------------------------------------------------------------------------------
          if not self.integrated_main_ram_size:
              self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
                  memtype        = "DDR3",
                  nphases        = 4,
                  sys_clk_freq   = sys_clk_freq)
              self.add_sdram("sdram",
                  phy           = self.ddrphy,
                  module        = MT41K128M16(sys_clk_freq, "1:4"),
                  l2_cache_size = kwargs.get("l2_size", 8192)
              )
  
          # SPI Flash --------------------------------------------------------------------------------
          if with_spi_flash:
              from litespi.modules import S25FL128S
              from litespi.opcodes import SpiNorFlashOpCodes as Codes
              self.add_spi_flash(mode="4x", module=S25FL128S(Codes.READ_1_1_4), with_master=True)
  
          # Leds -------------------------------------------------------------------------------------
          if with_led_chaser:
              self.submodules.leds = LedChaser(
                  pads         = platform.request_all("user_led"),
                  sys_clk_freq = sys_clk_freq)
  
  # Build --------------------------------------------------------------------------------------------
  
  def main():
      parser = argparse.ArgumentParser(description="LiteX SoC on Arty S7")
      parser.add_argument("--build",          action="store_true", help="Build bitstream")
      parser.add_argument("--load",           action="store_true", help="Load bitstream")
      parser.add_argument("--variant",        default="s7-50",     help="Board variant: s7-50 (default) or s7-25")
      parser.add_argument("--sys-clk-freq",   default=100e6,       help="System clock frequency (default: 100MHz)")
      parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
      builder_args(parser)
      soc_core_args(parser)
      vivado_build_args(parser)
      args = parser.parse_args()
  
      soc = BaseSoC(
          variant        = args.variant,
          sys_clk_freq   = int(float(args.sys_clk_freq)),
          with_spi_flash = args.with_spi_flash,
          **soc_core_argdict(args)
      )
      builder = Builder(soc, **builder_argdict(args))
      builder.build(**vivado_build_argdict(args), run=args.build)
  
      if args.load:
          prog = soc.platform.create_programmer()
          prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
  
  if __name__ == "__main__":
      main()
  