text: /*
  ** ###################################################################
  **     Processors:          MKS22FN256LH12
  **                          MKS22FN128LH12
  **                          MKS22FN256LL12
  **                          MKS22FN128LL12
  **
  **     Compilers:           Keil ARM C/C++ Compiler
  **                          Freescale C/C++ for Embedded ARM
  **                          GNU C Compiler
  **                          GNU C Compiler - CodeSourcery Sourcery G++
  **                          IAR ANSI C/C++ Compiler for ARM
  **
  **     Reference manual:    KS22P100M120SF0RM, Rev. 1, Sep. 2015
  **     Version:             rev. 2.0, 2015-10-10
  **     Build:               b151021
  **
  **     Abstract:
  **         CMSIS Peripheral Access Layer for MKS22F25612
  **
  **     Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
  **     All rights reserved.
  **
  **     Redistribution and use in source and binary forms, with or without modification,
  **     are permitted provided that the following conditions are met:
  **
  **     o Redistributions of source code must retain the above copyright notice, this list
  **       of conditions and the following disclaimer.
  **
  **     o Redistributions in binary form must reproduce the above copyright notice, this
  **       list of conditions and the following disclaimer in the documentation and/or
  **       other materials provided with the distribution.
  **
  **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  **       contributors may be used to endorse or promote products derived from this
  **       software without specific prior written permission.
  **
  **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  **
  **     http:                 www.freescale.com
  **     mail:                 support@freescale.com
  **
  **     Revisions:
  **     - rev. 1.0 (2015-06-23)
  **         Initial version.
  **     - rev. 2.0 (2015-10-10)
  **         Update according to Rev1 RM, Sep 2015.
  **
  ** ###################################################################
  */
  
  /*!
   * @file MKS22F25612.h
   * @version 2.0
   * @date 2015-10-10
   * @brief CMSIS Peripheral Access Layer for MKS22F25612
   *
   * CMSIS Peripheral Access Layer for MKS22F25612
   */
  
  
  /* ----------------------------------------------------------------------------
     -- MCU activation
     ---------------------------------------------------------------------------- */
  
  /* Prevention from multiple including the same memory map */
  #if !defined(MKS22F25612_H_)  /* Check if memory map has not been already included */
  #define MKS22F25612_H_
  #define MCU_MKS22F25612
  
  /* Check if another memory map has not been also included */
  #if (defined(MCU_ACTIVE))
    #error MKS22F25612 memory map: There is already included another memory map. Only one memory map can be included.
  #endif /* (defined(MCU_ACTIVE)) */
  #define MCU_ACTIVE
  
  #include <stdint.h>
  
  /** Memory map major version (memory maps with equal major version number are
   * compatible) */
  #define MCU_MEM_MAP_VERSION 0x0200u
  /** Memory map minor version */
  #define MCU_MEM_MAP_VERSION_MINOR 0x0000u
  
  /**
   * @brief Macro to calculate address of an aliased word in the peripheral
   *        bitband area for a peripheral register and bit (bit band region 0x40000000 to
   *        0x400FFFFF).
   * @param Reg Register to access.
   * @param Bit Bit number to access.
   * @return  Address of the aliased word in the peripheral bitband area.
   */
  #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
  /**
   * @brief Macro to access a single bit of a peripheral register (bit band region
   *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
   *        be used for peripherals with 32bit access allowed.
   * @param Reg Register to access.
   * @param Bit Bit number to access.
   * @return Value of the targeted bit in the bit band region.
   */
  #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
  #define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
  /**
   * @brief Macro to access a single bit of a peripheral register (bit band region
   *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
   *        be used for peripherals with 16bit access allowed.
   * @param Reg Register to access.
   * @param Bit Bit number to access.
   * @return Value of the targeted bit in the bit band region.
   */
  #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
  /**
   * @brief Macro to access a single bit of a peripheral register (bit band region
   *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
   *        be used for peripherals with 8bit access allowed.
   * @param Reg Register to access.
   * @param Bit Bit number to access.
   * @return Value of the targeted bit in the bit band region.
   */
  #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
  
  /* ----------------------------------------------------------------------------
     -- Interrupt vector numbers
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
   * @{
   */
  
  /** Interrupt Number Definitions */
  #define NUMBER_OF_INT_VECTORS 116                /**< Number of interrupts in the Vector table */
  
  typedef enum IRQn {
    /* Core interrupts */
    NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
    HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
    MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
    BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
    UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
    SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
    DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
    PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
    SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
  
    /* Device specific interrupts */
    DMA0_IRQn                    = 0,                /**< DMA Channel 0 Transfer Complete */
    DMA1_IRQn                    = 1,                /**< DMA Channel 1 Transfer Complete */
    DMA2_IRQn                    = 2,                /**< DMA Channel 2 Transfer Complete */
    DMA3_IRQn                    = 3,                /**< DMA Channel 3 Transfer Complete */
    DMA4_IRQn                    = 4,                /**< DMA Channel 4 Transfer Complete */
    DMA5_IRQn                    = 5,                /**< DMA Channel 5 Transfer Complete */
    DMA6_IRQn                    = 6,                /**< DMA Channel 6 Transfer Complete */
    DMA7_IRQn                    = 7,                /**< DMA Channel 7 Transfer Complete */
    DMA8_IRQn                    = 8,                /**< DMA Channel 8 Transfer Complete */
    DMA9_IRQn                    = 9,                /**< DMA Channel 9 Transfer Complete */
    DMA10_IRQn                   = 10,               /**< DMA Channel 10 Transfer Complete */
    DMA11_IRQn                   = 11,               /**< DMA Channel 11 Transfer Complete */
    DMA12_IRQn                   = 12,               /**< DMA Channel 12 Transfer Complete */
    DMA13_IRQn                   = 13,               /**< DMA Channel 13 Transfer Complete */
    DMA14_IRQn                   = 14,               /**< DMA Channel 14 Transfer Complete */
    DMA15_IRQn                   = 15,               /**< DMA Channel 15 Transfer Complete */
    DMA_Error_IRQn               = 16,               /**< DMA Error Interrupt */
    MCM_IRQn                     = 17,               /**< Normal Interrupt */
    FTF_IRQn                     = 18,               /**< FTFA Command complete interrupt */
    Read_Collision_IRQn          = 19,               /**< Read Collision Interrupt */
    LVD_LVW_IRQn                 = 20,               /**< Low Voltage Detect, Low Voltage Warning */
    LLWU_IRQn                    = 21,               /**< Low Leakage Wakeup Unit */
    WDOG_EWM_IRQn                = 22,               /**< WDOG Interrupt */
    RNG_IRQn                     = 23,               /**< RNG Interrupt */
    LPI2C0_IRQn                  = 24,               /**< LPI2C0 interrupt */
    LPI2C1_IRQn                  = 25,               /**< LPI2C1 interrupt */
    SPI0_IRQn                    = 26,               /**< SPI0 Interrupt */
    SPI1_IRQn                    = 27,               /**< SPI1 Interrupt */
    I2S0_Tx_IRQn                 = 28,               /**< I2S0 transmit interrupt */
    I2S0_Rx_IRQn                 = 29,               /**< I2S0 receive interrupt */
    LPUART0_IRQn                 = 30,               /**< LPUART0 status/error interrupt */
    UART0_RX_TX_IRQn             = 31,               /**< UART0 Status Sources interrupt */
    UART0_ERR_IRQn               = 32,               /**< UART0 Error Sources interrupt */
    UART1_RX_TX_IRQn             = 33,               /**< UART1 Status Sources interrupt */
    UART1_ERR_IRQn               = 34,               /**< UART1 Error Sources interrupt */
    UART2_RX_TX_IRQn             = 35,               /**< UART2 Status Sources interrupt */
    UART2_ERR_IRQn               = 36,               /**< UART2 Error Sources interrupt */
    Reserved53_IRQn              = 37,               /**< Reserved interrupt 53 */
    Reserved54_IRQn              = 38,               /**< Reserved interrupt 54 */
    ADC0_IRQn                    = 39,               /**< ADC0 interrupt */
    CMP0_IRQn                    = 40,               /**< CMP0 interrupt */
    Reserved57_IRQn              = 41,               /**< Reserved interrupt 57 */
    TPM0_IRQn                    = 42,               /**< TPM0 Timer Overflow and Channels interrupt */
    TPM1_IRQn                    = 43,               /**< TPM1 Timer Overflow and Channels interrupt */
    TPM2_IRQn                    = 44,               /**< TPM2 Timer Overflow and Channels interrupt */
    Reserved61_IRQn              = 45,               /**< Reserved interrupt 61 */
    RTC_IRQn                     = 46,               /**< RTC alarm interrupt */
    RTC_Seconds_IRQn             = 47,               /**< RTC seconds interrupt */
    PIT0_IRQn                    = 48,               /**< PIT timer channel 0 interrupt */
    PIT1_IRQn                    = 49,               /**< PIT timer channel 1 interrupt */
    PIT2_IRQn                    = 50,               /**< PIT timer channel 2 interrupt */
    PIT3_IRQn                    = 51,               /**< PIT timer channel 3 interrupt */
    PDB0_IRQn                    = 52,               /**< PDB0 Interrupt */
    USB0_IRQn                    = 53,               /**< USB0 interrupt */
    Reserved70_IRQn              = 54,               /**< Reserved interrupt 70 */
    Reserved71_IRQn              = 55,               /**< Reserved interrupt 71 */
    DAC0_IRQn                    = 56,               /**< DAC0 interrupt */
    MCG_IRQn                     = 57,               /**< MCG Interrupt */
    LPTMR0_IRQn                  = 58,               /**< LPTimer interrupt */
    PORTA_IRQn                   = 59,               /**< Port A interrupt */
    PORTB_IRQn                   = 60,               /**< Port B interrupt */
    PORTC_IRQn                   = 61,               /**< Port C interrupt */
    PORTD_IRQn                   = 62,               /**< Port D interrupt */
    PORTE_IRQn                   = 63,               /**< Port E interrupt */
    SWI_IRQn                     = 64,               /**< Software interrupt */
    Reserved81_IRQn              = 65,               /**< Reserved interrupt 81 */
    Reserved82_IRQn              = 66,               /**< Reserved interrupt 82 */
    Reserved83_IRQn              = 67,               /**< Reserved interrupt 83 */
    Reserved84_IRQn              = 68,               /**< Reserved interrupt 84 */
    Reserved85_IRQn              = 69,               /**< Reserved interrupt 85 */
    FLEXIO_IRQn                  = 70,               /**< Flexible IO interrupt */
    Reserved87_IRQn              = 71,               /**< Reserved interrupt 87 */
    Reserved88_IRQn              = 72,               /**< Reserved interrupt 88 */
    Reserved89_IRQn              = 73,               /**< Reserved interrupt 89 */
    Reserved90_IRQn              = 74,               /**< Reserved Interrupt 90 */
    CAN0_ORed_Message_buffer_IRQn = 75,              /**< CAN0 OR'd message buffers interrupt */
    CAN0_Bus_Off_IRQn            = 76,               /**< CAN0 bus off interrupt */
    CAN0_Error_IRQn              = 77,               /**< CAN0 error interrupt */
    CAN0_Tx_Warning_IRQn         = 78,               /**< CAN0 Tx warning interrupt */
    CAN0_Rx_Warning_IRQn         = 79,               /**< CAN0 Rx warning interrupt */
    CAN0_Wake_Up_IRQn            = 80,               /**< CAN0 wake up interrupt */
    Reserved97_IRQn              = 81,               /**< Reserved Interrupt 97 */
    Reserved98_IRQn              = 82,               /**< Reserved Interrupt 98 */
    Reserved99_IRQn              = 83,               /**< Reserved Interrupt 99 */
    Reserved100_IRQn             = 84,               /**< Reserved Interrupt 100 */
    Reserved101_IRQn             = 85,               /**< Reserved Interrupt 101 */
    Reserved102_IRQn             = 86,               /**< Reserved Interrupt 102 */
    Reserved103_IRQn             = 87,               /**< Reserved Interrupt 103 */
    I2S1_Tx_IRQn                 = 88,               /**< I2S1 transmit interrupt */
    I2S1_Rx_IRQn                 = 89,               /**< I2S1 receive interrupt */
    Reserved106_IRQn             = 90,               /**< Reserved Interrupt 106 */
    Reserved107_IRQn             = 91,               /**< Reserved Interrupt 107 */
    Reserved108_IRQn             = 92,               /**< Reserved Interrupt 108 */
    Reserved109_IRQn             = 93,               /**< Reserved Interrupt 109 */
    CAN1_ORed_Message_buffer_IRQn = 94,              /**< CAN0 OR'd message buffers interrupt */
    CAN1_Bus_Off_IRQn            = 95,               /**< CAN1 bus off interrupt */
    CAN1_Error_IRQn              = 96,               /**< CAN1 error interrupt */
    CAN1_Tx_Warning_IRQn         = 97,               /**< CAN1 Tx warning interrupt */
    CAN1_Rx_Warning_IRQn         = 98,               /**< CAN1 Rx warning interrupt */
    CAN1_Wake_Up_IRQn            = 99                /**< CAN1 wake up interrupt */
  } IRQn_Type;
  
  /*!
   * @}
   */ /* end of group Interrupt_vector_numbers */
  
  
  /* ----------------------------------------------------------------------------
     -- Cortex M4 Core Configuration
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
   * @{
   */
  
  #define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
  #define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
  #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
  #define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
  
  #include "core_cm4.h"                  /* Core Peripheral Access Layer */
  #include "system_MKS22F25612.h"        /* Device specific configuration file */
  
  /*!
   * @}
   */ /* end of group Cortex_Core_Configuration */
  
  
  /* ----------------------------------------------------------------------------
     -- Device Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
   * @{
   */
  
  
  /*
  ** Start of section using anonymous unions
  */
  
  #if defined(__ARMCC_VERSION)
    #pragma push
    #pragma anon_unions
  #elif defined(__CWCC__)
    #pragma push
    #pragma cpp_extensions on
  #elif defined(__GNUC__)
    /* anonymous unions are enabled by default */
  #elif defined(__IAR_SYSTEMS_ICC__)
    #pragma language=extended
  #else
    #error Not supported compiler type
  #endif
  
  /* ----------------------------------------------------------------------------
     -- ADC Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
   * @{
   */
  
  /** ADC - Register Layout Typedef */
  typedef struct {
    __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
    __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
    __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
    __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
    __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
    __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
    __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
    __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
    __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
    __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
    __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
    __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
    __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
    __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
    __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
    __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
    __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
    __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
         uint8_t RESERVED_0[4];
    __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
    __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
    __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
    __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
    __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
    __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
    __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
  } ADC_Type, *ADC_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- ADC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
   * @{
   */
  
  
  /* ADC - Register accessors */
  #define ADC_SC1_REG(base,index)                  ((base)->SC1[index])
  #define ADC_SC1_COUNT                            2
  #define ADC_CFG1_REG(base)                       ((base)->CFG1)
  #define ADC_CFG2_REG(base)                       ((base)->CFG2)
  #define ADC_R_REG(base,index)                    ((base)->R[index])
  #define ADC_R_COUNT                              2
  #define ADC_CV1_REG(base)                        ((base)->CV1)
  #define ADC_CV2_REG(base)                        ((base)->CV2)
  #define ADC_SC2_REG(base)                        ((base)->SC2)
  #define ADC_SC3_REG(base)                        ((base)->SC3)
  #define ADC_OFS_REG(base)                        ((base)->OFS)
  #define ADC_PG_REG(base)                         ((base)->PG)
  #define ADC_MG_REG(base)                         ((base)->MG)
  #define ADC_CLPD_REG(base)                       ((base)->CLPD)
  #define ADC_CLPS_REG(base)                       ((base)->CLPS)
  #define ADC_CLP4_REG(base)                       ((base)->CLP4)
  #define ADC_CLP3_REG(base)                       ((base)->CLP3)
  #define ADC_CLP2_REG(base)                       ((base)->CLP2)
  #define ADC_CLP1_REG(base)                       ((base)->CLP1)
  #define ADC_CLP0_REG(base)                       ((base)->CLP0)
  #define ADC_CLMD_REG(base)                       ((base)->CLMD)
  #define ADC_CLMS_REG(base)                       ((base)->CLMS)
  #define ADC_CLM4_REG(base)                       ((base)->CLM4)
  #define ADC_CLM3_REG(base)                       ((base)->CLM3)
  #define ADC_CLM2_REG(base)                       ((base)->CLM2)
  #define ADC_CLM1_REG(base)                       ((base)->CLM1)
  #define ADC_CLM0_REG(base)                       ((base)->CLM0)
  
  /*!
   * @}
   */ /* end of group ADC_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- ADC Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup ADC_Register_Masks ADC Register Masks
   * @{
   */
  
  /* SC1 Bit Fields */
  #define ADC_SC1_ADCH_MASK                        0x1Fu
  #define ADC_SC1_ADCH_SHIFT                       0
  #define ADC_SC1_ADCH_WIDTH                       5
  #define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
  #define ADC_SC1_DIFF_MASK                        0x20u
  #define ADC_SC1_DIFF_SHIFT                       5
  #define ADC_SC1_DIFF_WIDTH                       1
  #define ADC_SC1_DIFF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_DIFF_SHIFT))&ADC_SC1_DIFF_MASK)
  #define ADC_SC1_AIEN_MASK                        0x40u
  #define ADC_SC1_AIEN_SHIFT                       6
  #define ADC_SC1_AIEN_WIDTH                       1
  #define ADC_SC1_AIEN(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
  #define ADC_SC1_COCO_MASK                        0x80u
  #define ADC_SC1_COCO_SHIFT                       7
  #define ADC_SC1_COCO_WIDTH                       1
  #define ADC_SC1_COCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
  /* CFG1 Bit Fields */
  #define ADC_CFG1_ADICLK_MASK                     0x3u
  #define ADC_CFG1_ADICLK_SHIFT                    0
  #define ADC_CFG1_ADICLK_WIDTH                    2
  #define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
  #define ADC_CFG1_MODE_MASK                       0xCu
  #define ADC_CFG1_MODE_SHIFT                      2
  #define ADC_CFG1_MODE_WIDTH                      2
  #define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
  #define ADC_CFG1_ADLSMP_MASK                     0x10u
  #define ADC_CFG1_ADLSMP_SHIFT                    4
  #define ADC_CFG1_ADLSMP_WIDTH                    1
  #define ADC_CFG1_ADLSMP(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLSMP_SHIFT))&ADC_CFG1_ADLSMP_MASK)
  #define ADC_CFG1_ADIV_MASK                       0x60u
  #define ADC_CFG1_ADIV_SHIFT                      5
  #define ADC_CFG1_ADIV_WIDTH                      2
  #define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
  #define ADC_CFG1_ADLPC_MASK                      0x80u
  #define ADC_CFG1_ADLPC_SHIFT                     7
  #define ADC_CFG1_ADLPC_WIDTH                     1
  #define ADC_CFG1_ADLPC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADLPC_SHIFT))&ADC_CFG1_ADLPC_MASK)
  /* CFG2 Bit Fields */
  #define ADC_CFG2_ADLSTS_MASK                     0x3u
  #define ADC_CFG2_ADLSTS_SHIFT                    0
  #define ADC_CFG2_ADLSTS_WIDTH                    2
  #define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
  #define ADC_CFG2_ADHSC_MASK                      0x4u
  #define ADC_CFG2_ADHSC_SHIFT                     2
  #define ADC_CFG2_ADHSC_WIDTH                     1
  #define ADC_CFG2_ADHSC(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADHSC_SHIFT))&ADC_CFG2_ADHSC_MASK)
  #define ADC_CFG2_ADACKEN_MASK                    0x8u
  #define ADC_CFG2_ADACKEN_SHIFT                   3
  #define ADC_CFG2_ADACKEN_WIDTH                   1
  #define ADC_CFG2_ADACKEN(x)                      (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADACKEN_SHIFT))&ADC_CFG2_ADACKEN_MASK)
  #define ADC_CFG2_MUXSEL_MASK                     0x10u
  #define ADC_CFG2_MUXSEL_SHIFT                    4
  #define ADC_CFG2_MUXSEL_WIDTH                    1
  #define ADC_CFG2_MUXSEL(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_MUXSEL_SHIFT))&ADC_CFG2_MUXSEL_MASK)
  /* R Bit Fields */
  #define ADC_R_D_MASK                             0xFFFFu
  #define ADC_R_D_SHIFT                            0
  #define ADC_R_D_WIDTH                            16
  #define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
  /* CV1 Bit Fields */
  #define ADC_CV1_CV_MASK                          0xFFFFu
  #define ADC_CV1_CV_SHIFT                         0
  #define ADC_CV1_CV_WIDTH                         16
  #define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
  /* CV2 Bit Fields */
  #define ADC_CV2_CV_MASK                          0xFFFFu
  #define ADC_CV2_CV_SHIFT                         0
  #define ADC_CV2_CV_WIDTH                         16
  #define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
  /* SC2 Bit Fields */
  #define ADC_SC2_REFSEL_MASK                      0x3u
  #define ADC_SC2_REFSEL_SHIFT                     0
  #define ADC_SC2_REFSEL_WIDTH                     2
  #define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
  #define ADC_SC2_DMAEN_MASK                       0x4u
  #define ADC_SC2_DMAEN_SHIFT                      2
  #define ADC_SC2_DMAEN_WIDTH                      1
  #define ADC_SC2_DMAEN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
  #define ADC_SC2_ACREN_MASK                       0x8u
  #define ADC_SC2_ACREN_SHIFT                      3
  #define ADC_SC2_ACREN_WIDTH                      1
  #define ADC_SC2_ACREN(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
  #define ADC_SC2_ACFGT_MASK                       0x10u
  #define ADC_SC2_ACFGT_SHIFT                      4
  #define ADC_SC2_ACFGT_WIDTH                      1
  #define ADC_SC2_ACFGT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
  #define ADC_SC2_ACFE_MASK                        0x20u
  #define ADC_SC2_ACFE_SHIFT                       5
  #define ADC_SC2_ACFE_WIDTH                       1
  #define ADC_SC2_ACFE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
  #define ADC_SC2_ADTRG_MASK                       0x40u
  #define ADC_SC2_ADTRG_SHIFT                      6
  #define ADC_SC2_ADTRG_WIDTH                      1
  #define ADC_SC2_ADTRG(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
  #define ADC_SC2_ADACT_MASK                       0x80u
  #define ADC_SC2_ADACT_SHIFT                      7
  #define ADC_SC2_ADACT_WIDTH                      1
  #define ADC_SC2_ADACT(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
  /* SC3 Bit Fields */
  #define ADC_SC3_AVGS_MASK                        0x3u
  #define ADC_SC3_AVGS_SHIFT                       0
  #define ADC_SC3_AVGS_WIDTH                       2
  #define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
  #define ADC_SC3_AVGE_MASK                        0x4u
  #define ADC_SC3_AVGE_SHIFT                       2
  #define ADC_SC3_AVGE_WIDTH                       1
  #define ADC_SC3_AVGE(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
  #define ADC_SC3_ADCO_MASK                        0x8u
  #define ADC_SC3_ADCO_SHIFT                       3
  #define ADC_SC3_ADCO_WIDTH                       1
  #define ADC_SC3_ADCO(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
  #define ADC_SC3_CALF_MASK                        0x40u
  #define ADC_SC3_CALF_SHIFT                       6
  #define ADC_SC3_CALF_WIDTH                       1
  #define ADC_SC3_CALF(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CALF_SHIFT))&ADC_SC3_CALF_MASK)
  #define ADC_SC3_CAL_MASK                         0x80u
  #define ADC_SC3_CAL_SHIFT                        7
  #define ADC_SC3_CAL_WIDTH                        1
  #define ADC_SC3_CAL(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
  /* OFS Bit Fields */
  #define ADC_OFS_OFS_MASK                         0xFFFFu
  #define ADC_OFS_OFS_SHIFT                        0
  #define ADC_OFS_OFS_WIDTH                        16
  #define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
  /* PG Bit Fields */
  #define ADC_PG_PG_MASK                           0xFFFFu
  #define ADC_PG_PG_SHIFT                          0
  #define ADC_PG_PG_WIDTH                          16
  #define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
  /* MG Bit Fields */
  #define ADC_MG_MG_MASK                           0xFFFFu
  #define ADC_MG_MG_SHIFT                          0
  #define ADC_MG_MG_WIDTH                          16
  #define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
  /* CLPD Bit Fields */
  #define ADC_CLPD_CLPD_MASK                       0x3Fu
  #define ADC_CLPD_CLPD_SHIFT                      0
  #define ADC_CLPD_CLPD_WIDTH                      6
  #define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
  /* CLPS Bit Fields */
  #define ADC_CLPS_CLPS_MASK                       0x3Fu
  #define ADC_CLPS_CLPS_SHIFT                      0
  #define ADC_CLPS_CLPS_WIDTH                      6
  #define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
  /* CLP4 Bit Fields */
  #define ADC_CLP4_CLP4_MASK                       0x3FFu
  #define ADC_CLP4_CLP4_SHIFT                      0
  #define ADC_CLP4_CLP4_WIDTH                      10
  #define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
  /* CLP3 Bit Fields */
  #define ADC_CLP3_CLP3_MASK                       0x1FFu
  #define ADC_CLP3_CLP3_SHIFT                      0
  #define ADC_CLP3_CLP3_WIDTH                      9
  #define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
  /* CLP2 Bit Fields */
  #define ADC_CLP2_CLP2_MASK                       0xFFu
  #define ADC_CLP2_CLP2_SHIFT                      0
  #define ADC_CLP2_CLP2_WIDTH                      8
  #define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
  /* CLP1 Bit Fields */
  #define ADC_CLP1_CLP1_MASK                       0x7Fu
  #define ADC_CLP1_CLP1_SHIFT                      0
  #define ADC_CLP1_CLP1_WIDTH                      7
  #define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
  /* CLP0 Bit Fields */
  #define ADC_CLP0_CLP0_MASK                       0x3Fu
  #define ADC_CLP0_CLP0_SHIFT                      0
  #define ADC_CLP0_CLP0_WIDTH                      6
  #define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
  /* CLMD Bit Fields */
  #define ADC_CLMD_CLMD_MASK                       0x3Fu
  #define ADC_CLMD_CLMD_SHIFT                      0
  #define ADC_CLMD_CLMD_WIDTH                      6
  #define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
  /* CLMS Bit Fields */
  #define ADC_CLMS_CLMS_MASK                       0x3Fu
  #define ADC_CLMS_CLMS_SHIFT                      0
  #define ADC_CLMS_CLMS_WIDTH                      6
  #define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
  /* CLM4 Bit Fields */
  #define ADC_CLM4_CLM4_MASK                       0x3FFu
  #define ADC_CLM4_CLM4_SHIFT                      0
  #define ADC_CLM4_CLM4_WIDTH                      10
  #define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
  /* CLM3 Bit Fields */
  #define ADC_CLM3_CLM3_MASK                       0x1FFu
  #define ADC_CLM3_CLM3_SHIFT                      0
  #define ADC_CLM3_CLM3_WIDTH                      9
  #define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
  /* CLM2 Bit Fields */
  #define ADC_CLM2_CLM2_MASK                       0xFFu
  #define ADC_CLM2_CLM2_SHIFT                      0
  #define ADC_CLM2_CLM2_WIDTH                      8
  #define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
  /* CLM1 Bit Fields */
  #define ADC_CLM1_CLM1_MASK                       0x7Fu
  #define ADC_CLM1_CLM1_SHIFT                      0
  #define ADC_CLM1_CLM1_WIDTH                      7
  #define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
  /* CLM0 Bit Fields */
  #define ADC_CLM0_CLM0_MASK                       0x3Fu
  #define ADC_CLM0_CLM0_SHIFT                      0
  #define ADC_CLM0_CLM0_WIDTH                      6
  #define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
  
  /*!
   * @}
   */ /* end of group ADC_Register_Masks */
  
  
  /* ADC - Peripheral instance base addresses */
  /** Peripheral ADC0 base address */
  #define ADC0_BASE                                (0x4003B000u)
  /** Peripheral ADC0 base pointer */
  #define ADC0                                     ((ADC_Type *)ADC0_BASE)
  #define ADC0_BASE_PTR                            (ADC0)
  /** Array initializer of ADC peripheral base addresses */
  #define ADC_BASE_ADDRS                           { ADC0_BASE }
  /** Array initializer of ADC peripheral base pointers */
  #define ADC_BASE_PTRS                            { ADC0 }
  
  /* ----------------------------------------------------------------------------
     -- ADC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
   * @{
   */
  
  
  /* ADC - Register instance definitions */
  /* ADC0 */
  #define ADC0_SC1A                                ADC_SC1_REG(ADC0,0)
  #define ADC0_SC1B                                ADC_SC1_REG(ADC0,1)
  #define ADC0_CFG1                                ADC_CFG1_REG(ADC0)
  #define ADC0_CFG2                                ADC_CFG2_REG(ADC0)
  #define ADC0_RA                                  ADC_R_REG(ADC0,0)
  #define ADC0_RB                                  ADC_R_REG(ADC0,1)
  #define ADC0_CV1                                 ADC_CV1_REG(ADC0)
  #define ADC0_CV2                                 ADC_CV2_REG(ADC0)
  #define ADC0_SC2                                 ADC_SC2_REG(ADC0)
  #define ADC0_SC3                                 ADC_SC3_REG(ADC0)
  #define ADC0_OFS                                 ADC_OFS_REG(ADC0)
  #define ADC0_PG                                  ADC_PG_REG(ADC0)
  #define ADC0_MG                                  ADC_MG_REG(ADC0)
  #define ADC0_CLPD                                ADC_CLPD_REG(ADC0)
  #define ADC0_CLPS                                ADC_CLPS_REG(ADC0)
  #define ADC0_CLP4                                ADC_CLP4_REG(ADC0)
  #define ADC0_CLP3                                ADC_CLP3_REG(ADC0)
  #define ADC0_CLP2                                ADC_CLP2_REG(ADC0)
  #define ADC0_CLP1                                ADC_CLP1_REG(ADC0)
  #define ADC0_CLP0                                ADC_CLP0_REG(ADC0)
  #define ADC0_CLMD                                ADC_CLMD_REG(ADC0)
  #define ADC0_CLMS                                ADC_CLMS_REG(ADC0)
  #define ADC0_CLM4                                ADC_CLM4_REG(ADC0)
  #define ADC0_CLM3                                ADC_CLM3_REG(ADC0)
  #define ADC0_CLM2                                ADC_CLM2_REG(ADC0)
  #define ADC0_CLM1                                ADC_CLM1_REG(ADC0)
  #define ADC0_CLM0                                ADC_CLM0_REG(ADC0)
  
  /* ADC - Register array accessors */
  #define ADC0_SC1(index)                          ADC_SC1_REG(ADC0,index)
  #define ADC0_R(index)                            ADC_R_REG(ADC0,index)
  
  /*!
   * @}
   */ /* end of group ADC_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group ADC_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- CAN Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
   * @{
   */
  
  /** CAN - Register Layout Typedef */
  typedef struct {
    __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
    __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
    __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
         uint8_t RESERVED_0[4];
    __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
    __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
    __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
    __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
    __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
         uint8_t RESERVED_1[4];
    __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
         uint8_t RESERVED_2[4];
    __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
    __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
    __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
         uint8_t RESERVED_3[8];
    __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
    __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
    __I  uint32_t RXFIR;                             /**< Rx FIFO Information Register, offset: 0x4C */
    __IO uint32_t CBT;                               /**< CAN Bit Timing Register, offset: 0x50 */
         uint8_t RESERVED_4[44];
    struct {                                         /* offset: 0x80, array step: 0x10 */
      __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
      __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
      __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
      __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
    } MB[16];
         uint8_t RESERVED_5[1792];
    __IO uint32_t RXIMR[16];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
  } CAN_Type, *CAN_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- CAN - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
   * @{
   */
  
  
  /* CAN - Register accessors */
  #define CAN_MCR_REG(base)                        ((base)->MCR)
  #define CAN_CTRL1_REG(base)                      ((base)->CTRL1)
  #define CAN_TIMER_REG(base)                      ((base)->TIMER)
  #define CAN_RXMGMASK_REG(base)                   ((base)->RXMGMASK)
  #define CAN_RX14MASK_REG(base)                   ((base)->RX14MASK)
  #define CAN_RX15MASK_REG(base)                   ((base)->RX15MASK)
  #define CAN_ECR_REG(base)                        ((base)->ECR)
  #define CAN_ESR1_REG(base)                       ((base)->ESR1)
  #define CAN_IMASK1_REG(base)                     ((base)->IMASK1)
  #define CAN_IFLAG1_REG(base)                     ((base)->IFLAG1)
  #define CAN_CTRL2_REG(base)                      ((base)->CTRL2)
  #define CAN_ESR2_REG(base)                       ((base)->ESR2)
  #define CAN_CRCR_REG(base)                       ((base)->CRCR)
  #define CAN_RXFGMASK_REG(base)                   ((base)->RXFGMASK)
  #define CAN_RXFIR_REG(base)                      ((base)->RXFIR)
  #define CAN_CBT_REG(base)                        ((base)->CBT)
  #define CAN_CS_REG(base,index)                   ((base)->MB[index].CS)
  #define CAN_CS_COUNT                             16
  #define CAN_ID_REG(base,index)                   ((base)->MB[index].ID)
  #define CAN_ID_COUNT                             16
  #define CAN_WORD0_REG(base,index)                ((base)->MB[index].WORD0)
  #define CAN_WORD0_COUNT                          16
  #define CAN_WORD1_REG(base,index)                ((base)->MB[index].WORD1)
  #define CAN_WORD1_COUNT                          16
  #define CAN_RXIMR_REG(base,index)                ((base)->RXIMR[index])
  #define CAN_RXIMR_COUNT                          16
  
  /*!
   * @}
   */ /* end of group CAN_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- CAN Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CAN_Register_Masks CAN Register Masks
   * @{
   */
  
  /* MCR Bit Fields */
  #define CAN_MCR_MAXMB_MASK                       0x7Fu
  #define CAN_MCR_MAXMB_SHIFT                      0
  #define CAN_MCR_MAXMB_WIDTH                      7
  #define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
  #define CAN_MCR_IDAM_MASK                        0x300u
  #define CAN_MCR_IDAM_SHIFT                       8
  #define CAN_MCR_IDAM_WIDTH                       2
  #define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
  #define CAN_MCR_AEN_MASK                         0x1000u
  #define CAN_MCR_AEN_SHIFT                        12
  #define CAN_MCR_AEN_WIDTH                        1
  #define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_MCR_AEN_SHIFT))&CAN_MCR_AEN_MASK)
  #define CAN_MCR_LPRIOEN_MASK                     0x2000u
  #define CAN_MCR_LPRIOEN_SHIFT                    13
  #define CAN_MCR_LPRIOEN_WIDTH                    1
  #define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPRIOEN_SHIFT))&CAN_MCR_LPRIOEN_MASK)
  #define CAN_MCR_DMA_MASK                         0x8000u
  #define CAN_MCR_DMA_SHIFT                        15
  #define CAN_MCR_DMA_WIDTH                        1
  #define CAN_MCR_DMA(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_MCR_DMA_SHIFT))&CAN_MCR_DMA_MASK)
  #define CAN_MCR_IRMQ_MASK                        0x10000u
  #define CAN_MCR_IRMQ_SHIFT                       16
  #define CAN_MCR_IRMQ_WIDTH                       1
  #define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IRMQ_SHIFT))&CAN_MCR_IRMQ_MASK)
  #define CAN_MCR_SRXDIS_MASK                      0x20000u
  #define CAN_MCR_SRXDIS_SHIFT                     17
  #define CAN_MCR_SRXDIS_WIDTH                     1
  #define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SRXDIS_SHIFT))&CAN_MCR_SRXDIS_MASK)
  #define CAN_MCR_DOZE_MASK                        0x40000u
  #define CAN_MCR_DOZE_SHIFT                       18
  #define CAN_MCR_DOZE_WIDTH                       1
  #define CAN_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_DOZE_SHIFT))&CAN_MCR_DOZE_MASK)
  #define CAN_MCR_WAKSRC_MASK                      0x80000u
  #define CAN_MCR_WAKSRC_SHIFT                     19
  #define CAN_MCR_WAKSRC_WIDTH                     1
  #define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKSRC_SHIFT))&CAN_MCR_WAKSRC_MASK)
  #define CAN_MCR_LPMACK_MASK                      0x100000u
  #define CAN_MCR_LPMACK_SHIFT                     20
  #define CAN_MCR_LPMACK_WIDTH                     1
  #define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPMACK_SHIFT))&CAN_MCR_LPMACK_MASK)
  #define CAN_MCR_WRNEN_MASK                       0x200000u
  #define CAN_MCR_WRNEN_SHIFT                      21
  #define CAN_MCR_WRNEN_WIDTH                      1
  #define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WRNEN_SHIFT))&CAN_MCR_WRNEN_MASK)
  #define CAN_MCR_SLFWAK_MASK                      0x400000u
  #define CAN_MCR_SLFWAK_SHIFT                     22
  #define CAN_MCR_SLFWAK_WIDTH                     1
  #define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SLFWAK_SHIFT))&CAN_MCR_SLFWAK_MASK)
  #define CAN_MCR_SUPV_MASK                        0x800000u
  #define CAN_MCR_SUPV_SHIFT                       23
  #define CAN_MCR_SUPV_WIDTH                       1
  #define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SUPV_SHIFT))&CAN_MCR_SUPV_MASK)
  #define CAN_MCR_FRZACK_MASK                      0x1000000u
  #define CAN_MCR_FRZACK_SHIFT                     24
  #define CAN_MCR_FRZACK_WIDTH                     1
  #define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZACK_SHIFT))&CAN_MCR_FRZACK_MASK)
  #define CAN_MCR_SOFTRST_MASK                     0x2000000u
  #define CAN_MCR_SOFTRST_SHIFT                    25
  #define CAN_MCR_SOFTRST_WIDTH                    1
  #define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SOFTRST_SHIFT))&CAN_MCR_SOFTRST_MASK)
  #define CAN_MCR_WAKMSK_MASK                      0x4000000u
  #define CAN_MCR_WAKMSK_SHIFT                     26
  #define CAN_MCR_WAKMSK_WIDTH                     1
  #define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WAKMSK_SHIFT))&CAN_MCR_WAKMSK_MASK)
  #define CAN_MCR_NOTRDY_MASK                      0x8000000u
  #define CAN_MCR_NOTRDY_SHIFT                     27
  #define CAN_MCR_NOTRDY_WIDTH                     1
  #define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_MCR_NOTRDY_SHIFT))&CAN_MCR_NOTRDY_MASK)
  #define CAN_MCR_HALT_MASK                        0x10000000u
  #define CAN_MCR_HALT_SHIFT                       28
  #define CAN_MCR_HALT_WIDTH                       1
  #define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_HALT_SHIFT))&CAN_MCR_HALT_MASK)
  #define CAN_MCR_RFEN_MASK                        0x20000000u
  #define CAN_MCR_RFEN_SHIFT                       29
  #define CAN_MCR_RFEN_WIDTH                       1
  #define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_RFEN_SHIFT))&CAN_MCR_RFEN_MASK)
  #define CAN_MCR_FRZ_MASK                         0x40000000u
  #define CAN_MCR_FRZ_SHIFT                        30
  #define CAN_MCR_FRZ_WIDTH                        1
  #define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZ_SHIFT))&CAN_MCR_FRZ_MASK)
  #define CAN_MCR_MDIS_MASK                        0x80000000u
  #define CAN_MCR_MDIS_SHIFT                       31
  #define CAN_MCR_MDIS_WIDTH                       1
  #define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MDIS_SHIFT))&CAN_MCR_MDIS_MASK)
  /* CTRL1 Bit Fields */
  #define CAN_CTRL1_PROPSEG_MASK                   0x7u
  #define CAN_CTRL1_PROPSEG_SHIFT                  0
  #define CAN_CTRL1_PROPSEG_WIDTH                  3
  #define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
  #define CAN_CTRL1_LOM_MASK                       0x8u
  #define CAN_CTRL1_LOM_SHIFT                      3
  #define CAN_CTRL1_LOM_WIDTH                      1
  #define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LOM_SHIFT))&CAN_CTRL1_LOM_MASK)
  #define CAN_CTRL1_LBUF_MASK                      0x10u
  #define CAN_CTRL1_LBUF_SHIFT                     4
  #define CAN_CTRL1_LBUF_WIDTH                     1
  #define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LBUF_SHIFT))&CAN_CTRL1_LBUF_MASK)
  #define CAN_CTRL1_TSYN_MASK                      0x20u
  #define CAN_CTRL1_TSYN_SHIFT                     5
  #define CAN_CTRL1_TSYN_WIDTH                     1
  #define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TSYN_SHIFT))&CAN_CTRL1_TSYN_MASK)
  #define CAN_CTRL1_BOFFREC_MASK                   0x40u
  #define CAN_CTRL1_BOFFREC_SHIFT                  6
  #define CAN_CTRL1_BOFFREC_WIDTH                  1
  #define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFREC_SHIFT))&CAN_CTRL1_BOFFREC_MASK)
  #define CAN_CTRL1_SMP_MASK                       0x80u
  #define CAN_CTRL1_SMP_SHIFT                      7
  #define CAN_CTRL1_SMP_WIDTH                      1
  #define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_SMP_SHIFT))&CAN_CTRL1_SMP_MASK)
  #define CAN_CTRL1_RWRNMSK_MASK                   0x400u
  #define CAN_CTRL1_RWRNMSK_SHIFT                  10
  #define CAN_CTRL1_RWRNMSK_WIDTH                  1
  #define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RWRNMSK_SHIFT))&CAN_CTRL1_RWRNMSK_MASK)
  #define CAN_CTRL1_TWRNMSK_MASK                   0x800u
  #define CAN_CTRL1_TWRNMSK_SHIFT                  11
  #define CAN_CTRL1_TWRNMSK_WIDTH                  1
  #define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TWRNMSK_SHIFT))&CAN_CTRL1_TWRNMSK_MASK)
  #define CAN_CTRL1_LPB_MASK                       0x1000u
  #define CAN_CTRL1_LPB_SHIFT                      12
  #define CAN_CTRL1_LPB_WIDTH                      1
  #define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LPB_SHIFT))&CAN_CTRL1_LPB_MASK)
  #define CAN_CTRL1_CLKSRC_MASK                    0x2000u
  #define CAN_CTRL1_CLKSRC_SHIFT                   13
  #define CAN_CTRL1_CLKSRC_WIDTH                   1
  #define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_CLKSRC_SHIFT))&CAN_CTRL1_CLKSRC_MASK)
  #define CAN_CTRL1_ERRMSK_MASK                    0x4000u
  #define CAN_CTRL1_ERRMSK_SHIFT                   14
  #define CAN_CTRL1_ERRMSK_WIDTH                   1
  #define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_ERRMSK_SHIFT))&CAN_CTRL1_ERRMSK_MASK)
  #define CAN_CTRL1_BOFFMSK_MASK                   0x8000u
  #define CAN_CTRL1_BOFFMSK_SHIFT                  15
  #define CAN_CTRL1_BOFFMSK_WIDTH                  1
  #define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFMSK_SHIFT))&CAN_CTRL1_BOFFMSK_MASK)
  #define CAN_CTRL1_PSEG2_MASK                     0x70000u
  #define CAN_CTRL1_PSEG2_SHIFT                    16
  #define CAN_CTRL1_PSEG2_WIDTH                    3
  #define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
  #define CAN_CTRL1_PSEG1_MASK                     0x380000u
  #define CAN_CTRL1_PSEG1_SHIFT                    19
  #define CAN_CTRL1_PSEG1_WIDTH                    3
  #define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
  #define CAN_CTRL1_RJW_MASK                       0xC00000u
  #define CAN_CTRL1_RJW_SHIFT                      22
  #define CAN_CTRL1_RJW_WIDTH                      2
  #define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
  #define CAN_CTRL1_PRESDIV_MASK                   0xFF000000u
  #define CAN_CTRL1_PRESDIV_SHIFT                  24
  #define CAN_CTRL1_PRESDIV_WIDTH                  8
  #define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
  /* TIMER Bit Fields */
  #define CAN_TIMER_TIMER_MASK                     0xFFFFu
  #define CAN_TIMER_TIMER_SHIFT                    0
  #define CAN_TIMER_TIMER_WIDTH                    16
  #define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
  /* RXMGMASK Bit Fields */
  #define CAN_RXMGMASK_MG_MASK                     0xFFFFFFFFu
  #define CAN_RXMGMASK_MG_SHIFT                    0
  #define CAN_RXMGMASK_MG_WIDTH                    32
  #define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
  /* RX14MASK Bit Fields */
  #define CAN_RX14MASK_RX14M_MASK                  0xFFFFFFFFu
  #define CAN_RX14MASK_RX14M_SHIFT                 0
  #define CAN_RX14MASK_RX14M_WIDTH                 32
  #define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
  /* RX15MASK Bit Fields */
  #define CAN_RX15MASK_RX15M_MASK                  0xFFFFFFFFu
  #define CAN_RX15MASK_RX15M_SHIFT                 0
  #define CAN_RX15MASK_RX15M_WIDTH                 32
  #define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
  /* ECR Bit Fields */
  #define CAN_ECR_TXERRCNT_MASK                    0xFFu
  #define CAN_ECR_TXERRCNT_SHIFT                   0
  #define CAN_ECR_TXERRCNT_WIDTH                   8
  #define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
  #define CAN_ECR_RXERRCNT_MASK                    0xFF00u
  #define CAN_ECR_RXERRCNT_SHIFT                   8
  #define CAN_ECR_RXERRCNT_WIDTH                   8
  #define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
  /* ESR1 Bit Fields */
  #define CAN_ESR1_WAKINT_MASK                     0x1u
  #define CAN_ESR1_WAKINT_SHIFT                    0
  #define CAN_ESR1_WAKINT_WIDTH                    1
  #define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_WAKINT_SHIFT))&CAN_ESR1_WAKINT_MASK)
  #define CAN_ESR1_ERRINT_MASK                     0x2u
  #define CAN_ESR1_ERRINT_SHIFT                    1
  #define CAN_ESR1_ERRINT_WIDTH                    1
  #define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_SHIFT))&CAN_ESR1_ERRINT_MASK)
  #define CAN_ESR1_BOFFINT_MASK                    0x4u
  #define CAN_ESR1_BOFFINT_SHIFT                   2
  #define CAN_ESR1_BOFFINT_WIDTH                   1
  #define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFINT_SHIFT))&CAN_ESR1_BOFFINT_MASK)
  #define CAN_ESR1_RX_MASK                         0x8u
  #define CAN_ESR1_RX_SHIFT                        3
  #define CAN_ESR1_RX_WIDTH                        1
  #define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RX_SHIFT))&CAN_ESR1_RX_MASK)
  #define CAN_ESR1_FLTCONF_MASK                    0x30u
  #define CAN_ESR1_FLTCONF_SHIFT                   4
  #define CAN_ESR1_FLTCONF_WIDTH                   2
  #define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
  #define CAN_ESR1_TX_MASK                         0x40u
  #define CAN_ESR1_TX_SHIFT                        6
  #define CAN_ESR1_TX_WIDTH                        1
  #define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TX_SHIFT))&CAN_ESR1_TX_MASK)
  #define CAN_ESR1_IDLE_MASK                       0x80u
  #define CAN_ESR1_IDLE_SHIFT                      7
  #define CAN_ESR1_IDLE_WIDTH                      1
  #define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_IDLE_SHIFT))&CAN_ESR1_IDLE_MASK)
  #define CAN_ESR1_RXWRN_MASK                      0x100u
  #define CAN_ESR1_RXWRN_SHIFT                     8
  #define CAN_ESR1_RXWRN_WIDTH                     1
  #define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RXWRN_SHIFT))&CAN_ESR1_RXWRN_MASK)
  #define CAN_ESR1_TXWRN_MASK                      0x200u
  #define CAN_ESR1_TXWRN_SHIFT                     9
  #define CAN_ESR1_TXWRN_WIDTH                     1
  #define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TXWRN_SHIFT))&CAN_ESR1_TXWRN_MASK)
  #define CAN_ESR1_STFERR_MASK                     0x400u
  #define CAN_ESR1_STFERR_SHIFT                    10
  #define CAN_ESR1_STFERR_WIDTH                    1
  #define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_SHIFT))&CAN_ESR1_STFERR_MASK)
  #define CAN_ESR1_FRMERR_MASK                     0x800u
  #define CAN_ESR1_FRMERR_SHIFT                    11
  #define CAN_ESR1_FRMERR_WIDTH                    1
  #define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_SHIFT))&CAN_ESR1_FRMERR_MASK)
  #define CAN_ESR1_CRCERR_MASK                     0x1000u
  #define CAN_ESR1_CRCERR_SHIFT                    12
  #define CAN_ESR1_CRCERR_WIDTH                    1
  #define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_SHIFT))&CAN_ESR1_CRCERR_MASK)
  #define CAN_ESR1_ACKERR_MASK                     0x2000u
  #define CAN_ESR1_ACKERR_SHIFT                    13
  #define CAN_ESR1_ACKERR_WIDTH                    1
  #define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ACKERR_SHIFT))&CAN_ESR1_ACKERR_MASK)
  #define CAN_ESR1_BIT0ERR_MASK                    0x4000u
  #define CAN_ESR1_BIT0ERR_SHIFT                   14
  #define CAN_ESR1_BIT0ERR_WIDTH                   1
  #define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_SHIFT))&CAN_ESR1_BIT0ERR_MASK)
  #define CAN_ESR1_BIT1ERR_MASK                    0x8000u
  #define CAN_ESR1_BIT1ERR_SHIFT                   15
  #define CAN_ESR1_BIT1ERR_WIDTH                   1
  #define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_SHIFT))&CAN_ESR1_BIT1ERR_MASK)
  #define CAN_ESR1_RWRNINT_MASK                    0x10000u
  #define CAN_ESR1_RWRNINT_SHIFT                   16
  #define CAN_ESR1_RWRNINT_WIDTH                   1
  #define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RWRNINT_SHIFT))&CAN_ESR1_RWRNINT_MASK)
  #define CAN_ESR1_TWRNINT_MASK                    0x20000u
  #define CAN_ESR1_TWRNINT_SHIFT                   17
  #define CAN_ESR1_TWRNINT_WIDTH                   1
  #define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TWRNINT_SHIFT))&CAN_ESR1_TWRNINT_MASK)
  #define CAN_ESR1_SYNCH_MASK                      0x40000u
  #define CAN_ESR1_SYNCH_SHIFT                     18
  #define CAN_ESR1_SYNCH_WIDTH                     1
  #define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_SYNCH_SHIFT))&CAN_ESR1_SYNCH_MASK)
  #define CAN_ESR1_BOFFDONEINT_MASK                0x80000u
  #define CAN_ESR1_BOFFDONEINT_SHIFT               19
  #define CAN_ESR1_BOFFDONEINT_WIDTH               1
  #define CAN_ESR1_BOFFDONEINT(x)                  (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFDONEINT_SHIFT))&CAN_ESR1_BOFFDONEINT_MASK)
  #define CAN_ESR1_ERROVR_MASK                     0x200000u
  #define CAN_ESR1_ERROVR_SHIFT                    21
  #define CAN_ESR1_ERROVR_WIDTH                    1
  #define CAN_ESR1_ERROVR(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERROVR_SHIFT))&CAN_ESR1_ERROVR_MASK)
  /* IMASK1 Bit Fields */
  #define CAN_IMASK1_BUF31TO0M_MASK                0xFFFFFFFFu
  #define CAN_IMASK1_BUF31TO0M_SHIFT               0
  #define CAN_IMASK1_BUF31TO0M_WIDTH               32
  #define CAN_IMASK1_BUF31TO0M(x)                  (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUF31TO0M_SHIFT))&CAN_IMASK1_BUF31TO0M_MASK)
  /* IFLAG1 Bit Fields */
  #define CAN_IFLAG1_BUF0I_MASK                    0x1u
  #define CAN_IFLAG1_BUF0I_SHIFT                   0
  #define CAN_IFLAG1_BUF0I_WIDTH                   1
  #define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF0I_SHIFT))&CAN_IFLAG1_BUF0I_MASK)
  #define CAN_IFLAG1_BUF4TO1I_MASK                 0x1Eu
  #define CAN_IFLAG1_BUF4TO1I_SHIFT                1
  #define CAN_IFLAG1_BUF4TO1I_WIDTH                4
  #define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
  #define CAN_IFLAG1_BUF5I_MASK                    0x20u
  #define CAN_IFLAG1_BUF5I_SHIFT                   5
  #define CAN_IFLAG1_BUF5I_WIDTH                   1
  #define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF5I_SHIFT))&CAN_IFLAG1_BUF5I_MASK)
  #define CAN_IFLAG1_BUF6I_MASK                    0x40u
  #define CAN_IFLAG1_BUF6I_SHIFT                   6
  #define CAN_IFLAG1_BUF6I_WIDTH                   1
  #define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF6I_SHIFT))&CAN_IFLAG1_BUF6I_MASK)
  #define CAN_IFLAG1_BUF7I_MASK                    0x80u
  #define CAN_IFLAG1_BUF7I_SHIFT                   7
  #define CAN_IFLAG1_BUF7I_WIDTH                   1
  #define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF7I_SHIFT))&CAN_IFLAG1_BUF7I_MASK)
  #define CAN_IFLAG1_BUF31TO8I_MASK                0xFFFFFF00u
  #define CAN_IFLAG1_BUF31TO8I_SHIFT               8
  #define CAN_IFLAG1_BUF31TO8I_WIDTH               24
  #define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
  /* CTRL2 Bit Fields */
  #define CAN_CTRL2_EACEN_MASK                     0x10000u
  #define CAN_CTRL2_EACEN_SHIFT                    16
  #define CAN_CTRL2_EACEN_WIDTH                    1
  #define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EACEN_SHIFT))&CAN_CTRL2_EACEN_MASK)
  #define CAN_CTRL2_RRS_MASK                       0x20000u
  #define CAN_CTRL2_RRS_SHIFT                      17
  #define CAN_CTRL2_RRS_WIDTH                      1
  #define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RRS_SHIFT))&CAN_CTRL2_RRS_MASK)
  #define CAN_CTRL2_MRP_MASK                       0x40000u
  #define CAN_CTRL2_MRP_SHIFT                      18
  #define CAN_CTRL2_MRP_WIDTH                      1
  #define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_MRP_SHIFT))&CAN_CTRL2_MRP_MASK)
  #define CAN_CTRL2_TASD_MASK                      0xF80000u
  #define CAN_CTRL2_TASD_SHIFT                     19
  #define CAN_CTRL2_TASD_WIDTH                     5
  #define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
  #define CAN_CTRL2_RFFN_MASK                      0xF000000u
  #define CAN_CTRL2_RFFN_SHIFT                     24
  #define CAN_CTRL2_RFFN_WIDTH                     4
  #define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
  #define CAN_CTRL2_BOFFDONEMSK_MASK               0x40000000u
  #define CAN_CTRL2_BOFFDONEMSK_SHIFT              30
  #define CAN_CTRL2_BOFFDONEMSK_WIDTH              1
  #define CAN_CTRL2_BOFFDONEMSK(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_BOFFDONEMSK_SHIFT))&CAN_CTRL2_BOFFDONEMSK_MASK)
  /* ESR2 Bit Fields */
  #define CAN_ESR2_IMB_MASK                        0x2000u
  #define CAN_ESR2_IMB_SHIFT                       13
  #define CAN_ESR2_IMB_WIDTH                       1
  #define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_IMB_SHIFT))&CAN_ESR2_IMB_MASK)
  #define CAN_ESR2_VPS_MASK                        0x4000u
  #define CAN_ESR2_VPS_SHIFT                       14
  #define CAN_ESR2_VPS_WIDTH                       1
  #define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_VPS_SHIFT))&CAN_ESR2_VPS_MASK)
  #define CAN_ESR2_LPTM_MASK                       0x7F0000u
  #define CAN_ESR2_LPTM_SHIFT                      16
  #define CAN_ESR2_LPTM_WIDTH                      7
  #define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
  /* CRCR Bit Fields */
  #define CAN_CRCR_TXCRC_MASK                      0x7FFFu
  #define CAN_CRCR_TXCRC_SHIFT                     0
  #define CAN_CRCR_TXCRC_WIDTH                     15
  #define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
  #define CAN_CRCR_MBCRC_MASK                      0x7F0000u
  #define CAN_CRCR_MBCRC_SHIFT                     16
  #define CAN_CRCR_MBCRC_WIDTH                     7
  #define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
  /* RXFGMASK Bit Fields */
  #define CAN_RXFGMASK_FGM_MASK                    0xFFFFFFFFu
  #define CAN_RXFGMASK_FGM_SHIFT                   0
  #define CAN_RXFGMASK_FGM_WIDTH                   32
  #define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
  /* RXFIR Bit Fields */
  #define CAN_RXFIR_IDHIT_MASK                     0x1FFu
  #define CAN_RXFIR_IDHIT_SHIFT                    0
  #define CAN_RXFIR_IDHIT_WIDTH                    9
  #define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
  /* CBT Bit Fields */
  #define CAN_CBT_EPSEG2_MASK                      0x1Fu
  #define CAN_CBT_EPSEG2_SHIFT                     0
  #define CAN_CBT_EPSEG2_WIDTH                     5
  #define CAN_CBT_EPSEG2(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPSEG2_SHIFT))&CAN_CBT_EPSEG2_MASK)
  #define CAN_CBT_EPSEG1_MASK                      0x3E0u
  #define CAN_CBT_EPSEG1_SHIFT                     5
  #define CAN_CBT_EPSEG1_WIDTH                     5
  #define CAN_CBT_EPSEG1(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPSEG1_SHIFT))&CAN_CBT_EPSEG1_MASK)
  #define CAN_CBT_EPROPSEG_MASK                    0xFC00u
  #define CAN_CBT_EPROPSEG_SHIFT                   10
  #define CAN_CBT_EPROPSEG_WIDTH                   6
  #define CAN_CBT_EPROPSEG(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPROPSEG_SHIFT))&CAN_CBT_EPROPSEG_MASK)
  #define CAN_CBT_ERJW_MASK                        0xF0000u
  #define CAN_CBT_ERJW_SHIFT                       16
  #define CAN_CBT_ERJW_WIDTH                       4
  #define CAN_CBT_ERJW(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_CBT_ERJW_SHIFT))&CAN_CBT_ERJW_MASK)
  #define CAN_CBT_EPRESDIV_MASK                    0x7FE00000u
  #define CAN_CBT_EPRESDIV_SHIFT                   21
  #define CAN_CBT_EPRESDIV_WIDTH                   10
  #define CAN_CBT_EPRESDIV(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPRESDIV_SHIFT))&CAN_CBT_EPRESDIV_MASK)
  #define CAN_CBT_BTF_MASK                         0x80000000u
  #define CAN_CBT_BTF_SHIFT                        31
  #define CAN_CBT_BTF_WIDTH                        1
  #define CAN_CBT_BTF(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_CBT_BTF_SHIFT))&CAN_CBT_BTF_MASK)
  /* CS Bit Fields */
  #define CAN_CS_TIME_STAMP_MASK                   0xFFFFu
  #define CAN_CS_TIME_STAMP_SHIFT                  0
  #define CAN_CS_TIME_STAMP_WIDTH                  16
  #define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
  #define CAN_CS_DLC_MASK                          0xF0000u
  #define CAN_CS_DLC_SHIFT                         16
  #define CAN_CS_DLC_WIDTH                         4
  #define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
  #define CAN_CS_RTR_MASK                          0x100000u
  #define CAN_CS_RTR_SHIFT                         20
  #define CAN_CS_RTR_WIDTH                         1
  #define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_RTR_SHIFT))&CAN_CS_RTR_MASK)
  #define CAN_CS_IDE_MASK                          0x200000u
  #define CAN_CS_IDE_SHIFT                         21
  #define CAN_CS_IDE_WIDTH                         1
  #define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_IDE_SHIFT))&CAN_CS_IDE_MASK)
  #define CAN_CS_SRR_MASK                          0x400000u
  #define CAN_CS_SRR_SHIFT                         22
  #define CAN_CS_SRR_WIDTH                         1
  #define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_SRR_SHIFT))&CAN_CS_SRR_MASK)
  #define CAN_CS_CODE_MASK                         0xF000000u
  #define CAN_CS_CODE_SHIFT                        24
  #define CAN_CS_CODE_WIDTH                        4
  #define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
  /* ID Bit Fields */
  #define CAN_ID_EXT_MASK                          0x3FFFFu
  #define CAN_ID_EXT_SHIFT                         0
  #define CAN_ID_EXT_WIDTH                         18
  #define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
  #define CAN_ID_STD_MASK                          0x1FFC0000u
  #define CAN_ID_STD_SHIFT                         18
  #define CAN_ID_STD_WIDTH                         11
  #define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
  #define CAN_ID_PRIO_MASK                         0xE0000000u
  #define CAN_ID_PRIO_SHIFT                        29
  #define CAN_ID_PRIO_WIDTH                        3
  #define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
  /* WORD0 Bit Fields */
  #define CAN_WORD0_DATA_BYTE_3_MASK               0xFFu
  #define CAN_WORD0_DATA_BYTE_3_SHIFT              0
  #define CAN_WORD0_DATA_BYTE_3_WIDTH              8
  #define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
  #define CAN_WORD0_DATA_BYTE_2_MASK               0xFF00u
  #define CAN_WORD0_DATA_BYTE_2_SHIFT              8
  #define CAN_WORD0_DATA_BYTE_2_WIDTH              8
  #define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
  #define CAN_WORD0_DATA_BYTE_1_MASK               0xFF0000u
  #define CAN_WORD0_DATA_BYTE_1_SHIFT              16
  #define CAN_WORD0_DATA_BYTE_1_WIDTH              8
  #define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
  #define CAN_WORD0_DATA_BYTE_0_MASK               0xFF000000u
  #define CAN_WORD0_DATA_BYTE_0_SHIFT              24
  #define CAN_WORD0_DATA_BYTE_0_WIDTH              8
  #define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
  /* WORD1 Bit Fields */
  #define CAN_WORD1_DATA_BYTE_7_MASK               0xFFu
  #define CAN_WORD1_DATA_BYTE_7_SHIFT              0
  #define CAN_WORD1_DATA_BYTE_7_WIDTH              8
  #define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
  #define CAN_WORD1_DATA_BYTE_6_MASK               0xFF00u
  #define CAN_WORD1_DATA_BYTE_6_SHIFT              8
  #define CAN_WORD1_DATA_BYTE_6_WIDTH              8
  #define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
  #define CAN_WORD1_DATA_BYTE_5_MASK               0xFF0000u
  #define CAN_WORD1_DATA_BYTE_5_SHIFT              16
  #define CAN_WORD1_DATA_BYTE_5_WIDTH              8
  #define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
  #define CAN_WORD1_DATA_BYTE_4_MASK               0xFF000000u
  #define CAN_WORD1_DATA_BYTE_4_SHIFT              24
  #define CAN_WORD1_DATA_BYTE_4_WIDTH              8
  #define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
  /* RXIMR Bit Fields */
  #define CAN_RXIMR_MI_MASK                        0xFFFFFFFFu
  #define CAN_RXIMR_MI_SHIFT                       0
  #define CAN_RXIMR_MI_WIDTH                       32
  #define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
  
  /*!
   * @}
   */ /* end of group CAN_Register_Masks */
  
  
  /* CAN - Peripheral instance base addresses */
  /** Peripheral CAN0 base address */
  #define CAN0_BASE                                (0x40024000u)
  /** Peripheral CAN0 base pointer */
  #define CAN0                                     ((CAN_Type *)CAN0_BASE)
  #define CAN0_BASE_PTR                            (CAN0)
  /** Peripheral CAN1 base address */
  #define CAN1_BASE                                (0x40025000u)
  /** Peripheral CAN1 base pointer */
  #define CAN1                                     ((CAN_Type *)CAN1_BASE)
  #define CAN1_BASE_PTR                            (CAN1)
  /** Array initializer of CAN peripheral base addresses */
  #define CAN_BASE_ADDRS                           { CAN0_BASE, CAN1_BASE }
  /** Array initializer of CAN peripheral base pointers */
  #define CAN_BASE_PTRS                            { CAN0, CAN1 }
  
  /* ----------------------------------------------------------------------------
     -- CAN - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
   * @{
   */
  
  
  /* CAN - Register instance definitions */
  /* CAN0 */
  #define CAN0_MCR                                 CAN_MCR_REG(CAN0)
  #define CAN0_CTRL1                               CAN_CTRL1_REG(CAN0)
  #define CAN0_TIMER                               CAN_TIMER_REG(CAN0)
  #define CAN0_RXMGMASK                            CAN_RXMGMASK_REG(CAN0)
  #define CAN0_RX14MASK                            CAN_RX14MASK_REG(CAN0)
  #define CAN0_RX15MASK                            CAN_RX15MASK_REG(CAN0)
  #define CAN0_ECR                                 CAN_ECR_REG(CAN0)
  #define CAN0_ESR1                                CAN_ESR1_REG(CAN0)
  #define CAN0_IMASK1                              CAN_IMASK1_REG(CAN0)
  #define CAN0_IFLAG1                              CAN_IFLAG1_REG(CAN0)
  #define CAN0_CTRL2                               CAN_CTRL2_REG(CAN0)
  #define CAN0_ESR2                                CAN_ESR2_REG(CAN0)
  #define CAN0_CRCR                                CAN_CRCR_REG(CAN0)
  #define CAN0_RXFGMASK                            CAN_RXFGMASK_REG(CAN0)
  #define CAN0_RXFIR                               CAN_RXFIR_REG(CAN0)
  #define CAN0_CBT                                 CAN_CBT_REG(CAN0)
  #define CAN0_CS0                                 CAN_CS_REG(CAN0,0)
  #define CAN0_ID0                                 CAN_ID_REG(CAN0,0)
  #define CAN0_WORD00                              CAN_WORD0_REG(CAN0,0)
  #define CAN0_WORD10                              CAN_WORD1_REG(CAN0,0)
  #define CAN0_CS1                                 CAN_CS_REG(CAN0,1)
  #define CAN0_ID1                                 CAN_ID_REG(CAN0,1)
  #define CAN0_WORD01                              CAN_WORD0_REG(CAN0,1)
  #define CAN0_WORD11                              CAN_WORD1_REG(CAN0,1)
  #define CAN0_CS2                                 CAN_CS_REG(CAN0,2)
  #define CAN0_ID2                                 CAN_ID_REG(CAN0,2)
  #define CAN0_WORD02                              CAN_WORD0_REG(CAN0,2)
  #define CAN0_WORD12                              CAN_WORD1_REG(CAN0,2)
  #define CAN0_CS3                                 CAN_CS_REG(CAN0,3)
  #define CAN0_ID3                                 CAN_ID_REG(CAN0,3)
  #define CAN0_WORD03                              CAN_WORD0_REG(CAN0,3)
  #define CAN0_WORD13                              CAN_WORD1_REG(CAN0,3)
  #define CAN0_CS4                                 CAN_CS_REG(CAN0,4)
  #define CAN0_ID4                                 CAN_ID_REG(CAN0,4)
  #define CAN0_WORD04                              CAN_WORD0_REG(CAN0,4)
  #define CAN0_WORD14                              CAN_WORD1_REG(CAN0,4)
  #define CAN0_CS5                                 CAN_CS_REG(CAN0,5)
  #define CAN0_ID5                                 CAN_ID_REG(CAN0,5)
  #define CAN0_WORD05                              CAN_WORD0_REG(CAN0,5)
  #define CAN0_WORD15                              CAN_WORD1_REG(CAN0,5)
  #define CAN0_CS6                                 CAN_CS_REG(CAN0,6)
  #define CAN0_ID6                                 CAN_ID_REG(CAN0,6)
  #define CAN0_WORD06                              CAN_WORD0_REG(CAN0,6)
  #define CAN0_WORD16                              CAN_WORD1_REG(CAN0,6)
  #define CAN0_CS7                                 CAN_CS_REG(CAN0,7)
  #define CAN0_ID7                                 CAN_ID_REG(CAN0,7)
  #define CAN0_WORD07                              CAN_WORD0_REG(CAN0,7)
  #define CAN0_WORD17                              CAN_WORD1_REG(CAN0,7)
  #define CAN0_CS8                                 CAN_CS_REG(CAN0,8)
  #define CAN0_ID8                                 CAN_ID_REG(CAN0,8)
  #define CAN0_WORD08                              CAN_WORD0_REG(CAN0,8)
  #define CAN0_WORD18                              CAN_WORD1_REG(CAN0,8)
  #define CAN0_CS9                                 CAN_CS_REG(CAN0,9)
  #define CAN0_ID9                                 CAN_ID_REG(CAN0,9)
  #define CAN0_WORD09                              CAN_WORD0_REG(CAN0,9)
  #define CAN0_WORD19                              CAN_WORD1_REG(CAN0,9)
  #define CAN0_CS10                                CAN_CS_REG(CAN0,10)
  #define CAN0_ID10                                CAN_ID_REG(CAN0,10)
  #define CAN0_WORD010                             CAN_WORD0_REG(CAN0,10)
  #define CAN0_WORD110                             CAN_WORD1_REG(CAN0,10)
  #define CAN0_CS11                                CAN_CS_REG(CAN0,11)
  #define CAN0_ID11                                CAN_ID_REG(CAN0,11)
  #define CAN0_WORD011                             CAN_WORD0_REG(CAN0,11)
  #define CAN0_WORD111                             CAN_WORD1_REG(CAN0,11)
  #define CAN0_CS12                                CAN_CS_REG(CAN0,12)
  #define CAN0_ID12                                CAN_ID_REG(CAN0,12)
  #define CAN0_WORD012                             CAN_WORD0_REG(CAN0,12)
  #define CAN0_WORD112                             CAN_WORD1_REG(CAN0,12)
  #define CAN0_CS13                                CAN_CS_REG(CAN0,13)
  #define CAN0_ID13                                CAN_ID_REG(CAN0,13)
  #define CAN0_WORD013                             CAN_WORD0_REG(CAN0,13)
  #define CAN0_WORD113                             CAN_WORD1_REG(CAN0,13)
  #define CAN0_CS14                                CAN_CS_REG(CAN0,14)
  #define CAN0_ID14                                CAN_ID_REG(CAN0,14)
  #define CAN0_WORD014                             CAN_WORD0_REG(CAN0,14)
  #define CAN0_WORD114                             CAN_WORD1_REG(CAN0,14)
  #define CAN0_CS15                                CAN_CS_REG(CAN0,15)
  #define CAN0_ID15                                CAN_ID_REG(CAN0,15)
  #define CAN0_WORD015                             CAN_WORD0_REG(CAN0,15)
  #define CAN0_WORD115                             CAN_WORD1_REG(CAN0,15)
  #define CAN0_RXIMR0                              CAN_RXIMR_REG(CAN0,0)
  #define CAN0_RXIMR1                              CAN_RXIMR_REG(CAN0,1)
  #define CAN0_RXIMR2                              CAN_RXIMR_REG(CAN0,2)
  #define CAN0_RXIMR3                              CAN_RXIMR_REG(CAN0,3)
  #define CAN0_RXIMR4                              CAN_RXIMR_REG(CAN0,4)
  #define CAN0_RXIMR5                              CAN_RXIMR_REG(CAN0,5)
  #define CAN0_RXIMR6                              CAN_RXIMR_REG(CAN0,6)
  #define CAN0_RXIMR7                              CAN_RXIMR_REG(CAN0,7)
  #define CAN0_RXIMR8                              CAN_RXIMR_REG(CAN0,8)
  #define CAN0_RXIMR9                              CAN_RXIMR_REG(CAN0,9)
  #define CAN0_RXIMR10                             CAN_RXIMR_REG(CAN0,10)
  #define CAN0_RXIMR11                             CAN_RXIMR_REG(CAN0,11)
  #define CAN0_RXIMR12                             CAN_RXIMR_REG(CAN0,12)
  #define CAN0_RXIMR13                             CAN_RXIMR_REG(CAN0,13)
  #define CAN0_RXIMR14                             CAN_RXIMR_REG(CAN0,14)
  #define CAN0_RXIMR15                             CAN_RXIMR_REG(CAN0,15)
  /* CAN1 */
  #define CAN1_MCR                                 CAN_MCR_REG(CAN1)
  #define CAN1_CTRL1                               CAN_CTRL1_REG(CAN1)
  #define CAN1_TIMER                               CAN_TIMER_REG(CAN1)
  #define CAN1_RXMGMASK                            CAN_RXMGMASK_REG(CAN1)
  #define CAN1_RX14MASK                            CAN_RX14MASK_REG(CAN1)
  #define CAN1_RX15MASK                            CAN_RX15MASK_REG(CAN1)
  #define CAN1_ECR                                 CAN_ECR_REG(CAN1)
  #define CAN1_ESR1                                CAN_ESR1_REG(CAN1)
  #define CAN1_IMASK1                              CAN_IMASK1_REG(CAN1)
  #define CAN1_IFLAG1                              CAN_IFLAG1_REG(CAN1)
  #define CAN1_CTRL2                               CAN_CTRL2_REG(CAN1)
  #define CAN1_ESR2                                CAN_ESR2_REG(CAN1)
  #define CAN1_CRCR                                CAN_CRCR_REG(CAN1)
  #define CAN1_RXFGMASK                            CAN_RXFGMASK_REG(CAN1)
  #define CAN1_RXFIR                               CAN_RXFIR_REG(CAN1)
  #define CAN1_CBT                                 CAN_CBT_REG(CAN1)
  #define CAN1_CS0                                 CAN_CS_REG(CAN1,0)
  #define CAN1_ID0                                 CAN_ID_REG(CAN1,0)
  #define CAN1_WORD00                              CAN_WORD0_REG(CAN1,0)
  #define CAN1_WORD10                              CAN_WORD1_REG(CAN1,0)
  #define CAN1_CS1                                 CAN_CS_REG(CAN1,1)
  #define CAN1_ID1                                 CAN_ID_REG(CAN1,1)
  #define CAN1_WORD01                              CAN_WORD0_REG(CAN1,1)
  #define CAN1_WORD11                              CAN_WORD1_REG(CAN1,1)
  #define CAN1_CS2                                 CAN_CS_REG(CAN1,2)
  #define CAN1_ID2                                 CAN_ID_REG(CAN1,2)
  #define CAN1_WORD02                              CAN_WORD0_REG(CAN1,2)
  #define CAN1_WORD12                              CAN_WORD1_REG(CAN1,2)
  #define CAN1_CS3                                 CAN_CS_REG(CAN1,3)
  #define CAN1_ID3                                 CAN_ID_REG(CAN1,3)
  #define CAN1_WORD03                              CAN_WORD0_REG(CAN1,3)
  #define CAN1_WORD13                              CAN_WORD1_REG(CAN1,3)
  #define CAN1_CS4                                 CAN_CS_REG(CAN1,4)
  #define CAN1_ID4                                 CAN_ID_REG(CAN1,4)
  #define CAN1_WORD04                              CAN_WORD0_REG(CAN1,4)
  #define CAN1_WORD14                              CAN_WORD1_REG(CAN1,4)
  #define CAN1_CS5                                 CAN_CS_REG(CAN1,5)
  #define CAN1_ID5                                 CAN_ID_REG(CAN1,5)
  #define CAN1_WORD05                              CAN_WORD0_REG(CAN1,5)
  #define CAN1_WORD15                              CAN_WORD1_REG(CAN1,5)
  #define CAN1_CS6                                 CAN_CS_REG(CAN1,6)
  #define CAN1_ID6                                 CAN_ID_REG(CAN1,6)
  #define CAN1_WORD06                              CAN_WORD0_REG(CAN1,6)
  #define CAN1_WORD16                              CAN_WORD1_REG(CAN1,6)
  #define CAN1_CS7                                 CAN_CS_REG(CAN1,7)
  #define CAN1_ID7                                 CAN_ID_REG(CAN1,7)
  #define CAN1_WORD07                              CAN_WORD0_REG(CAN1,7)
  #define CAN1_WORD17                              CAN_WORD1_REG(CAN1,7)
  #define CAN1_CS8                                 CAN_CS_REG(CAN1,8)
  #define CAN1_ID8                                 CAN_ID_REG(CAN1,8)
  #define CAN1_WORD08                              CAN_WORD0_REG(CAN1,8)
  #define CAN1_WORD18                              CAN_WORD1_REG(CAN1,8)
  #define CAN1_CS9                                 CAN_CS_REG(CAN1,9)
  #define CAN1_ID9                                 CAN_ID_REG(CAN1,9)
  #define CAN1_WORD09                              CAN_WORD0_REG(CAN1,9)
  #define CAN1_WORD19                              CAN_WORD1_REG(CAN1,9)
  #define CAN1_CS10                                CAN_CS_REG(CAN1,10)
  #define CAN1_ID10                                CAN_ID_REG(CAN1,10)
  #define CAN1_WORD010                             CAN_WORD0_REG(CAN1,10)
  #define CAN1_WORD110                             CAN_WORD1_REG(CAN1,10)
  #define CAN1_CS11                                CAN_CS_REG(CAN1,11)
  #define CAN1_ID11                                CAN_ID_REG(CAN1,11)
  #define CAN1_WORD011                             CAN_WORD0_REG(CAN1,11)
  #define CAN1_WORD111                             CAN_WORD1_REG(CAN1,11)
  #define CAN1_CS12                                CAN_CS_REG(CAN1,12)
  #define CAN1_ID12                                CAN_ID_REG(CAN1,12)
  #define CAN1_WORD012                             CAN_WORD0_REG(CAN1,12)
  #define CAN1_WORD112                             CAN_WORD1_REG(CAN1,12)
  #define CAN1_CS13                                CAN_CS_REG(CAN1,13)
  #define CAN1_ID13                                CAN_ID_REG(CAN1,13)
  #define CAN1_WORD013                             CAN_WORD0_REG(CAN1,13)
  #define CAN1_WORD113                             CAN_WORD1_REG(CAN1,13)
  #define CAN1_CS14                                CAN_CS_REG(CAN1,14)
  #define CAN1_ID14                                CAN_ID_REG(CAN1,14)
  #define CAN1_WORD014                             CAN_WORD0_REG(CAN1,14)
  #define CAN1_WORD114                             CAN_WORD1_REG(CAN1,14)
  #define CAN1_CS15                                CAN_CS_REG(CAN1,15)
  #define CAN1_ID15                                CAN_ID_REG(CAN1,15)
  #define CAN1_WORD015                             CAN_WORD0_REG(CAN1,15)
  #define CAN1_WORD115                             CAN_WORD1_REG(CAN1,15)
  #define CAN1_RXIMR0                              CAN_RXIMR_REG(CAN1,0)
  #define CAN1_RXIMR1                              CAN_RXIMR_REG(CAN1,1)
  #define CAN1_RXIMR2                              CAN_RXIMR_REG(CAN1,2)
  #define CAN1_RXIMR3                              CAN_RXIMR_REG(CAN1,3)
  #define CAN1_RXIMR4                              CAN_RXIMR_REG(CAN1,4)
  #define CAN1_RXIMR5                              CAN_RXIMR_REG(CAN1,5)
  #define CAN1_RXIMR6                              CAN_RXIMR_REG(CAN1,6)
  #define CAN1_RXIMR7                              CAN_RXIMR_REG(CAN1,7)
  #define CAN1_RXIMR8                              CAN_RXIMR_REG(CAN1,8)
  #define CAN1_RXIMR9                              CAN_RXIMR_REG(CAN1,9)
  #define CAN1_RXIMR10                             CAN_RXIMR_REG(CAN1,10)
  #define CAN1_RXIMR11                             CAN_RXIMR_REG(CAN1,11)
  #define CAN1_RXIMR12                             CAN_RXIMR_REG(CAN1,12)
  #define CAN1_RXIMR13                             CAN_RXIMR_REG(CAN1,13)
  #define CAN1_RXIMR14                             CAN_RXIMR_REG(CAN1,14)
  #define CAN1_RXIMR15                             CAN_RXIMR_REG(CAN1,15)
  
  /* CAN - Register array accessors */
  #define CAN0_CS(index)                           CAN_CS_REG(CAN0,index)
  #define CAN1_CS(index)                           CAN_CS_REG(CAN1,index)
  #define CAN0_ID(index)                           CAN_ID_REG(CAN0,index)
  #define CAN1_ID(index)                           CAN_ID_REG(CAN1,index)
  #define CAN0_WORD0(index)                        CAN_WORD0_REG(CAN0,index)
  #define CAN1_WORD0(index)                        CAN_WORD0_REG(CAN1,index)
  #define CAN0_WORD1(index)                        CAN_WORD1_REG(CAN0,index)
  #define CAN1_WORD1(index)                        CAN_WORD1_REG(CAN1,index)
  #define CAN0_RXIMR(index)                        CAN_RXIMR_REG(CAN0,index)
  #define CAN1_RXIMR(index)                        CAN_RXIMR_REG(CAN1,index)
  
  /*!
   * @}
   */ /* end of group CAN_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group CAN_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- CMP Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
   * @{
   */
  
  /** CMP - Register Layout Typedef */
  typedef struct {
    __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
    __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
    __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
    __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
    __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
    __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
  } CMP_Type, *CMP_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- CMP - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
   * @{
   */
  
  
  /* CMP - Register accessors */
  #define CMP_CR0_REG(base)                        ((base)->CR0)
  #define CMP_CR1_REG(base)                        ((base)->CR1)
  #define CMP_FPR_REG(base)                        ((base)->FPR)
  #define CMP_SCR_REG(base)                        ((base)->SCR)
  #define CMP_DACCR_REG(base)                      ((base)->DACCR)
  #define CMP_MUXCR_REG(base)                      ((base)->MUXCR)
  
  /*!
   * @}
   */ /* end of group CMP_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- CMP Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CMP_Register_Masks CMP Register Masks
   * @{
   */
  
  /* CR0 Bit Fields */
  #define CMP_CR0_HYSTCTR_MASK                     0x3u
  #define CMP_CR0_HYSTCTR_SHIFT                    0
  #define CMP_CR0_HYSTCTR_WIDTH                    2
  #define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
  #define CMP_CR0_FILTER_CNT_MASK                  0x70u
  #define CMP_CR0_FILTER_CNT_SHIFT                 4
  #define CMP_CR0_FILTER_CNT_WIDTH                 3
  #define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
  /* CR1 Bit Fields */
  #define CMP_CR1_EN_MASK                          0x1u
  #define CMP_CR1_EN_SHIFT                         0
  #define CMP_CR1_EN_WIDTH                         1
  #define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_EN_SHIFT))&CMP_CR1_EN_MASK)
  #define CMP_CR1_OPE_MASK                         0x2u
  #define CMP_CR1_OPE_SHIFT                        1
  #define CMP_CR1_OPE_WIDTH                        1
  #define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_OPE_SHIFT))&CMP_CR1_OPE_MASK)
  #define CMP_CR1_COS_MASK                         0x4u
  #define CMP_CR1_COS_SHIFT                        2
  #define CMP_CR1_COS_WIDTH                        1
  #define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_COS_SHIFT))&CMP_CR1_COS_MASK)
  #define CMP_CR1_INV_MASK                         0x8u
  #define CMP_CR1_INV_SHIFT                        3
  #define CMP_CR1_INV_WIDTH                        1
  #define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_CR1_INV_SHIFT))&CMP_CR1_INV_MASK)
  #define CMP_CR1_PMODE_MASK                       0x10u
  #define CMP_CR1_PMODE_SHIFT                      4
  #define CMP_CR1_PMODE_WIDTH                      1
  #define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
  #define CMP_CR1_TRIGM_MASK                       0x20u
  #define CMP_CR1_TRIGM_SHIFT                      5
  #define CMP_CR1_TRIGM_WIDTH                      1
  #define CMP_CR1_TRIGM(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_CR1_TRIGM_SHIFT))&CMP_CR1_TRIGM_MASK)
  #define CMP_CR1_WE_MASK                          0x40u
  #define CMP_CR1_WE_SHIFT                         6
  #define CMP_CR1_WE_WIDTH                         1
  #define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_WE_SHIFT))&CMP_CR1_WE_MASK)
  #define CMP_CR1_SE_MASK                          0x80u
  #define CMP_CR1_SE_SHIFT                         7
  #define CMP_CR1_SE_WIDTH                         1
  #define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x))<<CMP_CR1_SE_SHIFT))&CMP_CR1_SE_MASK)
  /* FPR Bit Fields */
  #define CMP_FPR_FILT_PER_MASK                    0xFFu
  #define CMP_FPR_FILT_PER_SHIFT                   0
  #define CMP_FPR_FILT_PER_WIDTH                   8
  #define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
  /* SCR Bit Fields */
  #define CMP_SCR_COUT_MASK                        0x1u
  #define CMP_SCR_COUT_SHIFT                       0
  #define CMP_SCR_COUT_WIDTH                       1
  #define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x))<<CMP_SCR_COUT_SHIFT))&CMP_SCR_COUT_MASK)
  #define CMP_SCR_CFF_MASK                         0x2u
  #define CMP_SCR_CFF_SHIFT                        1
  #define CMP_SCR_CFF_WIDTH                        1
  #define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFF_SHIFT))&CMP_SCR_CFF_MASK)
  #define CMP_SCR_CFR_MASK                         0x4u
  #define CMP_SCR_CFR_SHIFT                        2
  #define CMP_SCR_CFR_WIDTH                        1
  #define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
  #define CMP_SCR_IEF_MASK                         0x8u
  #define CMP_SCR_IEF_SHIFT                        3
  #define CMP_SCR_IEF_WIDTH                        1
  #define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IEF_SHIFT))&CMP_SCR_IEF_MASK)
  #define CMP_SCR_IER_MASK                         0x10u
  #define CMP_SCR_IER_SHIFT                        4
  #define CMP_SCR_IER_WIDTH                        1
  #define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x))<<CMP_SCR_IER_SHIFT))&CMP_SCR_IER_MASK)
  #define CMP_SCR_DMAEN_MASK                       0x40u
  #define CMP_SCR_DMAEN_SHIFT                      6
  #define CMP_SCR_DMAEN_WIDTH                      1
  #define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x))<<CMP_SCR_DMAEN_SHIFT))&CMP_SCR_DMAEN_MASK)
  /* DACCR Bit Fields */
  #define CMP_DACCR_VOSEL_MASK                     0x3Fu
  #define CMP_DACCR_VOSEL_SHIFT                    0
  #define CMP_DACCR_VOSEL_WIDTH                    6
  #define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
  #define CMP_DACCR_VRSEL_MASK                     0x40u
  #define CMP_DACCR_VRSEL_SHIFT                    6
  #define CMP_DACCR_VRSEL_WIDTH                    1
  #define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
  #define CMP_DACCR_DACEN_MASK                     0x80u
  #define CMP_DACCR_DACEN_SHIFT                    7
  #define CMP_DACCR_DACEN_WIDTH                    1
  #define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
  /* MUXCR Bit Fields */
  #define CMP_MUXCR_MSEL_MASK                      0x7u
  #define CMP_MUXCR_MSEL_SHIFT                     0
  #define CMP_MUXCR_MSEL_WIDTH                     3
  #define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
  #define CMP_MUXCR_PSEL_MASK                      0x38u
  #define CMP_MUXCR_PSEL_SHIFT                     3
  #define CMP_MUXCR_PSEL_WIDTH                     3
  #define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
  
  /*!
   * @}
   */ /* end of group CMP_Register_Masks */
  
  
  /* CMP - Peripheral instance base addresses */
  /** Peripheral CMP0 base address */
  #define CMP0_BASE                                (0x40073000u)
  /** Peripheral CMP0 base pointer */
  #define CMP0                                     ((CMP_Type *)CMP0_BASE)
  #define CMP0_BASE_PTR                            (CMP0)
  /** Array initializer of CMP peripheral base addresses */
  #define CMP_BASE_ADDRS                           { CMP0_BASE }
  /** Array initializer of CMP peripheral base pointers */
  #define CMP_BASE_PTRS                            { CMP0 }
  
  /* ----------------------------------------------------------------------------
     -- CMP - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
   * @{
   */
  
  
  /* CMP - Register instance definitions */
  /* CMP0 */
  #define CMP0_CR0                                 CMP_CR0_REG(CMP0)
  #define CMP0_CR1                                 CMP_CR1_REG(CMP0)
  #define CMP0_FPR                                 CMP_FPR_REG(CMP0)
  #define CMP0_SCR                                 CMP_SCR_REG(CMP0)
  #define CMP0_DACCR                               CMP_DACCR_REG(CMP0)
  #define CMP0_MUXCR                               CMP_MUXCR_REG(CMP0)
  
  /*!
   * @}
   */ /* end of group CMP_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group CMP_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- CRC Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
   * @{
   */
  
  /** CRC - Register Layout Typedef */
  typedef struct {
    union {                                          /* offset: 0x0 */
      struct {                                         /* offset: 0x0 */
        __IO uint16_t DATAL;                             /**< CRC_DATAL register., offset: 0x0 */
        __IO uint16_t DATAH;                             /**< CRC_DATAH register., offset: 0x2 */
      } ACCESS16BIT;
      __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
      struct {                                         /* offset: 0x0 */
        __IO uint8_t DATALL;                             /**< CRC_DATALL register., offset: 0x0 */
        __IO uint8_t DATALU;                             /**< CRC_DATALU register., offset: 0x1 */
        __IO uint8_t DATAHL;                             /**< CRC_DATAHL register., offset: 0x2 */
        __IO uint8_t DATAHU;                             /**< CRC_DATAHU register., offset: 0x3 */
      } ACCESS8BIT;
    };
    union {                                          /* offset: 0x4 */
      struct {                                         /* offset: 0x4 */
        __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register., offset: 0x4 */
        __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register., offset: 0x6 */
      } GPOLY_ACCESS16BIT;
      __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
      struct {                                         /* offset: 0x4 */
        __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register., offset: 0x4 */
        __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register., offset: 0x5 */
        __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register., offset: 0x6 */
        __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register., offset: 0x7 */
      } GPOLY_ACCESS8BIT;
    };
    union {                                          /* offset: 0x8 */
      __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
      struct {                                         /* offset: 0x8 */
             uint8_t RESERVED_0[3];
        __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
      } CTRL_ACCESS8BIT;
    };
  } CRC_Type, *CRC_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- CRC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
   * @{
   */
  
  
  /* CRC - Register accessors */
  #define CRC_DATAL_REG(base)                      ((base)->ACCESS16BIT.DATAL)
  #define CRC_DATAH_REG(base)                      ((base)->ACCESS16BIT.DATAH)
  #define CRC_DATA_REG(base)                       ((base)->DATA)
  #define CRC_DATALL_REG(base)                     ((base)->ACCESS8BIT.DATALL)
  #define CRC_DATALU_REG(base)                     ((base)->ACCESS8BIT.DATALU)
  #define CRC_DATAHL_REG(base)                     ((base)->ACCESS8BIT.DATAHL)
  #define CRC_DATAHU_REG(base)                     ((base)->ACCESS8BIT.DATAHU)
  #define CRC_GPOLYL_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYL)
  #define CRC_GPOLYH_REG(base)                     ((base)->GPOLY_ACCESS16BIT.GPOLYH)
  #define CRC_GPOLY_REG(base)                      ((base)->GPOLY)
  #define CRC_GPOLYLL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
  #define CRC_GPOLYLU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
  #define CRC_GPOLYHL_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
  #define CRC_GPOLYHU_REG(base)                    ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
  #define CRC_CTRL_REG(base)                       ((base)->CTRL)
  #define CRC_CTRLHU_REG(base)                     ((base)->CTRL_ACCESS8BIT.CTRLHU)
  
  /*!
   * @}
   */ /* end of group CRC_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- CRC Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CRC_Register_Masks CRC Register Masks
   * @{
   */
  
  /* DATAL Bit Fields */
  #define CRC_DATAL_DATAL_MASK                     0xFFFFu
  #define CRC_DATAL_DATAL_SHIFT                    0
  #define CRC_DATAL_DATAL_WIDTH                    16
  #define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
  /* DATAH Bit Fields */
  #define CRC_DATAH_DATAH_MASK                     0xFFFFu
  #define CRC_DATAH_DATAH_SHIFT                    0
  #define CRC_DATAH_DATAH_WIDTH                    16
  #define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
  /* DATA Bit Fields */
  #define CRC_DATA_LL_MASK                         0xFFu
  #define CRC_DATA_LL_SHIFT                        0
  #define CRC_DATA_LL_WIDTH                        8
  #define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
  #define CRC_DATA_LU_MASK                         0xFF00u
  #define CRC_DATA_LU_SHIFT                        8
  #define CRC_DATA_LU_WIDTH                        8
  #define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
  #define CRC_DATA_HL_MASK                         0xFF0000u
  #define CRC_DATA_HL_SHIFT                        16
  #define CRC_DATA_HL_WIDTH                        8
  #define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
  #define CRC_DATA_HU_MASK                         0xFF000000u
  #define CRC_DATA_HU_SHIFT                        24
  #define CRC_DATA_HU_WIDTH                        8
  #define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
  /* DATALL Bit Fields */
  #define CRC_DATALL_DATALL_MASK                   0xFFu
  #define CRC_DATALL_DATALL_SHIFT                  0
  #define CRC_DATALL_DATALL_WIDTH                  8
  #define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
  /* DATALU Bit Fields */
  #define CRC_DATALU_DATALU_MASK                   0xFFu
  #define CRC_DATALU_DATALU_SHIFT                  0
  #define CRC_DATALU_DATALU_WIDTH                  8
  #define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
  /* DATAHL Bit Fields */
  #define CRC_DATAHL_DATAHL_MASK                   0xFFu
  #define CRC_DATAHL_DATAHL_SHIFT                  0
  #define CRC_DATAHL_DATAHL_WIDTH                  8
  #define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
  /* DATAHU Bit Fields */
  #define CRC_DATAHU_DATAHU_MASK                   0xFFu
  #define CRC_DATAHU_DATAHU_SHIFT                  0
  #define CRC_DATAHU_DATAHU_WIDTH                  8
  #define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
  /* GPOLYL Bit Fields */
  #define CRC_GPOLYL_GPOLYL_MASK                   0xFFFFu
  #define CRC_GPOLYL_GPOLYL_SHIFT                  0
  #define CRC_GPOLYL_GPOLYL_WIDTH                  16
  #define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
  /* GPOLYH Bit Fields */
  #define CRC_GPOLYH_GPOLYH_MASK                   0xFFFFu
  #define CRC_GPOLYH_GPOLYH_SHIFT                  0
  #define CRC_GPOLYH_GPOLYH_WIDTH                  16
  #define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
  /* GPOLY Bit Fields */
  #define CRC_GPOLY_LOW_MASK                       0xFFFFu
  #define CRC_GPOLY_LOW_SHIFT                      0
  #define CRC_GPOLY_LOW_WIDTH                      16
  #define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
  #define CRC_GPOLY_HIGH_MASK                      0xFFFF0000u
  #define CRC_GPOLY_HIGH_SHIFT                     16
  #define CRC_GPOLY_HIGH_WIDTH                     16
  #define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
  /* GPOLYLL Bit Fields */
  #define CRC_GPOLYLL_GPOLYLL_MASK                 0xFFu
  #define CRC_GPOLYLL_GPOLYLL_SHIFT                0
  #define CRC_GPOLYLL_GPOLYLL_WIDTH                8
  #define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
  /* GPOLYLU Bit Fields */
  #define CRC_GPOLYLU_GPOLYLU_MASK                 0xFFu
  #define CRC_GPOLYLU_GPOLYLU_SHIFT                0
  #define CRC_GPOLYLU_GPOLYLU_WIDTH                8
  #define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
  /* GPOLYHL Bit Fields */
  #define CRC_GPOLYHL_GPOLYHL_MASK                 0xFFu
  #define CRC_GPOLYHL_GPOLYHL_SHIFT                0
  #define CRC_GPOLYHL_GPOLYHL_WIDTH                8
  #define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
  /* GPOLYHU Bit Fields */
  #define CRC_GPOLYHU_GPOLYHU_MASK                 0xFFu
  #define CRC_GPOLYHU_GPOLYHU_SHIFT                0
  #define CRC_GPOLYHU_GPOLYHU_WIDTH                8
  #define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
  /* CTRL Bit Fields */
  #define CRC_CTRL_TCRC_MASK                       0x1000000u
  #define CRC_CTRL_TCRC_SHIFT                      24
  #define CRC_CTRL_TCRC_WIDTH                      1
  #define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
  #define CRC_CTRL_WAS_MASK                        0x2000000u
  #define CRC_CTRL_WAS_SHIFT                       25
  #define CRC_CTRL_WAS_WIDTH                       1
  #define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
  #define CRC_CTRL_FXOR_MASK                       0x4000000u
  #define CRC_CTRL_FXOR_SHIFT                      26
  #define CRC_CTRL_FXOR_WIDTH                      1
  #define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
  #define CRC_CTRL_TOTR_MASK                       0x30000000u
  #define CRC_CTRL_TOTR_SHIFT                      28
  #define CRC_CTRL_TOTR_WIDTH                      2
  #define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
  #define CRC_CTRL_TOT_MASK                        0xC0000000u
  #define CRC_CTRL_TOT_SHIFT                       30
  #define CRC_CTRL_TOT_WIDTH                       2
  #define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
  /* CTRLHU Bit Fields */
  #define CRC_CTRLHU_TCRC_MASK                     0x1u
  #define CRC_CTRLHU_TCRC_SHIFT                    0
  #define CRC_CTRLHU_TCRC_WIDTH                    1
  #define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TCRC_SHIFT))&CRC_CTRLHU_TCRC_MASK)
  #define CRC_CTRLHU_WAS_MASK                      0x2u
  #define CRC_CTRLHU_WAS_SHIFT                     1
  #define CRC_CTRLHU_WAS_WIDTH                     1
  #define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_WAS_SHIFT))&CRC_CTRLHU_WAS_MASK)
  #define CRC_CTRLHU_FXOR_MASK                     0x4u
  #define CRC_CTRLHU_FXOR_SHIFT                    2
  #define CRC_CTRLHU_FXOR_WIDTH                    1
  #define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_FXOR_SHIFT))&CRC_CTRLHU_FXOR_MASK)
  #define CRC_CTRLHU_TOTR_MASK                     0x30u
  #define CRC_CTRLHU_TOTR_SHIFT                    4
  #define CRC_CTRLHU_TOTR_WIDTH                    2
  #define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
  #define CRC_CTRLHU_TOT_MASK                      0xC0u
  #define CRC_CTRLHU_TOT_SHIFT                     6
  #define CRC_CTRLHU_TOT_WIDTH                     2
  #define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
  
  /*!
   * @}
   */ /* end of group CRC_Register_Masks */
  
  
  /* CRC - Peripheral instance base addresses */
  /** Peripheral CRC base address */
  #define CRC_BASE                                 (0x40032000u)
  /** Peripheral CRC base pointer */
  #define CRC0                                     ((CRC_Type *)CRC_BASE)
  #define CRC_BASE_PTR                             (CRC0)
  /** Array initializer of CRC peripheral base addresses */
  #define CRC_BASE_ADDRS                           { CRC_BASE }
  /** Array initializer of CRC peripheral base pointers */
  #define CRC_BASE_PTRS                            { CRC0 }
  
  /* ----------------------------------------------------------------------------
     -- CRC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
   * @{
   */
  
  
  /* CRC - Register instance definitions */
  /* CRC */
  #define CRC_DATA                                 CRC_DATA_REG(CRC0)
  #define CRC_DATAL                                CRC_DATAL_REG(CRC0)
  #define CRC_DATALL                               CRC_DATALL_REG(CRC0)
  #define CRC_DATALU                               CRC_DATALU_REG(CRC0)
  #define CRC_DATAH                                CRC_DATAH_REG(CRC0)
  #define CRC_DATAHL                               CRC_DATAHL_REG(CRC0)
  #define CRC_DATAHU                               CRC_DATAHU_REG(CRC0)
  #define CRC_GPOLY                                CRC_GPOLY_REG(CRC0)
  #define CRC_GPOLYL                               CRC_GPOLYL_REG(CRC0)
  #define CRC_GPOLYLL                              CRC_GPOLYLL_REG(CRC0)
  #define CRC_GPOLYLU                              CRC_GPOLYLU_REG(CRC0)
  #define CRC_GPOLYH                               CRC_GPOLYH_REG(CRC0)
  #define CRC_GPOLYHL                              CRC_GPOLYHL_REG(CRC0)
  #define CRC_GPOLYHU                              CRC_GPOLYHU_REG(CRC0)
  #define CRC_CTRL                                 CRC_CTRL_REG(CRC0)
  #define CRC_CTRLHU                               CRC_CTRLHU_REG(CRC0)
  
  /*!
   * @}
   */ /* end of group CRC_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group CRC_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- DAC Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
   * @{
   */
  
  /** DAC - Register Layout Typedef */
  typedef struct {
    struct {                                         /* offset: 0x0, array step: 0x2 */
      __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
      __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
    } DAT[16];
    __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
    __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
    __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
    __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
  } DAC_Type, *DAC_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- DAC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
   * @{
   */
  
  
  /* DAC - Register accessors */
  #define DAC_DATL_REG(base,index)                 ((base)->DAT[index].DATL)
  #define DAC_DATL_COUNT                           16
  #define DAC_DATH_REG(base,index)                 ((base)->DAT[index].DATH)
  #define DAC_DATH_COUNT                           16
  #define DAC_SR_REG(base)                         ((base)->SR)
  #define DAC_C0_REG(base)                         ((base)->C0)
  #define DAC_C1_REG(base)                         ((base)->C1)
  #define DAC_C2_REG(base)                         ((base)->C2)
  
  /*!
   * @}
   */ /* end of group DAC_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- DAC Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DAC_Register_Masks DAC Register Masks
   * @{
   */
  
  /* DATL Bit Fields */
  #define DAC_DATL_DATA0_MASK                      0xFFu
  #define DAC_DATL_DATA0_SHIFT                     0
  #define DAC_DATL_DATA0_WIDTH                     8
  #define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
  /* DATH Bit Fields */
  #define DAC_DATH_DATA1_MASK                      0xFu
  #define DAC_DATH_DATA1_SHIFT                     0
  #define DAC_DATH_DATA1_WIDTH                     4
  #define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
  /* SR Bit Fields */
  #define DAC_SR_DACBFRPBF_MASK                    0x1u
  #define DAC_SR_DACBFRPBF_SHIFT                   0
  #define DAC_SR_DACBFRPBF_WIDTH                   1
  #define DAC_SR_DACBFRPBF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPBF_SHIFT))&DAC_SR_DACBFRPBF_MASK)
  #define DAC_SR_DACBFRPTF_MASK                    0x2u
  #define DAC_SR_DACBFRPTF_SHIFT                   1
  #define DAC_SR_DACBFRPTF_WIDTH                   1
  #define DAC_SR_DACBFRPTF(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFRPTF_SHIFT))&DAC_SR_DACBFRPTF_MASK)
  #define DAC_SR_DACBFWMF_MASK                     0x4u
  #define DAC_SR_DACBFWMF_SHIFT                    2
  #define DAC_SR_DACBFWMF_WIDTH                    1
  #define DAC_SR_DACBFWMF(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_SR_DACBFWMF_SHIFT))&DAC_SR_DACBFWMF_MASK)
  /* C0 Bit Fields */
  #define DAC_C0_DACBBIEN_MASK                     0x1u
  #define DAC_C0_DACBBIEN_SHIFT                    0
  #define DAC_C0_DACBBIEN_WIDTH                    1
  #define DAC_C0_DACBBIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBBIEN_SHIFT))&DAC_C0_DACBBIEN_MASK)
  #define DAC_C0_DACBTIEN_MASK                     0x2u
  #define DAC_C0_DACBTIEN_SHIFT                    1
  #define DAC_C0_DACBTIEN_WIDTH                    1
  #define DAC_C0_DACBTIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBTIEN_SHIFT))&DAC_C0_DACBTIEN_MASK)
  #define DAC_C0_DACBWIEN_MASK                     0x4u
  #define DAC_C0_DACBWIEN_SHIFT                    2
  #define DAC_C0_DACBWIEN_WIDTH                    1
  #define DAC_C0_DACBWIEN(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACBWIEN_SHIFT))&DAC_C0_DACBWIEN_MASK)
  #define DAC_C0_LPEN_MASK                         0x8u
  #define DAC_C0_LPEN_SHIFT                        3
  #define DAC_C0_LPEN_WIDTH                        1
  #define DAC_C0_LPEN(x)                           (((uint8_t)(((uint8_t)(x))<<DAC_C0_LPEN_SHIFT))&DAC_C0_LPEN_MASK)
  #define DAC_C0_DACSWTRG_MASK                     0x10u
  #define DAC_C0_DACSWTRG_SHIFT                    4
  #define DAC_C0_DACSWTRG_WIDTH                    1
  #define DAC_C0_DACSWTRG(x)                       (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACSWTRG_SHIFT))&DAC_C0_DACSWTRG_MASK)
  #define DAC_C0_DACTRGSEL_MASK                    0x20u
  #define DAC_C0_DACTRGSEL_SHIFT                   5
  #define DAC_C0_DACTRGSEL_WIDTH                   1
  #define DAC_C0_DACTRGSEL(x)                      (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACTRGSEL_SHIFT))&DAC_C0_DACTRGSEL_MASK)
  #define DAC_C0_DACRFS_MASK                       0x40u
  #define DAC_C0_DACRFS_SHIFT                      6
  #define DAC_C0_DACRFS_WIDTH                      1
  #define DAC_C0_DACRFS(x)                         (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACRFS_SHIFT))&DAC_C0_DACRFS_MASK)
  #define DAC_C0_DACEN_MASK                        0x80u
  #define DAC_C0_DACEN_SHIFT                       7
  #define DAC_C0_DACEN_WIDTH                       1
  #define DAC_C0_DACEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C0_DACEN_SHIFT))&DAC_C0_DACEN_MASK)
  /* C1 Bit Fields */
  #define DAC_C1_DACBFEN_MASK                      0x1u
  #define DAC_C1_DACBFEN_SHIFT                     0
  #define DAC_C1_DACBFEN_WIDTH                     1
  #define DAC_C1_DACBFEN(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFEN_SHIFT))&DAC_C1_DACBFEN_MASK)
  #define DAC_C1_DACBFMD_MASK                      0x6u
  #define DAC_C1_DACBFMD_SHIFT                     1
  #define DAC_C1_DACBFMD_WIDTH                     2
  #define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
  #define DAC_C1_DACBFWM_MASK                      0x18u
  #define DAC_C1_DACBFWM_SHIFT                     3
  #define DAC_C1_DACBFWM_WIDTH                     2
  #define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
  #define DAC_C1_DMAEN_MASK                        0x80u
  #define DAC_C1_DMAEN_SHIFT                       7
  #define DAC_C1_DMAEN_WIDTH                       1
  #define DAC_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x))<<DAC_C1_DMAEN_SHIFT))&DAC_C1_DMAEN_MASK)
  /* C2 Bit Fields */
  #define DAC_C2_DACBFUP_MASK                      0xFu
  #define DAC_C2_DACBFUP_SHIFT                     0
  #define DAC_C2_DACBFUP_WIDTH                     4
  #define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
  #define DAC_C2_DACBFRP_MASK                      0xF0u
  #define DAC_C2_DACBFRP_SHIFT                     4
  #define DAC_C2_DACBFRP_WIDTH                     4
  #define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
  
  /*!
   * @}
   */ /* end of group DAC_Register_Masks */
  
  
  /* DAC - Peripheral instance base addresses */
  /** Peripheral DAC0 base address */
  #define DAC0_BASE                                (0x4003F000u)
  /** Peripheral DAC0 base pointer */
  #define DAC0                                     ((DAC_Type *)DAC0_BASE)
  #define DAC0_BASE_PTR                            (DAC0)
  /** Array initializer of DAC peripheral base addresses */
  #define DAC_BASE_ADDRS                           { DAC0_BASE }
  /** Array initializer of DAC peripheral base pointers */
  #define DAC_BASE_PTRS                            { DAC0 }
  
  /* ----------------------------------------------------------------------------
     -- DAC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
   * @{
   */
  
  
  /* DAC - Register instance definitions */
  /* DAC0 */
  #define DAC0_DAT0L                               DAC_DATL_REG(DAC0,0)
  #define DAC0_DAT0H                               DAC_DATH_REG(DAC0,0)
  #define DAC0_DAT1L                               DAC_DATL_REG(DAC0,1)
  #define DAC0_DAT1H                               DAC_DATH_REG(DAC0,1)
  #define DAC0_DAT2L                               DAC_DATL_REG(DAC0,2)
  #define DAC0_DAT2H                               DAC_DATH_REG(DAC0,2)
  #define DAC0_DAT3L                               DAC_DATL_REG(DAC0,3)
  #define DAC0_DAT3H                               DAC_DATH_REG(DAC0,3)
  #define DAC0_DAT4L                               DAC_DATL_REG(DAC0,4)
  #define DAC0_DAT4H                               DAC_DATH_REG(DAC0,4)
  #define DAC0_DAT5L                               DAC_DATL_REG(DAC0,5)
  #define DAC0_DAT5H                               DAC_DATH_REG(DAC0,5)
  #define DAC0_DAT6L                               DAC_DATL_REG(DAC0,6)
  #define DAC0_DAT6H                               DAC_DATH_REG(DAC0,6)
  #define DAC0_DAT7L                               DAC_DATL_REG(DAC0,7)
  #define DAC0_DAT7H                               DAC_DATH_REG(DAC0,7)
  #define DAC0_DAT8L                               DAC_DATL_REG(DAC0,8)
  #define DAC0_DAT8H                               DAC_DATH_REG(DAC0,8)
  #define DAC0_DAT9L                               DAC_DATL_REG(DAC0,9)
  #define DAC0_DAT9H                               DAC_DATH_REG(DAC0,9)
  #define DAC0_DAT10L                              DAC_DATL_REG(DAC0,10)
  #define DAC0_DAT10H                              DAC_DATH_REG(DAC0,10)
  #define DAC0_DAT11L                              DAC_DATL_REG(DAC0,11)
  #define DAC0_DAT11H                              DAC_DATH_REG(DAC0,11)
  #define DAC0_DAT12L                              DAC_DATL_REG(DAC0,12)
  #define DAC0_DAT12H                              DAC_DATH_REG(DAC0,12)
  #define DAC0_DAT13L                              DAC_DATL_REG(DAC0,13)
  #define DAC0_DAT13H                              DAC_DATH_REG(DAC0,13)
  #define DAC0_DAT14L                              DAC_DATL_REG(DAC0,14)
  #define DAC0_DAT14H                              DAC_DATH_REG(DAC0,14)
  #define DAC0_DAT15L                              DAC_DATL_REG(DAC0,15)
  #define DAC0_DAT15H                              DAC_DATH_REG(DAC0,15)
  #define DAC0_SR                                  DAC_SR_REG(DAC0)
  #define DAC0_C0                                  DAC_C0_REG(DAC0)
  #define DAC0_C1                                  DAC_C1_REG(DAC0)
  #define DAC0_C2                                  DAC_C2_REG(DAC0)
  
  /* DAC - Register array accessors */
  #define DAC0_DATL(index)                         DAC_DATL_REG(DAC0,index)
  #define DAC0_DATH(index)                         DAC_DATH_REG(DAC0,index)
  
  /*!
   * @}
   */ /* end of group DAC_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group DAC_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- DMA Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
   * @{
   */
  
  /** DMA - Register Layout Typedef */
  typedef struct {
    __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
    __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
         uint8_t RESERVED_0[4];
    __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
         uint8_t RESERVED_1[4];
    __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
    __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
    __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
    __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
    __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
    __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
    __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
    __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
    __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
         uint8_t RESERVED_2[4];
    __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
         uint8_t RESERVED_3[4];
    __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
         uint8_t RESERVED_4[4];
    __I  uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
         uint8_t RESERVED_5[12];
    __IO uint32_t EARS;                              /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
         uint8_t RESERVED_6[184];
    __IO uint8_t DCHPRI3;                            /**< Channel n Priority Register, offset: 0x100 */
    __IO uint8_t DCHPRI2;                            /**< Channel n Priority Register, offset: 0x101 */
    __IO uint8_t DCHPRI1;                            /**< Channel n Priority Register, offset: 0x102 */
    __IO uint8_t DCHPRI0;                            /**< Channel n Priority Register, offset: 0x103 */
    __IO uint8_t DCHPRI7;                            /**< Channel n Priority Register, offset: 0x104 */
    __IO uint8_t DCHPRI6;                            /**< Channel n Priority Register, offset: 0x105 */
    __IO uint8_t DCHPRI5;                            /**< Channel n Priority Register, offset: 0x106 */
    __IO uint8_t DCHPRI4;                            /**< Channel n Priority Register, offset: 0x107 */
    __IO uint8_t DCHPRI11;                           /**< Channel n Priority Register, offset: 0x108 */
    __IO uint8_t DCHPRI10;                           /**< Channel n Priority Register, offset: 0x109 */
    __IO uint8_t DCHPRI9;                            /**< Channel n Priority Register, offset: 0x10A */
    __IO uint8_t DCHPRI8;                            /**< Channel n Priority Register, offset: 0x10B */
    __IO uint8_t DCHPRI15;                           /**< Channel n Priority Register, offset: 0x10C */
    __IO uint8_t DCHPRI14;                           /**< Channel n Priority Register, offset: 0x10D */
    __IO uint8_t DCHPRI13;                           /**< Channel n Priority Register, offset: 0x10E */
    __IO uint8_t DCHPRI12;                           /**< Channel n Priority Register, offset: 0x10F */
         uint8_t RESERVED_7[3824];
    struct {                                         /* offset: 0x1000, array step: 0x20 */
      __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
      __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
      __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
      union {                                          /* offset: 0x1008, array step: 0x20 */
        __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
        __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
        __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
      };
      __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
      __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
      __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
      union {                                          /* offset: 0x1016, array step: 0x20 */
        __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
        __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
      };
      __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
      __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
      union {                                          /* offset: 0x101E, array step: 0x20 */
        __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
        __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
      };
    } TCD[16];
  } DMA_Type, *DMA_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- DMA - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
   * @{
   */
  
  
  /* DMA - Register accessors */
  #define DMA_CR_REG(base)                         ((base)->CR)
  #define DMA_ES_REG(base)                         ((base)->ES)
  #define DMA_ERQ_REG(base)                        ((base)->ERQ)
  #define DMA_EEI_REG(base)                        ((base)->EEI)
  #define DMA_CEEI_REG(base)                       ((base)->CEEI)
  #define DMA_SEEI_REG(base)                       ((base)->SEEI)
  #define DMA_CERQ_REG(base)                       ((base)->CERQ)
  #define DMA_SERQ_REG(base)                       ((base)->SERQ)
  #define DMA_CDNE_REG(base)                       ((base)->CDNE)
  #define DMA_SSRT_REG(base)                       ((base)->SSRT)
  #define DMA_CERR_REG(base)                       ((base)->CERR)
  #define DMA_CINT_REG(base)                       ((base)->CINT)
  #define DMA_INT_REG(base)                        ((base)->INT)
  #define DMA_ERR_REG(base)                        ((base)->ERR)
  #define DMA_HRS_REG(base)                        ((base)->HRS)
  #define DMA_EARS_REG(base)                       ((base)->EARS)
  #define DMA_DCHPRI3_REG(base)                    ((base)->DCHPRI3)
  #define DMA_DCHPRI2_REG(base)                    ((base)->DCHPRI2)
  #define DMA_DCHPRI1_REG(base)                    ((base)->DCHPRI1)
  #define DMA_DCHPRI0_REG(base)                    ((base)->DCHPRI0)
  #define DMA_DCHPRI7_REG(base)                    ((base)->DCHPRI7)
  #define DMA_DCHPRI6_REG(base)                    ((base)->DCHPRI6)
  #define DMA_DCHPRI5_REG(base)                    ((base)->DCHPRI5)
  #define DMA_DCHPRI4_REG(base)                    ((base)->DCHPRI4)
  #define DMA_DCHPRI11_REG(base)                   ((base)->DCHPRI11)
  #define DMA_DCHPRI10_REG(base)                   ((base)->DCHPRI10)
  #define DMA_DCHPRI9_REG(base)                    ((base)->DCHPRI9)
  #define DMA_DCHPRI8_REG(base)                    ((base)->DCHPRI8)
  #define DMA_DCHPRI15_REG(base)                   ((base)->DCHPRI15)
  #define DMA_DCHPRI14_REG(base)                   ((base)->DCHPRI14)
  #define DMA_DCHPRI13_REG(base)                   ((base)->DCHPRI13)
  #define DMA_DCHPRI12_REG(base)                   ((base)->DCHPRI12)
  #define DMA_SADDR_REG(base,index)                ((base)->TCD[index].SADDR)
  #define DMA_SADDR_COUNT                          16
  #define DMA_SOFF_REG(base,index)                 ((base)->TCD[index].SOFF)
  #define DMA_SOFF_COUNT                           16
  #define DMA_ATTR_REG(base,index)                 ((base)->TCD[index].ATTR)
  #define DMA_ATTR_COUNT                           16
  #define DMA_NBYTES_MLNO_REG(base,index)          ((base)->TCD[index].NBYTES_MLNO)
  #define DMA_NBYTES_MLNO_COUNT                    16
  #define DMA_NBYTES_MLOFFNO_REG(base,index)       ((base)->TCD[index].NBYTES_MLOFFNO)
  #define DMA_NBYTES_MLOFFNO_COUNT                 16
  #define DMA_NBYTES_MLOFFYES_REG(base,index)      ((base)->TCD[index].NBYTES_MLOFFYES)
  #define DMA_NBYTES_MLOFFYES_COUNT                16
  #define DMA_SLAST_REG(base,index)                ((base)->TCD[index].SLAST)
  #define DMA_SLAST_COUNT                          16
  #define DMA_DADDR_REG(base,index)                ((base)->TCD[index].DADDR)
  #define DMA_DADDR_COUNT                          16
  #define DMA_DOFF_REG(base,index)                 ((base)->TCD[index].DOFF)
  #define DMA_DOFF_COUNT                           16
  #define DMA_CITER_ELINKNO_REG(base,index)        ((base)->TCD[index].CITER_ELINKNO)
  #define DMA_CITER_ELINKNO_COUNT                  16
  #define DMA_CITER_ELINKYES_REG(base,index)       ((base)->TCD[index].CITER_ELINKYES)
  #define DMA_CITER_ELINKYES_COUNT                 16
  #define DMA_DLAST_SGA_REG(base,index)            ((base)->TCD[index].DLAST_SGA)
  #define DMA_DLAST_SGA_COUNT                      16
  #define DMA_CSR_REG(base,index)                  ((base)->TCD[index].CSR)
  #define DMA_CSR_COUNT                            16
  #define DMA_BITER_ELINKNO_REG(base,index)        ((base)->TCD[index].BITER_ELINKNO)
  #define DMA_BITER_ELINKNO_COUNT                  16
  #define DMA_BITER_ELINKYES_REG(base,index)       ((base)->TCD[index].BITER_ELINKYES)
  #define DMA_BITER_ELINKYES_COUNT                 16
  
  /*!
   * @}
   */ /* end of group DMA_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- DMA Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DMA_Register_Masks DMA Register Masks
   * @{
   */
  
  /* CR Bit Fields */
  #define DMA_CR_EDBG_MASK                         0x2u
  #define DMA_CR_EDBG_SHIFT                        1
  #define DMA_CR_EDBG_WIDTH                        1
  #define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
  #define DMA_CR_ERCA_MASK                         0x4u
  #define DMA_CR_ERCA_SHIFT                        2
  #define DMA_CR_ERCA_WIDTH                        1
  #define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
  #define DMA_CR_HOE_MASK                          0x10u
  #define DMA_CR_HOE_SHIFT                         4
  #define DMA_CR_HOE_WIDTH                         1
  #define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
  #define DMA_CR_HALT_MASK                         0x20u
  #define DMA_CR_HALT_SHIFT                        5
  #define DMA_CR_HALT_WIDTH                        1
  #define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
  #define DMA_CR_CLM_MASK                          0x40u
  #define DMA_CR_CLM_SHIFT                         6
  #define DMA_CR_CLM_WIDTH                         1
  #define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
  #define DMA_CR_EMLM_MASK                         0x80u
  #define DMA_CR_EMLM_SHIFT                        7
  #define DMA_CR_EMLM_WIDTH                        1
  #define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
  #define DMA_CR_ECX_MASK                          0x10000u
  #define DMA_CR_ECX_SHIFT                         16
  #define DMA_CR_ECX_WIDTH                         1
  #define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
  #define DMA_CR_CX_MASK                           0x20000u
  #define DMA_CR_CX_SHIFT                          17
  #define DMA_CR_CX_WIDTH                          1
  #define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
  /* ES Bit Fields */
  #define DMA_ES_DBE_MASK                          0x1u
  #define DMA_ES_DBE_SHIFT                         0
  #define DMA_ES_DBE_WIDTH                         1
  #define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
  #define DMA_ES_SBE_MASK                          0x2u
  #define DMA_ES_SBE_SHIFT                         1
  #define DMA_ES_SBE_WIDTH                         1
  #define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
  #define DMA_ES_SGE_MASK                          0x4u
  #define DMA_ES_SGE_SHIFT                         2
  #define DMA_ES_SGE_WIDTH                         1
  #define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
  #define DMA_ES_NCE_MASK                          0x8u
  #define DMA_ES_NCE_SHIFT                         3
  #define DMA_ES_NCE_WIDTH                         1
  #define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
  #define DMA_ES_DOE_MASK                          0x10u
  #define DMA_ES_DOE_SHIFT                         4
  #define DMA_ES_DOE_WIDTH                         1
  #define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
  #define DMA_ES_DAE_MASK                          0x20u
  #define DMA_ES_DAE_SHIFT                         5
  #define DMA_ES_DAE_WIDTH                         1
  #define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
  #define DMA_ES_SOE_MASK                          0x40u
  #define DMA_ES_SOE_SHIFT                         6
  #define DMA_ES_SOE_WIDTH                         1
  #define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
  #define DMA_ES_SAE_MASK                          0x80u
  #define DMA_ES_SAE_SHIFT                         7
  #define DMA_ES_SAE_WIDTH                         1
  #define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
  #define DMA_ES_ERRCHN_MASK                       0xF00u
  #define DMA_ES_ERRCHN_SHIFT                      8
  #define DMA_ES_ERRCHN_WIDTH                      4
  #define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
  #define DMA_ES_CPE_MASK                          0x4000u
  #define DMA_ES_CPE_SHIFT                         14
  #define DMA_ES_CPE_WIDTH                         1
  #define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
  #define DMA_ES_ECX_MASK                          0x10000u
  #define DMA_ES_ECX_SHIFT                         16
  #define DMA_ES_ECX_WIDTH                         1
  #define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
  #define DMA_ES_VLD_MASK                          0x80000000u
  #define DMA_ES_VLD_SHIFT                         31
  #define DMA_ES_VLD_WIDTH                         1
  #define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
  /* ERQ Bit Fields */
  #define DMA_ERQ_ERQ0_MASK                        0x1u
  #define DMA_ERQ_ERQ0_SHIFT                       0
  #define DMA_ERQ_ERQ0_WIDTH                       1
  #define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
  #define DMA_ERQ_ERQ1_MASK                        0x2u
  #define DMA_ERQ_ERQ1_SHIFT                       1
  #define DMA_ERQ_ERQ1_WIDTH                       1
  #define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
  #define DMA_ERQ_ERQ2_MASK                        0x4u
  #define DMA_ERQ_ERQ2_SHIFT                       2
  #define DMA_ERQ_ERQ2_WIDTH                       1
  #define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
  #define DMA_ERQ_ERQ3_MASK                        0x8u
  #define DMA_ERQ_ERQ3_SHIFT                       3
  #define DMA_ERQ_ERQ3_WIDTH                       1
  #define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
  #define DMA_ERQ_ERQ4_MASK                        0x10u
  #define DMA_ERQ_ERQ4_SHIFT                       4
  #define DMA_ERQ_ERQ4_WIDTH                       1
  #define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
  #define DMA_ERQ_ERQ5_MASK                        0x20u
  #define DMA_ERQ_ERQ5_SHIFT                       5
  #define DMA_ERQ_ERQ5_WIDTH                       1
  #define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
  #define DMA_ERQ_ERQ6_MASK                        0x40u
  #define DMA_ERQ_ERQ6_SHIFT                       6
  #define DMA_ERQ_ERQ6_WIDTH                       1
  #define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
  #define DMA_ERQ_ERQ7_MASK                        0x80u
  #define DMA_ERQ_ERQ7_SHIFT                       7
  #define DMA_ERQ_ERQ7_WIDTH                       1
  #define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
  #define DMA_ERQ_ERQ8_MASK                        0x100u
  #define DMA_ERQ_ERQ8_SHIFT                       8
  #define DMA_ERQ_ERQ8_WIDTH                       1
  #define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ8_SHIFT))&DMA_ERQ_ERQ8_MASK)
  #define DMA_ERQ_ERQ9_MASK                        0x200u
  #define DMA_ERQ_ERQ9_SHIFT                       9
  #define DMA_ERQ_ERQ9_WIDTH                       1
  #define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ9_SHIFT))&DMA_ERQ_ERQ9_MASK)
  #define DMA_ERQ_ERQ10_MASK                       0x400u
  #define DMA_ERQ_ERQ10_SHIFT                      10
  #define DMA_ERQ_ERQ10_WIDTH                      1
  #define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ10_SHIFT))&DMA_ERQ_ERQ10_MASK)
  #define DMA_ERQ_ERQ11_MASK                       0x800u
  #define DMA_ERQ_ERQ11_SHIFT                      11
  #define DMA_ERQ_ERQ11_WIDTH                      1
  #define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ11_SHIFT))&DMA_ERQ_ERQ11_MASK)
  #define DMA_ERQ_ERQ12_MASK                       0x1000u
  #define DMA_ERQ_ERQ12_SHIFT                      12
  #define DMA_ERQ_ERQ12_WIDTH                      1
  #define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ12_SHIFT))&DMA_ERQ_ERQ12_MASK)
  #define DMA_ERQ_ERQ13_MASK                       0x2000u
  #define DMA_ERQ_ERQ13_SHIFT                      13
  #define DMA_ERQ_ERQ13_WIDTH                      1
  #define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ13_SHIFT))&DMA_ERQ_ERQ13_MASK)
  #define DMA_ERQ_ERQ14_MASK                       0x4000u
  #define DMA_ERQ_ERQ14_SHIFT                      14
  #define DMA_ERQ_ERQ14_WIDTH                      1
  #define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ14_SHIFT))&DMA_ERQ_ERQ14_MASK)
  #define DMA_ERQ_ERQ15_MASK                       0x8000u
  #define DMA_ERQ_ERQ15_SHIFT                      15
  #define DMA_ERQ_ERQ15_WIDTH                      1
  #define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ15_SHIFT))&DMA_ERQ_ERQ15_MASK)
  /* EEI Bit Fields */
  #define DMA_EEI_EEI0_MASK                        0x1u
  #define DMA_EEI_EEI0_SHIFT                       0
  #define DMA_EEI_EEI0_WIDTH                       1
  #define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
  #define DMA_EEI_EEI1_MASK                        0x2u
  #define DMA_EEI_EEI1_SHIFT                       1
  #define DMA_EEI_EEI1_WIDTH                       1
  #define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
  #define DMA_EEI_EEI2_MASK                        0x4u
  #define DMA_EEI_EEI2_SHIFT                       2
  #define DMA_EEI_EEI2_WIDTH                       1
  #define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
  #define DMA_EEI_EEI3_MASK                        0x8u
  #define DMA_EEI_EEI3_SHIFT                       3
  #define DMA_EEI_EEI3_WIDTH                       1
  #define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
  #define DMA_EEI_EEI4_MASK                        0x10u
  #define DMA_EEI_EEI4_SHIFT                       4
  #define DMA_EEI_EEI4_WIDTH                       1
  #define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
  #define DMA_EEI_EEI5_MASK                        0x20u
  #define DMA_EEI_EEI5_SHIFT                       5
  #define DMA_EEI_EEI5_WIDTH                       1
  #define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
  #define DMA_EEI_EEI6_MASK                        0x40u
  #define DMA_EEI_EEI6_SHIFT                       6
  #define DMA_EEI_EEI6_WIDTH                       1
  #define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
  #define DMA_EEI_EEI7_MASK                        0x80u
  #define DMA_EEI_EEI7_SHIFT                       7
  #define DMA_EEI_EEI7_WIDTH                       1
  #define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
  #define DMA_EEI_EEI8_MASK                        0x100u
  #define DMA_EEI_EEI8_SHIFT                       8
  #define DMA_EEI_EEI8_WIDTH                       1
  #define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI8_SHIFT))&DMA_EEI_EEI8_MASK)
  #define DMA_EEI_EEI9_MASK                        0x200u
  #define DMA_EEI_EEI9_SHIFT                       9
  #define DMA_EEI_EEI9_WIDTH                       1
  #define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI9_SHIFT))&DMA_EEI_EEI9_MASK)
  #define DMA_EEI_EEI10_MASK                       0x400u
  #define DMA_EEI_EEI10_SHIFT                      10
  #define DMA_EEI_EEI10_WIDTH                      1
  #define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI10_SHIFT))&DMA_EEI_EEI10_MASK)
  #define DMA_EEI_EEI11_MASK                       0x800u
  #define DMA_EEI_EEI11_SHIFT                      11
  #define DMA_EEI_EEI11_WIDTH                      1
  #define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI11_SHIFT))&DMA_EEI_EEI11_MASK)
  #define DMA_EEI_EEI12_MASK                       0x1000u
  #define DMA_EEI_EEI12_SHIFT                      12
  #define DMA_EEI_EEI12_WIDTH                      1
  #define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI12_SHIFT))&DMA_EEI_EEI12_MASK)
  #define DMA_EEI_EEI13_MASK                       0x2000u
  #define DMA_EEI_EEI13_SHIFT                      13
  #define DMA_EEI_EEI13_WIDTH                      1
  #define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI13_SHIFT))&DMA_EEI_EEI13_MASK)
  #define DMA_EEI_EEI14_MASK                       0x4000u
  #define DMA_EEI_EEI14_SHIFT                      14
  #define DMA_EEI_EEI14_WIDTH                      1
  #define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI14_SHIFT))&DMA_EEI_EEI14_MASK)
  #define DMA_EEI_EEI15_MASK                       0x8000u
  #define DMA_EEI_EEI15_SHIFT                      15
  #define DMA_EEI_EEI15_WIDTH                      1
  #define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI15_SHIFT))&DMA_EEI_EEI15_MASK)
  /* CEEI Bit Fields */
  #define DMA_CEEI_CEEI_MASK                       0xFu
  #define DMA_CEEI_CEEI_SHIFT                      0
  #define DMA_CEEI_CEEI_WIDTH                      4
  #define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
  #define DMA_CEEI_CAEE_MASK                       0x40u
  #define DMA_CEEI_CAEE_SHIFT                      6
  #define DMA_CEEI_CAEE_WIDTH                      1
  #define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
  #define DMA_CEEI_NOP_MASK                        0x80u
  #define DMA_CEEI_NOP_SHIFT                       7
  #define DMA_CEEI_NOP_WIDTH                       1
  #define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
  /* SEEI Bit Fields */
  #define DMA_SEEI_SEEI_MASK                       0xFu
  #define DMA_SEEI_SEEI_SHIFT                      0
  #define DMA_SEEI_SEEI_WIDTH                      4
  #define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
  #define DMA_SEEI_SAEE_MASK                       0x40u
  #define DMA_SEEI_SAEE_SHIFT                      6
  #define DMA_SEEI_SAEE_WIDTH                      1
  #define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
  #define DMA_SEEI_NOP_MASK                        0x80u
  #define DMA_SEEI_NOP_SHIFT                       7
  #define DMA_SEEI_NOP_WIDTH                       1
  #define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
  /* CERQ Bit Fields */
  #define DMA_CERQ_CERQ_MASK                       0xFu
  #define DMA_CERQ_CERQ_SHIFT                      0
  #define DMA_CERQ_CERQ_WIDTH                      4
  #define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
  #define DMA_CERQ_CAER_MASK                       0x40u
  #define DMA_CERQ_CAER_SHIFT                      6
  #define DMA_CERQ_CAER_WIDTH                      1
  #define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
  #define DMA_CERQ_NOP_MASK                        0x80u
  #define DMA_CERQ_NOP_SHIFT                       7
  #define DMA_CERQ_NOP_WIDTH                       1
  #define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
  /* SERQ Bit Fields */
  #define DMA_SERQ_SERQ_MASK                       0xFu
  #define DMA_SERQ_SERQ_SHIFT                      0
  #define DMA_SERQ_SERQ_WIDTH                      4
  #define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
  #define DMA_SERQ_SAER_MASK                       0x40u
  #define DMA_SERQ_SAER_SHIFT                      6
  #define DMA_SERQ_SAER_WIDTH                      1
  #define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
  #define DMA_SERQ_NOP_MASK                        0x80u
  #define DMA_SERQ_NOP_SHIFT                       7
  #define DMA_SERQ_NOP_WIDTH                       1
  #define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
  /* CDNE Bit Fields */
  #define DMA_CDNE_CDNE_MASK                       0xFu
  #define DMA_CDNE_CDNE_SHIFT                      0
  #define DMA_CDNE_CDNE_WIDTH                      4
  #define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
  #define DMA_CDNE_CADN_MASK                       0x40u
  #define DMA_CDNE_CADN_SHIFT                      6
  #define DMA_CDNE_CADN_WIDTH                      1
  #define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
  #define DMA_CDNE_NOP_MASK                        0x80u
  #define DMA_CDNE_NOP_SHIFT                       7
  #define DMA_CDNE_NOP_WIDTH                       1
  #define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
  /* SSRT Bit Fields */
  #define DMA_SSRT_SSRT_MASK                       0xFu
  #define DMA_SSRT_SSRT_SHIFT                      0
  #define DMA_SSRT_SSRT_WIDTH                      4
  #define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
  #define DMA_SSRT_SAST_MASK                       0x40u
  #define DMA_SSRT_SAST_SHIFT                      6
  #define DMA_SSRT_SAST_WIDTH                      1
  #define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
  #define DMA_SSRT_NOP_MASK                        0x80u
  #define DMA_SSRT_NOP_SHIFT                       7
  #define DMA_SSRT_NOP_WIDTH                       1
  #define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
  /* CERR Bit Fields */
  #define DMA_CERR_CERR_MASK                       0xFu
  #define DMA_CERR_CERR_SHIFT                      0
  #define DMA_CERR_CERR_WIDTH                      4
  #define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
  #define DMA_CERR_CAEI_MASK                       0x40u
  #define DMA_CERR_CAEI_SHIFT                      6
  #define DMA_CERR_CAEI_WIDTH                      1
  #define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
  #define DMA_CERR_NOP_MASK                        0x80u
  #define DMA_CERR_NOP_SHIFT                       7
  #define DMA_CERR_NOP_WIDTH                       1
  #define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
  /* CINT Bit Fields */
  #define DMA_CINT_CINT_MASK                       0xFu
  #define DMA_CINT_CINT_SHIFT                      0
  #define DMA_CINT_CINT_WIDTH                      4
  #define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
  #define DMA_CINT_CAIR_MASK                       0x40u
  #define DMA_CINT_CAIR_SHIFT                      6
  #define DMA_CINT_CAIR_WIDTH                      1
  #define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
  #define DMA_CINT_NOP_MASK                        0x80u
  #define DMA_CINT_NOP_SHIFT                       7
  #define DMA_CINT_NOP_WIDTH                       1
  #define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
  /* INT Bit Fields */
  #define DMA_INT_INT0_MASK                        0x1u
  #define DMA_INT_INT0_SHIFT                       0
  #define DMA_INT_INT0_WIDTH                       1
  #define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
  #define DMA_INT_INT1_MASK                        0x2u
  #define DMA_INT_INT1_SHIFT                       1
  #define DMA_INT_INT1_WIDTH                       1
  #define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
  #define DMA_INT_INT2_MASK                        0x4u
  #define DMA_INT_INT2_SHIFT                       2
  #define DMA_INT_INT2_WIDTH                       1
  #define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
  #define DMA_INT_INT3_MASK                        0x8u
  #define DMA_INT_INT3_SHIFT                       3
  #define DMA_INT_INT3_WIDTH                       1
  #define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
  #define DMA_INT_INT4_MASK                        0x10u
  #define DMA_INT_INT4_SHIFT                       4
  #define DMA_INT_INT4_WIDTH                       1
  #define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
  #define DMA_INT_INT5_MASK                        0x20u
  #define DMA_INT_INT5_SHIFT                       5
  #define DMA_INT_INT5_WIDTH                       1
  #define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
  #define DMA_INT_INT6_MASK                        0x40u
  #define DMA_INT_INT6_SHIFT                       6
  #define DMA_INT_INT6_WIDTH                       1
  #define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
  #define DMA_INT_INT7_MASK                        0x80u
  #define DMA_INT_INT7_SHIFT                       7
  #define DMA_INT_INT7_WIDTH                       1
  #define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
  #define DMA_INT_INT8_MASK                        0x100u
  #define DMA_INT_INT8_SHIFT                       8
  #define DMA_INT_INT8_WIDTH                       1
  #define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT8_SHIFT))&DMA_INT_INT8_MASK)
  #define DMA_INT_INT9_MASK                        0x200u
  #define DMA_INT_INT9_SHIFT                       9
  #define DMA_INT_INT9_WIDTH                       1
  #define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT9_SHIFT))&DMA_INT_INT9_MASK)
  #define DMA_INT_INT10_MASK                       0x400u
  #define DMA_INT_INT10_SHIFT                      10
  #define DMA_INT_INT10_WIDTH                      1
  #define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT10_SHIFT))&DMA_INT_INT10_MASK)
  #define DMA_INT_INT11_MASK                       0x800u
  #define DMA_INT_INT11_SHIFT                      11
  #define DMA_INT_INT11_WIDTH                      1
  #define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT11_SHIFT))&DMA_INT_INT11_MASK)
  #define DMA_INT_INT12_MASK                       0x1000u
  #define DMA_INT_INT12_SHIFT                      12
  #define DMA_INT_INT12_WIDTH                      1
  #define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT12_SHIFT))&DMA_INT_INT12_MASK)
  #define DMA_INT_INT13_MASK                       0x2000u
  #define DMA_INT_INT13_SHIFT                      13
  #define DMA_INT_INT13_WIDTH                      1
  #define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT13_SHIFT))&DMA_INT_INT13_MASK)
  #define DMA_INT_INT14_MASK                       0x4000u
  #define DMA_INT_INT14_SHIFT                      14
  #define DMA_INT_INT14_WIDTH                      1
  #define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT14_SHIFT))&DMA_INT_INT14_MASK)
  #define DMA_INT_INT15_MASK                       0x8000u
  #define DMA_INT_INT15_SHIFT                      15
  #define DMA_INT_INT15_WIDTH                      1
  #define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT15_SHIFT))&DMA_INT_INT15_MASK)
  /* ERR Bit Fields */
  #define DMA_ERR_ERR0_MASK                        0x1u
  #define DMA_ERR_ERR0_SHIFT                       0
  #define DMA_ERR_ERR0_WIDTH                       1
  #define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
  #define DMA_ERR_ERR1_MASK                        0x2u
  #define DMA_ERR_ERR1_SHIFT                       1
  #define DMA_ERR_ERR1_WIDTH                       1
  #define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
  #define DMA_ERR_ERR2_MASK                        0x4u
  #define DMA_ERR_ERR2_SHIFT                       2
  #define DMA_ERR_ERR2_WIDTH                       1
  #define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
  #define DMA_ERR_ERR3_MASK                        0x8u
  #define DMA_ERR_ERR3_SHIFT                       3
  #define DMA_ERR_ERR3_WIDTH                       1
  #define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
  #define DMA_ERR_ERR4_MASK                        0x10u
  #define DMA_ERR_ERR4_SHIFT                       4
  #define DMA_ERR_ERR4_WIDTH                       1
  #define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
  #define DMA_ERR_ERR5_MASK                        0x20u
  #define DMA_ERR_ERR5_SHIFT                       5
  #define DMA_ERR_ERR5_WIDTH                       1
  #define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
  #define DMA_ERR_ERR6_MASK                        0x40u
  #define DMA_ERR_ERR6_SHIFT                       6
  #define DMA_ERR_ERR6_WIDTH                       1
  #define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
  #define DMA_ERR_ERR7_MASK                        0x80u
  #define DMA_ERR_ERR7_SHIFT                       7
  #define DMA_ERR_ERR7_WIDTH                       1
  #define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
  #define DMA_ERR_ERR8_MASK                        0x100u
  #define DMA_ERR_ERR8_SHIFT                       8
  #define DMA_ERR_ERR8_WIDTH                       1
  #define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR8_SHIFT))&DMA_ERR_ERR8_MASK)
  #define DMA_ERR_ERR9_MASK                        0x200u
  #define DMA_ERR_ERR9_SHIFT                       9
  #define DMA_ERR_ERR9_WIDTH                       1
  #define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR9_SHIFT))&DMA_ERR_ERR9_MASK)
  #define DMA_ERR_ERR10_MASK                       0x400u
  #define DMA_ERR_ERR10_SHIFT                      10
  #define DMA_ERR_ERR10_WIDTH                      1
  #define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR10_SHIFT))&DMA_ERR_ERR10_MASK)
  #define DMA_ERR_ERR11_MASK                       0x800u
  #define DMA_ERR_ERR11_SHIFT                      11
  #define DMA_ERR_ERR11_WIDTH                      1
  #define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR11_SHIFT))&DMA_ERR_ERR11_MASK)
  #define DMA_ERR_ERR12_MASK                       0x1000u
  #define DMA_ERR_ERR12_SHIFT                      12
  #define DMA_ERR_ERR12_WIDTH                      1
  #define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR12_SHIFT))&DMA_ERR_ERR12_MASK)
  #define DMA_ERR_ERR13_MASK                       0x2000u
  #define DMA_ERR_ERR13_SHIFT                      13
  #define DMA_ERR_ERR13_WIDTH                      1
  #define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR13_SHIFT))&DMA_ERR_ERR13_MASK)
  #define DMA_ERR_ERR14_MASK                       0x4000u
  #define DMA_ERR_ERR14_SHIFT                      14
  #define DMA_ERR_ERR14_WIDTH                      1
  #define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR14_SHIFT))&DMA_ERR_ERR14_MASK)
  #define DMA_ERR_ERR15_MASK                       0x8000u
  #define DMA_ERR_ERR15_SHIFT                      15
  #define DMA_ERR_ERR15_WIDTH                      1
  #define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR15_SHIFT))&DMA_ERR_ERR15_MASK)
  /* HRS Bit Fields */
  #define DMA_HRS_HRS0_MASK                        0x1u
  #define DMA_HRS_HRS0_SHIFT                       0
  #define DMA_HRS_HRS0_WIDTH                       1
  #define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
  #define DMA_HRS_HRS1_MASK                        0x2u
  #define DMA_HRS_HRS1_SHIFT                       1
  #define DMA_HRS_HRS1_WIDTH                       1
  #define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
  #define DMA_HRS_HRS2_MASK                        0x4u
  #define DMA_HRS_HRS2_SHIFT                       2
  #define DMA_HRS_HRS2_WIDTH                       1
  #define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
  #define DMA_HRS_HRS3_MASK                        0x8u
  #define DMA_HRS_HRS3_SHIFT                       3
  #define DMA_HRS_HRS3_WIDTH                       1
  #define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
  #define DMA_HRS_HRS4_MASK                        0x10u
  #define DMA_HRS_HRS4_SHIFT                       4
  #define DMA_HRS_HRS4_WIDTH                       1
  #define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
  #define DMA_HRS_HRS5_MASK                        0x20u
  #define DMA_HRS_HRS5_SHIFT                       5
  #define DMA_HRS_HRS5_WIDTH                       1
  #define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
  #define DMA_HRS_HRS6_MASK                        0x40u
  #define DMA_HRS_HRS6_SHIFT                       6
  #define DMA_HRS_HRS6_WIDTH                       1
  #define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
  #define DMA_HRS_HRS7_MASK                        0x80u
  #define DMA_HRS_HRS7_SHIFT                       7
  #define DMA_HRS_HRS7_WIDTH                       1
  #define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
  #define DMA_HRS_HRS8_MASK                        0x100u
  #define DMA_HRS_HRS8_SHIFT                       8
  #define DMA_HRS_HRS8_WIDTH                       1
  #define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS8_SHIFT))&DMA_HRS_HRS8_MASK)
  #define DMA_HRS_HRS9_MASK                        0x200u
  #define DMA_HRS_HRS9_SHIFT                       9
  #define DMA_HRS_HRS9_WIDTH                       1
  #define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS9_SHIFT))&DMA_HRS_HRS9_MASK)
  #define DMA_HRS_HRS10_MASK                       0x400u
  #define DMA_HRS_HRS10_SHIFT                      10
  #define DMA_HRS_HRS10_WIDTH                      1
  #define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS10_SHIFT))&DMA_HRS_HRS10_MASK)
  #define DMA_HRS_HRS11_MASK                       0x800u
  #define DMA_HRS_HRS11_SHIFT                      11
  #define DMA_HRS_HRS11_WIDTH                      1
  #define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS11_SHIFT))&DMA_HRS_HRS11_MASK)
  #define DMA_HRS_HRS12_MASK                       0x1000u
  #define DMA_HRS_HRS12_SHIFT                      12
  #define DMA_HRS_HRS12_WIDTH                      1
  #define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS12_SHIFT))&DMA_HRS_HRS12_MASK)
  #define DMA_HRS_HRS13_MASK                       0x2000u
  #define DMA_HRS_HRS13_SHIFT                      13
  #define DMA_HRS_HRS13_WIDTH                      1
  #define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS13_SHIFT))&DMA_HRS_HRS13_MASK)
  #define DMA_HRS_HRS14_MASK                       0x4000u
  #define DMA_HRS_HRS14_SHIFT                      14
  #define DMA_HRS_HRS14_WIDTH                      1
  #define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS14_SHIFT))&DMA_HRS_HRS14_MASK)
  #define DMA_HRS_HRS15_MASK                       0x8000u
  #define DMA_HRS_HRS15_SHIFT                      15
  #define DMA_HRS_HRS15_WIDTH                      1
  #define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS15_SHIFT))&DMA_HRS_HRS15_MASK)
  /* EARS Bit Fields */
  #define DMA_EARS_EDREQ_0_MASK                    0x1u
  #define DMA_EARS_EDREQ_0_SHIFT                   0
  #define DMA_EARS_EDREQ_0_WIDTH                   1
  #define DMA_EARS_EDREQ_0(x)                      (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_0_SHIFT))&DMA_EARS_EDREQ_0_MASK)
  #define DMA_EARS_EDREQ_1_MASK                    0x2u
  #define DMA_EARS_EDREQ_1_SHIFT                   1
  #define DMA_EARS_EDREQ_1_WIDTH                   1
  #define DMA_EARS_EDREQ_1(x)                      (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_1_SHIFT))&DMA_EARS_EDREQ_1_MASK)
  #define DMA_EARS_EDREQ_2_MASK                    0x4u
  #define DMA_EARS_EDREQ_2_SHIFT                   2
  #define DMA_EARS_EDREQ_2_WIDTH                   1
  #define DMA_EARS_EDREQ_2(x)                      (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_2_SHIFT))&DMA_EARS_EDREQ_2_MASK)
  #define DMA_EARS_EDREQ_3_MASK                    0x8u
  #define DMA_EARS_EDREQ_3_SHIFT                   3
  #define DMA_EARS_EDREQ_3_WIDTH                   1
  #define DMA_EARS_EDREQ_3(x)                      (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_3_SHIFT))&DMA_EARS_EDREQ_3_MASK)
  #define DMA_EARS_EDREQ_4_MASK                    0x10u
  #define DMA_EARS_EDREQ_4_SHIFT                   4
  #define DMA_EARS_EDREQ_4_WIDTH                   1
  #define DMA_EARS_EDREQ_4(x)                      (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_4_SHIFT))&DMA_EARS_EDREQ_4_MASK)
  #define DMA_EARS_EDREQ_5_MASK                    0x20u
  #define DMA_EARS_EDREQ_5_SHIFT                   5
  #define DMA_EARS_EDREQ_5_WIDTH                   1
  #define DMA_EARS_EDREQ_5(x)                      (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_5_SHIFT))&DMA_EARS_EDREQ_5_MASK)
  #define DMA_EARS_EDREQ_6_MASK                    0x40u
  #define DMA_EARS_EDREQ_6_SHIFT                   6
  #define DMA_EARS_EDREQ_6_WIDTH                   1
  #define DMA_EARS_EDREQ_6(x)                      (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_6_SHIFT))&DMA_EARS_EDREQ_6_MASK)
  #define DMA_EARS_EDREQ_7_MASK                    0x80u
  #define DMA_EARS_EDREQ_7_SHIFT                   7
  #define DMA_EARS_EDREQ_7_WIDTH                   1
  #define DMA_EARS_EDREQ_7(x)                      (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_7_SHIFT))&DMA_EARS_EDREQ_7_MASK)
  #define DMA_EARS_EDREQ_8_MASK                    0x100u
  #define DMA_EARS_EDREQ_8_SHIFT                   8
  #define DMA_EARS_EDREQ_8_WIDTH                   1
  #define DMA_EARS_EDREQ_8(x)                      (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_8_SHIFT))&DMA_EARS_EDREQ_8_MASK)
  #define DMA_EARS_EDREQ_9_MASK                    0x200u
  #define DMA_EARS_EDREQ_9_SHIFT                   9
  #define DMA_EARS_EDREQ_9_WIDTH                   1
  #define DMA_EARS_EDREQ_9(x)                      (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_9_SHIFT))&DMA_EARS_EDREQ_9_MASK)
  #define DMA_EARS_EDREQ_10_MASK                   0x400u
  #define DMA_EARS_EDREQ_10_SHIFT                  10
  #define DMA_EARS_EDREQ_10_WIDTH                  1
  #define DMA_EARS_EDREQ_10(x)                     (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_10_SHIFT))&DMA_EARS_EDREQ_10_MASK)
  #define DMA_EARS_EDREQ_11_MASK                   0x800u
  #define DMA_EARS_EDREQ_11_SHIFT                  11
  #define DMA_EARS_EDREQ_11_WIDTH                  1
  #define DMA_EARS_EDREQ_11(x)                     (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_11_SHIFT))&DMA_EARS_EDREQ_11_MASK)
  #define DMA_EARS_EDREQ_12_MASK                   0x1000u
  #define DMA_EARS_EDREQ_12_SHIFT                  12
  #define DMA_EARS_EDREQ_12_WIDTH                  1
  #define DMA_EARS_EDREQ_12(x)                     (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_12_SHIFT))&DMA_EARS_EDREQ_12_MASK)
  #define DMA_EARS_EDREQ_13_MASK                   0x2000u
  #define DMA_EARS_EDREQ_13_SHIFT                  13
  #define DMA_EARS_EDREQ_13_WIDTH                  1
  #define DMA_EARS_EDREQ_13(x)                     (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_13_SHIFT))&DMA_EARS_EDREQ_13_MASK)
  #define DMA_EARS_EDREQ_14_MASK                   0x4000u
  #define DMA_EARS_EDREQ_14_SHIFT                  14
  #define DMA_EARS_EDREQ_14_WIDTH                  1
  #define DMA_EARS_EDREQ_14(x)                     (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_14_SHIFT))&DMA_EARS_EDREQ_14_MASK)
  #define DMA_EARS_EDREQ_15_MASK                   0x8000u
  #define DMA_EARS_EDREQ_15_SHIFT                  15
  #define DMA_EARS_EDREQ_15_WIDTH                  1
  #define DMA_EARS_EDREQ_15(x)                     (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_15_SHIFT))&DMA_EARS_EDREQ_15_MASK)
  /* DCHPRI3 Bit Fields */
  #define DMA_DCHPRI3_CHPRI_MASK                   0xFu
  #define DMA_DCHPRI3_CHPRI_SHIFT                  0
  #define DMA_DCHPRI3_CHPRI_WIDTH                  4
  #define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
  #define DMA_DCHPRI3_DPA_MASK                     0x40u
  #define DMA_DCHPRI3_DPA_SHIFT                    6
  #define DMA_DCHPRI3_DPA_WIDTH                    1
  #define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_DPA_SHIFT))&DMA_DCHPRI3_DPA_MASK)
  #define DMA_DCHPRI3_ECP_MASK                     0x80u
  #define DMA_DCHPRI3_ECP_SHIFT                    7
  #define DMA_DCHPRI3_ECP_WIDTH                    1
  #define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_ECP_SHIFT))&DMA_DCHPRI3_ECP_MASK)
  /* DCHPRI2 Bit Fields */
  #define DMA_DCHPRI2_CHPRI_MASK                   0xFu
  #define DMA_DCHPRI2_CHPRI_SHIFT                  0
  #define DMA_DCHPRI2_CHPRI_WIDTH                  4
  #define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
  #define DMA_DCHPRI2_DPA_MASK                     0x40u
  #define DMA_DCHPRI2_DPA_SHIFT                    6
  #define DMA_DCHPRI2_DPA_WIDTH                    1
  #define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_DPA_SHIFT))&DMA_DCHPRI2_DPA_MASK)
  #define DMA_DCHPRI2_ECP_MASK                     0x80u
  #define DMA_DCHPRI2_ECP_SHIFT                    7
  #define DMA_DCHPRI2_ECP_WIDTH                    1
  #define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_ECP_SHIFT))&DMA_DCHPRI2_ECP_MASK)
  /* DCHPRI1 Bit Fields */
  #define DMA_DCHPRI1_CHPRI_MASK                   0xFu
  #define DMA_DCHPRI1_CHPRI_SHIFT                  0
  #define DMA_DCHPRI1_CHPRI_WIDTH                  4
  #define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
  #define DMA_DCHPRI1_DPA_MASK                     0x40u
  #define DMA_DCHPRI1_DPA_SHIFT                    6
  #define DMA_DCHPRI1_DPA_WIDTH                    1
  #define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_DPA_SHIFT))&DMA_DCHPRI1_DPA_MASK)
  #define DMA_DCHPRI1_ECP_MASK                     0x80u
  #define DMA_DCHPRI1_ECP_SHIFT                    7
  #define DMA_DCHPRI1_ECP_WIDTH                    1
  #define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_ECP_SHIFT))&DMA_DCHPRI1_ECP_MASK)
  /* DCHPRI0 Bit Fields */
  #define DMA_DCHPRI0_CHPRI_MASK                   0xFu
  #define DMA_DCHPRI0_CHPRI_SHIFT                  0
  #define DMA_DCHPRI0_CHPRI_WIDTH                  4
  #define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
  #define DMA_DCHPRI0_DPA_MASK                     0x40u
  #define DMA_DCHPRI0_DPA_SHIFT                    6
  #define DMA_DCHPRI0_DPA_WIDTH                    1
  #define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_DPA_SHIFT))&DMA_DCHPRI0_DPA_MASK)
  #define DMA_DCHPRI0_ECP_MASK                     0x80u
  #define DMA_DCHPRI0_ECP_SHIFT                    7
  #define DMA_DCHPRI0_ECP_WIDTH                    1
  #define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_ECP_SHIFT))&DMA_DCHPRI0_ECP_MASK)
  /* DCHPRI7 Bit Fields */
  #define DMA_DCHPRI7_CHPRI_MASK                   0xFu
  #define DMA_DCHPRI7_CHPRI_SHIFT                  0
  #define DMA_DCHPRI7_CHPRI_WIDTH                  4
  #define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
  #define DMA_DCHPRI7_DPA_MASK                     0x40u
  #define DMA_DCHPRI7_DPA_SHIFT                    6
  #define DMA_DCHPRI7_DPA_WIDTH                    1
  #define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_DPA_SHIFT))&DMA_DCHPRI7_DPA_MASK)
  #define DMA_DCHPRI7_ECP_MASK                     0x80u
  #define DMA_DCHPRI7_ECP_SHIFT                    7
  #define DMA_DCHPRI7_ECP_WIDTH                    1
  #define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_ECP_SHIFT))&DMA_DCHPRI7_ECP_MASK)
  /* DCHPRI6 Bit Fields */
  #define DMA_DCHPRI6_CHPRI_MASK                   0xFu
  #define DMA_DCHPRI6_CHPRI_SHIFT                  0
  #define DMA_DCHPRI6_CHPRI_WIDTH                  4
  #define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
  #define DMA_DCHPRI6_DPA_MASK                     0x40u
  #define DMA_DCHPRI6_DPA_SHIFT                    6
  #define DMA_DCHPRI6_DPA_WIDTH                    1
  #define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_DPA_SHIFT))&DMA_DCHPRI6_DPA_MASK)
  #define DMA_DCHPRI6_ECP_MASK                     0x80u
  #define DMA_DCHPRI6_ECP_SHIFT                    7
  #define DMA_DCHPRI6_ECP_WIDTH                    1
  #define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_ECP_SHIFT))&DMA_DCHPRI6_ECP_MASK)
  /* DCHPRI5 Bit Fields */
  #define DMA_DCHPRI5_CHPRI_MASK                   0xFu
  #define DMA_DCHPRI5_CHPRI_SHIFT                  0
  #define DMA_DCHPRI5_CHPRI_WIDTH                  4
  #define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
  #define DMA_DCHPRI5_DPA_MASK                     0x40u
  #define DMA_DCHPRI5_DPA_SHIFT                    6
  #define DMA_DCHPRI5_DPA_WIDTH                    1
  #define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_DPA_SHIFT))&DMA_DCHPRI5_DPA_MASK)
  #define DMA_DCHPRI5_ECP_MASK                     0x80u
  #define DMA_DCHPRI5_ECP_SHIFT                    7
  #define DMA_DCHPRI5_ECP_WIDTH                    1
  #define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_ECP_SHIFT))&DMA_DCHPRI5_ECP_MASK)
  /* DCHPRI4 Bit Fields */
  #define DMA_DCHPRI4_CHPRI_MASK                   0xFu
  #define DMA_DCHPRI4_CHPRI_SHIFT                  0
  #define DMA_DCHPRI4_CHPRI_WIDTH                  4
  #define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
  #define DMA_DCHPRI4_DPA_MASK                     0x40u
  #define DMA_DCHPRI4_DPA_SHIFT                    6
  #define DMA_DCHPRI4_DPA_WIDTH                    1
  #define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_DPA_SHIFT))&DMA_DCHPRI4_DPA_MASK)
  #define DMA_DCHPRI4_ECP_MASK                     0x80u
  #define DMA_DCHPRI4_ECP_SHIFT                    7
  #define DMA_DCHPRI4_ECP_WIDTH                    1
  #define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_ECP_SHIFT))&DMA_DCHPRI4_ECP_MASK)
  /* DCHPRI11 Bit Fields */
  #define DMA_DCHPRI11_CHPRI_MASK                  0xFu
  #define DMA_DCHPRI11_CHPRI_SHIFT                 0
  #define DMA_DCHPRI11_CHPRI_WIDTH                 4
  #define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
  #define DMA_DCHPRI11_DPA_MASK                    0x40u
  #define DMA_DCHPRI11_DPA_SHIFT                   6
  #define DMA_DCHPRI11_DPA_WIDTH                   1
  #define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_DPA_SHIFT))&DMA_DCHPRI11_DPA_MASK)
  #define DMA_DCHPRI11_ECP_MASK                    0x80u
  #define DMA_DCHPRI11_ECP_SHIFT                   7
  #define DMA_DCHPRI11_ECP_WIDTH                   1
  #define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_ECP_SHIFT))&DMA_DCHPRI11_ECP_MASK)
  /* DCHPRI10 Bit Fields */
  #define DMA_DCHPRI10_CHPRI_MASK                  0xFu
  #define DMA_DCHPRI10_CHPRI_SHIFT                 0
  #define DMA_DCHPRI10_CHPRI_WIDTH                 4
  #define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
  #define DMA_DCHPRI10_DPA_MASK                    0x40u
  #define DMA_DCHPRI10_DPA_SHIFT                   6
  #define DMA_DCHPRI10_DPA_WIDTH                   1
  #define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_DPA_SHIFT))&DMA_DCHPRI10_DPA_MASK)
  #define DMA_DCHPRI10_ECP_MASK                    0x80u
  #define DMA_DCHPRI10_ECP_SHIFT                   7
  #define DMA_DCHPRI10_ECP_WIDTH                   1
  #define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_ECP_SHIFT))&DMA_DCHPRI10_ECP_MASK)
  /* DCHPRI9 Bit Fields */
  #define DMA_DCHPRI9_CHPRI_MASK                   0xFu
  #define DMA_DCHPRI9_CHPRI_SHIFT                  0
  #define DMA_DCHPRI9_CHPRI_WIDTH                  4
  #define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
  #define DMA_DCHPRI9_DPA_MASK                     0x40u
  #define DMA_DCHPRI9_DPA_SHIFT                    6
  #define DMA_DCHPRI9_DPA_WIDTH                    1
  #define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_DPA_SHIFT))&DMA_DCHPRI9_DPA_MASK)
  #define DMA_DCHPRI9_ECP_MASK                     0x80u
  #define DMA_DCHPRI9_ECP_SHIFT                    7
  #define DMA_DCHPRI9_ECP_WIDTH                    1
  #define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_ECP_SHIFT))&DMA_DCHPRI9_ECP_MASK)
  /* DCHPRI8 Bit Fields */
  #define DMA_DCHPRI8_CHPRI_MASK                   0xFu
  #define DMA_DCHPRI8_CHPRI_SHIFT                  0
  #define DMA_DCHPRI8_CHPRI_WIDTH                  4
  #define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
  #define DMA_DCHPRI8_DPA_MASK                     0x40u
  #define DMA_DCHPRI8_DPA_SHIFT                    6
  #define DMA_DCHPRI8_DPA_WIDTH                    1
  #define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_DPA_SHIFT))&DMA_DCHPRI8_DPA_MASK)
  #define DMA_DCHPRI8_ECP_MASK                     0x80u
  #define DMA_DCHPRI8_ECP_SHIFT                    7
  #define DMA_DCHPRI8_ECP_WIDTH                    1
  #define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_ECP_SHIFT))&DMA_DCHPRI8_ECP_MASK)
  /* DCHPRI15 Bit Fields */
  #define DMA_DCHPRI15_CHPRI_MASK                  0xFu
  #define DMA_DCHPRI15_CHPRI_SHIFT                 0
  #define DMA_DCHPRI15_CHPRI_WIDTH                 4
  #define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
  #define DMA_DCHPRI15_DPA_MASK                    0x40u
  #define DMA_DCHPRI15_DPA_SHIFT                   6
  #define DMA_DCHPRI15_DPA_WIDTH                   1
  #define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_DPA_SHIFT))&DMA_DCHPRI15_DPA_MASK)
  #define DMA_DCHPRI15_ECP_MASK                    0x80u
  #define DMA_DCHPRI15_ECP_SHIFT                   7
  #define DMA_DCHPRI15_ECP_WIDTH                   1
  #define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_ECP_SHIFT))&DMA_DCHPRI15_ECP_MASK)
  /* DCHPRI14 Bit Fields */
  #define DMA_DCHPRI14_CHPRI_MASK                  0xFu
  #define DMA_DCHPRI14_CHPRI_SHIFT                 0
  #define DMA_DCHPRI14_CHPRI_WIDTH                 4
  #define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
  #define DMA_DCHPRI14_DPA_MASK                    0x40u
  #define DMA_DCHPRI14_DPA_SHIFT                   6
  #define DMA_DCHPRI14_DPA_WIDTH                   1
  #define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_DPA_SHIFT))&DMA_DCHPRI14_DPA_MASK)
  #define DMA_DCHPRI14_ECP_MASK                    0x80u
  #define DMA_DCHPRI14_ECP_SHIFT                   7
  #define DMA_DCHPRI14_ECP_WIDTH                   1
  #define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_ECP_SHIFT))&DMA_DCHPRI14_ECP_MASK)
  /* DCHPRI13 Bit Fields */
  #define DMA_DCHPRI13_CHPRI_MASK                  0xFu
  #define DMA_DCHPRI13_CHPRI_SHIFT                 0
  #define DMA_DCHPRI13_CHPRI_WIDTH                 4
  #define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
  #define DMA_DCHPRI13_DPA_MASK                    0x40u
  #define DMA_DCHPRI13_DPA_SHIFT                   6
  #define DMA_DCHPRI13_DPA_WIDTH                   1
  #define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_DPA_SHIFT))&DMA_DCHPRI13_DPA_MASK)
  #define DMA_DCHPRI13_ECP_MASK                    0x80u
  #define DMA_DCHPRI13_ECP_SHIFT                   7
  #define DMA_DCHPRI13_ECP_WIDTH                   1
  #define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_ECP_SHIFT))&DMA_DCHPRI13_ECP_MASK)
  /* DCHPRI12 Bit Fields */
  #define DMA_DCHPRI12_CHPRI_MASK                  0xFu
  #define DMA_DCHPRI12_CHPRI_SHIFT                 0
  #define DMA_DCHPRI12_CHPRI_WIDTH                 4
  #define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
  #define DMA_DCHPRI12_DPA_MASK                    0x40u
  #define DMA_DCHPRI12_DPA_SHIFT                   6
  #define DMA_DCHPRI12_DPA_WIDTH                   1
  #define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_DPA_SHIFT))&DMA_DCHPRI12_DPA_MASK)
  #define DMA_DCHPRI12_ECP_MASK                    0x80u
  #define DMA_DCHPRI12_ECP_SHIFT                   7
  #define DMA_DCHPRI12_ECP_WIDTH                   1
  #define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_ECP_SHIFT))&DMA_DCHPRI12_ECP_MASK)
  /* SADDR Bit Fields */
  #define DMA_SADDR_SADDR_MASK                     0xFFFFFFFFu
  #define DMA_SADDR_SADDR_SHIFT                    0
  #define DMA_SADDR_SADDR_WIDTH                    32
  #define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
  /* SOFF Bit Fields */
  #define DMA_SOFF_SOFF_MASK                       0xFFFFu
  #define DMA_SOFF_SOFF_SHIFT                      0
  #define DMA_SOFF_SOFF_WIDTH                      16
  #define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
  /* ATTR Bit Fields */
  #define DMA_ATTR_DSIZE_MASK                      0x7u
  #define DMA_ATTR_DSIZE_SHIFT                     0
  #define DMA_ATTR_DSIZE_WIDTH                     3
  #define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
  #define DMA_ATTR_DMOD_MASK                       0xF8u
  #define DMA_ATTR_DMOD_SHIFT                      3
  #define DMA_ATTR_DMOD_WIDTH                      5
  #define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
  #define DMA_ATTR_SSIZE_MASK                      0x700u
  #define DMA_ATTR_SSIZE_SHIFT                     8
  #define DMA_ATTR_SSIZE_WIDTH                     3
  #define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
  #define DMA_ATTR_SMOD_MASK                       0xF800u
  #define DMA_ATTR_SMOD_SHIFT                      11
  #define DMA_ATTR_SMOD_WIDTH                      5
  #define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
  /* NBYTES_MLNO Bit Fields */
  #define DMA_NBYTES_MLNO_NBYTES_MASK              0xFFFFFFFFu
  #define DMA_NBYTES_MLNO_NBYTES_SHIFT             0
  #define DMA_NBYTES_MLNO_NBYTES_WIDTH             32
  #define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
  /* NBYTES_MLOFFNO Bit Fields */
  #define DMA_NBYTES_MLOFFNO_NBYTES_MASK           0x3FFFFFFFu
  #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          0
  #define DMA_NBYTES_MLOFFNO_NBYTES_WIDTH          30
  #define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
  #define DMA_NBYTES_MLOFFNO_DMLOE_MASK            0x40000000u
  #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           30
  #define DMA_NBYTES_MLOFFNO_DMLOE_WIDTH           1
  #define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_DMLOE_MASK)
  #define DMA_NBYTES_MLOFFNO_SMLOE_MASK            0x80000000u
  #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           31
  #define DMA_NBYTES_MLOFFNO_SMLOE_WIDTH           1
  #define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_NBYTES_MLOFFNO_SMLOE_MASK)
  /* NBYTES_MLOFFYES Bit Fields */
  #define DMA_NBYTES_MLOFFYES_NBYTES_MASK          0x3FFu
  #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         0
  #define DMA_NBYTES_MLOFFYES_NBYTES_WIDTH         10
  #define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
  #define DMA_NBYTES_MLOFFYES_MLOFF_MASK           0x3FFFFC00u
  #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          10
  #define DMA_NBYTES_MLOFFYES_MLOFF_WIDTH          20
  #define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
  #define DMA_NBYTES_MLOFFYES_DMLOE_MASK           0x40000000u
  #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          30
  #define DMA_NBYTES_MLOFFYES_DMLOE_WIDTH          1
  #define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_DMLOE_MASK)
  #define DMA_NBYTES_MLOFFYES_SMLOE_MASK           0x80000000u
  #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          31
  #define DMA_NBYTES_MLOFFYES_SMLOE_WIDTH          1
  #define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_NBYTES_MLOFFYES_SMLOE_MASK)
  /* SLAST Bit Fields */
  #define DMA_SLAST_SLAST_MASK                     0xFFFFFFFFu
  #define DMA_SLAST_SLAST_SHIFT                    0
  #define DMA_SLAST_SLAST_WIDTH                    32
  #define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
  /* DADDR Bit Fields */
  #define DMA_DADDR_DADDR_MASK                     0xFFFFFFFFu
  #define DMA_DADDR_DADDR_SHIFT                    0
  #define DMA_DADDR_DADDR_WIDTH                    32
  #define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
  /* DOFF Bit Fields */
  #define DMA_DOFF_DOFF_MASK                       0xFFFFu
  #define DMA_DOFF_DOFF_SHIFT                      0
  #define DMA_DOFF_DOFF_WIDTH                      16
  #define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
  /* CITER_ELINKNO Bit Fields */
  #define DMA_CITER_ELINKNO_CITER_MASK             0x7FFFu
  #define DMA_CITER_ELINKNO_CITER_SHIFT            0
  #define DMA_CITER_ELINKNO_CITER_WIDTH            15
  #define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
  #define DMA_CITER_ELINKNO_ELINK_MASK             0x8000u
  #define DMA_CITER_ELINKNO_ELINK_SHIFT            15
  #define DMA_CITER_ELINKNO_ELINK_WIDTH            1
  #define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_ELINK_SHIFT))&DMA_CITER_ELINKNO_ELINK_MASK)
  /* CITER_ELINKYES Bit Fields */
  #define DMA_CITER_ELINKYES_CITER_MASK            0x1FFu
  #define DMA_CITER_ELINKYES_CITER_SHIFT           0
  #define DMA_CITER_ELINKYES_CITER_WIDTH           9
  #define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
  #define DMA_CITER_ELINKYES_LINKCH_MASK           0x1E00u
  #define DMA_CITER_ELINKYES_LINKCH_SHIFT          9
  #define DMA_CITER_ELINKYES_LINKCH_WIDTH          4
  #define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
  #define DMA_CITER_ELINKYES_ELINK_MASK            0x8000u
  #define DMA_CITER_ELINKYES_ELINK_SHIFT           15
  #define DMA_CITER_ELINKYES_ELINK_WIDTH           1
  #define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_ELINK_SHIFT))&DMA_CITER_ELINKYES_ELINK_MASK)
  /* DLAST_SGA Bit Fields */
  #define DMA_DLAST_SGA_DLASTSGA_MASK              0xFFFFFFFFu
  #define DMA_DLAST_SGA_DLASTSGA_SHIFT             0
  #define DMA_DLAST_SGA_DLASTSGA_WIDTH             32
  #define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
  /* CSR Bit Fields */
  #define DMA_CSR_START_MASK                       0x1u
  #define DMA_CSR_START_SHIFT                      0
  #define DMA_CSR_START_WIDTH                      1
  #define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_CSR_START_SHIFT))&DMA_CSR_START_MASK)
  #define DMA_CSR_INTMAJOR_MASK                    0x2u
  #define DMA_CSR_INTMAJOR_SHIFT                   1
  #define DMA_CSR_INTMAJOR_WIDTH                   1
  #define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTMAJOR_SHIFT))&DMA_CSR_INTMAJOR_MASK)
  #define DMA_CSR_INTHALF_MASK                     0x4u
  #define DMA_CSR_INTHALF_SHIFT                    2
  #define DMA_CSR_INTHALF_WIDTH                    1
  #define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x))<<DMA_CSR_INTHALF_SHIFT))&DMA_CSR_INTHALF_MASK)
  #define DMA_CSR_DREQ_MASK                        0x8u
  #define DMA_CSR_DREQ_SHIFT                       3
  #define DMA_CSR_DREQ_WIDTH                       1
  #define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DREQ_SHIFT))&DMA_CSR_DREQ_MASK)
  #define DMA_CSR_ESG_MASK                         0x10u
  #define DMA_CSR_ESG_SHIFT                        4
  #define DMA_CSR_ESG_WIDTH                        1
  #define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ESG_SHIFT))&DMA_CSR_ESG_MASK)
  #define DMA_CSR_MAJORELINK_MASK                  0x20u
  #define DMA_CSR_MAJORELINK_SHIFT                 5
  #define DMA_CSR_MAJORELINK_WIDTH                 1
  #define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORELINK_SHIFT))&DMA_CSR_MAJORELINK_MASK)
  #define DMA_CSR_ACTIVE_MASK                      0x40u
  #define DMA_CSR_ACTIVE_SHIFT                     6
  #define DMA_CSR_ACTIVE_WIDTH                     1
  #define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_CSR_ACTIVE_SHIFT))&DMA_CSR_ACTIVE_MASK)
  #define DMA_CSR_DONE_MASK                        0x80u
  #define DMA_CSR_DONE_SHIFT                       7
  #define DMA_CSR_DONE_WIDTH                       1
  #define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x))<<DMA_CSR_DONE_SHIFT))&DMA_CSR_DONE_MASK)
  #define DMA_CSR_MAJORLINKCH_MASK                 0xF00u
  #define DMA_CSR_MAJORLINKCH_SHIFT                8
  #define DMA_CSR_MAJORLINKCH_WIDTH                4
  #define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
  #define DMA_CSR_BWC_MASK                         0xC000u
  #define DMA_CSR_BWC_SHIFT                        14
  #define DMA_CSR_BWC_WIDTH                        2
  #define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
  /* BITER_ELINKNO Bit Fields */
  #define DMA_BITER_ELINKNO_BITER_MASK             0x7FFFu
  #define DMA_BITER_ELINKNO_BITER_SHIFT            0
  #define DMA_BITER_ELINKNO_BITER_WIDTH            15
  #define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
  #define DMA_BITER_ELINKNO_ELINK_MASK             0x8000u
  #define DMA_BITER_ELINKNO_ELINK_SHIFT            15
  #define DMA_BITER_ELINKNO_ELINK_WIDTH            1
  #define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_ELINK_SHIFT))&DMA_BITER_ELINKNO_ELINK_MASK)
  /* BITER_ELINKYES Bit Fields */
  #define DMA_BITER_ELINKYES_BITER_MASK            0x1FFu
  #define DMA_BITER_ELINKYES_BITER_SHIFT           0
  #define DMA_BITER_ELINKYES_BITER_WIDTH           9
  #define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
  #define DMA_BITER_ELINKYES_LINKCH_MASK           0x1E00u
  #define DMA_BITER_ELINKYES_LINKCH_SHIFT          9
  #define DMA_BITER_ELINKYES_LINKCH_WIDTH          4
  #define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
  #define DMA_BITER_ELINKYES_ELINK_MASK            0x8000u
  #define DMA_BITER_ELINKYES_ELINK_SHIFT           15
  #define DMA_BITER_ELINKYES_ELINK_WIDTH           1
  #define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_ELINK_SHIFT))&DMA_BITER_ELINKYES_ELINK_MASK)
  
  /*!
   * @}
   */ /* end of group DMA_Register_Masks */
  
  
  /* DMA - Peripheral instance base addresses */
  /** Peripheral DMA base address */
  #define DMA_BASE                                 (0x40008000u)
  /** Peripheral DMA base pointer */
  #define DMA0                                     ((DMA_Type *)DMA_BASE)
  #define DMA_BASE_PTR                             (DMA0)
  /** Array initializer of DMA peripheral base addresses */
  #define DMA_BASE_ADDRS                           { DMA_BASE }
  /** Array initializer of DMA peripheral base pointers */
  #define DMA_BASE_PTRS                            { DMA0 }
  
  /* ----------------------------------------------------------------------------
     -- DMA - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
   * @{
   */
  
  
  /* DMA - Register instance definitions */
  /* DMA */
  #define DMA_CR                                   DMA_CR_REG(DMA0)
  #define DMA_ES                                   DMA_ES_REG(DMA0)
  #define DMA_ERQ                                  DMA_ERQ_REG(DMA0)
  #define DMA_EEI                                  DMA_EEI_REG(DMA0)
  #define DMA_CEEI                                 DMA_CEEI_REG(DMA0)
  #define DMA_SEEI                                 DMA_SEEI_REG(DMA0)
  #define DMA_CERQ                                 DMA_CERQ_REG(DMA0)
  #define DMA_SERQ                                 DMA_SERQ_REG(DMA0)
  #define DMA_CDNE                                 DMA_CDNE_REG(DMA0)
  #define DMA_SSRT                                 DMA_SSRT_REG(DMA0)
  #define DMA_CERR                                 DMA_CERR_REG(DMA0)
  #define DMA_CINT                                 DMA_CINT_REG(DMA0)
  #define DMA_INT                                  DMA_INT_REG(DMA0)
  #define DMA_ERR                                  DMA_ERR_REG(DMA0)
  #define DMA_HRS                                  DMA_HRS_REG(DMA0)
  #define DMA_EARS                                 DMA_EARS_REG(DMA0)
  #define DMA_DCHPRI3                              DMA_DCHPRI3_REG(DMA0)
  #define DMA_DCHPRI2                              DMA_DCHPRI2_REG(DMA0)
  #define DMA_DCHPRI1                              DMA_DCHPRI1_REG(DMA0)
  #define DMA_DCHPRI0                              DMA_DCHPRI0_REG(DMA0)
  #define DMA_DCHPRI7                              DMA_DCHPRI7_REG(DMA0)
  #define DMA_DCHPRI6                              DMA_DCHPRI6_REG(DMA0)
  #define DMA_DCHPRI5                              DMA_DCHPRI5_REG(DMA0)
  #define DMA_DCHPRI4                              DMA_DCHPRI4_REG(DMA0)
  #define DMA_DCHPRI11                             DMA_DCHPRI11_REG(DMA0)
  #define DMA_DCHPRI10                             DMA_DCHPRI10_REG(DMA0)
  #define DMA_DCHPRI9                              DMA_DCHPRI9_REG(DMA0)
  #define DMA_DCHPRI8                              DMA_DCHPRI8_REG(DMA0)
  #define DMA_DCHPRI15                             DMA_DCHPRI15_REG(DMA0)
  #define DMA_DCHPRI14                             DMA_DCHPRI14_REG(DMA0)
  #define DMA_DCHPRI13                             DMA_DCHPRI13_REG(DMA0)
  #define DMA_DCHPRI12                             DMA_DCHPRI12_REG(DMA0)
  #define DMA_TCD0_SADDR                           DMA_SADDR_REG(DMA0,0)
  #define DMA_TCD0_SOFF                            DMA_SOFF_REG(DMA0,0)
  #define DMA_TCD0_ATTR                            DMA_ATTR_REG(DMA0,0)
  #define DMA_TCD0_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,0)
  #define DMA_TCD0_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,0)
  #define DMA_TCD0_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,0)
  #define DMA_TCD0_SLAST                           DMA_SLAST_REG(DMA0,0)
  #define DMA_TCD0_DADDR                           DMA_DADDR_REG(DMA0,0)
  #define DMA_TCD0_DOFF                            DMA_DOFF_REG(DMA0,0)
  #define DMA_TCD0_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,0)
  #define DMA_TCD0_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,0)
  #define DMA_TCD0_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,0)
  #define DMA_TCD0_CSR                             DMA_CSR_REG(DMA0,0)
  #define DMA_TCD0_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,0)
  #define DMA_TCD0_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,0)
  #define DMA_TCD1_SADDR                           DMA_SADDR_REG(DMA0,1)
  #define DMA_TCD1_SOFF                            DMA_SOFF_REG(DMA0,1)
  #define DMA_TCD1_ATTR                            DMA_ATTR_REG(DMA0,1)
  #define DMA_TCD1_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,1)
  #define DMA_TCD1_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,1)
  #define DMA_TCD1_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,1)
  #define DMA_TCD1_SLAST                           DMA_SLAST_REG(DMA0,1)
  #define DMA_TCD1_DADDR                           DMA_DADDR_REG(DMA0,1)
  #define DMA_TCD1_DOFF                            DMA_DOFF_REG(DMA0,1)
  #define DMA_TCD1_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,1)
  #define DMA_TCD1_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,1)
  #define DMA_TCD1_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,1)
  #define DMA_TCD1_CSR                             DMA_CSR_REG(DMA0,1)
  #define DMA_TCD1_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,1)
  #define DMA_TCD1_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,1)
  #define DMA_TCD2_SADDR                           DMA_SADDR_REG(DMA0,2)
  #define DMA_TCD2_SOFF                            DMA_SOFF_REG(DMA0,2)
  #define DMA_TCD2_ATTR                            DMA_ATTR_REG(DMA0,2)
  #define DMA_TCD2_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,2)
  #define DMA_TCD2_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,2)
  #define DMA_TCD2_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,2)
  #define DMA_TCD2_SLAST                           DMA_SLAST_REG(DMA0,2)
  #define DMA_TCD2_DADDR                           DMA_DADDR_REG(DMA0,2)
  #define DMA_TCD2_DOFF                            DMA_DOFF_REG(DMA0,2)
  #define DMA_TCD2_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,2)
  #define DMA_TCD2_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,2)
  #define DMA_TCD2_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,2)
  #define DMA_TCD2_CSR                             DMA_CSR_REG(DMA0,2)
  #define DMA_TCD2_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,2)
  #define DMA_TCD2_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,2)
  #define DMA_TCD3_SADDR                           DMA_SADDR_REG(DMA0,3)
  #define DMA_TCD3_SOFF                            DMA_SOFF_REG(DMA0,3)
  #define DMA_TCD3_ATTR                            DMA_ATTR_REG(DMA0,3)
  #define DMA_TCD3_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,3)
  #define DMA_TCD3_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,3)
  #define DMA_TCD3_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,3)
  #define DMA_TCD3_SLAST                           DMA_SLAST_REG(DMA0,3)
  #define DMA_TCD3_DADDR                           DMA_DADDR_REG(DMA0,3)
  #define DMA_TCD3_DOFF                            DMA_DOFF_REG(DMA0,3)
  #define DMA_TCD3_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,3)
  #define DMA_TCD3_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,3)
  #define DMA_TCD3_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,3)
  #define DMA_TCD3_CSR                             DMA_CSR_REG(DMA0,3)
  #define DMA_TCD3_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,3)
  #define DMA_TCD3_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,3)
  #define DMA_TCD4_SADDR                           DMA_SADDR_REG(DMA0,4)
  #define DMA_TCD4_SOFF                            DMA_SOFF_REG(DMA0,4)
  #define DMA_TCD4_ATTR                            DMA_ATTR_REG(DMA0,4)
  #define DMA_TCD4_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,4)
  #define DMA_TCD4_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,4)
  #define DMA_TCD4_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,4)
  #define DMA_TCD4_SLAST                           DMA_SLAST_REG(DMA0,4)
  #define DMA_TCD4_DADDR                           DMA_DADDR_REG(DMA0,4)
  #define DMA_TCD4_DOFF                            DMA_DOFF_REG(DMA0,4)
  #define DMA_TCD4_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,4)
  #define DMA_TCD4_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,4)
  #define DMA_TCD4_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,4)
  #define DMA_TCD4_CSR                             DMA_CSR_REG(DMA0,4)
  #define DMA_TCD4_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,4)
  #define DMA_TCD4_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,4)
  #define DMA_TCD5_SADDR                           DMA_SADDR_REG(DMA0,5)
  #define DMA_TCD5_SOFF                            DMA_SOFF_REG(DMA0,5)
  #define DMA_TCD5_ATTR                            DMA_ATTR_REG(DMA0,5)
  #define DMA_TCD5_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,5)
  #define DMA_TCD5_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,5)
  #define DMA_TCD5_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,5)
  #define DMA_TCD5_SLAST                           DMA_SLAST_REG(DMA0,5)
  #define DMA_TCD5_DADDR                           DMA_DADDR_REG(DMA0,5)
  #define DMA_TCD5_DOFF                            DMA_DOFF_REG(DMA0,5)
  #define DMA_TCD5_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,5)
  #define DMA_TCD5_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,5)
  #define DMA_TCD5_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,5)
  #define DMA_TCD5_CSR                             DMA_CSR_REG(DMA0,5)
  #define DMA_TCD5_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,5)
  #define DMA_TCD5_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,5)
  #define DMA_TCD6_SADDR                           DMA_SADDR_REG(DMA0,6)
  #define DMA_TCD6_SOFF                            DMA_SOFF_REG(DMA0,6)
  #define DMA_TCD6_ATTR                            DMA_ATTR_REG(DMA0,6)
  #define DMA_TCD6_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,6)
  #define DMA_TCD6_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,6)
  #define DMA_TCD6_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,6)
  #define DMA_TCD6_SLAST                           DMA_SLAST_REG(DMA0,6)
  #define DMA_TCD6_DADDR                           DMA_DADDR_REG(DMA0,6)
  #define DMA_TCD6_DOFF                            DMA_DOFF_REG(DMA0,6)
  #define DMA_TCD6_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,6)
  #define DMA_TCD6_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,6)
  #define DMA_TCD6_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,6)
  #define DMA_TCD6_CSR                             DMA_CSR_REG(DMA0,6)
  #define DMA_TCD6_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,6)
  #define DMA_TCD6_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,6)
  #define DMA_TCD7_SADDR                           DMA_SADDR_REG(DMA0,7)
  #define DMA_TCD7_SOFF                            DMA_SOFF_REG(DMA0,7)
  #define DMA_TCD7_ATTR                            DMA_ATTR_REG(DMA0,7)
  #define DMA_TCD7_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,7)
  #define DMA_TCD7_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,7)
  #define DMA_TCD7_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,7)
  #define DMA_TCD7_SLAST                           DMA_SLAST_REG(DMA0,7)
  #define DMA_TCD7_DADDR                           DMA_DADDR_REG(DMA0,7)
  #define DMA_TCD7_DOFF                            DMA_DOFF_REG(DMA0,7)
  #define DMA_TCD7_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,7)
  #define DMA_TCD7_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,7)
  #define DMA_TCD7_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,7)
  #define DMA_TCD7_CSR                             DMA_CSR_REG(DMA0,7)
  #define DMA_TCD7_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,7)
  #define DMA_TCD7_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,7)
  #define DMA_TCD8_SADDR                           DMA_SADDR_REG(DMA0,8)
  #define DMA_TCD8_SOFF                            DMA_SOFF_REG(DMA0,8)
  #define DMA_TCD8_ATTR                            DMA_ATTR_REG(DMA0,8)
  #define DMA_TCD8_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,8)
  #define DMA_TCD8_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,8)
  #define DMA_TCD8_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,8)
  #define DMA_TCD8_SLAST                           DMA_SLAST_REG(DMA0,8)
  #define DMA_TCD8_DADDR                           DMA_DADDR_REG(DMA0,8)
  #define DMA_TCD8_DOFF                            DMA_DOFF_REG(DMA0,8)
  #define DMA_TCD8_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,8)
  #define DMA_TCD8_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,8)
  #define DMA_TCD8_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,8)
  #define DMA_TCD8_CSR                             DMA_CSR_REG(DMA0,8)
  #define DMA_TCD8_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,8)
  #define DMA_TCD8_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,8)
  #define DMA_TCD9_SADDR                           DMA_SADDR_REG(DMA0,9)
  #define DMA_TCD9_SOFF                            DMA_SOFF_REG(DMA0,9)
  #define DMA_TCD9_ATTR                            DMA_ATTR_REG(DMA0,9)
  #define DMA_TCD9_NBYTES_MLNO                     DMA_NBYTES_MLNO_REG(DMA0,9)
  #define DMA_TCD9_NBYTES_MLOFFNO                  DMA_NBYTES_MLOFFNO_REG(DMA0,9)
  #define DMA_TCD9_NBYTES_MLOFFYES                 DMA_NBYTES_MLOFFYES_REG(DMA0,9)
  #define DMA_TCD9_SLAST                           DMA_SLAST_REG(DMA0,9)
  #define DMA_TCD9_DADDR                           DMA_DADDR_REG(DMA0,9)
  #define DMA_TCD9_DOFF                            DMA_DOFF_REG(DMA0,9)
  #define DMA_TCD9_CITER_ELINKNO                   DMA_CITER_ELINKNO_REG(DMA0,9)
  #define DMA_TCD9_CITER_ELINKYES                  DMA_CITER_ELINKYES_REG(DMA0,9)
  #define DMA_TCD9_DLASTSGA                        DMA_DLAST_SGA_REG(DMA0,9)
  #define DMA_TCD9_CSR                             DMA_CSR_REG(DMA0,9)
  #define DMA_TCD9_BITER_ELINKNO                   DMA_BITER_ELINKNO_REG(DMA0,9)
  #define DMA_TCD9_BITER_ELINKYES                  DMA_BITER_ELINKYES_REG(DMA0,9)
  #define DMA_TCD10_SADDR                          DMA_SADDR_REG(DMA0,10)
  #define DMA_TCD10_SOFF                           DMA_SOFF_REG(DMA0,10)
  #define DMA_TCD10_ATTR                           DMA_ATTR_REG(DMA0,10)
  #define DMA_TCD10_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,10)
  #define DMA_TCD10_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,10)
  #define DMA_TCD10_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,10)
  #define DMA_TCD10_SLAST                          DMA_SLAST_REG(DMA0,10)
  #define DMA_TCD10_DADDR                          DMA_DADDR_REG(DMA0,10)
  #define DMA_TCD10_DOFF                           DMA_DOFF_REG(DMA0,10)
  #define DMA_TCD10_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,10)
  #define DMA_TCD10_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,10)
  #define DMA_TCD10_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,10)
  #define DMA_TCD10_CSR                            DMA_CSR_REG(DMA0,10)
  #define DMA_TCD10_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,10)
  #define DMA_TCD10_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,10)
  #define DMA_TCD11_SADDR                          DMA_SADDR_REG(DMA0,11)
  #define DMA_TCD11_SOFF                           DMA_SOFF_REG(DMA0,11)
  #define DMA_TCD11_ATTR                           DMA_ATTR_REG(DMA0,11)
  #define DMA_TCD11_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,11)
  #define DMA_TCD11_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,11)
  #define DMA_TCD11_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,11)
  #define DMA_TCD11_SLAST                          DMA_SLAST_REG(DMA0,11)
  #define DMA_TCD11_DADDR                          DMA_DADDR_REG(DMA0,11)
  #define DMA_TCD11_DOFF                           DMA_DOFF_REG(DMA0,11)
  #define DMA_TCD11_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,11)
  #define DMA_TCD11_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,11)
  #define DMA_TCD11_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,11)
  #define DMA_TCD11_CSR                            DMA_CSR_REG(DMA0,11)
  #define DMA_TCD11_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,11)
  #define DMA_TCD11_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,11)
  #define DMA_TCD12_SADDR                          DMA_SADDR_REG(DMA0,12)
  #define DMA_TCD12_SOFF                           DMA_SOFF_REG(DMA0,12)
  #define DMA_TCD12_ATTR                           DMA_ATTR_REG(DMA0,12)
  #define DMA_TCD12_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,12)
  #define DMA_TCD12_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,12)
  #define DMA_TCD12_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,12)
  #define DMA_TCD12_SLAST                          DMA_SLAST_REG(DMA0,12)
  #define DMA_TCD12_DADDR                          DMA_DADDR_REG(DMA0,12)
  #define DMA_TCD12_DOFF                           DMA_DOFF_REG(DMA0,12)
  #define DMA_TCD12_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,12)
  #define DMA_TCD12_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,12)
  #define DMA_TCD12_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,12)
  #define DMA_TCD12_CSR                            DMA_CSR_REG(DMA0,12)
  #define DMA_TCD12_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,12)
  #define DMA_TCD12_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,12)
  #define DMA_TCD13_SADDR                          DMA_SADDR_REG(DMA0,13)
  #define DMA_TCD13_SOFF                           DMA_SOFF_REG(DMA0,13)
  #define DMA_TCD13_ATTR                           DMA_ATTR_REG(DMA0,13)
  #define DMA_TCD13_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,13)
  #define DMA_TCD13_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,13)
  #define DMA_TCD13_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,13)
  #define DMA_TCD13_SLAST                          DMA_SLAST_REG(DMA0,13)
  #define DMA_TCD13_DADDR                          DMA_DADDR_REG(DMA0,13)
  #define DMA_TCD13_DOFF                           DMA_DOFF_REG(DMA0,13)
  #define DMA_TCD13_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,13)
  #define DMA_TCD13_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,13)
  #define DMA_TCD13_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,13)
  #define DMA_TCD13_CSR                            DMA_CSR_REG(DMA0,13)
  #define DMA_TCD13_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,13)
  #define DMA_TCD13_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,13)
  #define DMA_TCD14_SADDR                          DMA_SADDR_REG(DMA0,14)
  #define DMA_TCD14_SOFF                           DMA_SOFF_REG(DMA0,14)
  #define DMA_TCD14_ATTR                           DMA_ATTR_REG(DMA0,14)
  #define DMA_TCD14_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,14)
  #define DMA_TCD14_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,14)
  #define DMA_TCD14_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,14)
  #define DMA_TCD14_SLAST                          DMA_SLAST_REG(DMA0,14)
  #define DMA_TCD14_DADDR                          DMA_DADDR_REG(DMA0,14)
  #define DMA_TCD14_DOFF                           DMA_DOFF_REG(DMA0,14)
  #define DMA_TCD14_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,14)
  #define DMA_TCD14_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,14)
  #define DMA_TCD14_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,14)
  #define DMA_TCD14_CSR                            DMA_CSR_REG(DMA0,14)
  #define DMA_TCD14_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,14)
  #define DMA_TCD14_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,14)
  #define DMA_TCD15_SADDR                          DMA_SADDR_REG(DMA0,15)
  #define DMA_TCD15_SOFF                           DMA_SOFF_REG(DMA0,15)
  #define DMA_TCD15_ATTR                           DMA_ATTR_REG(DMA0,15)
  #define DMA_TCD15_NBYTES_MLNO                    DMA_NBYTES_MLNO_REG(DMA0,15)
  #define DMA_TCD15_NBYTES_MLOFFNO                 DMA_NBYTES_MLOFFNO_REG(DMA0,15)
  #define DMA_TCD15_NBYTES_MLOFFYES                DMA_NBYTES_MLOFFYES_REG(DMA0,15)
  #define DMA_TCD15_SLAST                          DMA_SLAST_REG(DMA0,15)
  #define DMA_TCD15_DADDR                          DMA_DADDR_REG(DMA0,15)
  #define DMA_TCD15_DOFF                           DMA_DOFF_REG(DMA0,15)
  #define DMA_TCD15_CITER_ELINKNO                  DMA_CITER_ELINKNO_REG(DMA0,15)
  #define DMA_TCD15_CITER_ELINKYES                 DMA_CITER_ELINKYES_REG(DMA0,15)
  #define DMA_TCD15_DLASTSGA                       DMA_DLAST_SGA_REG(DMA0,15)
  #define DMA_TCD15_CSR                            DMA_CSR_REG(DMA0,15)
  #define DMA_TCD15_BITER_ELINKNO                  DMA_BITER_ELINKNO_REG(DMA0,15)
  #define DMA_TCD15_BITER_ELINKYES                 DMA_BITER_ELINKYES_REG(DMA0,15)
  
  /* DMA - Register array accessors */
  #define DMA_SADDR(index)                         DMA_SADDR_REG(DMA0,index)
  #define DMA_SOFF(index)                          DMA_SOFF_REG(DMA0,index)
  #define DMA_ATTR(index)                          DMA_ATTR_REG(DMA0,index)
  #define DMA_NBYTES_MLNO(index)                   DMA_NBYTES_MLNO_REG(DMA0,index)
  #define DMA_NBYTES_MLOFFNO(index)                DMA_NBYTES_MLOFFNO_REG(DMA0,index)
  #define DMA_NBYTES_MLOFFYES(index)               DMA_NBYTES_MLOFFYES_REG(DMA0,index)
  #define DMA_SLAST(index)                         DMA_SLAST_REG(DMA0,index)
  #define DMA_DADDR(index)                         DMA_DADDR_REG(DMA0,index)
  #define DMA_DOFF(index)                          DMA_DOFF_REG(DMA0,index)
  #define DMA_CITER_ELINKNO(index)                 DMA_CITER_ELINKNO_REG(DMA0,index)
  #define DMA_CITER_ELINKYES(index)                DMA_CITER_ELINKYES_REG(DMA0,index)
  #define DMA_DLAST_SGA(index)                     DMA_DLAST_SGA_REG(DMA0,index)
  #define DMA_CSR(index)                           DMA_CSR_REG(DMA0,index)
  #define DMA_BITER_ELINKNO(index)                 DMA_BITER_ELINKNO_REG(DMA0,index)
  #define DMA_BITER_ELINKYES(index)                DMA_BITER_ELINKYES_REG(DMA0,index)
  
  /*!
   * @}
   */ /* end of group DMA_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group DMA_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- DMAMUX Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
   * @{
   */
  
  /** DMAMUX - Register Layout Typedef */
  typedef struct {
    __IO uint8_t CHCFG[16];                          /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
  } DMAMUX_Type, *DMAMUX_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- DMAMUX - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
   * @{
   */
  
  
  /* DMAMUX - Register accessors */
  #define DMAMUX_CHCFG_REG(base,index)             ((base)->CHCFG[index])
  #define DMAMUX_CHCFG_COUNT                       16
  
  /*!
   * @}
   */ /* end of group DMAMUX_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- DMAMUX Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
   * @{
   */
  
  /* CHCFG Bit Fields */
  #define DMAMUX_CHCFG_SOURCE_MASK                 0x3Fu
  #define DMAMUX_CHCFG_SOURCE_SHIFT                0
  #define DMAMUX_CHCFG_SOURCE_WIDTH                6
  #define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
  #define DMAMUX_CHCFG_TRIG_MASK                   0x40u
  #define DMAMUX_CHCFG_TRIG_SHIFT                  6
  #define DMAMUX_CHCFG_TRIG_WIDTH                  1
  #define DMAMUX_CHCFG_TRIG(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
  #define DMAMUX_CHCFG_ENBL_MASK                   0x80u
  #define DMAMUX_CHCFG_ENBL_SHIFT                  7
  #define DMAMUX_CHCFG_ENBL_WIDTH                  1
  #define DMAMUX_CHCFG_ENBL(x)                     (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
  
  /*!
   * @}
   */ /* end of group DMAMUX_Register_Masks */
  
  
  /* DMAMUX - Peripheral instance base addresses */
  /** Peripheral DMAMUX base address */
  #define DMAMUX_BASE                              (0x40021000u)
  /** Peripheral DMAMUX base pointer */
  #define DMAMUX                                   ((DMAMUX_Type *)DMAMUX_BASE)
  #define DMAMUX_BASE_PTR                          (DMAMUX)
  /** Array initializer of DMAMUX peripheral base addresses */
  #define DMAMUX_BASE_ADDRS                        { DMAMUX_BASE }
  /** Array initializer of DMAMUX peripheral base pointers */
  #define DMAMUX_BASE_PTRS                         { DMAMUX }
  
  /* ----------------------------------------------------------------------------
     -- DMAMUX - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
   * @{
   */
  
  
  /* DMAMUX - Register instance definitions */
  /* DMAMUX */
  #define DMAMUX_CHCFG0                            DMAMUX_CHCFG_REG(DMAMUX,0)
  #define DMAMUX_CHCFG1                            DMAMUX_CHCFG_REG(DMAMUX,1)
  #define DMAMUX_CHCFG2                            DMAMUX_CHCFG_REG(DMAMUX,2)
  #define DMAMUX_CHCFG3                            DMAMUX_CHCFG_REG(DMAMUX,3)
  #define DMAMUX_CHCFG4                            DMAMUX_CHCFG_REG(DMAMUX,4)
  #define DMAMUX_CHCFG5                            DMAMUX_CHCFG_REG(DMAMUX,5)
  #define DMAMUX_CHCFG6                            DMAMUX_CHCFG_REG(DMAMUX,6)
  #define DMAMUX_CHCFG7                            DMAMUX_CHCFG_REG(DMAMUX,7)
  #define DMAMUX_CHCFG8                            DMAMUX_CHCFG_REG(DMAMUX,8)
  #define DMAMUX_CHCFG9                            DMAMUX_CHCFG_REG(DMAMUX,9)
  #define DMAMUX_CHCFG10                           DMAMUX_CHCFG_REG(DMAMUX,10)
  #define DMAMUX_CHCFG11                           DMAMUX_CHCFG_REG(DMAMUX,11)
  #define DMAMUX_CHCFG12                           DMAMUX_CHCFG_REG(DMAMUX,12)
  #define DMAMUX_CHCFG13                           DMAMUX_CHCFG_REG(DMAMUX,13)
  #define DMAMUX_CHCFG14                           DMAMUX_CHCFG_REG(DMAMUX,14)
  #define DMAMUX_CHCFG15                           DMAMUX_CHCFG_REG(DMAMUX,15)
  
  /* DMAMUX - Register array accessors */
  #define DMAMUX_CHCFG(index)                      DMAMUX_CHCFG_REG(DMAMUX,index)
  
  /*!
   * @}
   */ /* end of group DMAMUX_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group DMAMUX_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- EWM Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
   * @{
   */
  
  /** EWM - Register Layout Typedef */
  typedef struct {
    __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
    __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
    __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
    __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
         uint8_t RESERVED_0[1];
    __IO uint8_t CLKPRESCALER;                       /**< Clock Prescaler Register, offset: 0x5 */
  } EWM_Type, *EWM_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- EWM - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
   * @{
   */
  
  
  /* EWM - Register accessors */
  #define EWM_CTRL_REG(base)                       ((base)->CTRL)
  #define EWM_SERV_REG(base)                       ((base)->SERV)
  #define EWM_CMPL_REG(base)                       ((base)->CMPL)
  #define EWM_CMPH_REG(base)                       ((base)->CMPH)
  #define EWM_CLKPRESCALER_REG(base)               ((base)->CLKPRESCALER)
  
  /*!
   * @}
   */ /* end of group EWM_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- EWM Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup EWM_Register_Masks EWM Register Masks
   * @{
   */
  
  /* CTRL Bit Fields */
  #define EWM_CTRL_EWMEN_MASK                      0x1u
  #define EWM_CTRL_EWMEN_SHIFT                     0
  #define EWM_CTRL_EWMEN_WIDTH                     1
  #define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_EWMEN_SHIFT))&EWM_CTRL_EWMEN_MASK)
  #define EWM_CTRL_ASSIN_MASK                      0x2u
  #define EWM_CTRL_ASSIN_SHIFT                     1
  #define EWM_CTRL_ASSIN_WIDTH                     1
  #define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_ASSIN_SHIFT))&EWM_CTRL_ASSIN_MASK)
  #define EWM_CTRL_INEN_MASK                       0x4u
  #define EWM_CTRL_INEN_SHIFT                      2
  #define EWM_CTRL_INEN_WIDTH                      1
  #define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INEN_SHIFT))&EWM_CTRL_INEN_MASK)
  #define EWM_CTRL_INTEN_MASK                      0x8u
  #define EWM_CTRL_INTEN_SHIFT                     3
  #define EWM_CTRL_INTEN_WIDTH                     1
  #define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INTEN_SHIFT))&EWM_CTRL_INTEN_MASK)
  /* SERV Bit Fields */
  #define EWM_SERV_SERVICE_MASK                    0xFFu
  #define EWM_SERV_SERVICE_SHIFT                   0
  #define EWM_SERV_SERVICE_WIDTH                   8
  #define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
  /* CMPL Bit Fields */
  #define EWM_CMPL_COMPAREL_MASK                   0xFFu
  #define EWM_CMPL_COMPAREL_SHIFT                  0
  #define EWM_CMPL_COMPAREL_WIDTH                  8
  #define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
  /* CMPH Bit Fields */
  #define EWM_CMPH_COMPAREH_MASK                   0xFFu
  #define EWM_CMPH_COMPAREH_SHIFT                  0
  #define EWM_CMPH_COMPAREH_WIDTH                  8
  #define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
  /* CLKPRESCALER Bit Fields */
  #define EWM_CLKPRESCALER_CLK_DIV_MASK            0xFFu
  #define EWM_CLKPRESCALER_CLK_DIV_SHIFT           0
  #define EWM_CLKPRESCALER_CLK_DIV_WIDTH           8
  #define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
  
  /*!
   * @}
   */ /* end of group EWM_Register_Masks */
  
  
  /* EWM - Peripheral instance base addresses */
  /** Peripheral EWM base address */
  #define EWM_BASE                                 (0x40061000u)
  /** Peripheral EWM base pointer */
  #define EWM                                      ((EWM_Type *)EWM_BASE)
  #define EWM_BASE_PTR                             (EWM)
  /** Array initializer of EWM peripheral base addresses */
  #define EWM_BASE_ADDRS                           { EWM_BASE }
  /** Array initializer of EWM peripheral base pointers */
  #define EWM_BASE_PTRS                            { EWM }
  
  /* ----------------------------------------------------------------------------
     -- EWM - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
   * @{
   */
  
  
  /* EWM - Register instance definitions */
  /* EWM */
  #define EWM_CTRL                                 EWM_CTRL_REG(EWM)
  #define EWM_SERV                                 EWM_SERV_REG(EWM)
  #define EWM_CMPL                                 EWM_CMPL_REG(EWM)
  #define EWM_CMPH                                 EWM_CMPH_REG(EWM)
  #define EWM_CLKPRESCALER                         EWM_CLKPRESCALER_REG(EWM)
  
  /*!
   * @}
   */ /* end of group EWM_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group EWM_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- FLEXIO Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
   * @{
   */
  
  /** FLEXIO - Register Layout Typedef */
  typedef struct {
    __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
    __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
    __IO uint32_t CTRL;                              /**< FlexIO Control Register, offset: 0x8 */
    __I  uint32_t PIN;                               /**< Pin State Register, offset: 0xC */
    __IO uint32_t SHIFTSTAT;                         /**< Shifter Status Register, offset: 0x10 */
    __IO uint32_t SHIFTERR;                          /**< Shifter Error Register, offset: 0x14 */
    __IO uint32_t TIMSTAT;                           /**< Timer Status Register, offset: 0x18 */
         uint8_t RESERVED_0[4];
    __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
    __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
    __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable Register, offset: 0x28 */
         uint8_t RESERVED_1[4];
    __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
         uint8_t RESERVED_2[76];
    __IO uint32_t SHIFTCTL[4];                       /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
         uint8_t RESERVED_3[112];
    __IO uint32_t SHIFTCFG[4];                       /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
         uint8_t RESERVED_4[240];
    __IO uint32_t SHIFTBUF[4];                       /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
         uint8_t RESERVED_5[112];
    __IO uint32_t SHIFTBUFBIS[4];                    /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
         uint8_t RESERVED_6[112];
    __IO uint32_t SHIFTBUFBYS[4];                    /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
         uint8_t RESERVED_7[112];
    __IO uint32_t SHIFTBUFBBS[4];                    /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
         uint8_t RESERVED_8[112];
    __IO uint32_t TIMCTL[4];                         /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
         uint8_t RESERVED_9[112];
    __IO uint32_t TIMCFG[4];                         /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
         uint8_t RESERVED_10[112];
    __IO uint32_t TIMCMP[4];                         /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
  } FLEXIO_Type, *FLEXIO_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- FLEXIO - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
   * @{
   */
  
  
  /* FLEXIO - Register accessors */
  #define FLEXIO_VERID_REG(base)                   ((base)->VERID)
  #define FLEXIO_PARAM_REG(base)                   ((base)->PARAM)
  #define FLEXIO_CTRL_REG(base)                    ((base)->CTRL)
  #define FLEXIO_PIN_REG(base)                     ((base)->PIN)
  #define FLEXIO_SHIFTSTAT_REG(base)               ((base)->SHIFTSTAT)
  #define FLEXIO_SHIFTERR_REG(base)                ((base)->SHIFTERR)
  #define FLEXIO_TIMSTAT_REG(base)                 ((base)->TIMSTAT)
  #define FLEXIO_SHIFTSIEN_REG(base)               ((base)->SHIFTSIEN)
  #define FLEXIO_SHIFTEIEN_REG(base)               ((base)->SHIFTEIEN)
  #define FLEXIO_TIMIEN_REG(base)                  ((base)->TIMIEN)
  #define FLEXIO_SHIFTSDEN_REG(base)               ((base)->SHIFTSDEN)
  #define FLEXIO_SHIFTCTL_REG(base,index)          ((base)->SHIFTCTL[index])
  #define FLEXIO_SHIFTCTL_COUNT                    4
  #define FLEXIO_SHIFTCFG_REG(base,index)          ((base)->SHIFTCFG[index])
  #define FLEXIO_SHIFTCFG_COUNT                    4
  #define FLEXIO_SHIFTBUF_REG(base,index)          ((base)->SHIFTBUF[index])
  #define FLEXIO_SHIFTBUF_COUNT                    4
  #define FLEXIO_SHIFTBUFBIS_REG(base,index)       ((base)->SHIFTBUFBIS[index])
  #define FLEXIO_SHIFTBUFBIS_COUNT                 4
  #define FLEXIO_SHIFTBUFBYS_REG(base,index)       ((base)->SHIFTBUFBYS[index])
  #define FLEXIO_SHIFTBUFBYS_COUNT                 4
  #define FLEXIO_SHIFTBUFBBS_REG(base,index)       ((base)->SHIFTBUFBBS[index])
  #define FLEXIO_SHIFTBUFBBS_COUNT                 4
  #define FLEXIO_TIMCTL_REG(base,index)            ((base)->TIMCTL[index])
  #define FLEXIO_TIMCTL_COUNT                      4
  #define FLEXIO_TIMCFG_REG(base,index)            ((base)->TIMCFG[index])
  #define FLEXIO_TIMCFG_COUNT                      4
  #define FLEXIO_TIMCMP_REG(base,index)            ((base)->TIMCMP[index])
  #define FLEXIO_TIMCMP_COUNT                      4
  
  /*!
   * @}
   */ /* end of group FLEXIO_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- FLEXIO Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
   * @{
   */
  
  /* VERID Bit Fields */
  #define FLEXIO_VERID_FEATURE_MASK                0xFFFFu
  #define FLEXIO_VERID_FEATURE_SHIFT               0
  #define FLEXIO_VERID_FEATURE_WIDTH               16
  #define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK)
  #define FLEXIO_VERID_MINOR_MASK                  0xFF0000u
  #define FLEXIO_VERID_MINOR_SHIFT                 16
  #define FLEXIO_VERID_MINOR_WIDTH                 8
  #define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK)
  #define FLEXIO_VERID_MAJOR_MASK                  0xFF000000u
  #define FLEXIO_VERID_MAJOR_SHIFT                 24
  #define FLEXIO_VERID_MAJOR_WIDTH                 8
  #define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK)
  /* PARAM Bit Fields */
  #define FLEXIO_PARAM_SHIFTER_MASK                0xFFu
  #define FLEXIO_PARAM_SHIFTER_SHIFT               0
  #define FLEXIO_PARAM_SHIFTER_WIDTH               8
  #define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK)
  #define FLEXIO_PARAM_TIMER_MASK                  0xFF00u
  #define FLEXIO_PARAM_TIMER_SHIFT                 8
  #define FLEXIO_PARAM_TIMER_WIDTH                 8
  #define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK)
  #define FLEXIO_PARAM_PIN_MASK                    0xFF0000u
  #define FLEXIO_PARAM_PIN_SHIFT                   16
  #define FLEXIO_PARAM_PIN_WIDTH                   8
  #define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK)
  #define FLEXIO_PARAM_TRIGGER_MASK                0xFF000000u
  #define FLEXIO_PARAM_TRIGGER_SHIFT               24
  #define FLEXIO_PARAM_TRIGGER_WIDTH               8
  #define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK)
  /* CTRL Bit Fields */
  #define FLEXIO_CTRL_FLEXEN_MASK                  0x1u
  #define FLEXIO_CTRL_FLEXEN_SHIFT                 0
  #define FLEXIO_CTRL_FLEXEN_WIDTH                 1
  #define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FLEXEN_SHIFT))&FLEXIO_CTRL_FLEXEN_MASK)
  #define FLEXIO_CTRL_SWRST_MASK                   0x2u
  #define FLEXIO_CTRL_SWRST_SHIFT                  1
  #define FLEXIO_CTRL_SWRST_WIDTH                  1
  #define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_SWRST_SHIFT))&FLEXIO_CTRL_SWRST_MASK)
  #define FLEXIO_CTRL_FASTACC_MASK                 0x4u
  #define FLEXIO_CTRL_FASTACC_SHIFT                2
  #define FLEXIO_CTRL_FASTACC_WIDTH                1
  #define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FASTACC_SHIFT))&FLEXIO_CTRL_FASTACC_MASK)
  #define FLEXIO_CTRL_DBGE_MASK                    0x40000000u
  #define FLEXIO_CTRL_DBGE_SHIFT                   30
  #define FLEXIO_CTRL_DBGE_WIDTH                   1
  #define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DBGE_SHIFT))&FLEXIO_CTRL_DBGE_MASK)
  #define FLEXIO_CTRL_DOZEN_MASK                   0x80000000u
  #define FLEXIO_CTRL_DOZEN_SHIFT                  31
  #define FLEXIO_CTRL_DOZEN_WIDTH                  1
  #define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DOZEN_SHIFT))&FLEXIO_CTRL_DOZEN_MASK)
  /* PIN Bit Fields */
  #define FLEXIO_PIN_PDI_MASK                      0xFFu
  #define FLEXIO_PIN_PDI_SHIFT                     0
  #define FLEXIO_PIN_PDI_WIDTH                     8
  #define FLEXIO_PIN_PDI(x)                        (((uint32_t)(((uint32_t)(x))<<FLEXIO_PIN_PDI_SHIFT))&FLEXIO_PIN_PDI_MASK)
  /* SHIFTSTAT Bit Fields */
  #define FLEXIO_SHIFTSTAT_SSF_MASK                0xFu
  #define FLEXIO_SHIFTSTAT_SSF_SHIFT               0
  #define FLEXIO_SHIFTSTAT_SSF_WIDTH               4
  #define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK)
  /* SHIFTERR Bit Fields */
  #define FLEXIO_SHIFTERR_SEF_MASK                 0xFu
  #define FLEXIO_SHIFTERR_SEF_SHIFT                0
  #define FLEXIO_SHIFTERR_SEF_WIDTH                4
  #define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK)
  /* TIMSTAT Bit Fields */
  #define FLEXIO_TIMSTAT_TSF_MASK                  0xFu
  #define FLEXIO_TIMSTAT_TSF_SHIFT                 0
  #define FLEXIO_TIMSTAT_TSF_WIDTH                 4
  #define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK)
  /* SHIFTSIEN Bit Fields */
  #define FLEXIO_SHIFTSIEN_SSIE_MASK               0xFu
  #define FLEXIO_SHIFTSIEN_SSIE_SHIFT              0
  #define FLEXIO_SHIFTSIEN_SSIE_WIDTH              4
  #define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK)
  /* SHIFTEIEN Bit Fields */
  #define FLEXIO_SHIFTEIEN_SEIE_MASK               0xFu
  #define FLEXIO_SHIFTEIEN_SEIE_SHIFT              0
  #define FLEXIO_SHIFTEIEN_SEIE_WIDTH              4
  #define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK)
  /* TIMIEN Bit Fields */
  #define FLEXIO_TIMIEN_TEIE_MASK                  0xFu
  #define FLEXIO_TIMIEN_TEIE_SHIFT                 0
  #define FLEXIO_TIMIEN_TEIE_WIDTH                 4
  #define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK)
  /* SHIFTSDEN Bit Fields */
  #define FLEXIO_SHIFTSDEN_SSDE_MASK               0xFu
  #define FLEXIO_SHIFTSDEN_SSDE_SHIFT              0
  #define FLEXIO_SHIFTSDEN_SSDE_WIDTH              4
  #define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK)
  /* SHIFTCTL Bit Fields */
  #define FLEXIO_SHIFTCTL_SMOD_MASK                0x7u
  #define FLEXIO_SHIFTCTL_SMOD_SHIFT               0
  #define FLEXIO_SHIFTCTL_SMOD_WIDTH               3
  #define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK)
  #define FLEXIO_SHIFTCTL_PINPOL_MASK              0x80u
  #define FLEXIO_SHIFTCTL_PINPOL_SHIFT             7
  #define FLEXIO_SHIFTCTL_PINPOL_WIDTH             1
  #define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINPOL_SHIFT))&FLEXIO_SHIFTCTL_PINPOL_MASK)
  #define FLEXIO_SHIFTCTL_PINSEL_MASK              0x700u
  #define FLEXIO_SHIFTCTL_PINSEL_SHIFT             8
  #define FLEXIO_SHIFTCTL_PINSEL_WIDTH             3
  #define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK)
  #define FLEXIO_SHIFTCTL_PINCFG_MASK              0x30000u
  #define FLEXIO_SHIFTCTL_PINCFG_SHIFT             16
  #define FLEXIO_SHIFTCTL_PINCFG_WIDTH             2
  #define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK)
  #define FLEXIO_SHIFTCTL_TIMPOL_MASK              0x800000u
  #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             23
  #define FLEXIO_SHIFTCTL_TIMPOL_WIDTH             1
  #define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMPOL_SHIFT))&FLEXIO_SHIFTCTL_TIMPOL_MASK)
  #define FLEXIO_SHIFTCTL_TIMSEL_MASK              0x3000000u
  #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             24
  #define FLEXIO_SHIFTCTL_TIMSEL_WIDTH             2
  #define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK)
  /* SHIFTCFG Bit Fields */
  #define FLEXIO_SHIFTCFG_SSTART_MASK              0x3u
  #define FLEXIO_SHIFTCFG_SSTART_SHIFT             0
  #define FLEXIO_SHIFTCFG_SSTART_WIDTH             2
  #define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK)
  #define FLEXIO_SHIFTCFG_SSTOP_MASK               0x30u
  #define FLEXIO_SHIFTCFG_SSTOP_SHIFT              4
  #define FLEXIO_SHIFTCFG_SSTOP_WIDTH              2
  #define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK)
  #define FLEXIO_SHIFTCFG_INSRC_MASK               0x100u
  #define FLEXIO_SHIFTCFG_INSRC_SHIFT              8
  #define FLEXIO_SHIFTCFG_INSRC_WIDTH              1
  #define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_INSRC_SHIFT))&FLEXIO_SHIFTCFG_INSRC_MASK)
  /* SHIFTBUF Bit Fields */
  #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            0xFFFFFFFFu
  #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           0
  #define FLEXIO_SHIFTBUF_SHIFTBUF_WIDTH           32
  #define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
  /* SHIFTBUFBIS Bit Fields */
  #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      0xFFFFFFFFu
  #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     0
  #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_WIDTH     32
  #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
  /* SHIFTBUFBYS Bit Fields */
  #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      0xFFFFFFFFu
  #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     0
  #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_WIDTH     32
  #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
  /* SHIFTBUFBBS Bit Fields */
  #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      0xFFFFFFFFu
  #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     0
  #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_WIDTH     32
  #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
  /* TIMCTL Bit Fields */
  #define FLEXIO_TIMCTL_TIMOD_MASK                 0x3u
  #define FLEXIO_TIMCTL_TIMOD_SHIFT                0
  #define FLEXIO_TIMCTL_TIMOD_WIDTH                2
  #define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK)
  #define FLEXIO_TIMCTL_PINPOL_MASK                0x80u
  #define FLEXIO_TIMCTL_PINPOL_SHIFT               7
  #define FLEXIO_TIMCTL_PINPOL_WIDTH               1
  #define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINPOL_SHIFT))&FLEXIO_TIMCTL_PINPOL_MASK)
  #define FLEXIO_TIMCTL_PINSEL_MASK                0x700u
  #define FLEXIO_TIMCTL_PINSEL_SHIFT               8
  #define FLEXIO_TIMCTL_PINSEL_WIDTH               3
  #define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK)
  #define FLEXIO_TIMCTL_PINCFG_MASK                0x30000u
  #define FLEXIO_TIMCTL_PINCFG_SHIFT               16
  #define FLEXIO_TIMCTL_PINCFG_WIDTH               2
  #define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK)
  #define FLEXIO_TIMCTL_TRGSRC_MASK                0x400000u
  #define FLEXIO_TIMCTL_TRGSRC_SHIFT               22
  #define FLEXIO_TIMCTL_TRGSRC_WIDTH               1
  #define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSRC_SHIFT))&FLEXIO_TIMCTL_TRGSRC_MASK)
  #define FLEXIO_TIMCTL_TRGPOL_MASK                0x800000u
  #define FLEXIO_TIMCTL_TRGPOL_SHIFT               23
  #define FLEXIO_TIMCTL_TRGPOL_WIDTH               1
  #define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGPOL_SHIFT))&FLEXIO_TIMCTL_TRGPOL_MASK)
  #define FLEXIO_TIMCTL_TRGSEL_MASK                0xF000000u
  #define FLEXIO_TIMCTL_TRGSEL_SHIFT               24
  #define FLEXIO_TIMCTL_TRGSEL_WIDTH               4
  #define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK)
  /* TIMCFG Bit Fields */
  #define FLEXIO_TIMCFG_TSTART_MASK                0x2u
  #define FLEXIO_TIMCFG_TSTART_SHIFT               1
  #define FLEXIO_TIMCFG_TSTART_WIDTH               1
  #define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTART_SHIFT))&FLEXIO_TIMCFG_TSTART_MASK)
  #define FLEXIO_TIMCFG_TSTOP_MASK                 0x30u
  #define FLEXIO_TIMCFG_TSTOP_SHIFT                4
  #define FLEXIO_TIMCFG_TSTOP_WIDTH                2
  #define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK)
  #define FLEXIO_TIMCFG_TIMENA_MASK                0x700u
  #define FLEXIO_TIMCFG_TIMENA_SHIFT               8
  #define FLEXIO_TIMCFG_TIMENA_WIDTH               3
  #define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK)
  #define FLEXIO_TIMCFG_TIMDIS_MASK                0x7000u
  #define FLEXIO_TIMCFG_TIMDIS_SHIFT               12
  #define FLEXIO_TIMCFG_TIMDIS_WIDTH               3
  #define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK)
  #define FLEXIO_TIMCFG_TIMRST_MASK                0x70000u
  #define FLEXIO_TIMCFG_TIMRST_SHIFT               16
  #define FLEXIO_TIMCFG_TIMRST_WIDTH               3
  #define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK)
  #define FLEXIO_TIMCFG_TIMDEC_MASK                0x300000u
  #define FLEXIO_TIMCFG_TIMDEC_SHIFT               20
  #define FLEXIO_TIMCFG_TIMDEC_WIDTH               2
  #define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK)
  #define FLEXIO_TIMCFG_TIMOUT_MASK                0x3000000u
  #define FLEXIO_TIMCFG_TIMOUT_SHIFT               24
  #define FLEXIO_TIMCFG_TIMOUT_WIDTH               2
  #define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK)
  /* TIMCMP Bit Fields */
  #define FLEXIO_TIMCMP_CMP_MASK                   0xFFFFu
  #define FLEXIO_TIMCMP_CMP_SHIFT                  0
  #define FLEXIO_TIMCMP_CMP_WIDTH                  16
  #define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK)
  
  /*!
   * @}
   */ /* end of group FLEXIO_Register_Masks */
  
  
  /* FLEXIO - Peripheral instance base addresses */
  /** Peripheral FLEXIO base address */
  #define FLEXIO_BASE                              (0x4005F000u)
  /** Peripheral FLEXIO base pointer */
  #define FLEXIO                                   ((FLEXIO_Type *)FLEXIO_BASE)
  #define FLEXIO_BASE_PTR                          (FLEXIO)
  /** Array initializer of FLEXIO peripheral base addresses */
  #define FLEXIO_BASE_ADDRS                        { FLEXIO_BASE }
  /** Array initializer of FLEXIO peripheral base pointers */
  #define FLEXIO_BASE_PTRS                         { FLEXIO }
  
  /* ----------------------------------------------------------------------------
     -- FLEXIO - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
   * @{
   */
  
  
  /* FLEXIO - Register instance definitions */
  /* FLEXIO */
  #define FLEXIO_VERID                             FLEXIO_VERID_REG(FLEXIO)
  #define FLEXIO_PARAM                             FLEXIO_PARAM_REG(FLEXIO)
  #define FLEXIO_CTRL                              FLEXIO_CTRL_REG(FLEXIO)
  #define FLEXIO_PIN                               FLEXIO_PIN_REG(FLEXIO)
  #define FLEXIO_SHIFTSTAT                         FLEXIO_SHIFTSTAT_REG(FLEXIO)
  #define FLEXIO_SHIFTERR                          FLEXIO_SHIFTERR_REG(FLEXIO)
  #define FLEXIO_TIMSTAT                           FLEXIO_TIMSTAT_REG(FLEXIO)
  #define FLEXIO_SHIFTSIEN                         FLEXIO_SHIFTSIEN_REG(FLEXIO)
  #define FLEXIO_SHIFTEIEN                         FLEXIO_SHIFTEIEN_REG(FLEXIO)
  #define FLEXIO_TIMIEN                            FLEXIO_TIMIEN_REG(FLEXIO)
  #define FLEXIO_SHIFTSDEN                         FLEXIO_SHIFTSDEN_REG(FLEXIO)
  #define FLEXIO_SHIFTCTL0                         FLEXIO_SHIFTCTL_REG(FLEXIO,0)
  #define FLEXIO_SHIFTCTL1                         FLEXIO_SHIFTCTL_REG(FLEXIO,1)
  #define FLEXIO_SHIFTCTL2                         FLEXIO_SHIFTCTL_REG(FLEXIO,2)
  #define FLEXIO_SHIFTCTL3                         FLEXIO_SHIFTCTL_REG(FLEXIO,3)
  #define FLEXIO_SHIFTCFG0                         FLEXIO_SHIFTCFG_REG(FLEXIO,0)
  #define FLEXIO_SHIFTCFG1                         FLEXIO_SHIFTCFG_REG(FLEXIO,1)
  #define FLEXIO_SHIFTCFG2                         FLEXIO_SHIFTCFG_REG(FLEXIO,2)
  #define FLEXIO_SHIFTCFG3                         FLEXIO_SHIFTCFG_REG(FLEXIO,3)
  #define FLEXIO_SHIFTBUF0                         FLEXIO_SHIFTBUF_REG(FLEXIO,0)
  #define FLEXIO_SHIFTBUF1                         FLEXIO_SHIFTBUF_REG(FLEXIO,1)
  #define FLEXIO_SHIFTBUF2                         FLEXIO_SHIFTBUF_REG(FLEXIO,2)
  #define FLEXIO_SHIFTBUF3                         FLEXIO_SHIFTBUF_REG(FLEXIO,3)
  #define FLEXIO_SHIFTBUFBIS0                      FLEXIO_SHIFTBUFBIS_REG(FLEXIO,0)
  #define FLEXIO_SHIFTBUFBIS1                      FLEXIO_SHIFTBUFBIS_REG(FLEXIO,1)
  #define FLEXIO_SHIFTBUFBIS2                      FLEXIO_SHIFTBUFBIS_REG(FLEXIO,2)
  #define FLEXIO_SHIFTBUFBIS3                      FLEXIO_SHIFTBUFBIS_REG(FLEXIO,3)
  #define FLEXIO_SHIFTBUFBYS0                      FLEXIO_SHIFTBUFBYS_REG(FLEXIO,0)
  #define FLEXIO_SHIFTBUFBYS1                      FLEXIO_SHIFTBUFBYS_REG(FLEXIO,1)
  #define FLEXIO_SHIFTBUFBYS2                      FLEXIO_SHIFTBUFBYS_REG(FLEXIO,2)
  #define FLEXIO_SHIFTBUFBYS3                      FLEXIO_SHIFTBUFBYS_REG(FLEXIO,3)
  #define FLEXIO_SHIFTBUFBBS0                      FLEXIO_SHIFTBUFBBS_REG(FLEXIO,0)
  #define FLEXIO_SHIFTBUFBBS1                      FLEXIO_SHIFTBUFBBS_REG(FLEXIO,1)
  #define FLEXIO_SHIFTBUFBBS2                      FLEXIO_SHIFTBUFBBS_REG(FLEXIO,2)
  #define FLEXIO_SHIFTBUFBBS3                      FLEXIO_SHIFTBUFBBS_REG(FLEXIO,3)
  #define FLEXIO_TIMCTL0                           FLEXIO_TIMCTL_REG(FLEXIO,0)
  #define FLEXIO_TIMCTL1                           FLEXIO_TIMCTL_REG(FLEXIO,1)
  #define FLEXIO_TIMCTL2                           FLEXIO_TIMCTL_REG(FLEXIO,2)
  #define FLEXIO_TIMCTL3                           FLEXIO_TIMCTL_REG(FLEXIO,3)
  #define FLEXIO_TIMCFG0                           FLEXIO_TIMCFG_REG(FLEXIO,0)
  #define FLEXIO_TIMCFG1                           FLEXIO_TIMCFG_REG(FLEXIO,1)
  #define FLEXIO_TIMCFG2                           FLEXIO_TIMCFG_REG(FLEXIO,2)
  #define FLEXIO_TIMCFG3                           FLEXIO_TIMCFG_REG(FLEXIO,3)
  #define FLEXIO_TIMCMP0                           FLEXIO_TIMCMP_REG(FLEXIO,0)
  #define FLEXIO_TIMCMP1                           FLEXIO_TIMCMP_REG(FLEXIO,1)
  #define FLEXIO_TIMCMP2                           FLEXIO_TIMCMP_REG(FLEXIO,2)
  #define FLEXIO_TIMCMP3                           FLEXIO_TIMCMP_REG(FLEXIO,3)
  
  /* FLEXIO - Register array accessors */
  #define FLEXIO_SHIFTCTL(index)                   FLEXIO_SHIFTCTL_REG(FLEXIO,index)
  #define FLEXIO_SHIFTCFG(index)                   FLEXIO_SHIFTCFG_REG(FLEXIO,index)
  #define FLEXIO_SHIFTBUF(index)                   FLEXIO_SHIFTBUF_REG(FLEXIO,index)
  #define FLEXIO_SHIFTBUFBIS(index)                FLEXIO_SHIFTBUFBIS_REG(FLEXIO,index)
  #define FLEXIO_SHIFTBUFBYS(index)                FLEXIO_SHIFTBUFBYS_REG(FLEXIO,index)
  #define FLEXIO_SHIFTBUFBBS(index)                FLEXIO_SHIFTBUFBBS_REG(FLEXIO,index)
  #define FLEXIO_TIMCTL(index)                     FLEXIO_TIMCTL_REG(FLEXIO,index)
  #define FLEXIO_TIMCFG(index)                     FLEXIO_TIMCFG_REG(FLEXIO,index)
  #define FLEXIO_TIMCMP(index)                     FLEXIO_TIMCMP_REG(FLEXIO,index)
  
  /*!
   * @}
   */ /* end of group FLEXIO_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group FLEXIO_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- FMC Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
   * @{
   */
  
  /** FMC - Register Layout Typedef */
  typedef struct {
    __IO uint32_t PFAPR;                             /**< Flash Access Protection Register, offset: 0x0 */
    __IO uint32_t PFB0CR;                            /**< Flash Bank 0 Control Register, offset: 0x4 */
    __IO uint32_t PFB1CR;                            /**< Flash Bank 1 Control Register, offset: 0x8 */
         uint8_t RESERVED_0[244];
    __IO uint32_t TAGVDW0S[8];                       /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
    __IO uint32_t TAGVDW1S[8];                       /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
    __IO uint32_t TAGVDW2S[8];                       /**< Cache Tag Storage, array offset: 0x140, array step: 0x4 */
    __IO uint32_t TAGVDW3S[8];                       /**< Cache Tag Storage, array offset: 0x160, array step: 0x4 */
         uint8_t RESERVED_1[128];
    struct {                                         /* offset: 0x200, array step: index*0x40, index2*0x8 */
      __IO uint32_t DATA_U;                            /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
      __IO uint32_t DATA_L;                            /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
    } SET[4][8];
  } FMC_Type, *FMC_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- FMC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
   * @{
   */
  
  
  /* FMC - Register accessors */
  #define FMC_PFAPR_REG(base)                      ((base)->PFAPR)
  #define FMC_PFB0CR_REG(base)                     ((base)->PFB0CR)
  #define FMC_PFB1CR_REG(base)                     ((base)->PFB1CR)
  #define FMC_TAGVDW0S_REG(base,index)             ((base)->TAGVDW0S[index])
  #define FMC_TAGVDW0S_COUNT                       8
  #define FMC_TAGVDW1S_REG(base,index)             ((base)->TAGVDW1S[index])
  #define FMC_TAGVDW1S_COUNT                       8
  #define FMC_TAGVDW2S_REG(base,index)             ((base)->TAGVDW2S[index])
  #define FMC_TAGVDW2S_COUNT                       8
  #define FMC_TAGVDW3S_REG(base,index)             ((base)->TAGVDW3S[index])
  #define FMC_TAGVDW3S_COUNT                       8
  #define FMC_DATA_U_REG(base,index,index2)        ((base)->SET[index][index2].DATA_U)
  #define FMC_DATA_U_COUNT                         4
  #define FMC_DATA_U_COUNT2                        8
  #define FMC_DATA_L_REG(base,index,index2)        ((base)->SET[index][index2].DATA_L)
  #define FMC_DATA_L_COUNT                         4
  #define FMC_DATA_L_COUNT2                        8
  
  /*!
   * @}
   */ /* end of group FMC_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- FMC Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FMC_Register_Masks FMC Register Masks
   * @{
   */
  
  /* PFAPR Bit Fields */
  #define FMC_PFAPR_M0AP_MASK                      0x3u
  #define FMC_PFAPR_M0AP_SHIFT                     0
  #define FMC_PFAPR_M0AP_WIDTH                     2
  #define FMC_PFAPR_M0AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
  #define FMC_PFAPR_M1AP_MASK                      0xCu
  #define FMC_PFAPR_M1AP_SHIFT                     2
  #define FMC_PFAPR_M1AP_WIDTH                     2
  #define FMC_PFAPR_M1AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
  #define FMC_PFAPR_M2AP_MASK                      0x30u
  #define FMC_PFAPR_M2AP_SHIFT                     4
  #define FMC_PFAPR_M2AP_WIDTH                     2
  #define FMC_PFAPR_M2AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
  #define FMC_PFAPR_M3AP_MASK                      0xC0u
  #define FMC_PFAPR_M3AP_SHIFT                     6
  #define FMC_PFAPR_M3AP_WIDTH                     2
  #define FMC_PFAPR_M3AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
  #define FMC_PFAPR_M4AP_MASK                      0x300u
  #define FMC_PFAPR_M4AP_SHIFT                     8
  #define FMC_PFAPR_M4AP_WIDTH                     2
  #define FMC_PFAPR_M4AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
  #define FMC_PFAPR_M5AP_MASK                      0xC00u
  #define FMC_PFAPR_M5AP_SHIFT                     10
  #define FMC_PFAPR_M5AP_WIDTH                     2
  #define FMC_PFAPR_M5AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
  #define FMC_PFAPR_M6AP_MASK                      0x3000u
  #define FMC_PFAPR_M6AP_SHIFT                     12
  #define FMC_PFAPR_M6AP_WIDTH                     2
  #define FMC_PFAPR_M6AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
  #define FMC_PFAPR_M7AP_MASK                      0xC000u
  #define FMC_PFAPR_M7AP_SHIFT                     14
  #define FMC_PFAPR_M7AP_WIDTH                     2
  #define FMC_PFAPR_M7AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
  #define FMC_PFAPR_M0PFD_MASK                     0x10000u
  #define FMC_PFAPR_M0PFD_SHIFT                    16
  #define FMC_PFAPR_M0PFD_WIDTH                    1
  #define FMC_PFAPR_M0PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0PFD_SHIFT))&FMC_PFAPR_M0PFD_MASK)
  #define FMC_PFAPR_M1PFD_MASK                     0x20000u
  #define FMC_PFAPR_M1PFD_SHIFT                    17
  #define FMC_PFAPR_M1PFD_WIDTH                    1
  #define FMC_PFAPR_M1PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1PFD_SHIFT))&FMC_PFAPR_M1PFD_MASK)
  #define FMC_PFAPR_M2PFD_MASK                     0x40000u
  #define FMC_PFAPR_M2PFD_SHIFT                    18
  #define FMC_PFAPR_M2PFD_WIDTH                    1
  #define FMC_PFAPR_M2PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2PFD_SHIFT))&FMC_PFAPR_M2PFD_MASK)
  #define FMC_PFAPR_M3PFD_MASK                     0x80000u
  #define FMC_PFAPR_M3PFD_SHIFT                    19
  #define FMC_PFAPR_M3PFD_WIDTH                    1
  #define FMC_PFAPR_M3PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3PFD_SHIFT))&FMC_PFAPR_M3PFD_MASK)
  #define FMC_PFAPR_M4PFD_MASK                     0x100000u
  #define FMC_PFAPR_M4PFD_SHIFT                    20
  #define FMC_PFAPR_M4PFD_WIDTH                    1
  #define FMC_PFAPR_M4PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4PFD_SHIFT))&FMC_PFAPR_M4PFD_MASK)
  #define FMC_PFAPR_M5PFD_MASK                     0x200000u
  #define FMC_PFAPR_M5PFD_SHIFT                    21
  #define FMC_PFAPR_M5PFD_WIDTH                    1
  #define FMC_PFAPR_M5PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5PFD_SHIFT))&FMC_PFAPR_M5PFD_MASK)
  #define FMC_PFAPR_M6PFD_MASK                     0x400000u
  #define FMC_PFAPR_M6PFD_SHIFT                    22
  #define FMC_PFAPR_M6PFD_WIDTH                    1
  #define FMC_PFAPR_M6PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6PFD_SHIFT))&FMC_PFAPR_M6PFD_MASK)
  #define FMC_PFAPR_M7PFD_MASK                     0x800000u
  #define FMC_PFAPR_M7PFD_SHIFT                    23
  #define FMC_PFAPR_M7PFD_WIDTH                    1
  #define FMC_PFAPR_M7PFD(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7PFD_SHIFT))&FMC_PFAPR_M7PFD_MASK)
  /* PFB0CR Bit Fields */
  #define FMC_PFB0CR_B0SEBE_MASK                   0x1u
  #define FMC_PFB0CR_B0SEBE_SHIFT                  0
  #define FMC_PFB0CR_B0SEBE_WIDTH                  1
  #define FMC_PFB0CR_B0SEBE(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0SEBE_SHIFT))&FMC_PFB0CR_B0SEBE_MASK)
  #define FMC_PFB0CR_B0IPE_MASK                    0x2u
  #define FMC_PFB0CR_B0IPE_SHIFT                   1
  #define FMC_PFB0CR_B0IPE_WIDTH                   1
  #define FMC_PFB0CR_B0IPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0IPE_SHIFT))&FMC_PFB0CR_B0IPE_MASK)
  #define FMC_PFB0CR_B0DPE_MASK                    0x4u
  #define FMC_PFB0CR_B0DPE_SHIFT                   2
  #define FMC_PFB0CR_B0DPE_WIDTH                   1
  #define FMC_PFB0CR_B0DPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DPE_SHIFT))&FMC_PFB0CR_B0DPE_MASK)
  #define FMC_PFB0CR_B0ICE_MASK                    0x8u
  #define FMC_PFB0CR_B0ICE_SHIFT                   3
  #define FMC_PFB0CR_B0ICE_WIDTH                   1
  #define FMC_PFB0CR_B0ICE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0ICE_SHIFT))&FMC_PFB0CR_B0ICE_MASK)
  #define FMC_PFB0CR_B0DCE_MASK                    0x10u
  #define FMC_PFB0CR_B0DCE_SHIFT                   4
  #define FMC_PFB0CR_B0DCE_WIDTH                   1
  #define FMC_PFB0CR_B0DCE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0DCE_SHIFT))&FMC_PFB0CR_B0DCE_MASK)
  #define FMC_PFB0CR_CRC_MASK                      0xE0u
  #define FMC_PFB0CR_CRC_SHIFT                     5
  #define FMC_PFB0CR_CRC_WIDTH                     3
  #define FMC_PFB0CR_CRC(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
  #define FMC_PFB0CR_B0MW_MASK                     0x60000u
  #define FMC_PFB0CR_B0MW_SHIFT                    17
  #define FMC_PFB0CR_B0MW_WIDTH                    2
  #define FMC_PFB0CR_B0MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
  #define FMC_PFB0CR_S_B_INV_MASK                  0x80000u
  #define FMC_PFB0CR_S_B_INV_SHIFT                 19
  #define FMC_PFB0CR_S_B_INV_WIDTH                 1
  #define FMC_PFB0CR_S_B_INV(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_S_B_INV_SHIFT))&FMC_PFB0CR_S_B_INV_MASK)
  #define FMC_PFB0CR_CINV_WAY_MASK                 0xF00000u
  #define FMC_PFB0CR_CINV_WAY_SHIFT                20
  #define FMC_PFB0CR_CINV_WAY_WIDTH                4
  #define FMC_PFB0CR_CINV_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
  #define FMC_PFB0CR_CLCK_WAY_MASK                 0xF000000u
  #define FMC_PFB0CR_CLCK_WAY_SHIFT                24
  #define FMC_PFB0CR_CLCK_WAY_WIDTH                4
  #define FMC_PFB0CR_CLCK_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
  #define FMC_PFB0CR_B0RWSC_MASK                   0xF0000000u
  #define FMC_PFB0CR_B0RWSC_SHIFT                  28
  #define FMC_PFB0CR_B0RWSC_WIDTH                  4
  #define FMC_PFB0CR_B0RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
  /* PFB1CR Bit Fields */
  #define FMC_PFB1CR_B1SEBE_MASK                   0x1u
  #define FMC_PFB1CR_B1SEBE_SHIFT                  0
  #define FMC_PFB1CR_B1SEBE_WIDTH                  1
  #define FMC_PFB1CR_B1SEBE(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1SEBE_SHIFT))&FMC_PFB1CR_B1SEBE_MASK)
  #define FMC_PFB1CR_B1IPE_MASK                    0x2u
  #define FMC_PFB1CR_B1IPE_SHIFT                   1
  #define FMC_PFB1CR_B1IPE_WIDTH                   1
  #define FMC_PFB1CR_B1IPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1IPE_SHIFT))&FMC_PFB1CR_B1IPE_MASK)
  #define FMC_PFB1CR_B1DPE_MASK                    0x4u
  #define FMC_PFB1CR_B1DPE_SHIFT                   2
  #define FMC_PFB1CR_B1DPE_WIDTH                   1
  #define FMC_PFB1CR_B1DPE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DPE_SHIFT))&FMC_PFB1CR_B1DPE_MASK)
  #define FMC_PFB1CR_B1ICE_MASK                    0x8u
  #define FMC_PFB1CR_B1ICE_SHIFT                   3
  #define FMC_PFB1CR_B1ICE_WIDTH                   1
  #define FMC_PFB1CR_B1ICE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1ICE_SHIFT))&FMC_PFB1CR_B1ICE_MASK)
  #define FMC_PFB1CR_B1DCE_MASK                    0x10u
  #define FMC_PFB1CR_B1DCE_SHIFT                   4
  #define FMC_PFB1CR_B1DCE_WIDTH                   1
  #define FMC_PFB1CR_B1DCE(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1DCE_SHIFT))&FMC_PFB1CR_B1DCE_MASK)
  #define FMC_PFB1CR_B1MW_MASK                     0x60000u
  #define FMC_PFB1CR_B1MW_SHIFT                    17
  #define FMC_PFB1CR_B1MW_WIDTH                    2
  #define FMC_PFB1CR_B1MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
  #define FMC_PFB1CR_B1RWSC_MASK                   0xF0000000u
  #define FMC_PFB1CR_B1RWSC_SHIFT                  28
  #define FMC_PFB1CR_B1RWSC_WIDTH                  4
  #define FMC_PFB1CR_B1RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
  /* TAGVDW0S Bit Fields */
  #define FMC_TAGVDW0S_valid_MASK                  0x1u
  #define FMC_TAGVDW0S_valid_SHIFT                 0
  #define FMC_TAGVDW0S_valid_WIDTH                 1
  #define FMC_TAGVDW0S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_valid_SHIFT))&FMC_TAGVDW0S_valid_MASK)
  #define FMC_TAGVDW0S_tag_MASK                    0x7FFE0u
  #define FMC_TAGVDW0S_tag_SHIFT                   5
  #define FMC_TAGVDW0S_tag_WIDTH                   14
  #define FMC_TAGVDW0S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
  /* TAGVDW1S Bit Fields */
  #define FMC_TAGVDW1S_valid_MASK                  0x1u
  #define FMC_TAGVDW1S_valid_SHIFT                 0
  #define FMC_TAGVDW1S_valid_WIDTH                 1
  #define FMC_TAGVDW1S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_valid_SHIFT))&FMC_TAGVDW1S_valid_MASK)
  #define FMC_TAGVDW1S_tag_MASK                    0x7FFE0u
  #define FMC_TAGVDW1S_tag_SHIFT                   5
  #define FMC_TAGVDW1S_tag_WIDTH                   14
  #define FMC_TAGVDW1S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
  /* TAGVDW2S Bit Fields */
  #define FMC_TAGVDW2S_valid_MASK                  0x1u
  #define FMC_TAGVDW2S_valid_SHIFT                 0
  #define FMC_TAGVDW2S_valid_WIDTH                 1
  #define FMC_TAGVDW2S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_valid_SHIFT))&FMC_TAGVDW2S_valid_MASK)
  #define FMC_TAGVDW2S_tag_MASK                    0x7FFE0u
  #define FMC_TAGVDW2S_tag_SHIFT                   5
  #define FMC_TAGVDW2S_tag_WIDTH                   14
  #define FMC_TAGVDW2S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
  /* TAGVDW3S Bit Fields */
  #define FMC_TAGVDW3S_valid_MASK                  0x1u
  #define FMC_TAGVDW3S_valid_SHIFT                 0
  #define FMC_TAGVDW3S_valid_WIDTH                 1
  #define FMC_TAGVDW3S_valid(x)                    (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_valid_SHIFT))&FMC_TAGVDW3S_valid_MASK)
  #define FMC_TAGVDW3S_tag_MASK                    0x7FFE0u
  #define FMC_TAGVDW3S_tag_SHIFT                   5
  #define FMC_TAGVDW3S_tag_WIDTH                   14
  #define FMC_TAGVDW3S_tag(x)                      (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
  /* DATA_U Bit Fields */
  #define FMC_DATA_U_data_MASK                     0xFFFFFFFFu
  #define FMC_DATA_U_data_SHIFT                    0
  #define FMC_DATA_U_data_WIDTH                    32
  #define FMC_DATA_U_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
  /* DATA_L Bit Fields */
  #define FMC_DATA_L_data_MASK                     0xFFFFFFFFu
  #define FMC_DATA_L_data_SHIFT                    0
  #define FMC_DATA_L_data_WIDTH                    32
  #define FMC_DATA_L_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
  
  /*!
   * @}
   */ /* end of group FMC_Register_Masks */
  
  
  /* FMC - Peripheral instance base addresses */
  /** Peripheral FMC base address */
  #define FMC_BASE                                 (0x4001F000u)
  /** Peripheral FMC base pointer */
  #define FMC                                      ((FMC_Type *)FMC_BASE)
  #define FMC_BASE_PTR                             (FMC)
  /** Array initializer of FMC peripheral base addresses */
  #define FMC_BASE_ADDRS                           { FMC_BASE }
  /** Array initializer of FMC peripheral base pointers */
  #define FMC_BASE_PTRS                            { FMC }
  
  /* ----------------------------------------------------------------------------
     -- FMC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
   * @{
   */
  
  
  /* FMC - Register instance definitions */
  /* FMC */
  #define FMC_PFAPR                                FMC_PFAPR_REG(FMC)
  #define FMC_PFB0CR                               FMC_PFB0CR_REG(FMC)
  #define FMC_PFB1CR                               FMC_PFB1CR_REG(FMC)
  #define FMC_TAGVDW0S0                            FMC_TAGVDW0S_REG(FMC,0)
  #define FMC_TAGVDW0S1                            FMC_TAGVDW0S_REG(FMC,1)
  #define FMC_TAGVDW0S2                            FMC_TAGVDW0S_REG(FMC,2)
  #define FMC_TAGVDW0S3                            FMC_TAGVDW0S_REG(FMC,3)
  #define FMC_TAGVDW0S4                            FMC_TAGVDW0S_REG(FMC,4)
  #define FMC_TAGVDW0S5                            FMC_TAGVDW0S_REG(FMC,5)
  #define FMC_TAGVDW0S6                            FMC_TAGVDW0S_REG(FMC,6)
  #define FMC_TAGVDW0S7                            FMC_TAGVDW0S_REG(FMC,7)
  #define FMC_TAGVDW1S0                            FMC_TAGVDW1S_REG(FMC,0)
  #define FMC_TAGVDW1S1                            FMC_TAGVDW1S_REG(FMC,1)
  #define FMC_TAGVDW1S2                            FMC_TAGVDW1S_REG(FMC,2)
  #define FMC_TAGVDW1S3                            FMC_TAGVDW1S_REG(FMC,3)
  #define FMC_TAGVDW1S4                            FMC_TAGVDW1S_REG(FMC,4)
  #define FMC_TAGVDW1S5                            FMC_TAGVDW1S_REG(FMC,5)
  #define FMC_TAGVDW1S6                            FMC_TAGVDW1S_REG(FMC,6)
  #define FMC_TAGVDW1S7                            FMC_TAGVDW1S_REG(FMC,7)
  #define FMC_TAGVDW2S0                            FMC_TAGVDW2S_REG(FMC,0)
  #define FMC_TAGVDW2S1                            FMC_TAGVDW2S_REG(FMC,1)
  #define FMC_TAGVDW2S2                            FMC_TAGVDW2S_REG(FMC,2)
  #define FMC_TAGVDW2S3                            FMC_TAGVDW2S_REG(FMC,3)
  #define FMC_TAGVDW2S4                            FMC_TAGVDW2S_REG(FMC,4)
  #define FMC_TAGVDW2S5                            FMC_TAGVDW2S_REG(FMC,5)
  #define FMC_TAGVDW2S6                            FMC_TAGVDW2S_REG(FMC,6)
  #define FMC_TAGVDW2S7                            FMC_TAGVDW2S_REG(FMC,7)
  #define FMC_TAGVDW3S0                            FMC_TAGVDW3S_REG(FMC,0)
  #define FMC_TAGVDW3S1                            FMC_TAGVDW3S_REG(FMC,1)
  #define FMC_TAGVDW3S2                            FMC_TAGVDW3S_REG(FMC,2)
  #define FMC_TAGVDW3S3                            FMC_TAGVDW3S_REG(FMC,3)
  #define FMC_TAGVDW3S4                            FMC_TAGVDW3S_REG(FMC,4)
  #define FMC_TAGVDW3S5                            FMC_TAGVDW3S_REG(FMC,5)
  #define FMC_TAGVDW3S6                            FMC_TAGVDW3S_REG(FMC,6)
  #define FMC_TAGVDW3S7                            FMC_TAGVDW3S_REG(FMC,7)
  #define FMC_DATAW0S0U                            FMC_DATA_U_REG(FMC,0,0)
  #define FMC_DATAW0S0L                            FMC_DATA_L_REG(FMC,0,0)
  #define FMC_DATAW0S1U                            FMC_DATA_U_REG(FMC,0,1)
  #define FMC_DATAW0S1L                            FMC_DATA_L_REG(FMC,0,1)
  #define FMC_DATAW0S2U                            FMC_DATA_U_REG(FMC,0,2)
  #define FMC_DATAW0S2L                            FMC_DATA_L_REG(FMC,0,2)
  #define FMC_DATAW0S3U                            FMC_DATA_U_REG(FMC,0,3)
  #define FMC_DATAW0S3L                            FMC_DATA_L_REG(FMC,0,3)
  #define FMC_DATAW0S4U                            FMC_DATA_U_REG(FMC,0,4)
  #define FMC_DATAW0S4L                            FMC_DATA_L_REG(FMC,0,4)
  #define FMC_DATAW0S5U                            FMC_DATA_U_REG(FMC,0,5)
  #define FMC_DATAW0S5L                            FMC_DATA_L_REG(FMC,0,5)
  #define FMC_DATAW0S6U                            FMC_DATA_U_REG(FMC,0,6)
  #define FMC_DATAW0S6L                            FMC_DATA_L_REG(FMC,0,6)
  #define FMC_DATAW0S7U                            FMC_DATA_U_REG(FMC,0,7)
  #define FMC_DATAW0S7L                            FMC_DATA_L_REG(FMC,0,7)
  #define FMC_DATAW1S0U                            FMC_DATA_U_REG(FMC,1,0)
  #define FMC_DATAW1S0L                            FMC_DATA_L_REG(FMC,1,0)
  #define FMC_DATAW1S1U                            FMC_DATA_U_REG(FMC,1,1)
  #define FMC_DATAW1S1L                            FMC_DATA_L_REG(FMC,1,1)
  #define FMC_DATAW1S2U                            FMC_DATA_U_REG(FMC,1,2)
  #define FMC_DATAW1S2L                            FMC_DATA_L_REG(FMC,1,2)
  #define FMC_DATAW1S3U                            FMC_DATA_U_REG(FMC,1,3)
  #define FMC_DATAW1S3L                            FMC_DATA_L_REG(FMC,1,3)
  #define FMC_DATAW1S4U                            FMC_DATA_U_REG(FMC,1,4)
  #define FMC_DATAW1S4L                            FMC_DATA_L_REG(FMC,1,4)
  #define FMC_DATAW1S5U                            FMC_DATA_U_REG(FMC,1,5)
  #define FMC_DATAW1S5L                            FMC_DATA_L_REG(FMC,1,5)
  #define FMC_DATAW1S6U                            FMC_DATA_U_REG(FMC,1,6)
  #define FMC_DATAW1S6L                            FMC_DATA_L_REG(FMC,1,6)
  #define FMC_DATAW1S7U                            FMC_DATA_U_REG(FMC,1,7)
  #define FMC_DATAW1S7L                            FMC_DATA_L_REG(FMC,1,7)
  #define FMC_DATAW2S0U                            FMC_DATA_U_REG(FMC,2,0)
  #define FMC_DATAW2S0L                            FMC_DATA_L_REG(FMC,2,0)
  #define FMC_DATAW2S1U                            FMC_DATA_U_REG(FMC,2,1)
  #define FMC_DATAW2S1L                            FMC_DATA_L_REG(FMC,2,1)
  #define FMC_DATAW2S2U                            FMC_DATA_U_REG(FMC,2,2)
  #define FMC_DATAW2S2L                            FMC_DATA_L_REG(FMC,2,2)
  #define FMC_DATAW2S3U                            FMC_DATA_U_REG(FMC,2,3)
  #define FMC_DATAW2S3L                            FMC_DATA_L_REG(FMC,2,3)
  #define FMC_DATAW2S4U                            FMC_DATA_U_REG(FMC,2,4)
  #define FMC_DATAW2S4L                            FMC_DATA_L_REG(FMC,2,4)
  #define FMC_DATAW2S5U                            FMC_DATA_U_REG(FMC,2,5)
  #define FMC_DATAW2S5L                            FMC_DATA_L_REG(FMC,2,5)
  #define FMC_DATAW2S6U                            FMC_DATA_U_REG(FMC,2,6)
  #define FMC_DATAW2S6L                            FMC_DATA_L_REG(FMC,2,6)
  #define FMC_DATAW2S7U                            FMC_DATA_U_REG(FMC,2,7)
  #define FMC_DATAW2S7L                            FMC_DATA_L_REG(FMC,2,7)
  #define FMC_DATAW3S0U                            FMC_DATA_U_REG(FMC,3,0)
  #define FMC_DATAW3S0L                            FMC_DATA_L_REG(FMC,3,0)
  #define FMC_DATAW3S1U                            FMC_DATA_U_REG(FMC,3,1)
  #define FMC_DATAW3S1L                            FMC_DATA_L_REG(FMC,3,1)
  #define FMC_DATAW3S2U                            FMC_DATA_U_REG(FMC,3,2)
  #define FMC_DATAW3S2L                            FMC_DATA_L_REG(FMC,3,2)
  #define FMC_DATAW3S3U                            FMC_DATA_U_REG(FMC,3,3)
  #define FMC_DATAW3S3L                            FMC_DATA_L_REG(FMC,3,3)
  #define FMC_DATAW3S4U                            FMC_DATA_U_REG(FMC,3,4)
  #define FMC_DATAW3S4L                            FMC_DATA_L_REG(FMC,3,4)
  #define FMC_DATAW3S5U                            FMC_DATA_U_REG(FMC,3,5)
  #define FMC_DATAW3S5L                            FMC_DATA_L_REG(FMC,3,5)
  #define FMC_DATAW3S6U                            FMC_DATA_U_REG(FMC,3,6)
  #define FMC_DATAW3S6L                            FMC_DATA_L_REG(FMC,3,6)
  #define FMC_DATAW3S7U                            FMC_DATA_U_REG(FMC,3,7)
  #define FMC_DATAW3S7L                            FMC_DATA_L_REG(FMC,3,7)
  
  /* FMC - Register array accessors */
  #define FMC_TAGVDW0S(index)                      FMC_TAGVDW0S_REG(FMC,index)
  #define FMC_TAGVDW1S(index)                      FMC_TAGVDW1S_REG(FMC,index)
  #define FMC_TAGVDW2S(index)                      FMC_TAGVDW2S_REG(FMC,index)
  #define FMC_TAGVDW3S(index)                      FMC_TAGVDW3S_REG(FMC,index)
  #define FMC_DATA_U(index,index2)                 FMC_DATA_U_REG(FMC,index,index2)
  #define FMC_DATA_L(index,index2)                 FMC_DATA_L_REG(FMC,index,index2)
  
  /*!
   * @}
   */ /* end of group FMC_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group FMC_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- FTFA Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
   * @{
   */
  
  /** FTFA - Register Layout Typedef */
  typedef struct {
    __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
    __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
    __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
    __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
    __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
    __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
    __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
    __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
    __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
    __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
    __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
    __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
    __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
    __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
    __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
    __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
    __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
    __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
    __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
    __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
         uint8_t RESERVED_0[4];
    __I  uint8_t XACCH3;                             /**< Execute-only Access Registers, offset: 0x18 */
    __I  uint8_t XACCH2;                             /**< Execute-only Access Registers, offset: 0x19 */
    __I  uint8_t XACCH1;                             /**< Execute-only Access Registers, offset: 0x1A */
    __I  uint8_t XACCH0;                             /**< Execute-only Access Registers, offset: 0x1B */
    __I  uint8_t XACCL3;                             /**< Execute-only Access Registers, offset: 0x1C */
    __I  uint8_t XACCL2;                             /**< Execute-only Access Registers, offset: 0x1D */
    __I  uint8_t XACCL1;                             /**< Execute-only Access Registers, offset: 0x1E */
    __I  uint8_t XACCL0;                             /**< Execute-only Access Registers, offset: 0x1F */
    __I  uint8_t SACCH3;                             /**< Supervisor-only Access Registers, offset: 0x20 */
    __I  uint8_t SACCH2;                             /**< Supervisor-only Access Registers, offset: 0x21 */
    __I  uint8_t SACCH1;                             /**< Supervisor-only Access Registers, offset: 0x22 */
    __I  uint8_t SACCH0;                             /**< Supervisor-only Access Registers, offset: 0x23 */
    __I  uint8_t SACCL3;                             /**< Supervisor-only Access Registers, offset: 0x24 */
    __I  uint8_t SACCL2;                             /**< Supervisor-only Access Registers, offset: 0x25 */
    __I  uint8_t SACCL1;                             /**< Supervisor-only Access Registers, offset: 0x26 */
    __I  uint8_t SACCL0;                             /**< Supervisor-only Access Registers, offset: 0x27 */
    __I  uint8_t FACSS;                              /**< Flash Access Segment Size Register, offset: 0x28 */
         uint8_t RESERVED_1[2];
    __I  uint8_t FACSN;                              /**< Flash Access Segment Number Register, offset: 0x2B */
  } FTFA_Type, *FTFA_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- FTFA - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
   * @{
   */
  
  
  /* FTFA - Register accessors */
  #define FTFA_FSTAT_REG(base)                     ((base)->FSTAT)
  #define FTFA_FCNFG_REG(base)                     ((base)->FCNFG)
  #define FTFA_FSEC_REG(base)                      ((base)->FSEC)
  #define FTFA_FOPT_REG(base)                      ((base)->FOPT)
  #define FTFA_FCCOB3_REG(base)                    ((base)->FCCOB3)
  #define FTFA_FCCOB2_REG(base)                    ((base)->FCCOB2)
  #define FTFA_FCCOB1_REG(base)                    ((base)->FCCOB1)
  #define FTFA_FCCOB0_REG(base)                    ((base)->FCCOB0)
  #define FTFA_FCCOB7_REG(base)                    ((base)->FCCOB7)
  #define FTFA_FCCOB6_REG(base)                    ((base)->FCCOB6)
  #define FTFA_FCCOB5_REG(base)                    ((base)->FCCOB5)
  #define FTFA_FCCOB4_REG(base)                    ((base)->FCCOB4)
  #define FTFA_FCCOBB_REG(base)                    ((base)->FCCOBB)
  #define FTFA_FCCOBA_REG(base)                    ((base)->FCCOBA)
  #define FTFA_FCCOB9_REG(base)                    ((base)->FCCOB9)
  #define FTFA_FCCOB8_REG(base)                    ((base)->FCCOB8)
  #define FTFA_FPROT3_REG(base)                    ((base)->FPROT3)
  #define FTFA_FPROT2_REG(base)                    ((base)->FPROT2)
  #define FTFA_FPROT1_REG(base)                    ((base)->FPROT1)
  #define FTFA_FPROT0_REG(base)                    ((base)->FPROT0)
  #define FTFA_XACCH3_REG(base)                    ((base)->XACCH3)
  #define FTFA_XACCH2_REG(base)                    ((base)->XACCH2)
  #define FTFA_XACCH1_REG(base)                    ((base)->XACCH1)
  #define FTFA_XACCH0_REG(base)                    ((base)->XACCH0)
  #define FTFA_XACCL3_REG(base)                    ((base)->XACCL3)
  #define FTFA_XACCL2_REG(base)                    ((base)->XACCL2)
  #define FTFA_XACCL1_REG(base)                    ((base)->XACCL1)
  #define FTFA_XACCL0_REG(base)                    ((base)->XACCL0)
  #define FTFA_SACCH3_REG(base)                    ((base)->SACCH3)
  #define FTFA_SACCH2_REG(base)                    ((base)->SACCH2)
  #define FTFA_SACCH1_REG(base)                    ((base)->SACCH1)
  #define FTFA_SACCH0_REG(base)                    ((base)->SACCH0)
  #define FTFA_SACCL3_REG(base)                    ((base)->SACCL3)
  #define FTFA_SACCL2_REG(base)                    ((base)->SACCL2)
  #define FTFA_SACCL1_REG(base)                    ((base)->SACCL1)
  #define FTFA_SACCL0_REG(base)                    ((base)->SACCL0)
  #define FTFA_FACSS_REG(base)                     ((base)->FACSS)
  #define FTFA_FACSN_REG(base)                     ((base)->FACSN)
  
  /*!
   * @}
   */ /* end of group FTFA_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- FTFA Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FTFA_Register_Masks FTFA Register Masks
   * @{
   */
  
  /* FSTAT Bit Fields */
  #define FTFA_FSTAT_MGSTAT0_MASK                  0x1u
  #define FTFA_FSTAT_MGSTAT0_SHIFT                 0
  #define FTFA_FSTAT_MGSTAT0_WIDTH                 1
  #define FTFA_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_MGSTAT0_SHIFT))&FTFA_FSTAT_MGSTAT0_MASK)
  #define FTFA_FSTAT_FPVIOL_MASK                   0x10u
  #define FTFA_FSTAT_FPVIOL_SHIFT                  4
  #define FTFA_FSTAT_FPVIOL_WIDTH                  1
  #define FTFA_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_FPVIOL_SHIFT))&FTFA_FSTAT_FPVIOL_MASK)
  #define FTFA_FSTAT_ACCERR_MASK                   0x20u
  #define FTFA_FSTAT_ACCERR_SHIFT                  5
  #define FTFA_FSTAT_ACCERR_WIDTH                  1
  #define FTFA_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_ACCERR_SHIFT))&FTFA_FSTAT_ACCERR_MASK)
  #define FTFA_FSTAT_RDCOLERR_MASK                 0x40u
  #define FTFA_FSTAT_RDCOLERR_SHIFT                6
  #define FTFA_FSTAT_RDCOLERR_WIDTH                1
  #define FTFA_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_RDCOLERR_SHIFT))&FTFA_FSTAT_RDCOLERR_MASK)
  #define FTFA_FSTAT_CCIF_MASK                     0x80u
  #define FTFA_FSTAT_CCIF_SHIFT                    7
  #define FTFA_FSTAT_CCIF_WIDTH                    1
  #define FTFA_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x))<<FTFA_FSTAT_CCIF_SHIFT))&FTFA_FSTAT_CCIF_MASK)
  /* FCNFG Bit Fields */
  #define FTFA_FCNFG_ERSSUSP_MASK                  0x10u
  #define FTFA_FCNFG_ERSSUSP_SHIFT                 4
  #define FTFA_FCNFG_ERSSUSP_WIDTH                 1
  #define FTFA_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_ERSSUSP_SHIFT))&FTFA_FCNFG_ERSSUSP_MASK)
  #define FTFA_FCNFG_ERSAREQ_MASK                  0x20u
  #define FTFA_FCNFG_ERSAREQ_SHIFT                 5
  #define FTFA_FCNFG_ERSAREQ_WIDTH                 1
  #define FTFA_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_ERSAREQ_SHIFT))&FTFA_FCNFG_ERSAREQ_MASK)
  #define FTFA_FCNFG_RDCOLLIE_MASK                 0x40u
  #define FTFA_FCNFG_RDCOLLIE_SHIFT                6
  #define FTFA_FCNFG_RDCOLLIE_WIDTH                1
  #define FTFA_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_RDCOLLIE_SHIFT))&FTFA_FCNFG_RDCOLLIE_MASK)
  #define FTFA_FCNFG_CCIE_MASK                     0x80u
  #define FTFA_FCNFG_CCIE_SHIFT                    7
  #define FTFA_FCNFG_CCIE_WIDTH                    1
  #define FTFA_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x))<<FTFA_FCNFG_CCIE_SHIFT))&FTFA_FCNFG_CCIE_MASK)
  /* FSEC Bit Fields */
  #define FTFA_FSEC_SEC_MASK                       0x3u
  #define FTFA_FSEC_SEC_SHIFT                      0
  #define FTFA_FSEC_SEC_WIDTH                      2
  #define FTFA_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
  #define FTFA_FSEC_FSLACC_MASK                    0xCu
  #define FTFA_FSEC_FSLACC_SHIFT                   2
  #define FTFA_FSEC_FSLACC_WIDTH                   2
  #define FTFA_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
  #define FTFA_FSEC_MEEN_MASK                      0x30u
  #define FTFA_FSEC_MEEN_SHIFT                     4
  #define FTFA_FSEC_MEEN_WIDTH                     2
  #define FTFA_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
  #define FTFA_FSEC_KEYEN_MASK                     0xC0u
  #define FTFA_FSEC_KEYEN_SHIFT                    6
  #define FTFA_FSEC_KEYEN_WIDTH                    2
  #define FTFA_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
  /* FOPT Bit Fields */
  #define FTFA_FOPT_OPT_MASK                       0xFFu
  #define FTFA_FOPT_OPT_SHIFT                      0
  #define FTFA_FOPT_OPT_WIDTH                      8
  #define FTFA_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
  /* FCCOB3 Bit Fields */
  #define FTFA_FCCOB3_CCOBn_MASK                   0xFFu
  #define FTFA_FCCOB3_CCOBn_SHIFT                  0
  #define FTFA_FCCOB3_CCOBn_WIDTH                  8
  #define FTFA_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
  /* FCCOB2 Bit Fields */
  #define FTFA_FCCOB2_CCOBn_MASK                   0xFFu
  #define FTFA_FCCOB2_CCOBn_SHIFT                  0
  #define FTFA_FCCOB2_CCOBn_WIDTH                  8
  #define FTFA_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
  /* FCCOB1 Bit Fields */
  #define FTFA_FCCOB1_CCOBn_MASK                   0xFFu
  #define FTFA_FCCOB1_CCOBn_SHIFT                  0
  #define FTFA_FCCOB1_CCOBn_WIDTH                  8
  #define FTFA_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
  /* FCCOB0 Bit Fields */
  #define FTFA_FCCOB0_CCOBn_MASK                   0xFFu
  #define FTFA_FCCOB0_CCOBn_SHIFT                  0
  #define FTFA_FCCOB0_CCOBn_WIDTH                  8
  #define FTFA_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
  /* FCCOB7 Bit Fields */
  #define FTFA_FCCOB7_CCOBn_MASK                   0xFFu
  #define FTFA_FCCOB7_CCOBn_SHIFT                  0
  #define FTFA_FCCOB7_CCOBn_WIDTH                  8
  #define FTFA_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
  /* FCCOB6 Bit Fields */
  #define FTFA_FCCOB6_CCOBn_MASK                   0xFFu
  #define FTFA_FCCOB6_CCOBn_SHIFT                  0
  #define FTFA_FCCOB6_CCOBn_WIDTH                  8
  #define FTFA_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
  /* FCCOB5 Bit Fields */
  #define FTFA_FCCOB5_CCOBn_MASK                   0xFFu
  #define FTFA_FCCOB5_CCOBn_SHIFT                  0
  #define FTFA_FCCOB5_CCOBn_WIDTH                  8
  #define FTFA_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
  /* FCCOB4 Bit Fields */
  #define FTFA_FCCOB4_CCOBn_MASK                   0xFFu
  #define FTFA_FCCOB4_CCOBn_SHIFT                  0
  #define FTFA_FCCOB4_CCOBn_WIDTH                  8
  #define FTFA_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
  /* FCCOBB Bit Fields */
  #define FTFA_FCCOBB_CCOBn_MASK                   0xFFu
  #define FTFA_FCCOBB_CCOBn_SHIFT                  0
  #define FTFA_FCCOBB_CCOBn_WIDTH                  8
  #define FTFA_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
  /* FCCOBA Bit Fields */
  #define FTFA_FCCOBA_CCOBn_MASK                   0xFFu
  #define FTFA_FCCOBA_CCOBn_SHIFT                  0
  #define FTFA_FCCOBA_CCOBn_WIDTH                  8
  #define FTFA_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
  /* FCCOB9 Bit Fields */
  #define FTFA_FCCOB9_CCOBn_MASK                   0xFFu
  #define FTFA_FCCOB9_CCOBn_SHIFT                  0
  #define FTFA_FCCOB9_CCOBn_WIDTH                  8
  #define FTFA_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
  /* FCCOB8 Bit Fields */
  #define FTFA_FCCOB8_CCOBn_MASK                   0xFFu
  #define FTFA_FCCOB8_CCOBn_SHIFT                  0
  #define FTFA_FCCOB8_CCOBn_WIDTH                  8
  #define FTFA_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
  /* FPROT3 Bit Fields */
  #define FTFA_FPROT3_PROT_MASK                    0xFFu
  #define FTFA_FPROT3_PROT_SHIFT                   0
  #define FTFA_FPROT3_PROT_WIDTH                   8
  #define FTFA_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
  /* FPROT2 Bit Fields */
  #define FTFA_FPROT2_PROT_MASK                    0xFFu
  #define FTFA_FPROT2_PROT_SHIFT                   0
  #define FTFA_FPROT2_PROT_WIDTH                   8
  #define FTFA_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
  /* FPROT1 Bit Fields */
  #define FTFA_FPROT1_PROT_MASK                    0xFFu
  #define FTFA_FPROT1_PROT_SHIFT                   0
  #define FTFA_FPROT1_PROT_WIDTH                   8
  #define FTFA_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
  /* FPROT0 Bit Fields */
  #define FTFA_FPROT0_PROT_MASK                    0xFFu
  #define FTFA_FPROT0_PROT_SHIFT                   0
  #define FTFA_FPROT0_PROT_WIDTH                   8
  #define FTFA_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
  /* XACCH3 Bit Fields */
  #define FTFA_XACCH3_XA_MASK                      0xFFu
  #define FTFA_XACCH3_XA_SHIFT                     0
  #define FTFA_XACCH3_XA_WIDTH                     8
  #define FTFA_XACCH3_XA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH3_XA_SHIFT))&FTFA_XACCH3_XA_MASK)
  /* XACCH2 Bit Fields */
  #define FTFA_XACCH2_XA_MASK                      0xFFu
  #define FTFA_XACCH2_XA_SHIFT                     0
  #define FTFA_XACCH2_XA_WIDTH                     8
  #define FTFA_XACCH2_XA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH2_XA_SHIFT))&FTFA_XACCH2_XA_MASK)
  /* XACCH1 Bit Fields */
  #define FTFA_XACCH1_XA_MASK                      0xFFu
  #define FTFA_XACCH1_XA_SHIFT                     0
  #define FTFA_XACCH1_XA_WIDTH                     8
  #define FTFA_XACCH1_XA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH1_XA_SHIFT))&FTFA_XACCH1_XA_MASK)
  /* XACCH0 Bit Fields */
  #define FTFA_XACCH0_XA_MASK                      0xFFu
  #define FTFA_XACCH0_XA_SHIFT                     0
  #define FTFA_XACCH0_XA_WIDTH                     8
  #define FTFA_XACCH0_XA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH0_XA_SHIFT))&FTFA_XACCH0_XA_MASK)
  /* XACCL3 Bit Fields */
  #define FTFA_XACCL3_XA_MASK                      0xFFu
  #define FTFA_XACCL3_XA_SHIFT                     0
  #define FTFA_XACCL3_XA_WIDTH                     8
  #define FTFA_XACCL3_XA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL3_XA_SHIFT))&FTFA_XACCL3_XA_MASK)
  /* XACCL2 Bit Fields */
  #define FTFA_XACCL2_XA_MASK                      0xFFu
  #define FTFA_XACCL2_XA_SHIFT                     0
  #define FTFA_XACCL2_XA_WIDTH                     8
  #define FTFA_XACCL2_XA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL2_XA_SHIFT))&FTFA_XACCL2_XA_MASK)
  /* XACCL1 Bit Fields */
  #define FTFA_XACCL1_XA_MASK                      0xFFu
  #define FTFA_XACCL1_XA_SHIFT                     0
  #define FTFA_XACCL1_XA_WIDTH                     8
  #define FTFA_XACCL1_XA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL1_XA_SHIFT))&FTFA_XACCL1_XA_MASK)
  /* XACCL0 Bit Fields */
  #define FTFA_XACCL0_XA_MASK                      0xFFu
  #define FTFA_XACCL0_XA_SHIFT                     0
  #define FTFA_XACCL0_XA_WIDTH                     8
  #define FTFA_XACCL0_XA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL0_XA_SHIFT))&FTFA_XACCL0_XA_MASK)
  /* SACCH3 Bit Fields */
  #define FTFA_SACCH3_SA_MASK                      0xFFu
  #define FTFA_SACCH3_SA_SHIFT                     0
  #define FTFA_SACCH3_SA_WIDTH                     8
  #define FTFA_SACCH3_SA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH3_SA_SHIFT))&FTFA_SACCH3_SA_MASK)
  /* SACCH2 Bit Fields */
  #define FTFA_SACCH2_SA_MASK                      0xFFu
  #define FTFA_SACCH2_SA_SHIFT                     0
  #define FTFA_SACCH2_SA_WIDTH                     8
  #define FTFA_SACCH2_SA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH2_SA_SHIFT))&FTFA_SACCH2_SA_MASK)
  /* SACCH1 Bit Fields */
  #define FTFA_SACCH1_SA_MASK                      0xFFu
  #define FTFA_SACCH1_SA_SHIFT                     0
  #define FTFA_SACCH1_SA_WIDTH                     8
  #define FTFA_SACCH1_SA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH1_SA_SHIFT))&FTFA_SACCH1_SA_MASK)
  /* SACCH0 Bit Fields */
  #define FTFA_SACCH0_SA_MASK                      0xFFu
  #define FTFA_SACCH0_SA_SHIFT                     0
  #define FTFA_SACCH0_SA_WIDTH                     8
  #define FTFA_SACCH0_SA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH0_SA_SHIFT))&FTFA_SACCH0_SA_MASK)
  /* SACCL3 Bit Fields */
  #define FTFA_SACCL3_SA_MASK                      0xFFu
  #define FTFA_SACCL3_SA_SHIFT                     0
  #define FTFA_SACCL3_SA_WIDTH                     8
  #define FTFA_SACCL3_SA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL3_SA_SHIFT))&FTFA_SACCL3_SA_MASK)
  /* SACCL2 Bit Fields */
  #define FTFA_SACCL2_SA_MASK                      0xFFu
  #define FTFA_SACCL2_SA_SHIFT                     0
  #define FTFA_SACCL2_SA_WIDTH                     8
  #define FTFA_SACCL2_SA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL2_SA_SHIFT))&FTFA_SACCL2_SA_MASK)
  /* SACCL1 Bit Fields */
  #define FTFA_SACCL1_SA_MASK                      0xFFu
  #define FTFA_SACCL1_SA_SHIFT                     0
  #define FTFA_SACCL1_SA_WIDTH                     8
  #define FTFA_SACCL1_SA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL1_SA_SHIFT))&FTFA_SACCL1_SA_MASK)
  /* SACCL0 Bit Fields */
  #define FTFA_SACCL0_SA_MASK                      0xFFu
  #define FTFA_SACCL0_SA_SHIFT                     0
  #define FTFA_SACCL0_SA_WIDTH                     8
  #define FTFA_SACCL0_SA(x)                        (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL0_SA_SHIFT))&FTFA_SACCL0_SA_MASK)
  /* FACSS Bit Fields */
  #define FTFA_FACSS_SGSIZE_MASK                   0xFFu
  #define FTFA_FACSS_SGSIZE_SHIFT                  0
  #define FTFA_FACSS_SGSIZE_WIDTH                  8
  #define FTFA_FACSS_SGSIZE(x)                     (((uint8_t)(((uint8_t)(x))<<FTFA_FACSS_SGSIZE_SHIFT))&FTFA_FACSS_SGSIZE_MASK)
  /* FACSN Bit Fields */
  #define FTFA_FACSN_NUMSG_MASK                    0xFFu
  #define FTFA_FACSN_NUMSG_SHIFT                   0
  #define FTFA_FACSN_NUMSG_WIDTH                   8
  #define FTFA_FACSN_NUMSG(x)                      (((uint8_t)(((uint8_t)(x))<<FTFA_FACSN_NUMSG_SHIFT))&FTFA_FACSN_NUMSG_MASK)
  
  /*!
   * @}
   */ /* end of group FTFA_Register_Masks */
  
  
  /* FTFA - Peripheral instance base addresses */
  /** Peripheral FTFA base address */
  #define FTFA_BASE                                (0x40020000u)
  /** Peripheral FTFA base pointer */
  #define FTFA                                     ((FTFA_Type *)FTFA_BASE)
  #define FTFA_BASE_PTR                            (FTFA)
  /** Array initializer of FTFA peripheral base addresses */
  #define FTFA_BASE_ADDRS                          { FTFA_BASE }
  /** Array initializer of FTFA peripheral base pointers */
  #define FTFA_BASE_PTRS                           { FTFA }
  
  /* ----------------------------------------------------------------------------
     -- FTFA - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
   * @{
   */
  
  
  /* FTFA - Register instance definitions */
  /* FTFA */
  #define FTFA_FSTAT                               FTFA_FSTAT_REG(FTFA)
  #define FTFA_FCNFG                               FTFA_FCNFG_REG(FTFA)
  #define FTFA_FSEC                                FTFA_FSEC_REG(FTFA)
  #define FTFA_FOPT                                FTFA_FOPT_REG(FTFA)
  #define FTFA_FCCOB3                              FTFA_FCCOB3_REG(FTFA)
  #define FTFA_FCCOB2                              FTFA_FCCOB2_REG(FTFA)
  #define FTFA_FCCOB1                              FTFA_FCCOB1_REG(FTFA)
  #define FTFA_FCCOB0                              FTFA_FCCOB0_REG(FTFA)
  #define FTFA_FCCOB7                              FTFA_FCCOB7_REG(FTFA)
  #define FTFA_FCCOB6                              FTFA_FCCOB6_REG(FTFA)
  #define FTFA_FCCOB5                              FTFA_FCCOB5_REG(FTFA)
  #define FTFA_FCCOB4                              FTFA_FCCOB4_REG(FTFA)
  #define FTFA_FCCOBB                              FTFA_FCCOBB_REG(FTFA)
  #define FTFA_FCCOBA                              FTFA_FCCOBA_REG(FTFA)
  #define FTFA_FCCOB9                              FTFA_FCCOB9_REG(FTFA)
  #define FTFA_FCCOB8                              FTFA_FCCOB8_REG(FTFA)
  #define FTFA_FPROT3                              FTFA_FPROT3_REG(FTFA)
  #define FTFA_FPROT2                              FTFA_FPROT2_REG(FTFA)
  #define FTFA_FPROT1                              FTFA_FPROT1_REG(FTFA)
  #define FTFA_FPROT0                              FTFA_FPROT0_REG(FTFA)
  #define FTFA_XACCH3                              FTFA_XACCH3_REG(FTFA)
  #define FTFA_XACCH2                              FTFA_XACCH2_REG(FTFA)
  #define FTFA_XACCH1                              FTFA_XACCH1_REG(FTFA)
  #define FTFA_XACCH0                              FTFA_XACCH0_REG(FTFA)
  #define FTFA_XACCL3                              FTFA_XACCL3_REG(FTFA)
  #define FTFA_XACCL2                              FTFA_XACCL2_REG(FTFA)
  #define FTFA_XACCL1                              FTFA_XACCL1_REG(FTFA)
  #define FTFA_XACCL0                              FTFA_XACCL0_REG(FTFA)
  #define FTFA_SACCH3                              FTFA_SACCH3_REG(FTFA)
  #define FTFA_SACCH2                              FTFA_SACCH2_REG(FTFA)
  #define FTFA_SACCH1                              FTFA_SACCH1_REG(FTFA)
  #define FTFA_SACCH0                              FTFA_SACCH0_REG(FTFA)
  #define FTFA_SACCL3                              FTFA_SACCL3_REG(FTFA)
  #define FTFA_SACCL2                              FTFA_SACCL2_REG(FTFA)
  #define FTFA_SACCL1                              FTFA_SACCL1_REG(FTFA)
  #define FTFA_SACCL0                              FTFA_SACCL0_REG(FTFA)
  #define FTFA_FACSS                               FTFA_FACSS_REG(FTFA)
  #define FTFA_FACSN                               FTFA_FACSN_REG(FTFA)
  
  /*!
   * @}
   */ /* end of group FTFA_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group FTFA_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- GPIO Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
   * @{
   */
  
  /** GPIO - Register Layout Typedef */
  typedef struct {
    __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
    __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
    __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
    __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
    __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
    __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
  } GPIO_Type, *GPIO_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- GPIO - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
   * @{
   */
  
  
  /* GPIO - Register accessors */
  #define GPIO_PDOR_REG(base)                      ((base)->PDOR)
  #define GPIO_PSOR_REG(base)                      ((base)->PSOR)
  #define GPIO_PCOR_REG(base)                      ((base)->PCOR)
  #define GPIO_PTOR_REG(base)                      ((base)->PTOR)
  #define GPIO_PDIR_REG(base)                      ((base)->PDIR)
  #define GPIO_PDDR_REG(base)                      ((base)->PDDR)
  
  /*!
   * @}
   */ /* end of group GPIO_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- GPIO Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup GPIO_Register_Masks GPIO Register Masks
   * @{
   */
  
  /* PDOR Bit Fields */
  #define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
  #define GPIO_PDOR_PDO_SHIFT                      0
  #define GPIO_PDOR_PDO_WIDTH                      32
  #define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
  /* PSOR Bit Fields */
  #define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
  #define GPIO_PSOR_PTSO_SHIFT                     0
  #define GPIO_PSOR_PTSO_WIDTH                     32
  #define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
  /* PCOR Bit Fields */
  #define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
  #define GPIO_PCOR_PTCO_SHIFT                     0
  #define GPIO_PCOR_PTCO_WIDTH                     32
  #define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
  /* PTOR Bit Fields */
  #define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
  #define GPIO_PTOR_PTTO_SHIFT                     0
  #define GPIO_PTOR_PTTO_WIDTH                     32
  #define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
  /* PDIR Bit Fields */
  #define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
  #define GPIO_PDIR_PDI_SHIFT                      0
  #define GPIO_PDIR_PDI_WIDTH                      32
  #define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
  /* PDDR Bit Fields */
  #define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
  #define GPIO_PDDR_PDD_SHIFT                      0
  #define GPIO_PDDR_PDD_WIDTH                      32
  #define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
  
  /*!
   * @}
   */ /* end of group GPIO_Register_Masks */
  
  
  /* GPIO - Peripheral instance base addresses */
  /** Peripheral PTA base address */
  #define PTA_BASE                                 (0x400FF000u)
  /** Peripheral PTA base pointer */
  #define PTA                                      ((GPIO_Type *)PTA_BASE)
  #define PTA_BASE_PTR                             (PTA)
  /** Peripheral PTB base address */
  #define PTB_BASE                                 (0x400FF040u)
  /** Peripheral PTB base pointer */
  #define PTB                                      ((GPIO_Type *)PTB_BASE)
  #define PTB_BASE_PTR                             (PTB)
  /** Peripheral PTC base address */
  #define PTC_BASE                                 (0x400FF080u)
  /** Peripheral PTC base pointer */
  #define PTC                                      ((GPIO_Type *)PTC_BASE)
  #define PTC_BASE_PTR                             (PTC)
  /** Peripheral PTD base address */
  #define PTD_BASE                                 (0x400FF0C0u)
  /** Peripheral PTD base pointer */
  #define PTD                                      ((GPIO_Type *)PTD_BASE)
  #define PTD_BASE_PTR                             (PTD)
  /** Peripheral PTE base address */
  #define PTE_BASE                                 (0x400FF100u)
  /** Peripheral PTE base pointer */
  #define PTE                                      ((GPIO_Type *)PTE_BASE)
  #define PTE_BASE_PTR                             (PTE)
  /** Array initializer of GPIO peripheral base addresses */
  #define GPIO_BASE_ADDRS                          { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
  /** Array initializer of GPIO peripheral base pointers */
  #define GPIO_BASE_PTRS                           { PTA, PTB, PTC, PTD, PTE }
  
  /* ----------------------------------------------------------------------------
     -- GPIO - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
   * @{
   */
  
  
  /* GPIO - Register instance definitions */
  /* PTA */
  #define GPIOA_PDOR                               GPIO_PDOR_REG(PTA)
  #define GPIOA_PSOR                               GPIO_PSOR_REG(PTA)
  #define GPIOA_PCOR                               GPIO_PCOR_REG(PTA)
  #define GPIOA_PTOR                               GPIO_PTOR_REG(PTA)
  #define GPIOA_PDIR                               GPIO_PDIR_REG(PTA)
  #define GPIOA_PDDR                               GPIO_PDDR_REG(PTA)
  /* PTB */
  #define GPIOB_PDOR                               GPIO_PDOR_REG(PTB)
  #define GPIOB_PSOR                               GPIO_PSOR_REG(PTB)
  #define GPIOB_PCOR                               GPIO_PCOR_REG(PTB)
  #define GPIOB_PTOR                               GPIO_PTOR_REG(PTB)
  #define GPIOB_PDIR                               GPIO_PDIR_REG(PTB)
  #define GPIOB_PDDR                               GPIO_PDDR_REG(PTB)
  /* PTC */
  #define GPIOC_PDOR                               GPIO_PDOR_REG(PTC)
  #define GPIOC_PSOR                               GPIO_PSOR_REG(PTC)
  #define GPIOC_PCOR                               GPIO_PCOR_REG(PTC)
  #define GPIOC_PTOR                               GPIO_PTOR_REG(PTC)
  #define GPIOC_PDIR                               GPIO_PDIR_REG(PTC)
  #define GPIOC_PDDR                               GPIO_PDDR_REG(PTC)
  /* PTD */
  #define GPIOD_PDOR                               GPIO_PDOR_REG(PTD)
  #define GPIOD_PSOR                               GPIO_PSOR_REG(PTD)
  #define GPIOD_PCOR                               GPIO_PCOR_REG(PTD)
  #define GPIOD_PTOR                               GPIO_PTOR_REG(PTD)
  #define GPIOD_PDIR                               GPIO_PDIR_REG(PTD)
  #define GPIOD_PDDR                               GPIO_PDDR_REG(PTD)
  /* PTE */
  #define GPIOE_PDOR                               GPIO_PDOR_REG(PTE)
  #define GPIOE_PSOR                               GPIO_PSOR_REG(PTE)
  #define GPIOE_PCOR                               GPIO_PCOR_REG(PTE)
  #define GPIOE_PTOR                               GPIO_PTOR_REG(PTE)
  #define GPIOE_PDIR                               GPIO_PDIR_REG(PTE)
  #define GPIOE_PDDR                               GPIO_PDDR_REG(PTE)
  
  /*!
   * @}
   */ /* end of group GPIO_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group GPIO_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- I2S Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
   * @{
   */
  
  /** I2S - Register Layout Typedef */
  typedef struct {
    __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
    __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
    __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
    __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
    __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
    __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
         uint8_t RESERVED_0[8];
    __O  uint32_t TDR[1];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
         uint8_t RESERVED_1[28];
    __I  uint32_t TFR[1];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
         uint8_t RESERVED_2[28];
    __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
         uint8_t RESERVED_3[28];
    __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
    __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x84 */
    __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
    __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
    __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
    __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
         uint8_t RESERVED_4[8];
    __I  uint32_t RDR[1];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
         uint8_t RESERVED_5[28];
    __I  uint32_t RFR[1];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
         uint8_t RESERVED_6[28];
    __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
         uint8_t RESERVED_7[28];
    __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
    __IO uint32_t MDR;                               /**< SAI MCLK Divide Register, offset: 0x104 */
  } I2S_Type, *I2S_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- I2S - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
   * @{
   */
  
  
  /* I2S - Register accessors */
  #define I2S_TCSR_REG(base)                       ((base)->TCSR)
  #define I2S_TCR1_REG(base)                       ((base)->TCR1)
  #define I2S_TCR2_REG(base)                       ((base)->TCR2)
  #define I2S_TCR3_REG(base)                       ((base)->TCR3)
  #define I2S_TCR4_REG(base)                       ((base)->TCR4)
  #define I2S_TCR5_REG(base)                       ((base)->TCR5)
  #define I2S_TDR_REG(base,index)                  ((base)->TDR[index])
  #define I2S_TDR_COUNT                            1
  #define I2S_TFR_REG(base,index)                  ((base)->TFR[index])
  #define I2S_TFR_COUNT                            1
  #define I2S_TMR_REG(base)                        ((base)->TMR)
  #define I2S_RCSR_REG(base)                       ((base)->RCSR)
  #define I2S_RCR1_REG(base)                       ((base)->RCR1)
  #define I2S_RCR2_REG(base)                       ((base)->RCR2)
  #define I2S_RCR3_REG(base)                       ((base)->RCR3)
  #define I2S_RCR4_REG(base)                       ((base)->RCR4)
  #define I2S_RCR5_REG(base)                       ((base)->RCR5)
  #define I2S_RDR_REG(base,index)                  ((base)->RDR[index])
  #define I2S_RDR_COUNT                            1
  #define I2S_RFR_REG(base,index)                  ((base)->RFR[index])
  #define I2S_RFR_COUNT                            1
  #define I2S_RMR_REG(base)                        ((base)->RMR)
  #define I2S_MCR_REG(base)                        ((base)->MCR)
  #define I2S_MDR_REG(base)                        ((base)->MDR)
  
  /*!
   * @}
   */ /* end of group I2S_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- I2S Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup I2S_Register_Masks I2S Register Masks
   * @{
   */
  
  /* TCSR Bit Fields */
  #define I2S_TCSR_FRDE_MASK                       0x1u
  #define I2S_TCSR_FRDE_SHIFT                      0
  #define I2S_TCSR_FRDE_WIDTH                      1
  #define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRDE_SHIFT))&I2S_TCSR_FRDE_MASK)
  #define I2S_TCSR_FWDE_MASK                       0x2u
  #define I2S_TCSR_FWDE_SHIFT                      1
  #define I2S_TCSR_FWDE_WIDTH                      1
  #define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWDE_SHIFT))&I2S_TCSR_FWDE_MASK)
  #define I2S_TCSR_FRIE_MASK                       0x100u
  #define I2S_TCSR_FRIE_SHIFT                      8
  #define I2S_TCSR_FRIE_WIDTH                      1
  #define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRIE_SHIFT))&I2S_TCSR_FRIE_MASK)
  #define I2S_TCSR_FWIE_MASK                       0x200u
  #define I2S_TCSR_FWIE_SHIFT                      9
  #define I2S_TCSR_FWIE_WIDTH                      1
  #define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWIE_SHIFT))&I2S_TCSR_FWIE_MASK)
  #define I2S_TCSR_FEIE_MASK                       0x400u
  #define I2S_TCSR_FEIE_SHIFT                      10
  #define I2S_TCSR_FEIE_WIDTH                      1
  #define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEIE_SHIFT))&I2S_TCSR_FEIE_MASK)
  #define I2S_TCSR_SEIE_MASK                       0x800u
  #define I2S_TCSR_SEIE_SHIFT                      11
  #define I2S_TCSR_SEIE_WIDTH                      1
  #define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEIE_SHIFT))&I2S_TCSR_SEIE_MASK)
  #define I2S_TCSR_WSIE_MASK                       0x1000u
  #define I2S_TCSR_WSIE_SHIFT                      12
  #define I2S_TCSR_WSIE_WIDTH                      1
  #define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSIE_SHIFT))&I2S_TCSR_WSIE_MASK)
  #define I2S_TCSR_FRF_MASK                        0x10000u
  #define I2S_TCSR_FRF_SHIFT                       16
  #define I2S_TCSR_FRF_WIDTH                       1
  #define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FRF_SHIFT))&I2S_TCSR_FRF_MASK)
  #define I2S_TCSR_FWF_MASK                        0x20000u
  #define I2S_TCSR_FWF_SHIFT                       17
  #define I2S_TCSR_FWF_WIDTH                       1
  #define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FWF_SHIFT))&I2S_TCSR_FWF_MASK)
  #define I2S_TCSR_FEF_MASK                        0x40000u
  #define I2S_TCSR_FEF_SHIFT                       18
  #define I2S_TCSR_FEF_WIDTH                       1
  #define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FEF_SHIFT))&I2S_TCSR_FEF_MASK)
  #define I2S_TCSR_SEF_MASK                        0x80000u
  #define I2S_TCSR_SEF_SHIFT                       19
  #define I2S_TCSR_SEF_WIDTH                       1
  #define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SEF_SHIFT))&I2S_TCSR_SEF_MASK)
  #define I2S_TCSR_WSF_MASK                        0x100000u
  #define I2S_TCSR_WSF_SHIFT                       20
  #define I2S_TCSR_WSF_WIDTH                       1
  #define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_WSF_SHIFT))&I2S_TCSR_WSF_MASK)
  #define I2S_TCSR_SR_MASK                         0x1000000u
  #define I2S_TCSR_SR_SHIFT                        24
  #define I2S_TCSR_SR_WIDTH                        1
  #define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_SR_SHIFT))&I2S_TCSR_SR_MASK)
  #define I2S_TCSR_FR_MASK                         0x2000000u
  #define I2S_TCSR_FR_SHIFT                        25
  #define I2S_TCSR_FR_WIDTH                        1
  #define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_FR_SHIFT))&I2S_TCSR_FR_MASK)
  #define I2S_TCSR_BCE_MASK                        0x10000000u
  #define I2S_TCSR_BCE_SHIFT                       28
  #define I2S_TCSR_BCE_WIDTH                       1
  #define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_BCE_SHIFT))&I2S_TCSR_BCE_MASK)
  #define I2S_TCSR_DBGE_MASK                       0x20000000u
  #define I2S_TCSR_DBGE_SHIFT                      29
  #define I2S_TCSR_DBGE_WIDTH                      1
  #define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_DBGE_SHIFT))&I2S_TCSR_DBGE_MASK)
  #define I2S_TCSR_STOPE_MASK                      0x40000000u
  #define I2S_TCSR_STOPE_SHIFT                     30
  #define I2S_TCSR_STOPE_WIDTH                     1
  #define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_STOPE_SHIFT))&I2S_TCSR_STOPE_MASK)
  #define I2S_TCSR_TE_MASK                         0x80000000u
  #define I2S_TCSR_TE_SHIFT                        31
  #define I2S_TCSR_TE_WIDTH                        1
  #define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCSR_TE_SHIFT))&I2S_TCSR_TE_MASK)
  /* TCR1 Bit Fields */
  #define I2S_TCR1_TFW_MASK                        0x7u
  #define I2S_TCR1_TFW_SHIFT                       0
  #define I2S_TCR1_TFW_WIDTH                       3
  #define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
  /* TCR2 Bit Fields */
  #define I2S_TCR2_DIV_MASK                        0xFFu
  #define I2S_TCR2_DIV_SHIFT                       0
  #define I2S_TCR2_DIV_WIDTH                       8
  #define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
  #define I2S_TCR2_BCD_MASK                        0x1000000u
  #define I2S_TCR2_BCD_SHIFT                       24
  #define I2S_TCR2_BCD_WIDTH                       1
  #define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCD_SHIFT))&I2S_TCR2_BCD_MASK)
  #define I2S_TCR2_BCP_MASK                        0x2000000u
  #define I2S_TCR2_BCP_SHIFT                       25
  #define I2S_TCR2_BCP_WIDTH                       1
  #define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCP_SHIFT))&I2S_TCR2_BCP_MASK)
  #define I2S_TCR2_MSEL_MASK                       0xC000000u
  #define I2S_TCR2_MSEL_SHIFT                      26
  #define I2S_TCR2_MSEL_WIDTH                      2
  #define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
  #define I2S_TCR2_BCI_MASK                        0x10000000u
  #define I2S_TCR2_BCI_SHIFT                       28
  #define I2S_TCR2_BCI_WIDTH                       1
  #define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCI_SHIFT))&I2S_TCR2_BCI_MASK)
  #define I2S_TCR2_BCS_MASK                        0x20000000u
  #define I2S_TCR2_BCS_SHIFT                       29
  #define I2S_TCR2_BCS_WIDTH                       1
  #define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_BCS_SHIFT))&I2S_TCR2_BCS_MASK)
  #define I2S_TCR2_SYNC_MASK                       0xC0000000u
  #define I2S_TCR2_SYNC_SHIFT                      30
  #define I2S_TCR2_SYNC_WIDTH                      2
  #define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
  /* TCR3 Bit Fields */
  #define I2S_TCR3_WDFL_MASK                       0xFu
  #define I2S_TCR3_WDFL_SHIFT                      0
  #define I2S_TCR3_WDFL_WIDTH                      4
  #define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
  #define I2S_TCR3_TCE_MASK                        0x10000u
  #define I2S_TCR3_TCE_SHIFT                       16
  #define I2S_TCR3_TCE_WIDTH                       1
  #define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
  /* TCR4 Bit Fields */
  #define I2S_TCR4_FSD_MASK                        0x1u
  #define I2S_TCR4_FSD_SHIFT                       0
  #define I2S_TCR4_FSD_WIDTH                       1
  #define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSD_SHIFT))&I2S_TCR4_FSD_MASK)
  #define I2S_TCR4_FSP_MASK                        0x2u
  #define I2S_TCR4_FSP_SHIFT                       1
  #define I2S_TCR4_FSP_WIDTH                       1
  #define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSP_SHIFT))&I2S_TCR4_FSP_MASK)
  #define I2S_TCR4_ONDEM_MASK                      0x4u
  #define I2S_TCR4_ONDEM_SHIFT                     2
  #define I2S_TCR4_ONDEM_WIDTH                     1
  #define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_ONDEM_SHIFT))&I2S_TCR4_ONDEM_MASK)
  #define I2S_TCR4_FSE_MASK                        0x8u
  #define I2S_TCR4_FSE_SHIFT                       3
  #define I2S_TCR4_FSE_WIDTH                       1
  #define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FSE_SHIFT))&I2S_TCR4_FSE_MASK)
  #define I2S_TCR4_MF_MASK                         0x10u
  #define I2S_TCR4_MF_SHIFT                        4
  #define I2S_TCR4_MF_WIDTH                        1
  #define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_MF_SHIFT))&I2S_TCR4_MF_MASK)
  #define I2S_TCR4_SYWD_MASK                       0x1F00u
  #define I2S_TCR4_SYWD_SHIFT                      8
  #define I2S_TCR4_SYWD_WIDTH                      5
  #define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
  #define I2S_TCR4_FRSZ_MASK                       0xF0000u
  #define I2S_TCR4_FRSZ_SHIFT                      16
  #define I2S_TCR4_FRSZ_WIDTH                      4
  #define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
  #define I2S_TCR4_FPACK_MASK                      0x3000000u
  #define I2S_TCR4_FPACK_SHIFT                     24
  #define I2S_TCR4_FPACK_WIDTH                     2
  #define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
  #define I2S_TCR4_FCONT_MASK                      0x10000000u
  #define I2S_TCR4_FCONT_SHIFT                     28
  #define I2S_TCR4_FCONT_WIDTH                     1
  #define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FCONT_SHIFT))&I2S_TCR4_FCONT_MASK)
  /* TCR5 Bit Fields */
  #define I2S_TCR5_FBT_MASK                        0x1F00u
  #define I2S_TCR5_FBT_SHIFT                       8
  #define I2S_TCR5_FBT_WIDTH                       5
  #define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
  #define I2S_TCR5_W0W_MASK                        0x1F0000u
  #define I2S_TCR5_W0W_SHIFT                       16
  #define I2S_TCR5_W0W_WIDTH                       5
  #define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
  #define I2S_TCR5_WNW_MASK                        0x1F000000u
  #define I2S_TCR5_WNW_SHIFT                       24
  #define I2S_TCR5_WNW_WIDTH                       5
  #define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
  /* TDR Bit Fields */
  #define I2S_TDR_TDR_MASK                         0xFFFFFFFFu
  #define I2S_TDR_TDR_SHIFT                        0
  #define I2S_TDR_TDR_WIDTH                        32
  #define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
  /* TFR Bit Fields */
  #define I2S_TFR_RFP_MASK                         0xFu
  #define I2S_TFR_RFP_SHIFT                        0
  #define I2S_TFR_RFP_WIDTH                        4
  #define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
  #define I2S_TFR_WFP_MASK                         0xF0000u
  #define I2S_TFR_WFP_SHIFT                        16
  #define I2S_TFR_WFP_WIDTH                        4
  #define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
  /* TMR Bit Fields */
  #define I2S_TMR_TWM_MASK                         0xFFFFu
  #define I2S_TMR_TWM_SHIFT                        0
  #define I2S_TMR_TWM_WIDTH                        16
  #define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
  /* RCSR Bit Fields */
  #define I2S_RCSR_FRDE_MASK                       0x1u
  #define I2S_RCSR_FRDE_SHIFT                      0
  #define I2S_RCSR_FRDE_WIDTH                      1
  #define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRDE_SHIFT))&I2S_RCSR_FRDE_MASK)
  #define I2S_RCSR_FWDE_MASK                       0x2u
  #define I2S_RCSR_FWDE_SHIFT                      1
  #define I2S_RCSR_FWDE_WIDTH                      1
  #define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWDE_SHIFT))&I2S_RCSR_FWDE_MASK)
  #define I2S_RCSR_FRIE_MASK                       0x100u
  #define I2S_RCSR_FRIE_SHIFT                      8
  #define I2S_RCSR_FRIE_WIDTH                      1
  #define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRIE_SHIFT))&I2S_RCSR_FRIE_MASK)
  #define I2S_RCSR_FWIE_MASK                       0x200u
  #define I2S_RCSR_FWIE_SHIFT                      9
  #define I2S_RCSR_FWIE_WIDTH                      1
  #define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWIE_SHIFT))&I2S_RCSR_FWIE_MASK)
  #define I2S_RCSR_FEIE_MASK                       0x400u
  #define I2S_RCSR_FEIE_SHIFT                      10
  #define I2S_RCSR_FEIE_WIDTH                      1
  #define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEIE_SHIFT))&I2S_RCSR_FEIE_MASK)
  #define I2S_RCSR_SEIE_MASK                       0x800u
  #define I2S_RCSR_SEIE_SHIFT                      11
  #define I2S_RCSR_SEIE_WIDTH                      1
  #define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEIE_SHIFT))&I2S_RCSR_SEIE_MASK)
  #define I2S_RCSR_WSIE_MASK                       0x1000u
  #define I2S_RCSR_WSIE_SHIFT                      12
  #define I2S_RCSR_WSIE_WIDTH                      1
  #define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSIE_SHIFT))&I2S_RCSR_WSIE_MASK)
  #define I2S_RCSR_FRF_MASK                        0x10000u
  #define I2S_RCSR_FRF_SHIFT                       16
  #define I2S_RCSR_FRF_WIDTH                       1
  #define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FRF_SHIFT))&I2S_RCSR_FRF_MASK)
  #define I2S_RCSR_FWF_MASK                        0x20000u
  #define I2S_RCSR_FWF_SHIFT                       17
  #define I2S_RCSR_FWF_WIDTH                       1
  #define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FWF_SHIFT))&I2S_RCSR_FWF_MASK)
  #define I2S_RCSR_FEF_MASK                        0x40000u
  #define I2S_RCSR_FEF_SHIFT                       18
  #define I2S_RCSR_FEF_WIDTH                       1
  #define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FEF_SHIFT))&I2S_RCSR_FEF_MASK)
  #define I2S_RCSR_SEF_MASK                        0x80000u
  #define I2S_RCSR_SEF_SHIFT                       19
  #define I2S_RCSR_SEF_WIDTH                       1
  #define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SEF_SHIFT))&I2S_RCSR_SEF_MASK)
  #define I2S_RCSR_WSF_MASK                        0x100000u
  #define I2S_RCSR_WSF_SHIFT                       20
  #define I2S_RCSR_WSF_WIDTH                       1
  #define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_WSF_SHIFT))&I2S_RCSR_WSF_MASK)
  #define I2S_RCSR_SR_MASK                         0x1000000u
  #define I2S_RCSR_SR_SHIFT                        24
  #define I2S_RCSR_SR_WIDTH                        1
  #define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_SR_SHIFT))&I2S_RCSR_SR_MASK)
  #define I2S_RCSR_FR_MASK                         0x2000000u
  #define I2S_RCSR_FR_SHIFT                        25
  #define I2S_RCSR_FR_WIDTH                        1
  #define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_FR_SHIFT))&I2S_RCSR_FR_MASK)
  #define I2S_RCSR_BCE_MASK                        0x10000000u
  #define I2S_RCSR_BCE_SHIFT                       28
  #define I2S_RCSR_BCE_WIDTH                       1
  #define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_BCE_SHIFT))&I2S_RCSR_BCE_MASK)
  #define I2S_RCSR_DBGE_MASK                       0x20000000u
  #define I2S_RCSR_DBGE_SHIFT                      29
  #define I2S_RCSR_DBGE_WIDTH                      1
  #define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_DBGE_SHIFT))&I2S_RCSR_DBGE_MASK)
  #define I2S_RCSR_STOPE_MASK                      0x40000000u
  #define I2S_RCSR_STOPE_SHIFT                     30
  #define I2S_RCSR_STOPE_WIDTH                     1
  #define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_STOPE_SHIFT))&I2S_RCSR_STOPE_MASK)
  #define I2S_RCSR_RE_MASK                         0x80000000u
  #define I2S_RCSR_RE_SHIFT                        31
  #define I2S_RCSR_RE_WIDTH                        1
  #define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCSR_RE_SHIFT))&I2S_RCSR_RE_MASK)
  /* RCR1 Bit Fields */
  #define I2S_RCR1_RFW_MASK                        0x7u
  #define I2S_RCR1_RFW_SHIFT                       0
  #define I2S_RCR1_RFW_WIDTH                       3
  #define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
  /* RCR2 Bit Fields */
  #define I2S_RCR2_DIV_MASK                        0xFFu
  #define I2S_RCR2_DIV_SHIFT                       0
  #define I2S_RCR2_DIV_WIDTH                       8
  #define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
  #define I2S_RCR2_BCD_MASK                        0x1000000u
  #define I2S_RCR2_BCD_SHIFT                       24
  #define I2S_RCR2_BCD_WIDTH                       1
  #define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCD_SHIFT))&I2S_RCR2_BCD_MASK)
  #define I2S_RCR2_BCP_MASK                        0x2000000u
  #define I2S_RCR2_BCP_SHIFT                       25
  #define I2S_RCR2_BCP_WIDTH                       1
  #define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCP_SHIFT))&I2S_RCR2_BCP_MASK)
  #define I2S_RCR2_MSEL_MASK                       0xC000000u
  #define I2S_RCR2_MSEL_SHIFT                      26
  #define I2S_RCR2_MSEL_WIDTH                      2
  #define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
  #define I2S_RCR2_BCI_MASK                        0x10000000u
  #define I2S_RCR2_BCI_SHIFT                       28
  #define I2S_RCR2_BCI_WIDTH                       1
  #define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCI_SHIFT))&I2S_RCR2_BCI_MASK)
  #define I2S_RCR2_BCS_MASK                        0x20000000u
  #define I2S_RCR2_BCS_SHIFT                       29
  #define I2S_RCR2_BCS_WIDTH                       1
  #define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_BCS_SHIFT))&I2S_RCR2_BCS_MASK)
  #define I2S_RCR2_SYNC_MASK                       0xC0000000u
  #define I2S_RCR2_SYNC_SHIFT                      30
  #define I2S_RCR2_SYNC_WIDTH                      2
  #define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
  /* RCR3 Bit Fields */
  #define I2S_RCR3_WDFL_MASK                       0xFu
  #define I2S_RCR3_WDFL_SHIFT                      0
  #define I2S_RCR3_WDFL_WIDTH                      4
  #define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
  #define I2S_RCR3_RCE_MASK                        0x10000u
  #define I2S_RCR3_RCE_SHIFT                       16
  #define I2S_RCR3_RCE_WIDTH                       1
  #define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
  /* RCR4 Bit Fields */
  #define I2S_RCR4_FSD_MASK                        0x1u
  #define I2S_RCR4_FSD_SHIFT                       0
  #define I2S_RCR4_FSD_WIDTH                       1
  #define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSD_SHIFT))&I2S_RCR4_FSD_MASK)
  #define I2S_RCR4_FSP_MASK                        0x2u
  #define I2S_RCR4_FSP_SHIFT                       1
  #define I2S_RCR4_FSP_WIDTH                       1
  #define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSP_SHIFT))&I2S_RCR4_FSP_MASK)
  #define I2S_RCR4_ONDEM_MASK                      0x4u
  #define I2S_RCR4_ONDEM_SHIFT                     2
  #define I2S_RCR4_ONDEM_WIDTH                     1
  #define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_ONDEM_SHIFT))&I2S_RCR4_ONDEM_MASK)
  #define I2S_RCR4_FSE_MASK                        0x8u
  #define I2S_RCR4_FSE_SHIFT                       3
  #define I2S_RCR4_FSE_WIDTH                       1
  #define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FSE_SHIFT))&I2S_RCR4_FSE_MASK)
  #define I2S_RCR4_MF_MASK                         0x10u
  #define I2S_RCR4_MF_SHIFT                        4
  #define I2S_RCR4_MF_WIDTH                        1
  #define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_MF_SHIFT))&I2S_RCR4_MF_MASK)
  #define I2S_RCR4_SYWD_MASK                       0x1F00u
  #define I2S_RCR4_SYWD_SHIFT                      8
  #define I2S_RCR4_SYWD_WIDTH                      5
  #define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
  #define I2S_RCR4_FRSZ_MASK                       0xF0000u
  #define I2S_RCR4_FRSZ_SHIFT                      16
  #define I2S_RCR4_FRSZ_WIDTH                      4
  #define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
  #define I2S_RCR4_FPACK_MASK                      0x3000000u
  #define I2S_RCR4_FPACK_SHIFT                     24
  #define I2S_RCR4_FPACK_WIDTH                     2
  #define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
  #define I2S_RCR4_FCONT_MASK                      0x10000000u
  #define I2S_RCR4_FCONT_SHIFT                     28
  #define I2S_RCR4_FCONT_WIDTH                     1
  #define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FCONT_SHIFT))&I2S_RCR4_FCONT_MASK)
  /* RCR5 Bit Fields */
  #define I2S_RCR5_FBT_MASK                        0x1F00u
  #define I2S_RCR5_FBT_SHIFT                       8
  #define I2S_RCR5_FBT_WIDTH                       5
  #define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
  #define I2S_RCR5_W0W_MASK                        0x1F0000u
  #define I2S_RCR5_W0W_SHIFT                       16
  #define I2S_RCR5_W0W_WIDTH                       5
  #define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
  #define I2S_RCR5_WNW_MASK                        0x1F000000u
  #define I2S_RCR5_WNW_SHIFT                       24
  #define I2S_RCR5_WNW_WIDTH                       5
  #define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
  /* RDR Bit Fields */
  #define I2S_RDR_RDR_MASK                         0xFFFFFFFFu
  #define I2S_RDR_RDR_SHIFT                        0
  #define I2S_RDR_RDR_WIDTH                        32
  #define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
  /* RFR Bit Fields */
  #define I2S_RFR_RFP_MASK                         0xFu
  #define I2S_RFR_RFP_SHIFT                        0
  #define I2S_RFR_RFP_WIDTH                        4
  #define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
  #define I2S_RFR_WFP_MASK                         0xF0000u
  #define I2S_RFR_WFP_SHIFT                        16
  #define I2S_RFR_WFP_WIDTH                        4
  #define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
  /* RMR Bit Fields */
  #define I2S_RMR_RWM_MASK                         0xFFFFu
  #define I2S_RMR_RWM_SHIFT                        0
  #define I2S_RMR_RWM_WIDTH                        16
  #define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
  /* MCR Bit Fields */
  #define I2S_MCR_MICS_MASK                        0x3000000u
  #define I2S_MCR_MICS_SHIFT                       24
  #define I2S_MCR_MICS_WIDTH                       2
  #define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
  #define I2S_MCR_MOE_MASK                         0x40000000u
  #define I2S_MCR_MOE_SHIFT                        30
  #define I2S_MCR_MOE_WIDTH                        1
  #define I2S_MCR_MOE(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MOE_SHIFT))&I2S_MCR_MOE_MASK)
  #define I2S_MCR_DUF_MASK                         0x80000000u
  #define I2S_MCR_DUF_SHIFT                        31
  #define I2S_MCR_DUF_WIDTH                        1
  #define I2S_MCR_DUF(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_MCR_DUF_SHIFT))&I2S_MCR_DUF_MASK)
  /* MDR Bit Fields */
  #define I2S_MDR_DIVIDE_MASK                      0xFFFu
  #define I2S_MDR_DIVIDE_SHIFT                     0
  #define I2S_MDR_DIVIDE_WIDTH                     12
  #define I2S_MDR_DIVIDE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
  #define I2S_MDR_FRACT_MASK                       0xFF000u
  #define I2S_MDR_FRACT_SHIFT                      12
  #define I2S_MDR_FRACT_WIDTH                      8
  #define I2S_MDR_FRACT(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
  
  /*!
   * @}
   */ /* end of group I2S_Register_Masks */
  
  
  /* I2S - Peripheral instance base addresses */
  /** Peripheral I2S0 base address */
  #define I2S0_BASE                                (0x4002F000u)
  /** Peripheral I2S0 base pointer */
  #define I2S0                                     ((I2S_Type *)I2S0_BASE)
  #define I2S0_BASE_PTR                            (I2S0)
  /** Peripheral I2S1 base address */
  #define I2S1_BASE                                (0x40030000u)
  /** Peripheral I2S1 base pointer */
  #define I2S1                                     ((I2S_Type *)I2S1_BASE)
  #define I2S1_BASE_PTR                            (I2S1)
  /** Array initializer of I2S peripheral base addresses */
  #define I2S_BASE_ADDRS                           { I2S0_BASE, I2S1_BASE }
  /** Array initializer of I2S peripheral base pointers */
  #define I2S_BASE_PTRS                            { I2S0, I2S1 }
  
  /* ----------------------------------------------------------------------------
     -- I2S - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
   * @{
   */
  
  
  /* I2S - Register instance definitions */
  /* I2S0 */
  #define I2S0_TCSR                                I2S_TCSR_REG(I2S0)
  #define I2S0_TCR1                                I2S_TCR1_REG(I2S0)
  #define I2S0_TCR2                                I2S_TCR2_REG(I2S0)
  #define I2S0_TCR3                                I2S_TCR3_REG(I2S0)
  #define I2S0_TCR4                                I2S_TCR4_REG(I2S0)
  #define I2S0_TCR5                                I2S_TCR5_REG(I2S0)
  #define I2S0_TDR0                                I2S_TDR_REG(I2S0,0)
  #define I2S0_TFR0                                I2S_TFR_REG(I2S0,0)
  #define I2S0_TMR                                 I2S_TMR_REG(I2S0)
  #define I2S0_RCSR                                I2S_RCSR_REG(I2S0)
  #define I2S0_RCR1                                I2S_RCR1_REG(I2S0)
  #define I2S0_RCR2                                I2S_RCR2_REG(I2S0)
  #define I2S0_RCR3                                I2S_RCR3_REG(I2S0)
  #define I2S0_RCR4                                I2S_RCR4_REG(I2S0)
  #define I2S0_RCR5                                I2S_RCR5_REG(I2S0)
  #define I2S0_RDR0                                I2S_RDR_REG(I2S0,0)
  #define I2S0_RFR0                                I2S_RFR_REG(I2S0,0)
  #define I2S0_RMR                                 I2S_RMR_REG(I2S0)
  #define I2S0_MCR                                 I2S_MCR_REG(I2S0)
  #define I2S0_MDR                                 I2S_MDR_REG(I2S0)
  /* I2S1 */
  #define I2S1_TCSR                                I2S_TCSR_REG(I2S1)
  #define I2S1_TCR1                                I2S_TCR1_REG(I2S1)
  #define I2S1_TCR2                                I2S_TCR2_REG(I2S1)
  #define I2S1_TCR3                                I2S_TCR3_REG(I2S1)
  #define I2S1_TCR4                                I2S_TCR4_REG(I2S1)
  #define I2S1_TCR5                                I2S_TCR5_REG(I2S1)
  #define I2S1_TDR0                                I2S_TDR_REG(I2S1,0)
  #define I2S1_TFR0                                I2S_TFR_REG(I2S1,0)
  #define I2S1_TMR                                 I2S_TMR_REG(I2S1)
  #define I2S1_RCSR                                I2S_RCSR_REG(I2S1)
  #define I2S1_RCR1                                I2S_RCR1_REG(I2S1)
  #define I2S1_RCR2                                I2S_RCR2_REG(I2S1)
  #define I2S1_RCR3                                I2S_RCR3_REG(I2S1)
  #define I2S1_RCR4                                I2S_RCR4_REG(I2S1)
  #define I2S1_RCR5                                I2S_RCR5_REG(I2S1)
  #define I2S1_RDR0                                I2S_RDR_REG(I2S1,0)
  #define I2S1_RFR0                                I2S_RFR_REG(I2S1,0)
  #define I2S1_RMR                                 I2S_RMR_REG(I2S1)
  #define I2S1_MCR                                 I2S_MCR_REG(I2S1)
  #define I2S1_MDR                                 I2S_MDR_REG(I2S1)
  
  /* I2S - Register array accessors */
  #define I2S0_TDR(index)                          I2S_TDR_REG(I2S0,index)
  #define I2S1_TDR(index)                          I2S_TDR_REG(I2S1,index)
  #define I2S0_TFR(index)                          I2S_TFR_REG(I2S0,index)
  #define I2S1_TFR(index)                          I2S_TFR_REG(I2S1,index)
  #define I2S0_RDR(index)                          I2S_RDR_REG(I2S0,index)
  #define I2S1_RDR(index)                          I2S_RDR_REG(I2S1,index)
  #define I2S0_RFR(index)                          I2S_RFR_REG(I2S0,index)
  #define I2S1_RFR(index)                          I2S_RFR_REG(I2S1,index)
  
  /*!
   * @}
   */ /* end of group I2S_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group I2S_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- LLWU Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
   * @{
   */
  
  /** LLWU - Register Layout Typedef */
  typedef struct {
    __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
    __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
    __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
    __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
    __IO uint8_t PE5;                                /**< LLWU Pin Enable 5 register, offset: 0x4 */
    __IO uint8_t PE6;                                /**< LLWU Pin Enable 6 register, offset: 0x5 */
    __IO uint8_t PE7;                                /**< LLWU Pin Enable 7 register, offset: 0x6 */
    __IO uint8_t PE8;                                /**< LLWU Pin Enable 8 register, offset: 0x7 */
    __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x8 */
    __IO uint8_t PF1;                                /**< LLWU Pin Flag 1 register, offset: 0x9 */
    __IO uint8_t PF2;                                /**< LLWU Pin Flag 2 register, offset: 0xA */
    __IO uint8_t PF3;                                /**< LLWU Pin Flag 3 register, offset: 0xB */
    __IO uint8_t PF4;                                /**< LLWU Pin Flag 4 register, offset: 0xC */
    __I  uint8_t MF5;                                /**< LLWU Module Flag 5 register, offset: 0xD */
    __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0xE */
    __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0xF */
  } LLWU_Type, *LLWU_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- LLWU - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
   * @{
   */
  
  
  /* LLWU - Register accessors */
  #define LLWU_PE1_REG(base)                       ((base)->PE1)
  #define LLWU_PE2_REG(base)                       ((base)->PE2)
  #define LLWU_PE3_REG(base)                       ((base)->PE3)
  #define LLWU_PE4_REG(base)                       ((base)->PE4)
  #define LLWU_PE5_REG(base)                       ((base)->PE5)
  #define LLWU_PE6_REG(base)                       ((base)->PE6)
  #define LLWU_PE7_REG(base)                       ((base)->PE7)
  #define LLWU_PE8_REG(base)                       ((base)->PE8)
  #define LLWU_ME_REG(base)                        ((base)->ME)
  #define LLWU_PF1_REG(base)                       ((base)->PF1)
  #define LLWU_PF2_REG(base)                       ((base)->PF2)
  #define LLWU_PF3_REG(base)                       ((base)->PF3)
  #define LLWU_PF4_REG(base)                       ((base)->PF4)
  #define LLWU_MF5_REG(base)                       ((base)->MF5)
  #define LLWU_FILT1_REG(base)                     ((base)->FILT1)
  #define LLWU_FILT2_REG(base)                     ((base)->FILT2)
  
  /*!
   * @}
   */ /* end of group LLWU_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- LLWU Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LLWU_Register_Masks LLWU Register Masks
   * @{
   */
  
  /* PE1 Bit Fields */
  #define LLWU_PE1_WUPE0_MASK                      0x3u
  #define LLWU_PE1_WUPE0_SHIFT                     0
  #define LLWU_PE1_WUPE0_WIDTH                     2
  #define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
  #define LLWU_PE1_WUPE1_MASK                      0xCu
  #define LLWU_PE1_WUPE1_SHIFT                     2
  #define LLWU_PE1_WUPE1_WIDTH                     2
  #define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
  #define LLWU_PE1_WUPE2_MASK                      0x30u
  #define LLWU_PE1_WUPE2_SHIFT                     4
  #define LLWU_PE1_WUPE2_WIDTH                     2
  #define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
  #define LLWU_PE1_WUPE3_MASK                      0xC0u
  #define LLWU_PE1_WUPE3_SHIFT                     6
  #define LLWU_PE1_WUPE3_WIDTH                     2
  #define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
  /* PE2 Bit Fields */
  #define LLWU_PE2_WUPE4_MASK                      0x3u
  #define LLWU_PE2_WUPE4_SHIFT                     0
  #define LLWU_PE2_WUPE4_WIDTH                     2
  #define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
  #define LLWU_PE2_WUPE5_MASK                      0xCu
  #define LLWU_PE2_WUPE5_SHIFT                     2
  #define LLWU_PE2_WUPE5_WIDTH                     2
  #define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
  #define LLWU_PE2_WUPE6_MASK                      0x30u
  #define LLWU_PE2_WUPE6_SHIFT                     4
  #define LLWU_PE2_WUPE6_WIDTH                     2
  #define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
  #define LLWU_PE2_WUPE7_MASK                      0xC0u
  #define LLWU_PE2_WUPE7_SHIFT                     6
  #define LLWU_PE2_WUPE7_WIDTH                     2
  #define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
  /* PE3 Bit Fields */
  #define LLWU_PE3_WUPE8_MASK                      0x3u
  #define LLWU_PE3_WUPE8_SHIFT                     0
  #define LLWU_PE3_WUPE8_WIDTH                     2
  #define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
  #define LLWU_PE3_WUPE9_MASK                      0xCu
  #define LLWU_PE3_WUPE9_SHIFT                     2
  #define LLWU_PE3_WUPE9_WIDTH                     2
  #define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
  #define LLWU_PE3_WUPE10_MASK                     0x30u
  #define LLWU_PE3_WUPE10_SHIFT                    4
  #define LLWU_PE3_WUPE10_WIDTH                    2
  #define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
  #define LLWU_PE3_WUPE11_MASK                     0xC0u
  #define LLWU_PE3_WUPE11_SHIFT                    6
  #define LLWU_PE3_WUPE11_WIDTH                    2
  #define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
  /* PE4 Bit Fields */
  #define LLWU_PE4_WUPE12_MASK                     0x3u
  #define LLWU_PE4_WUPE12_SHIFT                    0
  #define LLWU_PE4_WUPE12_WIDTH                    2
  #define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
  #define LLWU_PE4_WUPE13_MASK                     0xCu
  #define LLWU_PE4_WUPE13_SHIFT                    2
  #define LLWU_PE4_WUPE13_WIDTH                    2
  #define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
  #define LLWU_PE4_WUPE14_MASK                     0x30u
  #define LLWU_PE4_WUPE14_SHIFT                    4
  #define LLWU_PE4_WUPE14_WIDTH                    2
  #define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
  #define LLWU_PE4_WUPE15_MASK                     0xC0u
  #define LLWU_PE4_WUPE15_SHIFT                    6
  #define LLWU_PE4_WUPE15_WIDTH                    2
  #define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
  /* PE5 Bit Fields */
  #define LLWU_PE5_WUPE16_MASK                     0x3u
  #define LLWU_PE5_WUPE16_SHIFT                    0
  #define LLWU_PE5_WUPE16_WIDTH                    2
  #define LLWU_PE5_WUPE16(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE5_WUPE16_SHIFT))&LLWU_PE5_WUPE16_MASK)
  #define LLWU_PE5_WUPE17_MASK                     0xCu
  #define LLWU_PE5_WUPE17_SHIFT                    2
  #define LLWU_PE5_WUPE17_WIDTH                    2
  #define LLWU_PE5_WUPE17(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE5_WUPE17_SHIFT))&LLWU_PE5_WUPE17_MASK)
  #define LLWU_PE5_WUPE18_MASK                     0x30u
  #define LLWU_PE5_WUPE18_SHIFT                    4
  #define LLWU_PE5_WUPE18_WIDTH                    2
  #define LLWU_PE5_WUPE18(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE5_WUPE18_SHIFT))&LLWU_PE5_WUPE18_MASK)
  #define LLWU_PE5_WUPE19_MASK                     0xC0u
  #define LLWU_PE5_WUPE19_SHIFT                    6
  #define LLWU_PE5_WUPE19_WIDTH                    2
  #define LLWU_PE5_WUPE19(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE5_WUPE19_SHIFT))&LLWU_PE5_WUPE19_MASK)
  /* PE6 Bit Fields */
  #define LLWU_PE6_WUPE20_MASK                     0x3u
  #define LLWU_PE6_WUPE20_SHIFT                    0
  #define LLWU_PE6_WUPE20_WIDTH                    2
  #define LLWU_PE6_WUPE20(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE6_WUPE20_SHIFT))&LLWU_PE6_WUPE20_MASK)
  #define LLWU_PE6_WUPE21_MASK                     0xCu
  #define LLWU_PE6_WUPE21_SHIFT                    2
  #define LLWU_PE6_WUPE21_WIDTH                    2
  #define LLWU_PE6_WUPE21(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE6_WUPE21_SHIFT))&LLWU_PE6_WUPE21_MASK)
  #define LLWU_PE6_WUPE22_MASK                     0x30u
  #define LLWU_PE6_WUPE22_SHIFT                    4
  #define LLWU_PE6_WUPE22_WIDTH                    2
  #define LLWU_PE6_WUPE22(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE6_WUPE22_SHIFT))&LLWU_PE6_WUPE22_MASK)
  #define LLWU_PE6_WUPE23_MASK                     0xC0u
  #define LLWU_PE6_WUPE23_SHIFT                    6
  #define LLWU_PE6_WUPE23_WIDTH                    2
  #define LLWU_PE6_WUPE23(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE6_WUPE23_SHIFT))&LLWU_PE6_WUPE23_MASK)
  /* PE7 Bit Fields */
  #define LLWU_PE7_WUPE24_MASK                     0x3u
  #define LLWU_PE7_WUPE24_SHIFT                    0
  #define LLWU_PE7_WUPE24_WIDTH                    2
  #define LLWU_PE7_WUPE24(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE7_WUPE24_SHIFT))&LLWU_PE7_WUPE24_MASK)
  #define LLWU_PE7_WUPE25_MASK                     0xCu
  #define LLWU_PE7_WUPE25_SHIFT                    2
  #define LLWU_PE7_WUPE25_WIDTH                    2
  #define LLWU_PE7_WUPE25(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE7_WUPE25_SHIFT))&LLWU_PE7_WUPE25_MASK)
  #define LLWU_PE7_WUPE26_MASK                     0x30u
  #define LLWU_PE7_WUPE26_SHIFT                    4
  #define LLWU_PE7_WUPE26_WIDTH                    2
  #define LLWU_PE7_WUPE26(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE7_WUPE26_SHIFT))&LLWU_PE7_WUPE26_MASK)
  #define LLWU_PE7_WUPE27_MASK                     0xC0u
  #define LLWU_PE7_WUPE27_SHIFT                    6
  #define LLWU_PE7_WUPE27_WIDTH                    2
  #define LLWU_PE7_WUPE27(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE7_WUPE27_SHIFT))&LLWU_PE7_WUPE27_MASK)
  /* PE8 Bit Fields */
  #define LLWU_PE8_WUPE28_MASK                     0x3u
  #define LLWU_PE8_WUPE28_SHIFT                    0
  #define LLWU_PE8_WUPE28_WIDTH                    2
  #define LLWU_PE8_WUPE28(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE8_WUPE28_SHIFT))&LLWU_PE8_WUPE28_MASK)
  #define LLWU_PE8_WUPE29_MASK                     0xCu
  #define LLWU_PE8_WUPE29_SHIFT                    2
  #define LLWU_PE8_WUPE29_WIDTH                    2
  #define LLWU_PE8_WUPE29(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE8_WUPE29_SHIFT))&LLWU_PE8_WUPE29_MASK)
  #define LLWU_PE8_WUPE30_MASK                     0x30u
  #define LLWU_PE8_WUPE30_SHIFT                    4
  #define LLWU_PE8_WUPE30_WIDTH                    2
  #define LLWU_PE8_WUPE30(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE8_WUPE30_SHIFT))&LLWU_PE8_WUPE30_MASK)
  #define LLWU_PE8_WUPE31_MASK                     0xC0u
  #define LLWU_PE8_WUPE31_SHIFT                    6
  #define LLWU_PE8_WUPE31_WIDTH                    2
  #define LLWU_PE8_WUPE31(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE8_WUPE31_SHIFT))&LLWU_PE8_WUPE31_MASK)
  /* ME Bit Fields */
  #define LLWU_ME_WUME0_MASK                       0x1u
  #define LLWU_ME_WUME0_SHIFT                      0
  #define LLWU_ME_WUME0_WIDTH                      1
  #define LLWU_ME_WUME0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME0_SHIFT))&LLWU_ME_WUME0_MASK)
  #define LLWU_ME_WUME1_MASK                       0x2u
  #define LLWU_ME_WUME1_SHIFT                      1
  #define LLWU_ME_WUME1_WIDTH                      1
  #define LLWU_ME_WUME1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME1_SHIFT))&LLWU_ME_WUME1_MASK)
  #define LLWU_ME_WUME2_MASK                       0x4u
  #define LLWU_ME_WUME2_SHIFT                      2
  #define LLWU_ME_WUME2_WIDTH                      1
  #define LLWU_ME_WUME2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME2_SHIFT))&LLWU_ME_WUME2_MASK)
  #define LLWU_ME_WUME3_MASK                       0x8u
  #define LLWU_ME_WUME3_SHIFT                      3
  #define LLWU_ME_WUME3_WIDTH                      1
  #define LLWU_ME_WUME3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME3_SHIFT))&LLWU_ME_WUME3_MASK)
  #define LLWU_ME_WUME4_MASK                       0x10u
  #define LLWU_ME_WUME4_SHIFT                      4
  #define LLWU_ME_WUME4_WIDTH                      1
  #define LLWU_ME_WUME4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME4_SHIFT))&LLWU_ME_WUME4_MASK)
  #define LLWU_ME_WUME5_MASK                       0x20u
  #define LLWU_ME_WUME5_SHIFT                      5
  #define LLWU_ME_WUME5_WIDTH                      1
  #define LLWU_ME_WUME5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME5_SHIFT))&LLWU_ME_WUME5_MASK)
  #define LLWU_ME_WUME6_MASK                       0x40u
  #define LLWU_ME_WUME6_SHIFT                      6
  #define LLWU_ME_WUME6_WIDTH                      1
  #define LLWU_ME_WUME6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME6_SHIFT))&LLWU_ME_WUME6_MASK)
  #define LLWU_ME_WUME7_MASK                       0x80u
  #define LLWU_ME_WUME7_SHIFT                      7
  #define LLWU_ME_WUME7_WIDTH                      1
  #define LLWU_ME_WUME7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_ME_WUME7_SHIFT))&LLWU_ME_WUME7_MASK)
  /* PF1 Bit Fields */
  #define LLWU_PF1_WUF0_MASK                       0x1u
  #define LLWU_PF1_WUF0_SHIFT                      0
  #define LLWU_PF1_WUF0_WIDTH                      1
  #define LLWU_PF1_WUF0(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF0_SHIFT))&LLWU_PF1_WUF0_MASK)
  #define LLWU_PF1_WUF1_MASK                       0x2u
  #define LLWU_PF1_WUF1_SHIFT                      1
  #define LLWU_PF1_WUF1_WIDTH                      1
  #define LLWU_PF1_WUF1(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF1_SHIFT))&LLWU_PF1_WUF1_MASK)
  #define LLWU_PF1_WUF2_MASK                       0x4u
  #define LLWU_PF1_WUF2_SHIFT                      2
  #define LLWU_PF1_WUF2_WIDTH                      1
  #define LLWU_PF1_WUF2(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF2_SHIFT))&LLWU_PF1_WUF2_MASK)
  #define LLWU_PF1_WUF3_MASK                       0x8u
  #define LLWU_PF1_WUF3_SHIFT                      3
  #define LLWU_PF1_WUF3_WIDTH                      1
  #define LLWU_PF1_WUF3(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF3_SHIFT))&LLWU_PF1_WUF3_MASK)
  #define LLWU_PF1_WUF4_MASK                       0x10u
  #define LLWU_PF1_WUF4_SHIFT                      4
  #define LLWU_PF1_WUF4_WIDTH                      1
  #define LLWU_PF1_WUF4(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF4_SHIFT))&LLWU_PF1_WUF4_MASK)
  #define LLWU_PF1_WUF5_MASK                       0x20u
  #define LLWU_PF1_WUF5_SHIFT                      5
  #define LLWU_PF1_WUF5_WIDTH                      1
  #define LLWU_PF1_WUF5(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF5_SHIFT))&LLWU_PF1_WUF5_MASK)
  #define LLWU_PF1_WUF6_MASK                       0x40u
  #define LLWU_PF1_WUF6_SHIFT                      6
  #define LLWU_PF1_WUF6_WIDTH                      1
  #define LLWU_PF1_WUF6(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF6_SHIFT))&LLWU_PF1_WUF6_MASK)
  #define LLWU_PF1_WUF7_MASK                       0x80u
  #define LLWU_PF1_WUF7_SHIFT                      7
  #define LLWU_PF1_WUF7_WIDTH                      1
  #define LLWU_PF1_WUF7(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_PF1_WUF7_SHIFT))&LLWU_PF1_WUF7_MASK)
  /* PF2 Bit Fields */
  #define LLWU_PF2_WUF8_MASK                       0x1u
  #define LLWU_PF2_WUF8_SHIFT                      0
  #define LLWU_PF2_WUF8_WIDTH                      1
  #define LLWU_PF2_WUF8(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF8_SHIFT))&LLWU_PF2_WUF8_MASK)
  #define LLWU_PF2_WUF9_MASK                       0x2u
  #define LLWU_PF2_WUF9_SHIFT                      1
  #define LLWU_PF2_WUF9_WIDTH                      1
  #define LLWU_PF2_WUF9(x)                         (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF9_SHIFT))&LLWU_PF2_WUF9_MASK)
  #define LLWU_PF2_WUF10_MASK                      0x4u
  #define LLWU_PF2_WUF10_SHIFT                     2
  #define LLWU_PF2_WUF10_WIDTH                     1
  #define LLWU_PF2_WUF10(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF10_SHIFT))&LLWU_PF2_WUF10_MASK)
  #define LLWU_PF2_WUF11_MASK                      0x8u
  #define LLWU_PF2_WUF11_SHIFT                     3
  #define LLWU_PF2_WUF11_WIDTH                     1
  #define LLWU_PF2_WUF11(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF11_SHIFT))&LLWU_PF2_WUF11_MASK)
  #define LLWU_PF2_WUF12_MASK                      0x10u
  #define LLWU_PF2_WUF12_SHIFT                     4
  #define LLWU_PF2_WUF12_WIDTH                     1
  #define LLWU_PF2_WUF12(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF12_SHIFT))&LLWU_PF2_WUF12_MASK)
  #define LLWU_PF2_WUF13_MASK                      0x20u
  #define LLWU_PF2_WUF13_SHIFT                     5
  #define LLWU_PF2_WUF13_WIDTH                     1
  #define LLWU_PF2_WUF13(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF13_SHIFT))&LLWU_PF2_WUF13_MASK)
  #define LLWU_PF2_WUF14_MASK                      0x40u
  #define LLWU_PF2_WUF14_SHIFT                     6
  #define LLWU_PF2_WUF14_WIDTH                     1
  #define LLWU_PF2_WUF14(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF14_SHIFT))&LLWU_PF2_WUF14_MASK)
  #define LLWU_PF2_WUF15_MASK                      0x80u
  #define LLWU_PF2_WUF15_SHIFT                     7
  #define LLWU_PF2_WUF15_WIDTH                     1
  #define LLWU_PF2_WUF15(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF2_WUF15_SHIFT))&LLWU_PF2_WUF15_MASK)
  /* PF3 Bit Fields */
  #define LLWU_PF3_WUF16_MASK                      0x1u
  #define LLWU_PF3_WUF16_SHIFT                     0
  #define LLWU_PF3_WUF16_WIDTH                     1
  #define LLWU_PF3_WUF16(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF16_SHIFT))&LLWU_PF3_WUF16_MASK)
  #define LLWU_PF3_WUF17_MASK                      0x2u
  #define LLWU_PF3_WUF17_SHIFT                     1
  #define LLWU_PF3_WUF17_WIDTH                     1
  #define LLWU_PF3_WUF17(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF17_SHIFT))&LLWU_PF3_WUF17_MASK)
  #define LLWU_PF3_WUF18_MASK                      0x4u
  #define LLWU_PF3_WUF18_SHIFT                     2
  #define LLWU_PF3_WUF18_WIDTH                     1
  #define LLWU_PF3_WUF18(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF18_SHIFT))&LLWU_PF3_WUF18_MASK)
  #define LLWU_PF3_WUF19_MASK                      0x8u
  #define LLWU_PF3_WUF19_SHIFT                     3
  #define LLWU_PF3_WUF19_WIDTH                     1
  #define LLWU_PF3_WUF19(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF19_SHIFT))&LLWU_PF3_WUF19_MASK)
  #define LLWU_PF3_WUF20_MASK                      0x10u
  #define LLWU_PF3_WUF20_SHIFT                     4
  #define LLWU_PF3_WUF20_WIDTH                     1
  #define LLWU_PF3_WUF20(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF20_SHIFT))&LLWU_PF3_WUF20_MASK)
  #define LLWU_PF3_WUF21_MASK                      0x20u
  #define LLWU_PF3_WUF21_SHIFT                     5
  #define LLWU_PF3_WUF21_WIDTH                     1
  #define LLWU_PF3_WUF21(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF21_SHIFT))&LLWU_PF3_WUF21_MASK)
  #define LLWU_PF3_WUF22_MASK                      0x40u
  #define LLWU_PF3_WUF22_SHIFT                     6
  #define LLWU_PF3_WUF22_WIDTH                     1
  #define LLWU_PF3_WUF22(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF22_SHIFT))&LLWU_PF3_WUF22_MASK)
  #define LLWU_PF3_WUF23_MASK                      0x80u
  #define LLWU_PF3_WUF23_SHIFT                     7
  #define LLWU_PF3_WUF23_WIDTH                     1
  #define LLWU_PF3_WUF23(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF3_WUF23_SHIFT))&LLWU_PF3_WUF23_MASK)
  /* PF4 Bit Fields */
  #define LLWU_PF4_WUF24_MASK                      0x1u
  #define LLWU_PF4_WUF24_SHIFT                     0
  #define LLWU_PF4_WUF24_WIDTH                     1
  #define LLWU_PF4_WUF24(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF24_SHIFT))&LLWU_PF4_WUF24_MASK)
  #define LLWU_PF4_WUF25_MASK                      0x2u
  #define LLWU_PF4_WUF25_SHIFT                     1
  #define LLWU_PF4_WUF25_WIDTH                     1
  #define LLWU_PF4_WUF25(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF25_SHIFT))&LLWU_PF4_WUF25_MASK)
  #define LLWU_PF4_WUF26_MASK                      0x4u
  #define LLWU_PF4_WUF26_SHIFT                     2
  #define LLWU_PF4_WUF26_WIDTH                     1
  #define LLWU_PF4_WUF26(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF26_SHIFT))&LLWU_PF4_WUF26_MASK)
  #define LLWU_PF4_WUF27_MASK                      0x8u
  #define LLWU_PF4_WUF27_SHIFT                     3
  #define LLWU_PF4_WUF27_WIDTH                     1
  #define LLWU_PF4_WUF27(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF27_SHIFT))&LLWU_PF4_WUF27_MASK)
  #define LLWU_PF4_WUF28_MASK                      0x10u
  #define LLWU_PF4_WUF28_SHIFT                     4
  #define LLWU_PF4_WUF28_WIDTH                     1
  #define LLWU_PF4_WUF28(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF28_SHIFT))&LLWU_PF4_WUF28_MASK)
  #define LLWU_PF4_WUF29_MASK                      0x20u
  #define LLWU_PF4_WUF29_SHIFT                     5
  #define LLWU_PF4_WUF29_WIDTH                     1
  #define LLWU_PF4_WUF29(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF29_SHIFT))&LLWU_PF4_WUF29_MASK)
  #define LLWU_PF4_WUF30_MASK                      0x40u
  #define LLWU_PF4_WUF30_SHIFT                     6
  #define LLWU_PF4_WUF30_WIDTH                     1
  #define LLWU_PF4_WUF30(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF30_SHIFT))&LLWU_PF4_WUF30_MASK)
  #define LLWU_PF4_WUF31_MASK                      0x80u
  #define LLWU_PF4_WUF31_SHIFT                     7
  #define LLWU_PF4_WUF31_WIDTH                     1
  #define LLWU_PF4_WUF31(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PF4_WUF31_SHIFT))&LLWU_PF4_WUF31_MASK)
  /* MF5 Bit Fields */
  #define LLWU_MF5_MWUF0_MASK                      0x1u
  #define LLWU_MF5_MWUF0_SHIFT                     0
  #define LLWU_MF5_MWUF0_WIDTH                     1
  #define LLWU_MF5_MWUF0(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF0_SHIFT))&LLWU_MF5_MWUF0_MASK)
  #define LLWU_MF5_MWUF1_MASK                      0x2u
  #define LLWU_MF5_MWUF1_SHIFT                     1
  #define LLWU_MF5_MWUF1_WIDTH                     1
  #define LLWU_MF5_MWUF1(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF1_SHIFT))&LLWU_MF5_MWUF1_MASK)
  #define LLWU_MF5_MWUF2_MASK                      0x4u
  #define LLWU_MF5_MWUF2_SHIFT                     2
  #define LLWU_MF5_MWUF2_WIDTH                     1
  #define LLWU_MF5_MWUF2(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF2_SHIFT))&LLWU_MF5_MWUF2_MASK)
  #define LLWU_MF5_MWUF3_MASK                      0x8u
  #define LLWU_MF5_MWUF3_SHIFT                     3
  #define LLWU_MF5_MWUF3_WIDTH                     1
  #define LLWU_MF5_MWUF3(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF3_SHIFT))&LLWU_MF5_MWUF3_MASK)
  #define LLWU_MF5_MWUF4_MASK                      0x10u
  #define LLWU_MF5_MWUF4_SHIFT                     4
  #define LLWU_MF5_MWUF4_WIDTH                     1
  #define LLWU_MF5_MWUF4(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF4_SHIFT))&LLWU_MF5_MWUF4_MASK)
  #define LLWU_MF5_MWUF5_MASK                      0x20u
  #define LLWU_MF5_MWUF5_SHIFT                     5
  #define LLWU_MF5_MWUF5_WIDTH                     1
  #define LLWU_MF5_MWUF5(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF5_SHIFT))&LLWU_MF5_MWUF5_MASK)
  #define LLWU_MF5_MWUF6_MASK                      0x40u
  #define LLWU_MF5_MWUF6_SHIFT                     6
  #define LLWU_MF5_MWUF6_WIDTH                     1
  #define LLWU_MF5_MWUF6(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF6_SHIFT))&LLWU_MF5_MWUF6_MASK)
  #define LLWU_MF5_MWUF7_MASK                      0x80u
  #define LLWU_MF5_MWUF7_SHIFT                     7
  #define LLWU_MF5_MWUF7_WIDTH                     1
  #define LLWU_MF5_MWUF7(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_MF5_MWUF7_SHIFT))&LLWU_MF5_MWUF7_MASK)
  /* FILT1 Bit Fields */
  #define LLWU_FILT1_FILTSEL_MASK                  0x1Fu
  #define LLWU_FILT1_FILTSEL_SHIFT                 0
  #define LLWU_FILT1_FILTSEL_WIDTH                 5
  #define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
  #define LLWU_FILT1_FILTE_MASK                    0x60u
  #define LLWU_FILT1_FILTE_SHIFT                   5
  #define LLWU_FILT1_FILTE_WIDTH                   2
  #define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
  #define LLWU_FILT1_FILTF_MASK                    0x80u
  #define LLWU_FILT1_FILTF_SHIFT                   7
  #define LLWU_FILT1_FILTF_WIDTH                   1
  #define LLWU_FILT1_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTF_SHIFT))&LLWU_FILT1_FILTF_MASK)
  /* FILT2 Bit Fields */
  #define LLWU_FILT2_FILTSEL_MASK                  0x1Fu
  #define LLWU_FILT2_FILTSEL_SHIFT                 0
  #define LLWU_FILT2_FILTSEL_WIDTH                 5
  #define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
  #define LLWU_FILT2_FILTE_MASK                    0x60u
  #define LLWU_FILT2_FILTE_SHIFT                   5
  #define LLWU_FILT2_FILTE_WIDTH                   2
  #define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
  #define LLWU_FILT2_FILTF_MASK                    0x80u
  #define LLWU_FILT2_FILTF_SHIFT                   7
  #define LLWU_FILT2_FILTF_WIDTH                   1
  #define LLWU_FILT2_FILTF(x)                      (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTF_SHIFT))&LLWU_FILT2_FILTF_MASK)
  
  /*!
   * @}
   */ /* end of group LLWU_Register_Masks */
  
  
  /* LLWU - Peripheral instance base addresses */
  /** Peripheral LLWU base address */
  #define LLWU_BASE                                (0x4007C000u)
  /** Peripheral LLWU base pointer */
  #define LLWU                                     ((LLWU_Type *)LLWU_BASE)
  #define LLWU_BASE_PTR                            (LLWU)
  /** Array initializer of LLWU peripheral base addresses */
  #define LLWU_BASE_ADDRS                          { LLWU_BASE }
  /** Array initializer of LLWU peripheral base pointers */
  #define LLWU_BASE_PTRS                           { LLWU }
  
  /* ----------------------------------------------------------------------------
     -- LLWU - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
   * @{
   */
  
  
  /* LLWU - Register instance definitions */
  /* LLWU */
  #define LLWU_PE1                                 LLWU_PE1_REG(LLWU)
  #define LLWU_PE2                                 LLWU_PE2_REG(LLWU)
  #define LLWU_PE3                                 LLWU_PE3_REG(LLWU)
  #define LLWU_PE4                                 LLWU_PE4_REG(LLWU)
  #define LLWU_PE5                                 LLWU_PE5_REG(LLWU)
  #define LLWU_PE6                                 LLWU_PE6_REG(LLWU)
  #define LLWU_PE7                                 LLWU_PE7_REG(LLWU)
  #define LLWU_PE8                                 LLWU_PE8_REG(LLWU)
  #define LLWU_ME                                  LLWU_ME_REG(LLWU)
  #define LLWU_PF1                                 LLWU_PF1_REG(LLWU)
  #define LLWU_PF2                                 LLWU_PF2_REG(LLWU)
  #define LLWU_PF3                                 LLWU_PF3_REG(LLWU)
  #define LLWU_PF4                                 LLWU_PF4_REG(LLWU)
  #define LLWU_MF5                                 LLWU_MF5_REG(LLWU)
  #define LLWU_FILT1                               LLWU_FILT1_REG(LLWU)
  #define LLWU_FILT2                               LLWU_FILT2_REG(LLWU)
  
  /*!
   * @}
   */ /* end of group LLWU_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group LLWU_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- LPI2C Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
   * @{
   */
  
  /** LPI2C - Register Layout Typedef */
  typedef struct {
    __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
    __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
         uint8_t RESERVED_0[8];
    __IO uint32_t MCR;                               /**< Master Control Register, offset: 0x10 */
    __IO uint32_t MSR;                               /**< Master Status Register, offset: 0x14 */
    __IO uint32_t MIER;                              /**< Master Interrupt Enable Register, offset: 0x18 */
    __IO uint32_t MDER;                              /**< Master DMA Enable Register, offset: 0x1C */
    __IO uint32_t MCFGR0;                            /**< Master Configuration Register 0, offset: 0x20 */
    __IO uint32_t MCFGR1;                            /**< Master Configuration Register 1, offset: 0x24 */
    __IO uint32_t MCFGR2;                            /**< Master Configuration Register 2, offset: 0x28 */
    __IO uint32_t MCFGR3;                            /**< Master Configuration Register 3, offset: 0x2C */
         uint8_t RESERVED_1[16];
    __IO uint32_t MDMR;                              /**< Master Data Match Register, offset: 0x40 */
         uint8_t RESERVED_2[4];
    __IO uint32_t MCCR0;                             /**< Master Clock Configuration Register 0, offset: 0x48 */
         uint8_t RESERVED_3[4];
    __IO uint32_t MCCR1;                             /**< Master Clock Configuration Register 1, offset: 0x50 */
         uint8_t RESERVED_4[4];
    __IO uint32_t MFCR;                              /**< Master FIFO Control Register, offset: 0x58 */
    __I  uint32_t MFSR;                              /**< Master FIFO Status Register, offset: 0x5C */
    __O  uint32_t MTDR;                              /**< Master Transmit Data Register, offset: 0x60 */
         uint8_t RESERVED_5[12];
    __I  uint32_t MRDR;                              /**< Master Receive Data Register, offset: 0x70 */
         uint8_t RESERVED_6[156];
    __IO uint32_t SCR;                               /**< Slave Control Register, offset: 0x110 */
    __IO uint32_t SSR;                               /**< Slave Status Register, offset: 0x114 */
    __IO uint32_t SIER;                              /**< Slave Interrupt Enable Register, offset: 0x118 */
    __IO uint32_t SDER;                              /**< Slave DMA Enable Register, offset: 0x11C */
         uint8_t RESERVED_7[4];
    __IO uint32_t SCFGR1;                            /**< Slave Configuration Register 1, offset: 0x124 */
    __IO uint32_t SCFGR2;                            /**< Slave Configuration Register 2, offset: 0x128 */
         uint8_t RESERVED_8[20];
    __IO uint32_t SAMR;                              /**< Slave Address Match Register, offset: 0x140 */
         uint8_t RESERVED_9[12];
    __I  uint32_t SASR;                              /**< Slave Address Status Register, offset: 0x150 */
    __IO uint32_t STAR;                              /**< Slave Transmit ACK Register, offset: 0x154 */
         uint8_t RESERVED_10[8];
    __O  uint32_t STDR;                              /**< Slave Transmit Data Register, offset: 0x160 */
         uint8_t RESERVED_11[12];
    __I  uint32_t SRDR;                              /**< Slave Receive Data Register, offset: 0x170 */
  } LPI2C_Type, *LPI2C_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- LPI2C - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPI2C_Register_Accessor_Macros LPI2C - Register accessor macros
   * @{
   */
  
  
  /* LPI2C - Register accessors */
  #define LPI2C_VERID_REG(base)                    ((base)->VERID)
  #define LPI2C_PARAM_REG(base)                    ((base)->PARAM)
  #define LPI2C_MCR_REG(base)                      ((base)->MCR)
  #define LPI2C_MSR_REG(base)                      ((base)->MSR)
  #define LPI2C_MIER_REG(base)                     ((base)->MIER)
  #define LPI2C_MDER_REG(base)                     ((base)->MDER)
  #define LPI2C_MCFGR0_REG(base)                   ((base)->MCFGR0)
  #define LPI2C_MCFGR1_REG(base)                   ((base)->MCFGR1)
  #define LPI2C_MCFGR2_REG(base)                   ((base)->MCFGR2)
  #define LPI2C_MCFGR3_REG(base)                   ((base)->MCFGR3)
  #define LPI2C_MDMR_REG(base)                     ((base)->MDMR)
  #define LPI2C_MCCR0_REG(base)                    ((base)->MCCR0)
  #define LPI2C_MCCR1_REG(base)                    ((base)->MCCR1)
  #define LPI2C_MFCR_REG(base)                     ((base)->MFCR)
  #define LPI2C_MFSR_REG(base)                     ((base)->MFSR)
  #define LPI2C_MTDR_REG(base)                     ((base)->MTDR)
  #define LPI2C_MRDR_REG(base)                     ((base)->MRDR)
  #define LPI2C_SCR_REG(base)                      ((base)->SCR)
  #define LPI2C_SSR_REG(base)                      ((base)->SSR)
  #define LPI2C_SIER_REG(base)                     ((base)->SIER)
  #define LPI2C_SDER_REG(base)                     ((base)->SDER)
  #define LPI2C_SCFGR1_REG(base)                   ((base)->SCFGR1)
  #define LPI2C_SCFGR2_REG(base)                   ((base)->SCFGR2)
  #define LPI2C_SAMR_REG(base)                     ((base)->SAMR)
  #define LPI2C_SASR_REG(base)                     ((base)->SASR)
  #define LPI2C_STAR_REG(base)                     ((base)->STAR)
  #define LPI2C_STDR_REG(base)                     ((base)->STDR)
  #define LPI2C_SRDR_REG(base)                     ((base)->SRDR)
  
  /*!
   * @}
   */ /* end of group LPI2C_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- LPI2C Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
   * @{
   */
  
  /* VERID Bit Fields */
  #define LPI2C_VERID_FEATURE_MASK                 0xFFFFu
  #define LPI2C_VERID_FEATURE_SHIFT                0
  #define LPI2C_VERID_FEATURE_WIDTH                16
  #define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_FEATURE_SHIFT))&LPI2C_VERID_FEATURE_MASK)
  #define LPI2C_VERID_MINOR_MASK                   0xFF0000u
  #define LPI2C_VERID_MINOR_SHIFT                  16
  #define LPI2C_VERID_MINOR_WIDTH                  8
  #define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MINOR_SHIFT))&LPI2C_VERID_MINOR_MASK)
  #define LPI2C_VERID_MAJOR_MASK                   0xFF000000u
  #define LPI2C_VERID_MAJOR_SHIFT                  24
  #define LPI2C_VERID_MAJOR_WIDTH                  8
  #define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MAJOR_SHIFT))&LPI2C_VERID_MAJOR_MASK)
  /* PARAM Bit Fields */
  #define LPI2C_PARAM_MTXFIFO_MASK                 0xFu
  #define LPI2C_PARAM_MTXFIFO_SHIFT                0
  #define LPI2C_PARAM_MTXFIFO_WIDTH                4
  #define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MTXFIFO_SHIFT))&LPI2C_PARAM_MTXFIFO_MASK)
  #define LPI2C_PARAM_MRXFIFO_MASK                 0xF00u
  #define LPI2C_PARAM_MRXFIFO_SHIFT                8
  #define LPI2C_PARAM_MRXFIFO_WIDTH                4
  #define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MRXFIFO_SHIFT))&LPI2C_PARAM_MRXFIFO_MASK)
  /* MCR Bit Fields */
  #define LPI2C_MCR_MEN_MASK                       0x1u
  #define LPI2C_MCR_MEN_SHIFT                      0
  #define LPI2C_MCR_MEN_WIDTH                      1
  #define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_MEN_SHIFT))&LPI2C_MCR_MEN_MASK)
  #define LPI2C_MCR_RST_MASK                       0x2u
  #define LPI2C_MCR_RST_SHIFT                      1
  #define LPI2C_MCR_RST_WIDTH                      1
  #define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RST_SHIFT))&LPI2C_MCR_RST_MASK)
  #define LPI2C_MCR_DOZEN_MASK                     0x4u
  #define LPI2C_MCR_DOZEN_SHIFT                    2
  #define LPI2C_MCR_DOZEN_WIDTH                    1
  #define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DOZEN_SHIFT))&LPI2C_MCR_DOZEN_MASK)
  #define LPI2C_MCR_DBGEN_MASK                     0x8u
  #define LPI2C_MCR_DBGEN_SHIFT                    3
  #define LPI2C_MCR_DBGEN_WIDTH                    1
  #define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DBGEN_SHIFT))&LPI2C_MCR_DBGEN_MASK)
  #define LPI2C_MCR_RTF_MASK                       0x100u
  #define LPI2C_MCR_RTF_SHIFT                      8
  #define LPI2C_MCR_RTF_WIDTH                      1
  #define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RTF_SHIFT))&LPI2C_MCR_RTF_MASK)
  #define LPI2C_MCR_RRF_MASK                       0x200u
  #define LPI2C_MCR_RRF_SHIFT                      9
  #define LPI2C_MCR_RRF_WIDTH                      1
  #define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RRF_SHIFT))&LPI2C_MCR_RRF_MASK)
  /* MSR Bit Fields */
  #define LPI2C_MSR_TDF_MASK                       0x1u
  #define LPI2C_MSR_TDF_SHIFT                      0
  #define LPI2C_MSR_TDF_WIDTH                      1
  #define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_TDF_SHIFT))&LPI2C_MSR_TDF_MASK)
  #define LPI2C_MSR_RDF_MASK                       0x2u
  #define LPI2C_MSR_RDF_SHIFT                      1
  #define LPI2C_MSR_RDF_WIDTH                      1
  #define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_RDF_SHIFT))&LPI2C_MSR_RDF_MASK)
  #define LPI2C_MSR_EPF_MASK                       0x100u
  #define LPI2C_MSR_EPF_SHIFT                      8
  #define LPI2C_MSR_EPF_WIDTH                      1
  #define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_EPF_SHIFT))&LPI2C_MSR_EPF_MASK)
  #define LPI2C_MSR_SDF_MASK                       0x200u
  #define LPI2C_MSR_SDF_SHIFT                      9
  #define LPI2C_MSR_SDF_WIDTH                      1
  #define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_SDF_SHIFT))&LPI2C_MSR_SDF_MASK)
  #define LPI2C_MSR_NDF_MASK                       0x400u
  #define LPI2C_MSR_NDF_SHIFT                      10
  #define LPI2C_MSR_NDF_WIDTH                      1
  #define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_NDF_SHIFT))&LPI2C_MSR_NDF_MASK)
  #define LPI2C_MSR_ALF_MASK                       0x800u
  #define LPI2C_MSR_ALF_SHIFT                      11
  #define LPI2C_MSR_ALF_WIDTH                      1
  #define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_ALF_SHIFT))&LPI2C_MSR_ALF_MASK)
  #define LPI2C_MSR_FEF_MASK                       0x1000u
  #define LPI2C_MSR_FEF_SHIFT                      12
  #define LPI2C_MSR_FEF_WIDTH                      1
  #define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_FEF_SHIFT))&LPI2C_MSR_FEF_MASK)
  #define LPI2C_MSR_PLTF_MASK                      0x2000u
  #define LPI2C_MSR_PLTF_SHIFT                     13
  #define LPI2C_MSR_PLTF_WIDTH                     1
  #define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_PLTF_SHIFT))&LPI2C_MSR_PLTF_MASK)
  #define LPI2C_MSR_DMF_MASK                       0x4000u
  #define LPI2C_MSR_DMF_SHIFT                      14
  #define LPI2C_MSR_DMF_WIDTH                      1
  #define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_DMF_SHIFT))&LPI2C_MSR_DMF_MASK)
  #define LPI2C_MSR_MBF_MASK                       0x1000000u
  #define LPI2C_MSR_MBF_SHIFT                      24
  #define LPI2C_MSR_MBF_WIDTH                      1
  #define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_MBF_SHIFT))&LPI2C_MSR_MBF_MASK)
  #define LPI2C_MSR_BBF_MASK                       0x2000000u
  #define LPI2C_MSR_BBF_SHIFT                      25
  #define LPI2C_MSR_BBF_WIDTH                      1
  #define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_BBF_SHIFT))&LPI2C_MSR_BBF_MASK)
  /* MIER Bit Fields */
  #define LPI2C_MIER_TDIE_MASK                     0x1u
  #define LPI2C_MIER_TDIE_SHIFT                    0
  #define LPI2C_MIER_TDIE_WIDTH                    1
  #define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_TDIE_SHIFT))&LPI2C_MIER_TDIE_MASK)
  #define LPI2C_MIER_RDIE_MASK                     0x2u
  #define LPI2C_MIER_RDIE_SHIFT                    1
  #define LPI2C_MIER_RDIE_WIDTH                    1
  #define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_RDIE_SHIFT))&LPI2C_MIER_RDIE_MASK)
  #define LPI2C_MIER_EPIE_MASK                     0x100u
  #define LPI2C_MIER_EPIE_SHIFT                    8
  #define LPI2C_MIER_EPIE_WIDTH                    1
  #define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_EPIE_SHIFT))&LPI2C_MIER_EPIE_MASK)
  #define LPI2C_MIER_SDIE_MASK                     0x200u
  #define LPI2C_MIER_SDIE_SHIFT                    9
  #define LPI2C_MIER_SDIE_WIDTH                    1
  #define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_SDIE_SHIFT))&LPI2C_MIER_SDIE_MASK)
  #define LPI2C_MIER_NDIE_MASK                     0x400u
  #define LPI2C_MIER_NDIE_SHIFT                    10
  #define LPI2C_MIER_NDIE_WIDTH                    1
  #define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_NDIE_SHIFT))&LPI2C_MIER_NDIE_MASK)
  #define LPI2C_MIER_ALIE_MASK                     0x800u
  #define LPI2C_MIER_ALIE_SHIFT                    11
  #define LPI2C_MIER_ALIE_WIDTH                    1
  #define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_ALIE_SHIFT))&LPI2C_MIER_ALIE_MASK)
  #define LPI2C_MIER_FEIE_MASK                     0x1000u
  #define LPI2C_MIER_FEIE_SHIFT                    12
  #define LPI2C_MIER_FEIE_WIDTH                    1
  #define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_FEIE_SHIFT))&LPI2C_MIER_FEIE_MASK)
  #define LPI2C_MIER_PLTIE_MASK                    0x2000u
  #define LPI2C_MIER_PLTIE_SHIFT                   13
  #define LPI2C_MIER_PLTIE_WIDTH                   1
  #define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_PLTIE_SHIFT))&LPI2C_MIER_PLTIE_MASK)
  #define LPI2C_MIER_DMIE_MASK                     0x4000u
  #define LPI2C_MIER_DMIE_SHIFT                    14
  #define LPI2C_MIER_DMIE_WIDTH                    1
  #define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_DMIE_SHIFT))&LPI2C_MIER_DMIE_MASK)
  /* MDER Bit Fields */
  #define LPI2C_MDER_TDDE_MASK                     0x1u
  #define LPI2C_MDER_TDDE_SHIFT                    0
  #define LPI2C_MDER_TDDE_WIDTH                    1
  #define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_TDDE_SHIFT))&LPI2C_MDER_TDDE_MASK)
  #define LPI2C_MDER_RDDE_MASK                     0x2u
  #define LPI2C_MDER_RDDE_SHIFT                    1
  #define LPI2C_MDER_RDDE_WIDTH                    1
  #define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_RDDE_SHIFT))&LPI2C_MDER_RDDE_MASK)
  /* MCFGR0 Bit Fields */
  #define LPI2C_MCFGR0_HREN_MASK                   0x1u
  #define LPI2C_MCFGR0_HREN_SHIFT                  0
  #define LPI2C_MCFGR0_HREN_WIDTH                  1
  #define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HREN_SHIFT))&LPI2C_MCFGR0_HREN_MASK)
  #define LPI2C_MCFGR0_HRPOL_MASK                  0x2u
  #define LPI2C_MCFGR0_HRPOL_SHIFT                 1
  #define LPI2C_MCFGR0_HRPOL_WIDTH                 1
  #define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRPOL_SHIFT))&LPI2C_MCFGR0_HRPOL_MASK)
  #define LPI2C_MCFGR0_HRSEL_MASK                  0x4u
  #define LPI2C_MCFGR0_HRSEL_SHIFT                 2
  #define LPI2C_MCFGR0_HRSEL_WIDTH                 1
  #define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRSEL_SHIFT))&LPI2C_MCFGR0_HRSEL_MASK)
  #define LPI2C_MCFGR0_CIRFIFO_MASK                0x100u
  #define LPI2C_MCFGR0_CIRFIFO_SHIFT               8
  #define LPI2C_MCFGR0_CIRFIFO_WIDTH               1
  #define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_CIRFIFO_SHIFT))&LPI2C_MCFGR0_CIRFIFO_MASK)
  #define LPI2C_MCFGR0_RDMO_MASK                   0x200u
  #define LPI2C_MCFGR0_RDMO_SHIFT                  9
  #define LPI2C_MCFGR0_RDMO_WIDTH                  1
  #define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_RDMO_SHIFT))&LPI2C_MCFGR0_RDMO_MASK)
  /* MCFGR1 Bit Fields */
  #define LPI2C_MCFGR1_PRESCALE_MASK               0x7u
  #define LPI2C_MCFGR1_PRESCALE_SHIFT              0
  #define LPI2C_MCFGR1_PRESCALE_WIDTH              3
  #define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PRESCALE_SHIFT))&LPI2C_MCFGR1_PRESCALE_MASK)
  #define LPI2C_MCFGR1_AUTOSTOP_MASK               0x100u
  #define LPI2C_MCFGR1_AUTOSTOP_SHIFT              8
  #define LPI2C_MCFGR1_AUTOSTOP_WIDTH              1
  #define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_AUTOSTOP_SHIFT))&LPI2C_MCFGR1_AUTOSTOP_MASK)
  #define LPI2C_MCFGR1_IGNACK_MASK                 0x200u
  #define LPI2C_MCFGR1_IGNACK_SHIFT                9
  #define LPI2C_MCFGR1_IGNACK_WIDTH                1
  #define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_IGNACK_SHIFT))&LPI2C_MCFGR1_IGNACK_MASK)
  #define LPI2C_MCFGR1_TIMECFG_MASK                0x400u
  #define LPI2C_MCFGR1_TIMECFG_SHIFT               10
  #define LPI2C_MCFGR1_TIMECFG_WIDTH               1
  #define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_TIMECFG_SHIFT))&LPI2C_MCFGR1_TIMECFG_MASK)
  #define LPI2C_MCFGR1_MATCFG_MASK                 0x70000u
  #define LPI2C_MCFGR1_MATCFG_SHIFT                16
  #define LPI2C_MCFGR1_MATCFG_WIDTH                3
  #define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_MATCFG_SHIFT))&LPI2C_MCFGR1_MATCFG_MASK)
  #define LPI2C_MCFGR1_PINCFG_MASK                 0x7000000u
  #define LPI2C_MCFGR1_PINCFG_SHIFT                24
  #define LPI2C_MCFGR1_PINCFG_WIDTH                3
  #define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PINCFG_SHIFT))&LPI2C_MCFGR1_PINCFG_MASK)
  /* MCFGR2 Bit Fields */
  #define LPI2C_MCFGR2_BUSIDLE_MASK                0xFFFu
  #define LPI2C_MCFGR2_BUSIDLE_SHIFT               0
  #define LPI2C_MCFGR2_BUSIDLE_WIDTH               12
  #define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_BUSIDLE_SHIFT))&LPI2C_MCFGR2_BUSIDLE_MASK)
  #define LPI2C_MCFGR2_FILTSCL_MASK                0xF0000u
  #define LPI2C_MCFGR2_FILTSCL_SHIFT               16
  #define LPI2C_MCFGR2_FILTSCL_WIDTH               4
  #define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSCL_SHIFT))&LPI2C_MCFGR2_FILTSCL_MASK)
  #define LPI2C_MCFGR2_FILTSDA_MASK                0xF000000u
  #define LPI2C_MCFGR2_FILTSDA_SHIFT               24
  #define LPI2C_MCFGR2_FILTSDA_WIDTH               4
  #define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSDA_SHIFT))&LPI2C_MCFGR2_FILTSDA_MASK)
  /* MCFGR3 Bit Fields */
  #define LPI2C_MCFGR3_PINLOW_MASK                 0xFFF00u
  #define LPI2C_MCFGR3_PINLOW_SHIFT                8
  #define LPI2C_MCFGR3_PINLOW_WIDTH                12
  #define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR3_PINLOW_SHIFT))&LPI2C_MCFGR3_PINLOW_MASK)
  /* MDMR Bit Fields */
  #define LPI2C_MDMR_MATCH0_MASK                   0xFFu
  #define LPI2C_MDMR_MATCH0_SHIFT                  0
  #define LPI2C_MDMR_MATCH0_WIDTH                  8
  #define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH0_SHIFT))&LPI2C_MDMR_MATCH0_MASK)
  #define LPI2C_MDMR_MATCH1_MASK                   0xFF0000u
  #define LPI2C_MDMR_MATCH1_SHIFT                  16
  #define LPI2C_MDMR_MATCH1_WIDTH                  8
  #define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH1_SHIFT))&LPI2C_MDMR_MATCH1_MASK)
  /* MCCR0 Bit Fields */
  #define LPI2C_MCCR0_CLKLO_MASK                   0x3Fu
  #define LPI2C_MCCR0_CLKLO_SHIFT                  0
  #define LPI2C_MCCR0_CLKLO_WIDTH                  6
  #define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKLO_SHIFT))&LPI2C_MCCR0_CLKLO_MASK)
  #define LPI2C_MCCR0_CLKHI_MASK                   0x3F00u
  #define LPI2C_MCCR0_CLKHI_SHIFT                  8
  #define LPI2C_MCCR0_CLKHI_WIDTH                  6
  #define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKHI_SHIFT))&LPI2C_MCCR0_CLKHI_MASK)
  #define LPI2C_MCCR0_SETHOLD_MASK                 0x3F0000u
  #define LPI2C_MCCR0_SETHOLD_SHIFT                16
  #define LPI2C_MCCR0_SETHOLD_WIDTH                6
  #define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_SETHOLD_SHIFT))&LPI2C_MCCR0_SETHOLD_MASK)
  #define LPI2C_MCCR0_DATAVD_MASK                  0x3F000000u
  #define LPI2C_MCCR0_DATAVD_SHIFT                 24
  #define LPI2C_MCCR0_DATAVD_WIDTH                 6
  #define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_DATAVD_SHIFT))&LPI2C_MCCR0_DATAVD_MASK)
  /* MCCR1 Bit Fields */
  #define LPI2C_MCCR1_CLKLO_MASK                   0x3Fu
  #define LPI2C_MCCR1_CLKLO_SHIFT                  0
  #define LPI2C_MCCR1_CLKLO_WIDTH                  6
  #define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKLO_SHIFT))&LPI2C_MCCR1_CLKLO_MASK)
  #define LPI2C_MCCR1_CLKHI_MASK                   0x3F00u
  #define LPI2C_MCCR1_CLKHI_SHIFT                  8
  #define LPI2C_MCCR1_CLKHI_WIDTH                  6
  #define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKHI_SHIFT))&LPI2C_MCCR1_CLKHI_MASK)
  #define LPI2C_MCCR1_SETHOLD_MASK                 0x3F0000u
  #define LPI2C_MCCR1_SETHOLD_SHIFT                16
  #define LPI2C_MCCR1_SETHOLD_WIDTH                6
  #define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_SETHOLD_SHIFT))&LPI2C_MCCR1_SETHOLD_MASK)
  #define LPI2C_MCCR1_DATAVD_MASK                  0x3F000000u
  #define LPI2C_MCCR1_DATAVD_SHIFT                 24
  #define LPI2C_MCCR1_DATAVD_WIDTH                 6
  #define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_DATAVD_SHIFT))&LPI2C_MCCR1_DATAVD_MASK)
  /* MFCR Bit Fields */
  #define LPI2C_MFCR_TXWATER_MASK                  0xFFu
  #define LPI2C_MFCR_TXWATER_SHIFT                 0
  #define LPI2C_MFCR_TXWATER_WIDTH                 8
  #define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_TXWATER_SHIFT))&LPI2C_MFCR_TXWATER_MASK)
  #define LPI2C_MFCR_RXWATER_MASK                  0xFF0000u
  #define LPI2C_MFCR_RXWATER_SHIFT                 16
  #define LPI2C_MFCR_RXWATER_WIDTH                 8
  #define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_RXWATER_SHIFT))&LPI2C_MFCR_RXWATER_MASK)
  /* MFSR Bit Fields */
  #define LPI2C_MFSR_TXCOUNT_MASK                  0xFFu
  #define LPI2C_MFSR_TXCOUNT_SHIFT                 0
  #define LPI2C_MFSR_TXCOUNT_WIDTH                 8
  #define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_TXCOUNT_SHIFT))&LPI2C_MFSR_TXCOUNT_MASK)
  #define LPI2C_MFSR_RXCOUNT_MASK                  0xFF0000u
  #define LPI2C_MFSR_RXCOUNT_SHIFT                 16
  #define LPI2C_MFSR_RXCOUNT_WIDTH                 8
  #define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_RXCOUNT_SHIFT))&LPI2C_MFSR_RXCOUNT_MASK)
  /* MTDR Bit Fields */
  #define LPI2C_MTDR_DATA_MASK                     0xFFu
  #define LPI2C_MTDR_DATA_SHIFT                    0
  #define LPI2C_MTDR_DATA_WIDTH                    8
  #define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_DATA_SHIFT))&LPI2C_MTDR_DATA_MASK)
  #define LPI2C_MTDR_CMD_MASK                      0x700u
  #define LPI2C_MTDR_CMD_SHIFT                     8
  #define LPI2C_MTDR_CMD_WIDTH                     3
  #define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_CMD_SHIFT))&LPI2C_MTDR_CMD_MASK)
  /* MRDR Bit Fields */
  #define LPI2C_MRDR_DATA_MASK                     0xFFu
  #define LPI2C_MRDR_DATA_SHIFT                    0
  #define LPI2C_MRDR_DATA_WIDTH                    8
  #define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_DATA_SHIFT))&LPI2C_MRDR_DATA_MASK)
  #define LPI2C_MRDR_RXEMPTY_MASK                  0x4000u
  #define LPI2C_MRDR_RXEMPTY_SHIFT                 14
  #define LPI2C_MRDR_RXEMPTY_WIDTH                 1
  #define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_RXEMPTY_SHIFT))&LPI2C_MRDR_RXEMPTY_MASK)
  /* SCR Bit Fields */
  #define LPI2C_SCR_SEN_MASK                       0x1u
  #define LPI2C_SCR_SEN_SHIFT                      0
  #define LPI2C_SCR_SEN_WIDTH                      1
  #define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_SEN_SHIFT))&LPI2C_SCR_SEN_MASK)
  #define LPI2C_SCR_RST_MASK                       0x2u
  #define LPI2C_SCR_RST_SHIFT                      1
  #define LPI2C_SCR_RST_WIDTH                      1
  #define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RST_SHIFT))&LPI2C_SCR_RST_MASK)
  #define LPI2C_SCR_FILTEN_MASK                    0x10u
  #define LPI2C_SCR_FILTEN_SHIFT                   4
  #define LPI2C_SCR_FILTEN_WIDTH                   1
  #define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTEN_SHIFT))&LPI2C_SCR_FILTEN_MASK)
  #define LPI2C_SCR_FILTDZ_MASK                    0x20u
  #define LPI2C_SCR_FILTDZ_SHIFT                   5
  #define LPI2C_SCR_FILTDZ_WIDTH                   1
  #define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTDZ_SHIFT))&LPI2C_SCR_FILTDZ_MASK)
  #define LPI2C_SCR_RTF_MASK                       0x100u
  #define LPI2C_SCR_RTF_SHIFT                      8
  #define LPI2C_SCR_RTF_WIDTH                      1
  #define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RTF_SHIFT))&LPI2C_SCR_RTF_MASK)
  #define LPI2C_SCR_RRF_MASK                       0x200u
  #define LPI2C_SCR_RRF_SHIFT                      9
  #define LPI2C_SCR_RRF_WIDTH                      1
  #define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RRF_SHIFT))&LPI2C_SCR_RRF_MASK)
  /* SSR Bit Fields */
  #define LPI2C_SSR_TDF_MASK                       0x1u
  #define LPI2C_SSR_TDF_SHIFT                      0
  #define LPI2C_SSR_TDF_WIDTH                      1
  #define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TDF_SHIFT))&LPI2C_SSR_TDF_MASK)
  #define LPI2C_SSR_RDF_MASK                       0x2u
  #define LPI2C_SSR_RDF_SHIFT                      1
  #define LPI2C_SSR_RDF_WIDTH                      1
  #define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RDF_SHIFT))&LPI2C_SSR_RDF_MASK)
  #define LPI2C_SSR_AVF_MASK                       0x4u
  #define LPI2C_SSR_AVF_SHIFT                      2
  #define LPI2C_SSR_AVF_WIDTH                      1
  #define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AVF_SHIFT))&LPI2C_SSR_AVF_MASK)
  #define LPI2C_SSR_TAF_MASK                       0x8u
  #define LPI2C_SSR_TAF_SHIFT                      3
  #define LPI2C_SSR_TAF_WIDTH                      1
  #define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TAF_SHIFT))&LPI2C_SSR_TAF_MASK)
  #define LPI2C_SSR_RSF_MASK                       0x100u
  #define LPI2C_SSR_RSF_SHIFT                      8
  #define LPI2C_SSR_RSF_WIDTH                      1
  #define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RSF_SHIFT))&LPI2C_SSR_RSF_MASK)
  #define LPI2C_SSR_SDF_MASK                       0x200u
  #define LPI2C_SSR_SDF_SHIFT                      9
  #define LPI2C_SSR_SDF_WIDTH                      1
  #define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SDF_SHIFT))&LPI2C_SSR_SDF_MASK)
  #define LPI2C_SSR_BEF_MASK                       0x400u
  #define LPI2C_SSR_BEF_SHIFT                      10
  #define LPI2C_SSR_BEF_WIDTH                      1
  #define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BEF_SHIFT))&LPI2C_SSR_BEF_MASK)
  #define LPI2C_SSR_FEF_MASK                       0x800u
  #define LPI2C_SSR_FEF_SHIFT                      11
  #define LPI2C_SSR_FEF_WIDTH                      1
  #define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_FEF_SHIFT))&LPI2C_SSR_FEF_MASK)
  #define LPI2C_SSR_AM0F_MASK                      0x1000u
  #define LPI2C_SSR_AM0F_SHIFT                     12
  #define LPI2C_SSR_AM0F_WIDTH                     1
  #define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM0F_SHIFT))&LPI2C_SSR_AM0F_MASK)
  #define LPI2C_SSR_AM1F_MASK                      0x2000u
  #define LPI2C_SSR_AM1F_SHIFT                     13
  #define LPI2C_SSR_AM1F_WIDTH                     1
  #define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM1F_SHIFT))&LPI2C_SSR_AM1F_MASK)
  #define LPI2C_SSR_GCF_MASK                       0x4000u
  #define LPI2C_SSR_GCF_SHIFT                      14
  #define LPI2C_SSR_GCF_WIDTH                      1
  #define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_GCF_SHIFT))&LPI2C_SSR_GCF_MASK)
  #define LPI2C_SSR_SARF_MASK                      0x8000u
  #define LPI2C_SSR_SARF_SHIFT                     15
  #define LPI2C_SSR_SARF_WIDTH                     1
  #define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SARF_SHIFT))&LPI2C_SSR_SARF_MASK)
  #define LPI2C_SSR_SBF_MASK                       0x1000000u
  #define LPI2C_SSR_SBF_SHIFT                      24
  #define LPI2C_SSR_SBF_WIDTH                      1
  #define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SBF_SHIFT))&LPI2C_SSR_SBF_MASK)
  #define LPI2C_SSR_BBF_MASK                       0x2000000u
  #define LPI2C_SSR_BBF_SHIFT                      25
  #define LPI2C_SSR_BBF_WIDTH                      1
  #define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BBF_SHIFT))&LPI2C_SSR_BBF_MASK)
  /* SIER Bit Fields */
  #define LPI2C_SIER_TDIE_MASK                     0x1u
  #define LPI2C_SIER_TDIE_SHIFT                    0
  #define LPI2C_SIER_TDIE_WIDTH                    1
  #define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TDIE_SHIFT))&LPI2C_SIER_TDIE_MASK)
  #define LPI2C_SIER_RDIE_MASK                     0x2u
  #define LPI2C_SIER_RDIE_SHIFT                    1
  #define LPI2C_SIER_RDIE_WIDTH                    1
  #define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RDIE_SHIFT))&LPI2C_SIER_RDIE_MASK)
  #define LPI2C_SIER_AVIE_MASK                     0x4u
  #define LPI2C_SIER_AVIE_SHIFT                    2
  #define LPI2C_SIER_AVIE_WIDTH                    1
  #define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AVIE_SHIFT))&LPI2C_SIER_AVIE_MASK)
  #define LPI2C_SIER_TAIE_MASK                     0x8u
  #define LPI2C_SIER_TAIE_SHIFT                    3
  #define LPI2C_SIER_TAIE_WIDTH                    1
  #define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TAIE_SHIFT))&LPI2C_SIER_TAIE_MASK)
  #define LPI2C_SIER_RSIE_MASK                     0x100u
  #define LPI2C_SIER_RSIE_SHIFT                    8
  #define LPI2C_SIER_RSIE_WIDTH                    1
  #define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RSIE_SHIFT))&LPI2C_SIER_RSIE_MASK)
  #define LPI2C_SIER_SDIE_MASK                     0x200u
  #define LPI2C_SIER_SDIE_SHIFT                    9
  #define LPI2C_SIER_SDIE_WIDTH                    1
  #define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SDIE_SHIFT))&LPI2C_SIER_SDIE_MASK)
  #define LPI2C_SIER_BEIE_MASK                     0x400u
  #define LPI2C_SIER_BEIE_SHIFT                    10
  #define LPI2C_SIER_BEIE_WIDTH                    1
  #define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_BEIE_SHIFT))&LPI2C_SIER_BEIE_MASK)
  #define LPI2C_SIER_FEIE_MASK                     0x800u
  #define LPI2C_SIER_FEIE_SHIFT                    11
  #define LPI2C_SIER_FEIE_WIDTH                    1
  #define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_FEIE_SHIFT))&LPI2C_SIER_FEIE_MASK)
  #define LPI2C_SIER_AM0IE_MASK                    0x1000u
  #define LPI2C_SIER_AM0IE_SHIFT                   12
  #define LPI2C_SIER_AM0IE_WIDTH                   1
  #define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM0IE_SHIFT))&LPI2C_SIER_AM0IE_MASK)
  #define LPI2C_SIER_AM1F_MASK                     0x2000u
  #define LPI2C_SIER_AM1F_SHIFT                    13
  #define LPI2C_SIER_AM1F_WIDTH                    1
  #define LPI2C_SIER_AM1F(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM1F_SHIFT))&LPI2C_SIER_AM1F_MASK)
  #define LPI2C_SIER_GCIE_MASK                     0x4000u
  #define LPI2C_SIER_GCIE_SHIFT                    14
  #define LPI2C_SIER_GCIE_WIDTH                    1
  #define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_GCIE_SHIFT))&LPI2C_SIER_GCIE_MASK)
  #define LPI2C_SIER_SARIE_MASK                    0x8000u
  #define LPI2C_SIER_SARIE_SHIFT                   15
  #define LPI2C_SIER_SARIE_WIDTH                   1
  #define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SARIE_SHIFT))&LPI2C_SIER_SARIE_MASK)
  /* SDER Bit Fields */
  #define LPI2C_SDER_TDDE_MASK                     0x1u
  #define LPI2C_SDER_TDDE_SHIFT                    0
  #define LPI2C_SDER_TDDE_WIDTH                    1
  #define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_TDDE_SHIFT))&LPI2C_SDER_TDDE_MASK)
  #define LPI2C_SDER_RDDE_MASK                     0x2u
  #define LPI2C_SDER_RDDE_SHIFT                    1
  #define LPI2C_SDER_RDDE_WIDTH                    1
  #define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_RDDE_SHIFT))&LPI2C_SDER_RDDE_MASK)
  #define LPI2C_SDER_AVDE_MASK                     0x4u
  #define LPI2C_SDER_AVDE_SHIFT                    2
  #define LPI2C_SDER_AVDE_WIDTH                    1
  #define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_AVDE_SHIFT))&LPI2C_SDER_AVDE_MASK)
  /* SCFGR1 Bit Fields */
  #define LPI2C_SCFGR1_ADRSTALL_MASK               0x1u
  #define LPI2C_SCFGR1_ADRSTALL_SHIFT              0
  #define LPI2C_SCFGR1_ADRSTALL_WIDTH              1
  #define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADRSTALL_SHIFT))&LPI2C_SCFGR1_ADRSTALL_MASK)
  #define LPI2C_SCFGR1_RXSTALL_MASK                0x2u
  #define LPI2C_SCFGR1_RXSTALL_SHIFT               1
  #define LPI2C_SCFGR1_RXSTALL_WIDTH               1
  #define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXSTALL_SHIFT))&LPI2C_SCFGR1_RXSTALL_MASK)
  #define LPI2C_SCFGR1_TXDSTALL_MASK               0x4u
  #define LPI2C_SCFGR1_TXDSTALL_SHIFT              2
  #define LPI2C_SCFGR1_TXDSTALL_WIDTH              1
  #define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXDSTALL_SHIFT))&LPI2C_SCFGR1_TXDSTALL_MASK)
  #define LPI2C_SCFGR1_ACKSTALL_MASK               0x8u
  #define LPI2C_SCFGR1_ACKSTALL_SHIFT              3
  #define LPI2C_SCFGR1_ACKSTALL_WIDTH              1
  #define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ACKSTALL_SHIFT))&LPI2C_SCFGR1_ACKSTALL_MASK)
  #define LPI2C_SCFGR1_GCEN_MASK                   0x100u
  #define LPI2C_SCFGR1_GCEN_SHIFT                  8
  #define LPI2C_SCFGR1_GCEN_WIDTH                  1
  #define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_GCEN_SHIFT))&LPI2C_SCFGR1_GCEN_MASK)
  #define LPI2C_SCFGR1_SAEN_MASK                   0x200u
  #define LPI2C_SCFGR1_SAEN_SHIFT                  9
  #define LPI2C_SCFGR1_SAEN_WIDTH                  1
  #define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_SAEN_SHIFT))&LPI2C_SCFGR1_SAEN_MASK)
  #define LPI2C_SCFGR1_TXCFG_MASK                  0x400u
  #define LPI2C_SCFGR1_TXCFG_SHIFT                 10
  #define LPI2C_SCFGR1_TXCFG_WIDTH                 1
  #define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXCFG_SHIFT))&LPI2C_SCFGR1_TXCFG_MASK)
  #define LPI2C_SCFGR1_RXCFG_MASK                  0x800u
  #define LPI2C_SCFGR1_RXCFG_SHIFT                 11
  #define LPI2C_SCFGR1_RXCFG_WIDTH                 1
  #define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXCFG_SHIFT))&LPI2C_SCFGR1_RXCFG_MASK)
  #define LPI2C_SCFGR1_IGNACK_MASK                 0x1000u
  #define LPI2C_SCFGR1_IGNACK_SHIFT                12
  #define LPI2C_SCFGR1_IGNACK_WIDTH                1
  #define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_IGNACK_SHIFT))&LPI2C_SCFGR1_IGNACK_MASK)
  #define LPI2C_SCFGR1_HSMEN_MASK                  0x2000u
  #define LPI2C_SCFGR1_HSMEN_SHIFT                 13
  #define LPI2C_SCFGR1_HSMEN_WIDTH                 1
  #define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_HSMEN_SHIFT))&LPI2C_SCFGR1_HSMEN_MASK)
  #define LPI2C_SCFGR1_ADDRCFG_MASK                0x70000u
  #define LPI2C_SCFGR1_ADDRCFG_SHIFT               16
  #define LPI2C_SCFGR1_ADDRCFG_WIDTH               3
  #define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADDRCFG_SHIFT))&LPI2C_SCFGR1_ADDRCFG_MASK)
  /* SCFGR2 Bit Fields */
  #define LPI2C_SCFGR2_CLKHOLD_MASK                0xFu
  #define LPI2C_SCFGR2_CLKHOLD_SHIFT               0
  #define LPI2C_SCFGR2_CLKHOLD_WIDTH               4
  #define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_CLKHOLD_SHIFT))&LPI2C_SCFGR2_CLKHOLD_MASK)
  #define LPI2C_SCFGR2_DATAVD_MASK                 0x3F00u
  #define LPI2C_SCFGR2_DATAVD_SHIFT                8
  #define LPI2C_SCFGR2_DATAVD_WIDTH                6
  #define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_DATAVD_SHIFT))&LPI2C_SCFGR2_DATAVD_MASK)
  #define LPI2C_SCFGR2_FILTSCL_MASK                0xF0000u
  #define LPI2C_SCFGR2_FILTSCL_SHIFT               16
  #define LPI2C_SCFGR2_FILTSCL_WIDTH               4
  #define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSCL_SHIFT))&LPI2C_SCFGR2_FILTSCL_MASK)
  #define LPI2C_SCFGR2_FILTSDA_MASK                0xF000000u
  #define LPI2C_SCFGR2_FILTSDA_SHIFT               24
  #define LPI2C_SCFGR2_FILTSDA_WIDTH               4
  #define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSDA_SHIFT))&LPI2C_SCFGR2_FILTSDA_MASK)
  /* SAMR Bit Fields */
  #define LPI2C_SAMR_ADDR0_MASK                    0x7FEu
  #define LPI2C_SAMR_ADDR0_SHIFT                   1
  #define LPI2C_SAMR_ADDR0_WIDTH                   10
  #define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR0_SHIFT))&LPI2C_SAMR_ADDR0_MASK)
  #define LPI2C_SAMR_ADDR1_MASK                    0x7FE0000u
  #define LPI2C_SAMR_ADDR1_SHIFT                   17
  #define LPI2C_SAMR_ADDR1_WIDTH                   10
  #define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR1_SHIFT))&LPI2C_SAMR_ADDR1_MASK)
  /* SASR Bit Fields */
  #define LPI2C_SASR_RADDR_MASK                    0x7FFu
  #define LPI2C_SASR_RADDR_SHIFT                   0
  #define LPI2C_SASR_RADDR_WIDTH                   11
  #define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_RADDR_SHIFT))&LPI2C_SASR_RADDR_MASK)
  #define LPI2C_SASR_ANV_MASK                      0x4000u
  #define LPI2C_SASR_ANV_SHIFT                     14
  #define LPI2C_SASR_ANV_WIDTH                     1
  #define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_ANV_SHIFT))&LPI2C_SASR_ANV_MASK)
  /* STAR Bit Fields */
  #define LPI2C_STAR_TXNACK_MASK                   0x1u
  #define LPI2C_STAR_TXNACK_SHIFT                  0
  #define LPI2C_STAR_TXNACK_WIDTH                  1
  #define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x))<<LPI2C_STAR_TXNACK_SHIFT))&LPI2C_STAR_TXNACK_MASK)
  /* STDR Bit Fields */
  #define LPI2C_STDR_DATA_MASK                     0xFFu
  #define LPI2C_STDR_DATA_SHIFT                    0
  #define LPI2C_STDR_DATA_WIDTH                    8
  #define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_STDR_DATA_SHIFT))&LPI2C_STDR_DATA_MASK)
  /* SRDR Bit Fields */
  #define LPI2C_SRDR_DATA_MASK                     0xFFu
  #define LPI2C_SRDR_DATA_SHIFT                    0
  #define LPI2C_SRDR_DATA_WIDTH                    8
  #define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_DATA_SHIFT))&LPI2C_SRDR_DATA_MASK)
  #define LPI2C_SRDR_RXEMPTY_MASK                  0x4000u
  #define LPI2C_SRDR_RXEMPTY_SHIFT                 14
  #define LPI2C_SRDR_RXEMPTY_WIDTH                 1
  #define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_RXEMPTY_SHIFT))&LPI2C_SRDR_RXEMPTY_MASK)
  #define LPI2C_SRDR_SOF_MASK                      0x8000u
  #define LPI2C_SRDR_SOF_SHIFT                     15
  #define LPI2C_SRDR_SOF_WIDTH                     1
  #define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_SOF_SHIFT))&LPI2C_SRDR_SOF_MASK)
  
  /*!
   * @}
   */ /* end of group LPI2C_Register_Masks */
  
  
  /* LPI2C - Peripheral instance base addresses */
  /** Peripheral LPI2C0 base address */
  #define LPI2C0_BASE                              (0x40066000u)
  /** Peripheral LPI2C0 base pointer */
  #define LPI2C0                                   ((LPI2C_Type *)LPI2C0_BASE)
  #define LPI2C0_BASE_PTR                          (LPI2C0)
  /** Peripheral LPI2C1 base address */
  #define LPI2C1_BASE                              (0x40067000u)
  /** Peripheral LPI2C1 base pointer */
  #define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
  #define LPI2C1_BASE_PTR                          (LPI2C1)
  /** Array initializer of LPI2C peripheral base addresses */
  #define LPI2C_BASE_ADDRS                         { LPI2C0_BASE, LPI2C1_BASE }
  /** Array initializer of LPI2C peripheral base pointers */
  #define LPI2C_BASE_PTRS                          { LPI2C0, LPI2C1 }
  
  /* ----------------------------------------------------------------------------
     -- LPI2C - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPI2C_Register_Accessor_Macros LPI2C - Register accessor macros
   * @{
   */
  
  
  /* LPI2C - Register instance definitions */
  /* LPI2C0 */
  #define LPI2C0_VERID                             LPI2C_VERID_REG(LPI2C0)
  #define LPI2C0_PARAM                             LPI2C_PARAM_REG(LPI2C0)
  #define LPI2C0_MCR                               LPI2C_MCR_REG(LPI2C0)
  #define LPI2C0_MSR                               LPI2C_MSR_REG(LPI2C0)
  #define LPI2C0_MIER                              LPI2C_MIER_REG(LPI2C0)
  #define LPI2C0_MDER                              LPI2C_MDER_REG(LPI2C0)
  #define LPI2C0_MCFGR0                            LPI2C_MCFGR0_REG(LPI2C0)
  #define LPI2C0_MCFGR1                            LPI2C_MCFGR1_REG(LPI2C0)
  #define LPI2C0_MCFGR2                            LPI2C_MCFGR2_REG(LPI2C0)
  #define LPI2C0_MCFGR3                            LPI2C_MCFGR3_REG(LPI2C0)
  #define LPI2C0_MDMR                              LPI2C_MDMR_REG(LPI2C0)
  #define LPI2C0_MCCR0                             LPI2C_MCCR0_REG(LPI2C0)
  #define LPI2C0_MCCR1                             LPI2C_MCCR1_REG(LPI2C0)
  #define LPI2C0_MFCR                              LPI2C_MFCR_REG(LPI2C0)
  #define LPI2C0_MFSR                              LPI2C_MFSR_REG(LPI2C0)
  #define LPI2C0_MTDR                              LPI2C_MTDR_REG(LPI2C0)
  #define LPI2C0_MRDR                              LPI2C_MRDR_REG(LPI2C0)
  #define LPI2C0_SCR                               LPI2C_SCR_REG(LPI2C0)
  #define LPI2C0_SSR                               LPI2C_SSR_REG(LPI2C0)
  #define LPI2C0_SIER                              LPI2C_SIER_REG(LPI2C0)
  #define LPI2C0_SDER                              LPI2C_SDER_REG(LPI2C0)
  #define LPI2C0_SCFGR1                            LPI2C_SCFGR1_REG(LPI2C0)
  #define LPI2C0_SCFGR2                            LPI2C_SCFGR2_REG(LPI2C0)
  #define LPI2C0_SAMR                              LPI2C_SAMR_REG(LPI2C0)
  #define LPI2C0_SASR                              LPI2C_SASR_REG(LPI2C0)
  #define LPI2C0_STAR                              LPI2C_STAR_REG(LPI2C0)
  #define LPI2C0_STDR                              LPI2C_STDR_REG(LPI2C0)
  #define LPI2C0_SRDR                              LPI2C_SRDR_REG(LPI2C0)
  /* LPI2C1 */
  #define LPI2C1_VERID                             LPI2C_VERID_REG(LPI2C1)
  #define LPI2C1_PARAM                             LPI2C_PARAM_REG(LPI2C1)
  #define LPI2C1_MCR                               LPI2C_MCR_REG(LPI2C1)
  #define LPI2C1_MSR                               LPI2C_MSR_REG(LPI2C1)
  #define LPI2C1_MIER                              LPI2C_MIER_REG(LPI2C1)
  #define LPI2C1_MDER                              LPI2C_MDER_REG(LPI2C1)
  #define LPI2C1_MCFGR0                            LPI2C_MCFGR0_REG(LPI2C1)
  #define LPI2C1_MCFGR1                            LPI2C_MCFGR1_REG(LPI2C1)
  #define LPI2C1_MCFGR2                            LPI2C_MCFGR2_REG(LPI2C1)
  #define LPI2C1_MCFGR3                            LPI2C_MCFGR3_REG(LPI2C1)
  #define LPI2C1_MDMR                              LPI2C_MDMR_REG(LPI2C1)
  #define LPI2C1_MCCR0                             LPI2C_MCCR0_REG(LPI2C1)
  #define LPI2C1_MCCR1                             LPI2C_MCCR1_REG(LPI2C1)
  #define LPI2C1_MFCR                              LPI2C_MFCR_REG(LPI2C1)
  #define LPI2C1_MFSR                              LPI2C_MFSR_REG(LPI2C1)
  #define LPI2C1_MTDR                              LPI2C_MTDR_REG(LPI2C1)
  #define LPI2C1_MRDR                              LPI2C_MRDR_REG(LPI2C1)
  #define LPI2C1_SCR                               LPI2C_SCR_REG(LPI2C1)
  #define LPI2C1_SSR                               LPI2C_SSR_REG(LPI2C1)
  #define LPI2C1_SIER                              LPI2C_SIER_REG(LPI2C1)
  #define LPI2C1_SDER                              LPI2C_SDER_REG(LPI2C1)
  #define LPI2C1_SCFGR1                            LPI2C_SCFGR1_REG(LPI2C1)
  #define LPI2C1_SCFGR2                            LPI2C_SCFGR2_REG(LPI2C1)
  #define LPI2C1_SAMR                              LPI2C_SAMR_REG(LPI2C1)
  #define LPI2C1_SASR                              LPI2C_SASR_REG(LPI2C1)
  #define LPI2C1_STAR                              LPI2C_STAR_REG(LPI2C1)
  #define LPI2C1_STDR                              LPI2C_STDR_REG(LPI2C1)
  #define LPI2C1_SRDR                              LPI2C_SRDR_REG(LPI2C1)
  
  /*!
   * @}
   */ /* end of group LPI2C_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group LPI2C_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- LPTMR Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
   * @{
   */
  
  /** LPTMR - Register Layout Typedef */
  typedef struct {
    __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
    __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
    __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
    __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
  } LPTMR_Type, *LPTMR_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- LPTMR - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
   * @{
   */
  
  
  /* LPTMR - Register accessors */
  #define LPTMR_CSR_REG(base)                      ((base)->CSR)
  #define LPTMR_PSR_REG(base)                      ((base)->PSR)
  #define LPTMR_CMR_REG(base)                      ((base)->CMR)
  #define LPTMR_CNR_REG(base)                      ((base)->CNR)
  
  /*!
   * @}
   */ /* end of group LPTMR_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- LPTMR Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
   * @{
   */
  
  /* CSR Bit Fields */
  #define LPTMR_CSR_TEN_MASK                       0x1u
  #define LPTMR_CSR_TEN_SHIFT                      0
  #define LPTMR_CSR_TEN_WIDTH                      1
  #define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
  #define LPTMR_CSR_TMS_MASK                       0x2u
  #define LPTMR_CSR_TMS_SHIFT                      1
  #define LPTMR_CSR_TMS_WIDTH                      1
  #define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
  #define LPTMR_CSR_TFC_MASK                       0x4u
  #define LPTMR_CSR_TFC_SHIFT                      2
  #define LPTMR_CSR_TFC_WIDTH                      1
  #define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
  #define LPTMR_CSR_TPP_MASK                       0x8u
  #define LPTMR_CSR_TPP_SHIFT                      3
  #define LPTMR_CSR_TPP_WIDTH                      1
  #define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
  #define LPTMR_CSR_TPS_MASK                       0x30u
  #define LPTMR_CSR_TPS_SHIFT                      4
  #define LPTMR_CSR_TPS_WIDTH                      2
  #define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
  #define LPTMR_CSR_TIE_MASK                       0x40u
  #define LPTMR_CSR_TIE_SHIFT                      6
  #define LPTMR_CSR_TIE_WIDTH                      1
  #define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
  #define LPTMR_CSR_TCF_MASK                       0x80u
  #define LPTMR_CSR_TCF_SHIFT                      7
  #define LPTMR_CSR_TCF_WIDTH                      1
  #define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
  /* PSR Bit Fields */
  #define LPTMR_PSR_PCS_MASK                       0x3u
  #define LPTMR_PSR_PCS_SHIFT                      0
  #define LPTMR_PSR_PCS_WIDTH                      2
  #define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
  #define LPTMR_PSR_PBYP_MASK                      0x4u
  #define LPTMR_PSR_PBYP_SHIFT                     2
  #define LPTMR_PSR_PBYP_WIDTH                     1
  #define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
  #define LPTMR_PSR_PRESCALE_MASK                  0x78u
  #define LPTMR_PSR_PRESCALE_SHIFT                 3
  #define LPTMR_PSR_PRESCALE_WIDTH                 4
  #define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
  /* CMR Bit Fields */
  #define LPTMR_CMR_COMPARE_MASK                   0xFFFFu
  #define LPTMR_CMR_COMPARE_SHIFT                  0
  #define LPTMR_CMR_COMPARE_WIDTH                  16
  #define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
  /* CNR Bit Fields */
  #define LPTMR_CNR_COUNTER_MASK                   0xFFFFu
  #define LPTMR_CNR_COUNTER_SHIFT                  0
  #define LPTMR_CNR_COUNTER_WIDTH                  16
  #define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
  
  /*!
   * @}
   */ /* end of group LPTMR_Register_Masks */
  
  
  /* LPTMR - Peripheral instance base addresses */
  /** Peripheral LPTMR0 base address */
  #define LPTMR0_BASE                              (0x40040000u)
  /** Peripheral LPTMR0 base pointer */
  #define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
  #define LPTMR0_BASE_PTR                          (LPTMR0)
  /** Array initializer of LPTMR peripheral base addresses */
  #define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
  /** Array initializer of LPTMR peripheral base pointers */
  #define LPTMR_BASE_PTRS                          { LPTMR0 }
  
  /* ----------------------------------------------------------------------------
     -- LPTMR - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
   * @{
   */
  
  
  /* LPTMR - Register instance definitions */
  /* LPTMR0 */
  #define LPTMR0_CSR                               LPTMR_CSR_REG(LPTMR0)
  #define LPTMR0_PSR                               LPTMR_PSR_REG(LPTMR0)
  #define LPTMR0_CMR                               LPTMR_CMR_REG(LPTMR0)
  #define LPTMR0_CNR                               LPTMR_CNR_REG(LPTMR0)
  
  /*!
   * @}
   */ /* end of group LPTMR_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group LPTMR_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- LPUART Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
   * @{
   */
  
  /** LPUART - Register Layout Typedef */
  typedef struct {
    __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x0 */
    __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x4 */
    __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x8 */
    __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0xC */
    __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x10 */
    __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x14 */
  } LPUART_Type, *LPUART_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- LPUART - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
   * @{
   */
  
  
  /* LPUART - Register accessors */
  #define LPUART_BAUD_REG(base)                    ((base)->BAUD)
  #define LPUART_STAT_REG(base)                    ((base)->STAT)
  #define LPUART_CTRL_REG(base)                    ((base)->CTRL)
  #define LPUART_DATA_REG(base)                    ((base)->DATA)
  #define LPUART_MATCH_REG(base)                   ((base)->MATCH)
  #define LPUART_MODIR_REG(base)                   ((base)->MODIR)
  
  /*!
   * @}
   */ /* end of group LPUART_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- LPUART Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPUART_Register_Masks LPUART Register Masks
   * @{
   */
  
  /* BAUD Bit Fields */
  #define LPUART_BAUD_SBR_MASK                     0x1FFFu
  #define LPUART_BAUD_SBR_SHIFT                    0
  #define LPUART_BAUD_SBR_WIDTH                    13
  #define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
  #define LPUART_BAUD_SBNS_MASK                    0x2000u
  #define LPUART_BAUD_SBNS_SHIFT                   13
  #define LPUART_BAUD_SBNS_WIDTH                   1
  #define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBNS_SHIFT))&LPUART_BAUD_SBNS_MASK)
  #define LPUART_BAUD_RXEDGIE_MASK                 0x4000u
  #define LPUART_BAUD_RXEDGIE_SHIFT                14
  #define LPUART_BAUD_RXEDGIE_WIDTH                1
  #define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RXEDGIE_SHIFT))&LPUART_BAUD_RXEDGIE_MASK)
  #define LPUART_BAUD_LBKDIE_MASK                  0x8000u
  #define LPUART_BAUD_LBKDIE_SHIFT                 15
  #define LPUART_BAUD_LBKDIE_WIDTH                 1
  #define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_LBKDIE_SHIFT))&LPUART_BAUD_LBKDIE_MASK)
  #define LPUART_BAUD_RESYNCDIS_MASK               0x10000u
  #define LPUART_BAUD_RESYNCDIS_SHIFT              16
  #define LPUART_BAUD_RESYNCDIS_WIDTH              1
  #define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RESYNCDIS_SHIFT))&LPUART_BAUD_RESYNCDIS_MASK)
  #define LPUART_BAUD_BOTHEDGE_MASK                0x20000u
  #define LPUART_BAUD_BOTHEDGE_SHIFT               17
  #define LPUART_BAUD_BOTHEDGE_WIDTH               1
  #define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_BOTHEDGE_SHIFT))&LPUART_BAUD_BOTHEDGE_MASK)
  #define LPUART_BAUD_MATCFG_MASK                  0xC0000u
  #define LPUART_BAUD_MATCFG_SHIFT                 18
  #define LPUART_BAUD_MATCFG_WIDTH                 2
  #define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
  #define LPUART_BAUD_RDMAE_MASK                   0x200000u
  #define LPUART_BAUD_RDMAE_SHIFT                  21
  #define LPUART_BAUD_RDMAE_WIDTH                  1
  #define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RDMAE_SHIFT))&LPUART_BAUD_RDMAE_MASK)
  #define LPUART_BAUD_TDMAE_MASK                   0x800000u
  #define LPUART_BAUD_TDMAE_SHIFT                  23
  #define LPUART_BAUD_TDMAE_WIDTH                  1
  #define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_TDMAE_SHIFT))&LPUART_BAUD_TDMAE_MASK)
  #define LPUART_BAUD_OSR_MASK                     0x1F000000u
  #define LPUART_BAUD_OSR_SHIFT                    24
  #define LPUART_BAUD_OSR_WIDTH                    5
  #define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
  #define LPUART_BAUD_M10_MASK                     0x20000000u
  #define LPUART_BAUD_M10_SHIFT                    29
  #define LPUART_BAUD_M10_WIDTH                    1
  #define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_M10_SHIFT))&LPUART_BAUD_M10_MASK)
  #define LPUART_BAUD_MAEN2_MASK                   0x40000000u
  #define LPUART_BAUD_MAEN2_SHIFT                  30
  #define LPUART_BAUD_MAEN2_WIDTH                  1
  #define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN2_SHIFT))&LPUART_BAUD_MAEN2_MASK)
  #define LPUART_BAUD_MAEN1_MASK                   0x80000000u
  #define LPUART_BAUD_MAEN1_SHIFT                  31
  #define LPUART_BAUD_MAEN1_WIDTH                  1
  #define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN1_SHIFT))&LPUART_BAUD_MAEN1_MASK)
  /* STAT Bit Fields */
  #define LPUART_STAT_MA2F_MASK                    0x4000u
  #define LPUART_STAT_MA2F_SHIFT                   14
  #define LPUART_STAT_MA2F_WIDTH                   1
  #define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA2F_SHIFT))&LPUART_STAT_MA2F_MASK)
  #define LPUART_STAT_MA1F_MASK                    0x8000u
  #define LPUART_STAT_MA1F_SHIFT                   15
  #define LPUART_STAT_MA1F_WIDTH                   1
  #define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA1F_SHIFT))&LPUART_STAT_MA1F_MASK)
  #define LPUART_STAT_PF_MASK                      0x10000u
  #define LPUART_STAT_PF_SHIFT                     16
  #define LPUART_STAT_PF_WIDTH                     1
  #define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_PF_SHIFT))&LPUART_STAT_PF_MASK)
  #define LPUART_STAT_FE_MASK                      0x20000u
  #define LPUART_STAT_FE_SHIFT                     17
  #define LPUART_STAT_FE_WIDTH                     1
  #define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_FE_SHIFT))&LPUART_STAT_FE_MASK)
  #define LPUART_STAT_NF_MASK                      0x40000u
  #define LPUART_STAT_NF_SHIFT                     18
  #define LPUART_STAT_NF_WIDTH                     1
  #define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_NF_SHIFT))&LPUART_STAT_NF_MASK)
  #define LPUART_STAT_OR_MASK                      0x80000u
  #define LPUART_STAT_OR_SHIFT                     19
  #define LPUART_STAT_OR_WIDTH                     1
  #define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_OR_SHIFT))&LPUART_STAT_OR_MASK)
  #define LPUART_STAT_IDLE_MASK                    0x100000u
  #define LPUART_STAT_IDLE_SHIFT                   20
  #define LPUART_STAT_IDLE_WIDTH                   1
  #define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_IDLE_SHIFT))&LPUART_STAT_IDLE_MASK)
  #define LPUART_STAT_RDRF_MASK                    0x200000u
  #define LPUART_STAT_RDRF_SHIFT                   21
  #define LPUART_STAT_RDRF_WIDTH                   1
  #define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RDRF_SHIFT))&LPUART_STAT_RDRF_MASK)
  #define LPUART_STAT_TC_MASK                      0x400000u
  #define LPUART_STAT_TC_SHIFT                     22
  #define LPUART_STAT_TC_WIDTH                     1
  #define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TC_SHIFT))&LPUART_STAT_TC_MASK)
  #define LPUART_STAT_TDRE_MASK                    0x800000u
  #define LPUART_STAT_TDRE_SHIFT                   23
  #define LPUART_STAT_TDRE_WIDTH                   1
  #define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TDRE_SHIFT))&LPUART_STAT_TDRE_MASK)
  #define LPUART_STAT_RAF_MASK                     0x1000000u
  #define LPUART_STAT_RAF_SHIFT                    24
  #define LPUART_STAT_RAF_WIDTH                    1
  #define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RAF_SHIFT))&LPUART_STAT_RAF_MASK)
  #define LPUART_STAT_LBKDE_MASK                   0x2000000u
  #define LPUART_STAT_LBKDE_SHIFT                  25
  #define LPUART_STAT_LBKDE_WIDTH                  1
  #define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDE_SHIFT))&LPUART_STAT_LBKDE_MASK)
  #define LPUART_STAT_BRK13_MASK                   0x4000000u
  #define LPUART_STAT_BRK13_SHIFT                  26
  #define LPUART_STAT_BRK13_WIDTH                  1
  #define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_BRK13_SHIFT))&LPUART_STAT_BRK13_MASK)
  #define LPUART_STAT_RWUID_MASK                   0x8000000u
  #define LPUART_STAT_RWUID_SHIFT                  27
  #define LPUART_STAT_RWUID_WIDTH                  1
  #define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RWUID_SHIFT))&LPUART_STAT_RWUID_MASK)
  #define LPUART_STAT_RXINV_MASK                   0x10000000u
  #define LPUART_STAT_RXINV_SHIFT                  28
  #define LPUART_STAT_RXINV_WIDTH                  1
  #define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXINV_SHIFT))&LPUART_STAT_RXINV_MASK)
  #define LPUART_STAT_MSBF_MASK                    0x20000000u
  #define LPUART_STAT_MSBF_SHIFT                   29
  #define LPUART_STAT_MSBF_WIDTH                   1
  #define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MSBF_SHIFT))&LPUART_STAT_MSBF_MASK)
  #define LPUART_STAT_RXEDGIF_MASK                 0x40000000u
  #define LPUART_STAT_RXEDGIF_SHIFT                30
  #define LPUART_STAT_RXEDGIF_WIDTH                1
  #define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXEDGIF_SHIFT))&LPUART_STAT_RXEDGIF_MASK)
  #define LPUART_STAT_LBKDIF_MASK                  0x80000000u
  #define LPUART_STAT_LBKDIF_SHIFT                 31
  #define LPUART_STAT_LBKDIF_WIDTH                 1
  #define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDIF_SHIFT))&LPUART_STAT_LBKDIF_MASK)
  /* CTRL Bit Fields */
  #define LPUART_CTRL_PT_MASK                      0x1u
  #define LPUART_CTRL_PT_SHIFT                     0
  #define LPUART_CTRL_PT_WIDTH                     1
  #define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PT_SHIFT))&LPUART_CTRL_PT_MASK)
  #define LPUART_CTRL_PE_MASK                      0x2u
  #define LPUART_CTRL_PE_SHIFT                     1
  #define LPUART_CTRL_PE_WIDTH                     1
  #define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PE_SHIFT))&LPUART_CTRL_PE_MASK)
  #define LPUART_CTRL_ILT_MASK                     0x4u
  #define LPUART_CTRL_ILT_SHIFT                    2
  #define LPUART_CTRL_ILT_WIDTH                    1
  #define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILT_SHIFT))&LPUART_CTRL_ILT_MASK)
  #define LPUART_CTRL_WAKE_MASK                    0x8u
  #define LPUART_CTRL_WAKE_SHIFT                   3
  #define LPUART_CTRL_WAKE_WIDTH                   1
  #define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_WAKE_SHIFT))&LPUART_CTRL_WAKE_MASK)
  #define LPUART_CTRL_M_MASK                       0x10u
  #define LPUART_CTRL_M_SHIFT                      4
  #define LPUART_CTRL_M_WIDTH                      1
  #define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_M_SHIFT))&LPUART_CTRL_M_MASK)
  #define LPUART_CTRL_RSRC_MASK                    0x20u
  #define LPUART_CTRL_RSRC_SHIFT                   5
  #define LPUART_CTRL_RSRC_WIDTH                   1
  #define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RSRC_SHIFT))&LPUART_CTRL_RSRC_MASK)
  #define LPUART_CTRL_DOZEEN_MASK                  0x40u
  #define LPUART_CTRL_DOZEEN_SHIFT                 6
  #define LPUART_CTRL_DOZEEN_WIDTH                 1
  #define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_DOZEEN_SHIFT))&LPUART_CTRL_DOZEEN_MASK)
  #define LPUART_CTRL_LOOPS_MASK                   0x80u
  #define LPUART_CTRL_LOOPS_SHIFT                  7
  #define LPUART_CTRL_LOOPS_WIDTH                  1
  #define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_LOOPS_SHIFT))&LPUART_CTRL_LOOPS_MASK)
  #define LPUART_CTRL_IDLECFG_MASK                 0x700u
  #define LPUART_CTRL_IDLECFG_SHIFT                8
  #define LPUART_CTRL_IDLECFG_WIDTH                3
  #define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
  #define LPUART_CTRL_MA2IE_MASK                   0x4000u
  #define LPUART_CTRL_MA2IE_SHIFT                  14
  #define LPUART_CTRL_MA2IE_WIDTH                  1
  #define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA2IE_SHIFT))&LPUART_CTRL_MA2IE_MASK)
  #define LPUART_CTRL_MA1IE_MASK                   0x8000u
  #define LPUART_CTRL_MA1IE_SHIFT                  15
  #define LPUART_CTRL_MA1IE_WIDTH                  1
  #define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA1IE_SHIFT))&LPUART_CTRL_MA1IE_MASK)
  #define LPUART_CTRL_SBK_MASK                     0x10000u
  #define LPUART_CTRL_SBK_SHIFT                    16
  #define LPUART_CTRL_SBK_WIDTH                    1
  #define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_SBK_SHIFT))&LPUART_CTRL_SBK_MASK)
  #define LPUART_CTRL_RWU_MASK                     0x20000u
  #define LPUART_CTRL_RWU_SHIFT                    17
  #define LPUART_CTRL_RWU_WIDTH                    1
  #define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RWU_SHIFT))&LPUART_CTRL_RWU_MASK)
  #define LPUART_CTRL_RE_MASK                      0x40000u
  #define LPUART_CTRL_RE_SHIFT                     18
  #define LPUART_CTRL_RE_WIDTH                     1
  #define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RE_SHIFT))&LPUART_CTRL_RE_MASK)
  #define LPUART_CTRL_TE_MASK                      0x80000u
  #define LPUART_CTRL_TE_SHIFT                     19
  #define LPUART_CTRL_TE_WIDTH                     1
  #define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TE_SHIFT))&LPUART_CTRL_TE_MASK)
  #define LPUART_CTRL_ILIE_MASK                    0x100000u
  #define LPUART_CTRL_ILIE_SHIFT                   20
  #define LPUART_CTRL_ILIE_WIDTH                   1
  #define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILIE_SHIFT))&LPUART_CTRL_ILIE_MASK)
  #define LPUART_CTRL_RIE_MASK                     0x200000u
  #define LPUART_CTRL_RIE_SHIFT                    21
  #define LPUART_CTRL_RIE_WIDTH                    1
  #define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RIE_SHIFT))&LPUART_CTRL_RIE_MASK)
  #define LPUART_CTRL_TCIE_MASK                    0x400000u
  #define LPUART_CTRL_TCIE_SHIFT                   22
  #define LPUART_CTRL_TCIE_WIDTH                   1
  #define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TCIE_SHIFT))&LPUART_CTRL_TCIE_MASK)
  #define LPUART_CTRL_TIE_MASK                     0x800000u
  #define LPUART_CTRL_TIE_SHIFT                    23
  #define LPUART_CTRL_TIE_WIDTH                    1
  #define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TIE_SHIFT))&LPUART_CTRL_TIE_MASK)
  #define LPUART_CTRL_PEIE_MASK                    0x1000000u
  #define LPUART_CTRL_PEIE_SHIFT                   24
  #define LPUART_CTRL_PEIE_WIDTH                   1
  #define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PEIE_SHIFT))&LPUART_CTRL_PEIE_MASK)
  #define LPUART_CTRL_FEIE_MASK                    0x2000000u
  #define LPUART_CTRL_FEIE_SHIFT                   25
  #define LPUART_CTRL_FEIE_WIDTH                   1
  #define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_FEIE_SHIFT))&LPUART_CTRL_FEIE_MASK)
  #define LPUART_CTRL_NEIE_MASK                    0x4000000u
  #define LPUART_CTRL_NEIE_SHIFT                   26
  #define LPUART_CTRL_NEIE_WIDTH                   1
  #define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_NEIE_SHIFT))&LPUART_CTRL_NEIE_MASK)
  #define LPUART_CTRL_ORIE_MASK                    0x8000000u
  #define LPUART_CTRL_ORIE_SHIFT                   27
  #define LPUART_CTRL_ORIE_WIDTH                   1
  #define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ORIE_SHIFT))&LPUART_CTRL_ORIE_MASK)
  #define LPUART_CTRL_TXINV_MASK                   0x10000000u
  #define LPUART_CTRL_TXINV_SHIFT                  28
  #define LPUART_CTRL_TXINV_WIDTH                  1
  #define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXINV_SHIFT))&LPUART_CTRL_TXINV_MASK)
  #define LPUART_CTRL_TXDIR_MASK                   0x20000000u
  #define LPUART_CTRL_TXDIR_SHIFT                  29
  #define LPUART_CTRL_TXDIR_WIDTH                  1
  #define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXDIR_SHIFT))&LPUART_CTRL_TXDIR_MASK)
  #define LPUART_CTRL_R9T8_MASK                    0x40000000u
  #define LPUART_CTRL_R9T8_SHIFT                   30
  #define LPUART_CTRL_R9T8_WIDTH                   1
  #define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R9T8_SHIFT))&LPUART_CTRL_R9T8_MASK)
  #define LPUART_CTRL_R8T9_MASK                    0x80000000u
  #define LPUART_CTRL_R8T9_SHIFT                   31
  #define LPUART_CTRL_R8T9_WIDTH                   1
  #define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R8T9_SHIFT))&LPUART_CTRL_R8T9_MASK)
  /* DATA Bit Fields */
  #define LPUART_DATA_R0T0_MASK                    0x1u
  #define LPUART_DATA_R0T0_SHIFT                   0
  #define LPUART_DATA_R0T0_WIDTH                   1
  #define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R0T0_SHIFT))&LPUART_DATA_R0T0_MASK)
  #define LPUART_DATA_R1T1_MASK                    0x2u
  #define LPUART_DATA_R1T1_SHIFT                   1
  #define LPUART_DATA_R1T1_WIDTH                   1
  #define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R1T1_SHIFT))&LPUART_DATA_R1T1_MASK)
  #define LPUART_DATA_R2T2_MASK                    0x4u
  #define LPUART_DATA_R2T2_SHIFT                   2
  #define LPUART_DATA_R2T2_WIDTH                   1
  #define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R2T2_SHIFT))&LPUART_DATA_R2T2_MASK)
  #define LPUART_DATA_R3T3_MASK                    0x8u
  #define LPUART_DATA_R3T3_SHIFT                   3
  #define LPUART_DATA_R3T3_WIDTH                   1
  #define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R3T3_SHIFT))&LPUART_DATA_R3T3_MASK)
  #define LPUART_DATA_R4T4_MASK                    0x10u
  #define LPUART_DATA_R4T4_SHIFT                   4
  #define LPUART_DATA_R4T4_WIDTH                   1
  #define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R4T4_SHIFT))&LPUART_DATA_R4T4_MASK)
  #define LPUART_DATA_R5T5_MASK                    0x20u
  #define LPUART_DATA_R5T5_SHIFT                   5
  #define LPUART_DATA_R5T5_WIDTH                   1
  #define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R5T5_SHIFT))&LPUART_DATA_R5T5_MASK)
  #define LPUART_DATA_R6T6_MASK                    0x40u
  #define LPUART_DATA_R6T6_SHIFT                   6
  #define LPUART_DATA_R6T6_WIDTH                   1
  #define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R6T6_SHIFT))&LPUART_DATA_R6T6_MASK)
  #define LPUART_DATA_R7T7_MASK                    0x80u
  #define LPUART_DATA_R7T7_SHIFT                   7
  #define LPUART_DATA_R7T7_WIDTH                   1
  #define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R7T7_SHIFT))&LPUART_DATA_R7T7_MASK)
  #define LPUART_DATA_R8T8_MASK                    0x100u
  #define LPUART_DATA_R8T8_SHIFT                   8
  #define LPUART_DATA_R8T8_WIDTH                   1
  #define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R8T8_SHIFT))&LPUART_DATA_R8T8_MASK)
  #define LPUART_DATA_R9T9_MASK                    0x200u
  #define LPUART_DATA_R9T9_SHIFT                   9
  #define LPUART_DATA_R9T9_WIDTH                   1
  #define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R9T9_SHIFT))&LPUART_DATA_R9T9_MASK)
  #define LPUART_DATA_IDLINE_MASK                  0x800u
  #define LPUART_DATA_IDLINE_SHIFT                 11
  #define LPUART_DATA_IDLINE_WIDTH                 1
  #define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_IDLINE_SHIFT))&LPUART_DATA_IDLINE_MASK)
  #define LPUART_DATA_RXEMPT_MASK                  0x1000u
  #define LPUART_DATA_RXEMPT_SHIFT                 12
  #define LPUART_DATA_RXEMPT_WIDTH                 1
  #define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_RXEMPT_SHIFT))&LPUART_DATA_RXEMPT_MASK)
  #define LPUART_DATA_FRETSC_MASK                  0x2000u
  #define LPUART_DATA_FRETSC_SHIFT                 13
  #define LPUART_DATA_FRETSC_WIDTH                 1
  #define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_FRETSC_SHIFT))&LPUART_DATA_FRETSC_MASK)
  #define LPUART_DATA_PARITYE_MASK                 0x4000u
  #define LPUART_DATA_PARITYE_SHIFT                14
  #define LPUART_DATA_PARITYE_WIDTH                1
  #define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_PARITYE_SHIFT))&LPUART_DATA_PARITYE_MASK)
  #define LPUART_DATA_NOISY_MASK                   0x8000u
  #define LPUART_DATA_NOISY_SHIFT                  15
  #define LPUART_DATA_NOISY_WIDTH                  1
  #define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_NOISY_SHIFT))&LPUART_DATA_NOISY_MASK)
  /* MATCH Bit Fields */
  #define LPUART_MATCH_MA1_MASK                    0x3FFu
  #define LPUART_MATCH_MA1_SHIFT                   0
  #define LPUART_MATCH_MA1_WIDTH                   10
  #define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
  #define LPUART_MATCH_MA2_MASK                    0x3FF0000u
  #define LPUART_MATCH_MA2_SHIFT                   16
  #define LPUART_MATCH_MA2_WIDTH                   10
  #define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
  /* MODIR Bit Fields */
  #define LPUART_MODIR_TXCTSE_MASK                 0x1u
  #define LPUART_MODIR_TXCTSE_SHIFT                0
  #define LPUART_MODIR_TXCTSE_WIDTH                1
  #define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSE_SHIFT))&LPUART_MODIR_TXCTSE_MASK)
  #define LPUART_MODIR_TXRTSE_MASK                 0x2u
  #define LPUART_MODIR_TXRTSE_SHIFT                1
  #define LPUART_MODIR_TXRTSE_WIDTH                1
  #define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSE_SHIFT))&LPUART_MODIR_TXRTSE_MASK)
  #define LPUART_MODIR_TXRTSPOL_MASK               0x4u
  #define LPUART_MODIR_TXRTSPOL_SHIFT              2
  #define LPUART_MODIR_TXRTSPOL_WIDTH              1
  #define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSPOL_SHIFT))&LPUART_MODIR_TXRTSPOL_MASK)
  #define LPUART_MODIR_RXRTSE_MASK                 0x8u
  #define LPUART_MODIR_RXRTSE_SHIFT                3
  #define LPUART_MODIR_RXRTSE_WIDTH                1
  #define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_RXRTSE_SHIFT))&LPUART_MODIR_RXRTSE_MASK)
  #define LPUART_MODIR_TXCTSC_MASK                 0x10u
  #define LPUART_MODIR_TXCTSC_SHIFT                4
  #define LPUART_MODIR_TXCTSC_WIDTH                1
  #define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSC_SHIFT))&LPUART_MODIR_TXCTSC_MASK)
  #define LPUART_MODIR_TXCTSSRC_MASK               0x20u
  #define LPUART_MODIR_TXCTSSRC_SHIFT              5
  #define LPUART_MODIR_TXCTSSRC_WIDTH              1
  #define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSSRC_SHIFT))&LPUART_MODIR_TXCTSSRC_MASK)
  #define LPUART_MODIR_TNP_MASK                    0x30000u
  #define LPUART_MODIR_TNP_SHIFT                   16
  #define LPUART_MODIR_TNP_WIDTH                   2
  #define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TNP_SHIFT))&LPUART_MODIR_TNP_MASK)
  #define LPUART_MODIR_IREN_MASK                   0x40000u
  #define LPUART_MODIR_IREN_SHIFT                  18
  #define LPUART_MODIR_IREN_WIDTH                  1
  #define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_IREN_SHIFT))&LPUART_MODIR_IREN_MASK)
  
  /*!
   * @}
   */ /* end of group LPUART_Register_Masks */
  
  
  /* LPUART - Peripheral instance base addresses */
  /** Peripheral LPUART0 base address */
  #define LPUART0_BASE                             (0x4002A000u)
  /** Peripheral LPUART0 base pointer */
  #define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
  #define LPUART0_BASE_PTR                         (LPUART0)
  /** Array initializer of LPUART peripheral base addresses */
  #define LPUART_BASE_ADDRS                        { LPUART0_BASE }
  /** Array initializer of LPUART peripheral base pointers */
  #define LPUART_BASE_PTRS                         { LPUART0 }
  
  /* ----------------------------------------------------------------------------
     -- LPUART - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
   * @{
   */
  
  
  /* LPUART - Register instance definitions */
  /* LPUART0 */
  #define LPUART0_BAUD                             LPUART_BAUD_REG(LPUART0)
  #define LPUART0_STAT                             LPUART_STAT_REG(LPUART0)
  #define LPUART0_CTRL                             LPUART_CTRL_REG(LPUART0)
  #define LPUART0_DATA                             LPUART_DATA_REG(LPUART0)
  #define LPUART0_MATCH                            LPUART_MATCH_REG(LPUART0)
  #define LPUART0_MODIR                            LPUART_MODIR_REG(LPUART0)
  
  /*!
   * @}
   */ /* end of group LPUART_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group LPUART_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- MCG Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
   * @{
   */
  
  /** MCG - Register Layout Typedef */
  typedef struct {
    __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
    __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
    __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
    __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
    __IO uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
    __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
    __IO uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
         uint8_t RESERVED_0[1];
    __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
         uint8_t RESERVED_1[1];
    __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
    __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
    __IO uint8_t C7;                                 /**< MCG Control 7 Register, offset: 0xC */
    __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
         uint8_t RESERVED_2[3];
    __I  uint8_t C12;                                /**< MCG Control 12 Register, offset: 0x11 */
    __I  uint8_t S2;                                 /**< MCG Status 2 Register, offset: 0x12 */
    __I  uint8_t T3;                                 /**< MCG Test 3 Register, offset: 0x13 */
  } MCG_Type, *MCG_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- MCG - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
   * @{
   */
  
  
  /* MCG - Register accessors */
  #define MCG_C1_REG(base)                         ((base)->C1)
  #define MCG_C2_REG(base)                         ((base)->C2)
  #define MCG_C3_REG(base)                         ((base)->C3)
  #define MCG_C4_REG(base)                         ((base)->C4)
  #define MCG_C5_REG(base)                         ((base)->C5)
  #define MCG_C6_REG(base)                         ((base)->C6)
  #define MCG_S_REG(base)                          ((base)->S)
  #define MCG_SC_REG(base)                         ((base)->SC)
  #define MCG_ATCVH_REG(base)                      ((base)->ATCVH)
  #define MCG_ATCVL_REG(base)                      ((base)->ATCVL)
  #define MCG_C7_REG(base)                         ((base)->C7)
  #define MCG_C8_REG(base)                         ((base)->C8)
  #define MCG_C12_REG(base)                        ((base)->C12)
  #define MCG_S2_REG(base)                         ((base)->S2)
  #define MCG_T3_REG(base)                         ((base)->T3)
  
  /*!
   * @}
   */ /* end of group MCG_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- MCG Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup MCG_Register_Masks MCG Register Masks
   * @{
   */
  
  /* C1 Bit Fields */
  #define MCG_C1_IREFSTEN_MASK                     0x1u
  #define MCG_C1_IREFSTEN_SHIFT                    0
  #define MCG_C1_IREFSTEN_WIDTH                    1
  #define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFSTEN_SHIFT))&MCG_C1_IREFSTEN_MASK)
  #define MCG_C1_IRCLKEN_MASK                      0x2u
  #define MCG_C1_IRCLKEN_SHIFT                     1
  #define MCG_C1_IRCLKEN_WIDTH                     1
  #define MCG_C1_IRCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C1_IRCLKEN_SHIFT))&MCG_C1_IRCLKEN_MASK)
  #define MCG_C1_IREFS_MASK                        0x4u
  #define MCG_C1_IREFS_SHIFT                       2
  #define MCG_C1_IREFS_WIDTH                       1
  #define MCG_C1_IREFS(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_IREFS_SHIFT))&MCG_C1_IREFS_MASK)
  #define MCG_C1_FRDIV_MASK                        0x38u
  #define MCG_C1_FRDIV_SHIFT                       3
  #define MCG_C1_FRDIV_WIDTH                       3
  #define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
  #define MCG_C1_CLKS_MASK                         0xC0u
  #define MCG_C1_CLKS_SHIFT                        6
  #define MCG_C1_CLKS_WIDTH                        2
  #define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
  /* C2 Bit Fields */
  #define MCG_C2_IRCS_MASK                         0x1u
  #define MCG_C2_IRCS_SHIFT                        0
  #define MCG_C2_IRCS_WIDTH                        1
  #define MCG_C2_IRCS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C2_IRCS_SHIFT))&MCG_C2_IRCS_MASK)
  #define MCG_C2_LP_MASK                           0x2u
  #define MCG_C2_LP_SHIFT                          1
  #define MCG_C2_LP_WIDTH                          1
  #define MCG_C2_LP(x)                             (((uint8_t)(((uint8_t)(x))<<MCG_C2_LP_SHIFT))&MCG_C2_LP_MASK)
  #define MCG_C2_EREFS_MASK                        0x4u
  #define MCG_C2_EREFS_SHIFT                       2
  #define MCG_C2_EREFS_WIDTH                       1
  #define MCG_C2_EREFS(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C2_EREFS_SHIFT))&MCG_C2_EREFS_MASK)
  #define MCG_C2_HGO_MASK                          0x8u
  #define MCG_C2_HGO_SHIFT                         3
  #define MCG_C2_HGO_WIDTH                         1
  #define MCG_C2_HGO(x)                            (((uint8_t)(((uint8_t)(x))<<MCG_C2_HGO_SHIFT))&MCG_C2_HGO_MASK)
  #define MCG_C2_RANGE_MASK                        0x30u
  #define MCG_C2_RANGE_SHIFT                       4
  #define MCG_C2_RANGE_WIDTH                       2
  #define MCG_C2_RANGE(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
  #define MCG_C2_FCFTRIM_MASK                      0x40u
  #define MCG_C2_FCFTRIM_SHIFT                     6
  #define MCG_C2_FCFTRIM_WIDTH                     1
  #define MCG_C2_FCFTRIM(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C2_FCFTRIM_SHIFT))&MCG_C2_FCFTRIM_MASK)
  #define MCG_C2_LOCRE0_MASK                       0x80u
  #define MCG_C2_LOCRE0_SHIFT                      7
  #define MCG_C2_LOCRE0_WIDTH                      1
  #define MCG_C2_LOCRE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C2_LOCRE0_SHIFT))&MCG_C2_LOCRE0_MASK)
  /* C3 Bit Fields */
  #define MCG_C3_SCTRIM_MASK                       0xFFu
  #define MCG_C3_SCTRIM_SHIFT                      0
  #define MCG_C3_SCTRIM_WIDTH                      8
  #define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
  /* C4 Bit Fields */
  #define MCG_C4_SCFTRIM_MASK                      0x1u
  #define MCG_C4_SCFTRIM_SHIFT                     0
  #define MCG_C4_SCFTRIM_WIDTH                     1
  #define MCG_C4_SCFTRIM(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_C4_SCFTRIM_SHIFT))&MCG_C4_SCFTRIM_MASK)
  #define MCG_C4_FCTRIM_MASK                       0x1Eu
  #define MCG_C4_FCTRIM_SHIFT                      1
  #define MCG_C4_FCTRIM_WIDTH                      4
  #define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
  #define MCG_C4_DRST_DRS_MASK                     0x60u
  #define MCG_C4_DRST_DRS_SHIFT                    5
  #define MCG_C4_DRST_DRS_WIDTH                    2
  #define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
  #define MCG_C4_DMX32_MASK                        0x80u
  #define MCG_C4_DMX32_SHIFT                       7
  #define MCG_C4_DMX32_WIDTH                       1
  #define MCG_C4_DMX32(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C4_DMX32_SHIFT))&MCG_C4_DMX32_MASK)
  /* C5 Bit Fields */
  #define MCG_C5_PRDIV0_MASK                       0x1Fu
  #define MCG_C5_PRDIV0_SHIFT                      0
  #define MCG_C5_PRDIV0_WIDTH                      5
  #define MCG_C5_PRDIV0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
  #define MCG_C5_PLLSTEN0_MASK                     0x20u
  #define MCG_C5_PLLSTEN0_SHIFT                    5
  #define MCG_C5_PLLSTEN0_WIDTH                    1
  #define MCG_C5_PLLSTEN0(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLSTEN0_SHIFT))&MCG_C5_PLLSTEN0_MASK)
  #define MCG_C5_PLLCLKEN0_MASK                    0x40u
  #define MCG_C5_PLLCLKEN0_SHIFT                   6
  #define MCG_C5_PLLCLKEN0_WIDTH                   1
  #define MCG_C5_PLLCLKEN0(x)                      (((uint8_t)(((uint8_t)(x))<<MCG_C5_PLLCLKEN0_SHIFT))&MCG_C5_PLLCLKEN0_MASK)
  /* C6 Bit Fields */
  #define MCG_C6_VDIV0_MASK                        0x1Fu
  #define MCG_C6_VDIV0_SHIFT                       0
  #define MCG_C6_VDIV0_WIDTH                       5
  #define MCG_C6_VDIV0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
  #define MCG_C6_CME0_MASK                         0x20u
  #define MCG_C6_CME0_SHIFT                        5
  #define MCG_C6_CME0_WIDTH                        1
  #define MCG_C6_CME0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C6_CME0_SHIFT))&MCG_C6_CME0_MASK)
  #define MCG_C6_PLLS_MASK                         0x40u
  #define MCG_C6_PLLS_SHIFT                        6
  #define MCG_C6_PLLS_WIDTH                        1
  #define MCG_C6_PLLS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C6_PLLS_SHIFT))&MCG_C6_PLLS_MASK)
  #define MCG_C6_LOLIE0_MASK                       0x80u
  #define MCG_C6_LOLIE0_SHIFT                      7
  #define MCG_C6_LOLIE0_WIDTH                      1
  #define MCG_C6_LOLIE0(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C6_LOLIE0_SHIFT))&MCG_C6_LOLIE0_MASK)
  /* S Bit Fields */
  #define MCG_S_IRCST_MASK                         0x1u
  #define MCG_S_IRCST_SHIFT                        0
  #define MCG_S_IRCST_WIDTH                        1
  #define MCG_S_IRCST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_IRCST_SHIFT))&MCG_S_IRCST_MASK)
  #define MCG_S_OSCINIT0_MASK                      0x2u
  #define MCG_S_OSCINIT0_SHIFT                     1
  #define MCG_S_OSCINIT0_WIDTH                     1
  #define MCG_S_OSCINIT0(x)                        (((uint8_t)(((uint8_t)(x))<<MCG_S_OSCINIT0_SHIFT))&MCG_S_OSCINIT0_MASK)
  #define MCG_S_CLKST_MASK                         0xCu
  #define MCG_S_CLKST_SHIFT                        2
  #define MCG_S_CLKST_WIDTH                        2
  #define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
  #define MCG_S_IREFST_MASK                        0x10u
  #define MCG_S_IREFST_SHIFT                       4
  #define MCG_S_IREFST_WIDTH                       1
  #define MCG_S_IREFST(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_S_IREFST_SHIFT))&MCG_S_IREFST_MASK)
  #define MCG_S_PLLST_MASK                         0x20u
  #define MCG_S_PLLST_SHIFT                        5
  #define MCG_S_PLLST_WIDTH                        1
  #define MCG_S_PLLST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_PLLST_SHIFT))&MCG_S_PLLST_MASK)
  #define MCG_S_LOCK0_MASK                         0x40u
  #define MCG_S_LOCK0_SHIFT                        6
  #define MCG_S_LOCK0_WIDTH                        1
  #define MCG_S_LOCK0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_LOCK0_SHIFT))&MCG_S_LOCK0_MASK)
  #define MCG_S_LOLS0_MASK                         0x80u
  #define MCG_S_LOLS0_SHIFT                        7
  #define MCG_S_LOLS0_WIDTH                        1
  #define MCG_S_LOLS0(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_LOLS0_SHIFT))&MCG_S_LOLS0_MASK)
  /* SC Bit Fields */
  #define MCG_SC_LOCS0_MASK                        0x1u
  #define MCG_SC_LOCS0_SHIFT                       0
  #define MCG_SC_LOCS0_WIDTH                       1
  #define MCG_SC_LOCS0(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_SC_LOCS0_SHIFT))&MCG_SC_LOCS0_MASK)
  #define MCG_SC_FCRDIV_MASK                       0xEu
  #define MCG_SC_FCRDIV_SHIFT                      1
  #define MCG_SC_FCRDIV_WIDTH                      3
  #define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
  #define MCG_SC_FLTPRSRV_MASK                     0x10u
  #define MCG_SC_FLTPRSRV_SHIFT                    4
  #define MCG_SC_FLTPRSRV_WIDTH                    1
  #define MCG_SC_FLTPRSRV(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_SC_FLTPRSRV_SHIFT))&MCG_SC_FLTPRSRV_MASK)
  #define MCG_SC_ATMF_MASK                         0x20u
  #define MCG_SC_ATMF_SHIFT                        5
  #define MCG_SC_ATMF_WIDTH                        1
  #define MCG_SC_ATMF(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMF_SHIFT))&MCG_SC_ATMF_MASK)
  #define MCG_SC_ATMS_MASK                         0x40u
  #define MCG_SC_ATMS_SHIFT                        6
  #define MCG_SC_ATMS_WIDTH                        1
  #define MCG_SC_ATMS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATMS_SHIFT))&MCG_SC_ATMS_MASK)
  #define MCG_SC_ATME_MASK                         0x80u
  #define MCG_SC_ATME_SHIFT                        7
  #define MCG_SC_ATME_WIDTH                        1
  #define MCG_SC_ATME(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_SC_ATME_SHIFT))&MCG_SC_ATME_MASK)
  /* ATCVH Bit Fields */
  #define MCG_ATCVH_ATCVH_MASK                     0xFFu
  #define MCG_ATCVH_ATCVH_SHIFT                    0
  #define MCG_ATCVH_ATCVH_WIDTH                    8
  #define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
  /* ATCVL Bit Fields */
  #define MCG_ATCVL_ATCVL_MASK                     0xFFu
  #define MCG_ATCVL_ATCVL_SHIFT                    0
  #define MCG_ATCVL_ATCVL_WIDTH                    8
  #define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
  /* C7 Bit Fields */
  #define MCG_C7_OSCSEL_MASK                       0x3u
  #define MCG_C7_OSCSEL_SHIFT                      0
  #define MCG_C7_OSCSEL_WIDTH                      2
  #define MCG_C7_OSCSEL(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
  /* C8 Bit Fields */
  #define MCG_C8_LOCS1_MASK                        0x1u
  #define MCG_C8_LOCS1_SHIFT                       0
  #define MCG_C8_LOCS1_WIDTH                       1
  #define MCG_C8_LOCS1(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCS1_SHIFT))&MCG_C8_LOCS1_MASK)
  #define MCG_C8_CME1_MASK                         0x20u
  #define MCG_C8_CME1_SHIFT                        5
  #define MCG_C8_CME1_WIDTH                        1
  #define MCG_C8_CME1(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C8_CME1_SHIFT))&MCG_C8_CME1_MASK)
  #define MCG_C8_LOLRE_MASK                        0x40u
  #define MCG_C8_LOLRE_SHIFT                       6
  #define MCG_C8_LOLRE_WIDTH                       1
  #define MCG_C8_LOLRE(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOLRE_SHIFT))&MCG_C8_LOLRE_MASK)
  #define MCG_C8_LOCRE1_MASK                       0x80u
  #define MCG_C8_LOCRE1_SHIFT                      7
  #define MCG_C8_LOCRE1_WIDTH                      1
  #define MCG_C8_LOCRE1(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C8_LOCRE1_SHIFT))&MCG_C8_LOCRE1_MASK)
  
  /*!
   * @}
   */ /* end of group MCG_Register_Masks */
  
  
  /* MCG - Peripheral instance base addresses */
  /** Peripheral MCG base address */
  #define MCG_BASE                                 (0x40064000u)
  /** Peripheral MCG base pointer */
  #define MCG                                      ((MCG_Type *)MCG_BASE)
  #define MCG_BASE_PTR                             (MCG)
  /** Array initializer of MCG peripheral base addresses */
  #define MCG_BASE_ADDRS                           { MCG_BASE }
  /** Array initializer of MCG peripheral base pointers */
  #define MCG_BASE_PTRS                            { MCG }
  
  /* ----------------------------------------------------------------------------
     -- MCG - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
   * @{
   */
  
  
  /* MCG - Register instance definitions */
  /* MCG */
  #define MCG_C1                                   MCG_C1_REG(MCG)
  #define MCG_C2                                   MCG_C2_REG(MCG)
  #define MCG_C3                                   MCG_C3_REG(MCG)
  #define MCG_C4                                   MCG_C4_REG(MCG)
  #define MCG_C5                                   MCG_C5_REG(MCG)
  #define MCG_C6                                   MCG_C6_REG(MCG)
  #define MCG_S                                    MCG_S_REG(MCG)
  #define MCG_SC                                   MCG_SC_REG(MCG)
  #define MCG_ATCVH                                MCG_ATCVH_REG(MCG)
  #define MCG_ATCVL                                MCG_ATCVL_REG(MCG)
  #define MCG_C7                                   MCG_C7_REG(MCG)
  #define MCG_C8                                   MCG_C8_REG(MCG)
  #define MCG_C12                                  MCG_C12_REG(MCG)
  #define MCG_S2                                   MCG_S2_REG(MCG)
  #define MCG_T3                                   MCG_T3_REG(MCG)
  
  /*!
   * @}
   */ /* end of group MCG_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group MCG_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- MCM Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
   * @{
   */
  
  /** MCM - Register Layout Typedef */
  typedef struct {
         uint8_t RESERVED_0[8];
    __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
    __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
    __IO uint32_t PLACR;                             /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
    __IO uint32_t ISCR;                              /**< Interrupt Status and Control Register, offset: 0x10 */
         uint8_t RESERVED_1[44];
    __IO uint32_t CPO;                               /**< Compute Operation Control Register, offset: 0x40 */
  } MCM_Type, *MCM_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- MCM - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
   * @{
   */
  
  
  /* MCM - Register accessors */
  #define MCM_PLASC_REG(base)                      ((base)->PLASC)
  #define MCM_PLAMC_REG(base)                      ((base)->PLAMC)
  #define MCM_PLACR_REG(base)                      ((base)->PLACR)
  #define MCM_ISCR_REG(base)                       ((base)->ISCR)
  #define MCM_CPO_REG(base)                        ((base)->CPO)
  
  /*!
   * @}
   */ /* end of group MCM_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- MCM Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup MCM_Register_Masks MCM Register Masks
   * @{
   */
  
  /* PLASC Bit Fields */
  #define MCM_PLASC_ASC_MASK                       0xFFu
  #define MCM_PLASC_ASC_SHIFT                      0
  #define MCM_PLASC_ASC_WIDTH                      8
  #define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
  /* PLAMC Bit Fields */
  #define MCM_PLAMC_AMC_MASK                       0xFFu
  #define MCM_PLAMC_AMC_SHIFT                      0
  #define MCM_PLAMC_AMC_WIDTH                      8
  #define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
  /* PLACR Bit Fields */
  #define MCM_PLACR_ARB_MASK                       0x200u
  #define MCM_PLACR_ARB_SHIFT                      9
  #define MCM_PLACR_ARB_WIDTH                      1
  #define MCM_PLACR_ARB(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_ARB_SHIFT))&MCM_PLACR_ARB_MASK)
  /* ISCR Bit Fields */
  #define MCM_ISCR_FIOC_MASK                       0x100u
  #define MCM_ISCR_FIOC_SHIFT                      8
  #define MCM_ISCR_FIOC_WIDTH                      1
  #define MCM_ISCR_FIOC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOC_SHIFT))&MCM_ISCR_FIOC_MASK)
  #define MCM_ISCR_FDZC_MASK                       0x200u
  #define MCM_ISCR_FDZC_SHIFT                      9
  #define MCM_ISCR_FDZC_WIDTH                      1
  #define MCM_ISCR_FDZC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZC_SHIFT))&MCM_ISCR_FDZC_MASK)
  #define MCM_ISCR_FOFC_MASK                       0x400u
  #define MCM_ISCR_FOFC_SHIFT                      10
  #define MCM_ISCR_FOFC_WIDTH                      1
  #define MCM_ISCR_FOFC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFC_SHIFT))&MCM_ISCR_FOFC_MASK)
  #define MCM_ISCR_FUFC_MASK                       0x800u
  #define MCM_ISCR_FUFC_SHIFT                      11
  #define MCM_ISCR_FUFC_WIDTH                      1
  #define MCM_ISCR_FUFC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFC_SHIFT))&MCM_ISCR_FUFC_MASK)
  #define MCM_ISCR_FIXC_MASK                       0x1000u
  #define MCM_ISCR_FIXC_SHIFT                      12
  #define MCM_ISCR_FIXC_WIDTH                      1
  #define MCM_ISCR_FIXC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXC_SHIFT))&MCM_ISCR_FIXC_MASK)
  #define MCM_ISCR_FIDC_MASK                       0x8000u
  #define MCM_ISCR_FIDC_SHIFT                      15
  #define MCM_ISCR_FIDC_WIDTH                      1
  #define MCM_ISCR_FIDC(x)                         (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDC_SHIFT))&MCM_ISCR_FIDC_MASK)
  #define MCM_ISCR_FIOCE_MASK                      0x1000000u
  #define MCM_ISCR_FIOCE_SHIFT                     24
  #define MCM_ISCR_FIOCE_WIDTH                     1
  #define MCM_ISCR_FIOCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOCE_SHIFT))&MCM_ISCR_FIOCE_MASK)
  #define MCM_ISCR_FDZCE_MASK                      0x2000000u
  #define MCM_ISCR_FDZCE_SHIFT                     25
  #define MCM_ISCR_FDZCE_WIDTH                     1
  #define MCM_ISCR_FDZCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZCE_SHIFT))&MCM_ISCR_FDZCE_MASK)
  #define MCM_ISCR_FOFCE_MASK                      0x4000000u
  #define MCM_ISCR_FOFCE_SHIFT                     26
  #define MCM_ISCR_FOFCE_WIDTH                     1
  #define MCM_ISCR_FOFCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFCE_SHIFT))&MCM_ISCR_FOFCE_MASK)
  #define MCM_ISCR_FUFCE_MASK                      0x8000000u
  #define MCM_ISCR_FUFCE_SHIFT                     27
  #define MCM_ISCR_FUFCE_WIDTH                     1
  #define MCM_ISCR_FUFCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFCE_SHIFT))&MCM_ISCR_FUFCE_MASK)
  #define MCM_ISCR_FIXCE_MASK                      0x10000000u
  #define MCM_ISCR_FIXCE_SHIFT                     28
  #define MCM_ISCR_FIXCE_WIDTH                     1
  #define MCM_ISCR_FIXCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXCE_SHIFT))&MCM_ISCR_FIXCE_MASK)
  #define MCM_ISCR_FIDCE_MASK                      0x80000000u
  #define MCM_ISCR_FIDCE_SHIFT                     31
  #define MCM_ISCR_FIDCE_WIDTH                     1
  #define MCM_ISCR_FIDCE(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDCE_SHIFT))&MCM_ISCR_FIDCE_MASK)
  /* CPO Bit Fields */
  #define MCM_CPO_CPOREQ_MASK                      0x1u
  #define MCM_CPO_CPOREQ_SHIFT                     0
  #define MCM_CPO_CPOREQ_WIDTH                     1
  #define MCM_CPO_CPOREQ(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOREQ_SHIFT))&MCM_CPO_CPOREQ_MASK)
  #define MCM_CPO_CPOACK_MASK                      0x2u
  #define MCM_CPO_CPOACK_SHIFT                     1
  #define MCM_CPO_CPOACK_WIDTH                     1
  #define MCM_CPO_CPOACK(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOACK_SHIFT))&MCM_CPO_CPOACK_MASK)
  #define MCM_CPO_CPOWOI_MASK                      0x4u
  #define MCM_CPO_CPOWOI_SHIFT                     2
  #define MCM_CPO_CPOWOI_WIDTH                     1
  #define MCM_CPO_CPOWOI(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOWOI_SHIFT))&MCM_CPO_CPOWOI_MASK)
  
  /*!
   * @}
   */ /* end of group MCM_Register_Masks */
  
  
  /* MCM - Peripheral instance base addresses */
  /** Peripheral MCM base address */
  #define MCM_BASE                                 (0xE0080000u)
  /** Peripheral MCM base pointer */
  #define MCM                                      ((MCM_Type *)MCM_BASE)
  #define MCM_BASE_PTR                             (MCM)
  /** Array initializer of MCM peripheral base addresses */
  #define MCM_BASE_ADDRS                           { MCM_BASE }
  /** Array initializer of MCM peripheral base pointers */
  #define MCM_BASE_PTRS                            { MCM }
  
  /* ----------------------------------------------------------------------------
     -- MCM - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
   * @{
   */
  
  
  /* MCM - Register instance definitions */
  /* MCM */
  #define MCM_PLASC                                MCM_PLASC_REG(MCM)
  #define MCM_PLAMC                                MCM_PLAMC_REG(MCM)
  #define MCM_PLACR                                MCM_PLACR_REG(MCM)
  #define MCM_ISCR                                 MCM_ISCR_REG(MCM)
  #define MCM_CPO                                  MCM_CPO_REG(MCM)
  
  /*!
   * @}
   */ /* end of group MCM_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group MCM_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- NV Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
   * @{
   */
  
  /** NV - Register Layout Typedef */
  typedef struct {
    __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
    __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
    __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
    __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
    __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
    __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
    __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
    __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
    __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
    __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
    __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
    __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
    __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
    __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
  } NV_Type, *NV_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- NV - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
   * @{
   */
  
  
  /* NV - Register accessors */
  #define NV_BACKKEY3_REG(base)                    ((base)->BACKKEY3)
  #define NV_BACKKEY2_REG(base)                    ((base)->BACKKEY2)
  #define NV_BACKKEY1_REG(base)                    ((base)->BACKKEY1)
  #define NV_BACKKEY0_REG(base)                    ((base)->BACKKEY0)
  #define NV_BACKKEY7_REG(base)                    ((base)->BACKKEY7)
  #define NV_BACKKEY6_REG(base)                    ((base)->BACKKEY6)
  #define NV_BACKKEY5_REG(base)                    ((base)->BACKKEY5)
  #define NV_BACKKEY4_REG(base)                    ((base)->BACKKEY4)
  #define NV_FPROT3_REG(base)                      ((base)->FPROT3)
  #define NV_FPROT2_REG(base)                      ((base)->FPROT2)
  #define NV_FPROT1_REG(base)                      ((base)->FPROT1)
  #define NV_FPROT0_REG(base)                      ((base)->FPROT0)
  #define NV_FSEC_REG(base)                        ((base)->FSEC)
  #define NV_FOPT_REG(base)                        ((base)->FOPT)
  
  /*!
   * @}
   */ /* end of group NV_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- NV Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup NV_Register_Masks NV Register Masks
   * @{
   */
  
  /* BACKKEY3 Bit Fields */
  #define NV_BACKKEY3_KEY_MASK                     0xFFu
  #define NV_BACKKEY3_KEY_SHIFT                    0
  #define NV_BACKKEY3_KEY_WIDTH                    8
  #define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
  /* BACKKEY2 Bit Fields */
  #define NV_BACKKEY2_KEY_MASK                     0xFFu
  #define NV_BACKKEY2_KEY_SHIFT                    0
  #define NV_BACKKEY2_KEY_WIDTH                    8
  #define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
  /* BACKKEY1 Bit Fields */
  #define NV_BACKKEY1_KEY_MASK                     0xFFu
  #define NV_BACKKEY1_KEY_SHIFT                    0
  #define NV_BACKKEY1_KEY_WIDTH                    8
  #define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
  /* BACKKEY0 Bit Fields */
  #define NV_BACKKEY0_KEY_MASK                     0xFFu
  #define NV_BACKKEY0_KEY_SHIFT                    0
  #define NV_BACKKEY0_KEY_WIDTH                    8
  #define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
  /* BACKKEY7 Bit Fields */
  #define NV_BACKKEY7_KEY_MASK                     0xFFu
  #define NV_BACKKEY7_KEY_SHIFT                    0
  #define NV_BACKKEY7_KEY_WIDTH                    8
  #define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
  /* BACKKEY6 Bit Fields */
  #define NV_BACKKEY6_KEY_MASK                     0xFFu
  #define NV_BACKKEY6_KEY_SHIFT                    0
  #define NV_BACKKEY6_KEY_WIDTH                    8
  #define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
  /* BACKKEY5 Bit Fields */
  #define NV_BACKKEY5_KEY_MASK                     0xFFu
  #define NV_BACKKEY5_KEY_SHIFT                    0
  #define NV_BACKKEY5_KEY_WIDTH                    8
  #define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
  /* BACKKEY4 Bit Fields */
  #define NV_BACKKEY4_KEY_MASK                     0xFFu
  #define NV_BACKKEY4_KEY_SHIFT                    0
  #define NV_BACKKEY4_KEY_WIDTH                    8
  #define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
  /* FPROT3 Bit Fields */
  #define NV_FPROT3_PROT_MASK                      0xFFu
  #define NV_FPROT3_PROT_SHIFT                     0
  #define NV_FPROT3_PROT_WIDTH                     8
  #define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
  /* FPROT2 Bit Fields */
  #define NV_FPROT2_PROT_MASK                      0xFFu
  #define NV_FPROT2_PROT_SHIFT                     0
  #define NV_FPROT2_PROT_WIDTH                     8
  #define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
  /* FPROT1 Bit Fields */
  #define NV_FPROT1_PROT_MASK                      0xFFu
  #define NV_FPROT1_PROT_SHIFT                     0
  #define NV_FPROT1_PROT_WIDTH                     8
  #define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
  /* FPROT0 Bit Fields */
  #define NV_FPROT0_PROT_MASK                      0xFFu
  #define NV_FPROT0_PROT_SHIFT                     0
  #define NV_FPROT0_PROT_WIDTH                     8
  #define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
  /* FSEC Bit Fields */
  #define NV_FSEC_SEC_MASK                         0x3u
  #define NV_FSEC_SEC_SHIFT                        0
  #define NV_FSEC_SEC_WIDTH                        2
  #define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
  #define NV_FSEC_FSLACC_MASK                      0xCu
  #define NV_FSEC_FSLACC_SHIFT                     2
  #define NV_FSEC_FSLACC_WIDTH                     2
  #define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
  #define NV_FSEC_MEEN_MASK                        0x30u
  #define NV_FSEC_MEEN_SHIFT                       4
  #define NV_FSEC_MEEN_WIDTH                       2
  #define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
  #define NV_FSEC_KEYEN_MASK                       0xC0u
  #define NV_FSEC_KEYEN_SHIFT                      6
  #define NV_FSEC_KEYEN_WIDTH                      2
  #define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
  /* FOPT Bit Fields */
  #define NV_FOPT_LPBOOT_MASK                      0x1u
  #define NV_FOPT_LPBOOT_SHIFT                     0
  #define NV_FOPT_LPBOOT_WIDTH                     1
  #define NV_FOPT_LPBOOT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FOPT_LPBOOT_SHIFT))&NV_FOPT_LPBOOT_MASK)
  #define NV_FOPT_EZPORT_DIS_MASK                  0x2u
  #define NV_FOPT_EZPORT_DIS_SHIFT                 1
  #define NV_FOPT_EZPORT_DIS_WIDTH                 1
  #define NV_FOPT_EZPORT_DIS(x)                    (((uint8_t)(((uint8_t)(x))<<NV_FOPT_EZPORT_DIS_SHIFT))&NV_FOPT_EZPORT_DIS_MASK)
  #define NV_FOPT_NMI_DIS_MASK                     0x4u
  #define NV_FOPT_NMI_DIS_SHIFT                    2
  #define NV_FOPT_NMI_DIS_WIDTH                    1
  #define NV_FOPT_NMI_DIS(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FOPT_NMI_DIS_SHIFT))&NV_FOPT_NMI_DIS_MASK)
  #define NV_FOPT_FAST_INIT_MASK                   0x20u
  #define NV_FOPT_FAST_INIT_SHIFT                  5
  #define NV_FOPT_FAST_INIT_WIDTH                  1
  #define NV_FOPT_FAST_INIT(x)                     (((uint8_t)(((uint8_t)(x))<<NV_FOPT_FAST_INIT_SHIFT))&NV_FOPT_FAST_INIT_MASK)
  
  /*!
   * @}
   */ /* end of group NV_Register_Masks */
  
  
  /* NV - Peripheral instance base addresses */
  /** Peripheral FTFA_FlashConfig base address */
  #define FTFA_FlashConfig_BASE                    (0x400u)
  /** Peripheral FTFA_FlashConfig base pointer */
  #define FTFA_FlashConfig                         ((NV_Type *)FTFA_FlashConfig_BASE)
  #define FTFA_FlashConfig_BASE_PTR                (FTFA_FlashConfig)
  /** Array initializer of NV peripheral base addresses */
  #define NV_BASE_ADDRS                            { FTFA_FlashConfig_BASE }
  /** Array initializer of NV peripheral base pointers */
  #define NV_BASE_PTRS                             { FTFA_FlashConfig }
  
  /* ----------------------------------------------------------------------------
     -- NV - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
   * @{
   */
  
  
  /* NV - Register instance definitions */
  /* FTFA_FlashConfig */
  #define NV_BACKKEY3                              NV_BACKKEY3_REG(FTFA_FlashConfig)
  #define NV_BACKKEY2                              NV_BACKKEY2_REG(FTFA_FlashConfig)
  #define NV_BACKKEY1                              NV_BACKKEY1_REG(FTFA_FlashConfig)
  #define NV_BACKKEY0                              NV_BACKKEY0_REG(FTFA_FlashConfig)
  #define NV_BACKKEY7                              NV_BACKKEY7_REG(FTFA_FlashConfig)
  #define NV_BACKKEY6                              NV_BACKKEY6_REG(FTFA_FlashConfig)
  #define NV_BACKKEY5                              NV_BACKKEY5_REG(FTFA_FlashConfig)
  #define NV_BACKKEY4                              NV_BACKKEY4_REG(FTFA_FlashConfig)
  #define NV_FPROT3                                NV_FPROT3_REG(FTFA_FlashConfig)
  #define NV_FPROT2                                NV_FPROT2_REG(FTFA_FlashConfig)
  #define NV_FPROT1                                NV_FPROT1_REG(FTFA_FlashConfig)
  #define NV_FPROT0                                NV_FPROT0_REG(FTFA_FlashConfig)
  #define NV_FSEC                                  NV_FSEC_REG(FTFA_FlashConfig)
  #define NV_FOPT                                  NV_FOPT_REG(FTFA_FlashConfig)
  
  /*!
   * @}
   */ /* end of group NV_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group NV_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- OSC Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
   * @{
   */
  
  /** OSC - Register Layout Typedef */
  typedef struct {
    __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
         uint8_t RESERVED_0[1];
    __IO uint8_t DIV;                                /**< OSC_DIV, offset: 0x2 */
  } OSC_Type, *OSC_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- OSC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
   * @{
   */
  
  
  /* OSC - Register accessors */
  #define OSC_CR_REG(base)                         ((base)->CR)
  #define OSC_DIV_REG(base)                        ((base)->DIV)
  
  /*!
   * @}
   */ /* end of group OSC_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- OSC Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup OSC_Register_Masks OSC Register Masks
   * @{
   */
  
  /* CR Bit Fields */
  #define OSC_CR_SC16P_MASK                        0x1u
  #define OSC_CR_SC16P_SHIFT                       0
  #define OSC_CR_SC16P_WIDTH                       1
  #define OSC_CR_SC16P(x)                          (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC16P_SHIFT))&OSC_CR_SC16P_MASK)
  #define OSC_CR_SC8P_MASK                         0x2u
  #define OSC_CR_SC8P_SHIFT                        1
  #define OSC_CR_SC8P_WIDTH                        1
  #define OSC_CR_SC8P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC8P_SHIFT))&OSC_CR_SC8P_MASK)
  #define OSC_CR_SC4P_MASK                         0x4u
  #define OSC_CR_SC4P_SHIFT                        2
  #define OSC_CR_SC4P_WIDTH                        1
  #define OSC_CR_SC4P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC4P_SHIFT))&OSC_CR_SC4P_MASK)
  #define OSC_CR_SC2P_MASK                         0x8u
  #define OSC_CR_SC2P_SHIFT                        3
  #define OSC_CR_SC2P_WIDTH                        1
  #define OSC_CR_SC2P(x)                           (((uint8_t)(((uint8_t)(x))<<OSC_CR_SC2P_SHIFT))&OSC_CR_SC2P_MASK)
  #define OSC_CR_EREFSTEN_MASK                     0x20u
  #define OSC_CR_EREFSTEN_SHIFT                    5
  #define OSC_CR_EREFSTEN_WIDTH                    1
  #define OSC_CR_EREFSTEN(x)                       (((uint8_t)(((uint8_t)(x))<<OSC_CR_EREFSTEN_SHIFT))&OSC_CR_EREFSTEN_MASK)
  #define OSC_CR_ERCLKEN_MASK                      0x80u
  #define OSC_CR_ERCLKEN_SHIFT                     7
  #define OSC_CR_ERCLKEN_WIDTH                     1
  #define OSC_CR_ERCLKEN(x)                        (((uint8_t)(((uint8_t)(x))<<OSC_CR_ERCLKEN_SHIFT))&OSC_CR_ERCLKEN_MASK)
  /* DIV Bit Fields */
  #define OSC_DIV_ERPS_MASK                        0xC0u
  #define OSC_DIV_ERPS_SHIFT                       6
  #define OSC_DIV_ERPS_WIDTH                       2
  #define OSC_DIV_ERPS(x)                          (((uint8_t)(((uint8_t)(x))<<OSC_DIV_ERPS_SHIFT))&OSC_DIV_ERPS_MASK)
  
  /*!
   * @}
   */ /* end of group OSC_Register_Masks */
  
  
  /* OSC - Peripheral instance base addresses */
  /** Peripheral OSC base address */
  #define OSC_BASE                                 (0x40065000u)
  /** Peripheral OSC base pointer */
  #define OSC                                      ((OSC_Type *)OSC_BASE)
  #define OSC_BASE_PTR                             (OSC)
  /** Array initializer of OSC peripheral base addresses */
  #define OSC_BASE_ADDRS                           { OSC_BASE }
  /** Array initializer of OSC peripheral base pointers */
  #define OSC_BASE_PTRS                            { OSC }
  
  /* ----------------------------------------------------------------------------
     -- OSC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
   * @{
   */
  
  
  /* OSC - Register instance definitions */
  /* OSC */
  #define OSC_CR                                   OSC_CR_REG(OSC)
  #define OSC_DIV                                  OSC_DIV_REG(OSC)
  
  /*!
   * @}
   */ /* end of group OSC_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group OSC_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- PDB Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
   * @{
   */
  
  /** PDB - Register Layout Typedef */
  typedef struct {
    __IO uint32_t SC;                                /**< Status and Control register, offset: 0x0 */
    __IO uint32_t MOD;                               /**< Modulus register, offset: 0x4 */
    __I  uint32_t CNT;                               /**< Counter register, offset: 0x8 */
    __IO uint32_t IDLY;                              /**< Interrupt Delay register, offset: 0xC */
    struct {                                         /* offset: 0x10, array step: 0x10 */
      __IO uint32_t C1;                                /**< Channel n Control register 1, array offset: 0x10, array step: 0x10 */
      __IO uint32_t S;                                 /**< Channel n Status register, array offset: 0x14, array step: 0x10 */
      __IO uint32_t DLY[2];                            /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x10, index2*0x4 */
    } CH[1];
         uint8_t RESERVED_0[304];
    struct {                                         /* offset: 0x150, array step: 0x8 */
      __IO uint32_t INTC;                              /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
      __IO uint32_t INT;                               /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
    } DAC[1];
         uint8_t RESERVED_1[56];
    __IO uint32_t POEN;                              /**< Pulse-Out n Enable register, offset: 0x190 */
    __IO uint32_t PODLY[1];                          /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
  } PDB_Type, *PDB_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- PDB - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
   * @{
   */
  
  
  /* PDB - Register accessors */
  #define PDB_SC_REG(base)                         ((base)->SC)
  #define PDB_MOD_REG(base)                        ((base)->MOD)
  #define PDB_CNT_REG(base)                        ((base)->CNT)
  #define PDB_IDLY_REG(base)                       ((base)->IDLY)
  #define PDB_C1_REG(base,index)                   ((base)->CH[index].C1)
  #define PDB_C1_COUNT                             1
  #define PDB_S_REG(base,index)                    ((base)->CH[index].S)
  #define PDB_S_COUNT                              1
  #define PDB_DLY_REG(base,index,index2)           ((base)->CH[index].DLY[index2])
  #define PDB_DLY_COUNT                            1
  #define PDB_DLY_COUNT2                           2
  #define PDB_INTC_REG(base,index)                 ((base)->DAC[index].INTC)
  #define PDB_INTC_COUNT                           1
  #define PDB_INT_REG(base,index)                  ((base)->DAC[index].INT)
  #define PDB_INT_COUNT                            1
  #define PDB_POEN_REG(base)                       ((base)->POEN)
  #define PDB_PODLY_REG(base,index)                ((base)->PODLY[index])
  #define PDB_PODLY_COUNT                          1
  
  /*!
   * @}
   */ /* end of group PDB_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- PDB Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PDB_Register_Masks PDB Register Masks
   * @{
   */
  
  /* SC Bit Fields */
  #define PDB_SC_LDOK_MASK                         0x1u
  #define PDB_SC_LDOK_SHIFT                        0
  #define PDB_SC_LDOK_WIDTH                        1
  #define PDB_SC_LDOK(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDOK_SHIFT))&PDB_SC_LDOK_MASK)
  #define PDB_SC_CONT_MASK                         0x2u
  #define PDB_SC_CONT_SHIFT                        1
  #define PDB_SC_CONT_WIDTH                        1
  #define PDB_SC_CONT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_CONT_SHIFT))&PDB_SC_CONT_MASK)
  #define PDB_SC_MULT_MASK                         0xCu
  #define PDB_SC_MULT_SHIFT                        2
  #define PDB_SC_MULT_WIDTH                        2
  #define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
  #define PDB_SC_PDBIE_MASK                        0x20u
  #define PDB_SC_PDBIE_SHIFT                       5
  #define PDB_SC_PDBIE_WIDTH                       1
  #define PDB_SC_PDBIE(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIE_SHIFT))&PDB_SC_PDBIE_MASK)
  #define PDB_SC_PDBIF_MASK                        0x40u
  #define PDB_SC_PDBIF_SHIFT                       6
  #define PDB_SC_PDBIF_WIDTH                       1
  #define PDB_SC_PDBIF(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIF_SHIFT))&PDB_SC_PDBIF_MASK)
  #define PDB_SC_PDBEN_MASK                        0x80u
  #define PDB_SC_PDBEN_SHIFT                       7
  #define PDB_SC_PDBEN_WIDTH                       1
  #define PDB_SC_PDBEN(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEN_SHIFT))&PDB_SC_PDBEN_MASK)
  #define PDB_SC_TRGSEL_MASK                       0xF00u
  #define PDB_SC_TRGSEL_SHIFT                      8
  #define PDB_SC_TRGSEL_WIDTH                      4
  #define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
  #define PDB_SC_PRESCALER_MASK                    0x7000u
  #define PDB_SC_PRESCALER_SHIFT                   12
  #define PDB_SC_PRESCALER_WIDTH                   3
  #define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
  #define PDB_SC_DMAEN_MASK                        0x8000u
  #define PDB_SC_DMAEN_SHIFT                       15
  #define PDB_SC_DMAEN_WIDTH                       1
  #define PDB_SC_DMAEN(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_DMAEN_SHIFT))&PDB_SC_DMAEN_MASK)
  #define PDB_SC_SWTRIG_MASK                       0x10000u
  #define PDB_SC_SWTRIG_SHIFT                      16
  #define PDB_SC_SWTRIG_WIDTH                      1
  #define PDB_SC_SWTRIG(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_SWTRIG_SHIFT))&PDB_SC_SWTRIG_MASK)
  #define PDB_SC_PDBEIE_MASK                       0x20000u
  #define PDB_SC_PDBEIE_SHIFT                      17
  #define PDB_SC_PDBEIE_WIDTH                      1
  #define PDB_SC_PDBEIE(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEIE_SHIFT))&PDB_SC_PDBEIE_MASK)
  #define PDB_SC_LDMOD_MASK                        0xC0000u
  #define PDB_SC_LDMOD_SHIFT                       18
  #define PDB_SC_LDMOD_WIDTH                       2
  #define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
  /* MOD Bit Fields */
  #define PDB_MOD_MOD_MASK                         0xFFFFu
  #define PDB_MOD_MOD_SHIFT                        0
  #define PDB_MOD_MOD_WIDTH                        16
  #define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
  /* CNT Bit Fields */
  #define PDB_CNT_CNT_MASK                         0xFFFFu
  #define PDB_CNT_CNT_SHIFT                        0
  #define PDB_CNT_CNT_WIDTH                        16
  #define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
  /* IDLY Bit Fields */
  #define PDB_IDLY_IDLY_MASK                       0xFFFFu
  #define PDB_IDLY_IDLY_SHIFT                      0
  #define PDB_IDLY_IDLY_WIDTH                      16
  #define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
  /* C1 Bit Fields */
  #define PDB_C1_EN_MASK                           0xFFu
  #define PDB_C1_EN_SHIFT                          0
  #define PDB_C1_EN_WIDTH                          8
  #define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
  #define PDB_C1_TOS_MASK                          0xFF00u
  #define PDB_C1_TOS_SHIFT                         8
  #define PDB_C1_TOS_WIDTH                         8
  #define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
  #define PDB_C1_BB_MASK                           0xFF0000u
  #define PDB_C1_BB_SHIFT                          16
  #define PDB_C1_BB_WIDTH                          8
  #define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
  /* S Bit Fields */
  #define PDB_S_ERR_MASK                           0xFFu
  #define PDB_S_ERR_SHIFT                          0
  #define PDB_S_ERR_WIDTH                          8
  #define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
  #define PDB_S_CF_MASK                            0xFF0000u
  #define PDB_S_CF_SHIFT                           16
  #define PDB_S_CF_WIDTH                           8
  #define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
  /* DLY Bit Fields */
  #define PDB_DLY_DLY_MASK                         0xFFFFu
  #define PDB_DLY_DLY_SHIFT                        0
  #define PDB_DLY_DLY_WIDTH                        16
  #define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
  /* INTC Bit Fields */
  #define PDB_INTC_TOE_MASK                        0x1u
  #define PDB_INTC_TOE_SHIFT                       0
  #define PDB_INTC_TOE_WIDTH                       1
  #define PDB_INTC_TOE(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_INTC_TOE_SHIFT))&PDB_INTC_TOE_MASK)
  #define PDB_INTC_EXT_MASK                        0x2u
  #define PDB_INTC_EXT_SHIFT                       1
  #define PDB_INTC_EXT_WIDTH                       1
  #define PDB_INTC_EXT(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_INTC_EXT_SHIFT))&PDB_INTC_EXT_MASK)
  /* INT Bit Fields */
  #define PDB_INT_INT_MASK                         0xFFFFu
  #define PDB_INT_INT_SHIFT                        0
  #define PDB_INT_INT_WIDTH                        16
  #define PDB_INT_INT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
  /* POEN Bit Fields */
  #define PDB_POEN_POEN_MASK                       0xFFu
  #define PDB_POEN_POEN_SHIFT                      0
  #define PDB_POEN_POEN_WIDTH                      8
  #define PDB_POEN_POEN(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
  /* PODLY Bit Fields */
  #define PDB_PODLY_DLY2_MASK                      0xFFFFu
  #define PDB_PODLY_DLY2_SHIFT                     0
  #define PDB_PODLY_DLY2_WIDTH                     16
  #define PDB_PODLY_DLY2(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
  #define PDB_PODLY_DLY1_MASK                      0xFFFF0000u
  #define PDB_PODLY_DLY1_SHIFT                     16
  #define PDB_PODLY_DLY1_WIDTH                     16
  #define PDB_PODLY_DLY1(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
  
  /*!
   * @}
   */ /* end of group PDB_Register_Masks */
  
  
  /* PDB - Peripheral instance base addresses */
  /** Peripheral PDB0 base address */
  #define PDB0_BASE                                (0x40036000u)
  /** Peripheral PDB0 base pointer */
  #define PDB0                                     ((PDB_Type *)PDB0_BASE)
  #define PDB0_BASE_PTR                            (PDB0)
  /** Array initializer of PDB peripheral base addresses */
  #define PDB_BASE_ADDRS                           { PDB0_BASE }
  /** Array initializer of PDB peripheral base pointers */
  #define PDB_BASE_PTRS                            { PDB0 }
  
  /* ----------------------------------------------------------------------------
     -- PDB - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
   * @{
   */
  
  
  /* PDB - Register instance definitions */
  /* PDB0 */
  #define PDB0_SC                                  PDB_SC_REG(PDB0)
  #define PDB0_MOD                                 PDB_MOD_REG(PDB0)
  #define PDB0_CNT                                 PDB_CNT_REG(PDB0)
  #define PDB0_IDLY                                PDB_IDLY_REG(PDB0)
  #define PDB0_CH0C1                               PDB_C1_REG(PDB0,0)
  #define PDB0_CH0S                                PDB_S_REG(PDB0,0)
  #define PDB0_CH0DLY0                             PDB_DLY_REG(PDB0,0,0)
  #define PDB0_CH0DLY1                             PDB_DLY_REG(PDB0,0,1)
  #define PDB0_DACINTC0                            PDB_INTC_REG(PDB0,0)
  #define PDB0_DACINT0                             PDB_INT_REG(PDB0,0)
  #define PDB0_POEN                                PDB_POEN_REG(PDB0)
  #define PDB0_PO0DLY                              PDB_PODLY_REG(PDB0,0)
  
  /* PDB - Register array accessors */
  #define PDB0_C1(index)                           PDB_C1_REG(PDB0,index)
  #define PDB0_S(index)                            PDB_S_REG(PDB0,index)
  #define PDB0_DLY(index,index2)                   PDB_DLY_REG(PDB0,index,index2)
  #define PDB0_INTC(index)                         PDB_INTC_REG(PDB0,index)
  #define PDB0_INT(index)                          PDB_INT_REG(PDB0,index)
  #define PDB0_PODLY(index)                        PDB_PODLY_REG(PDB0,index)
  
  /*!
   * @}
   */ /* end of group PDB_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group PDB_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- PIT Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
   * @{
   */
  
  /** PIT - Register Layout Typedef */
  typedef struct {
    __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
         uint8_t RESERVED_0[220];
    __I  uint32_t LTMR64H;                           /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
    __I  uint32_t LTMR64L;                           /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
         uint8_t RESERVED_1[24];
    struct {                                         /* offset: 0x100, array step: 0x10 */
      __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
      __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
      __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
      __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
    } CHANNEL[4];
  } PIT_Type, *PIT_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- PIT - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
   * @{
   */
  
  
  /* PIT - Register accessors */
  #define PIT_MCR_REG(base)                        ((base)->MCR)
  #define PIT_LTMR64H_REG(base)                    ((base)->LTMR64H)
  #define PIT_LTMR64L_REG(base)                    ((base)->LTMR64L)
  #define PIT_LDVAL_REG(base,index)                ((base)->CHANNEL[index].LDVAL)
  #define PIT_LDVAL_COUNT                          4
  #define PIT_CVAL_REG(base,index)                 ((base)->CHANNEL[index].CVAL)
  #define PIT_CVAL_COUNT                           4
  #define PIT_TCTRL_REG(base,index)                ((base)->CHANNEL[index].TCTRL)
  #define PIT_TCTRL_COUNT                          4
  #define PIT_TFLG_REG(base,index)                 ((base)->CHANNEL[index].TFLG)
  #define PIT_TFLG_COUNT                           4
  
  /*!
   * @}
   */ /* end of group PIT_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- PIT Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PIT_Register_Masks PIT Register Masks
   * @{
   */
  
  /* MCR Bit Fields */
  #define PIT_MCR_FRZ_MASK                         0x1u
  #define PIT_MCR_FRZ_SHIFT                        0
  #define PIT_MCR_FRZ_WIDTH                        1
  #define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<PIT_MCR_FRZ_SHIFT))&PIT_MCR_FRZ_MASK)
  #define PIT_MCR_MDIS_MASK                        0x2u
  #define PIT_MCR_MDIS_SHIFT                       1
  #define PIT_MCR_MDIS_WIDTH                       1
  #define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_MCR_MDIS_SHIFT))&PIT_MCR_MDIS_MASK)
  /* LTMR64H Bit Fields */
  #define PIT_LTMR64H_LTH_MASK                     0xFFFFFFFFu
  #define PIT_LTMR64H_LTH_SHIFT                    0
  #define PIT_LTMR64H_LTH_WIDTH                    32
  #define PIT_LTMR64H_LTH(x)                       (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
  /* LTMR64L Bit Fields */
  #define PIT_LTMR64L_LTL_MASK                     0xFFFFFFFFu
  #define PIT_LTMR64L_LTL_SHIFT                    0
  #define PIT_LTMR64L_LTL_WIDTH                    32
  #define PIT_LTMR64L_LTL(x)                       (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
  /* LDVAL Bit Fields */
  #define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
  #define PIT_LDVAL_TSV_SHIFT                      0
  #define PIT_LDVAL_TSV_WIDTH                      32
  #define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
  /* CVAL Bit Fields */
  #define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
  #define PIT_CVAL_TVL_SHIFT                       0
  #define PIT_CVAL_TVL_WIDTH                       32
  #define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
  /* TCTRL Bit Fields */
  #define PIT_TCTRL_TEN_MASK                       0x1u
  #define PIT_TCTRL_TEN_SHIFT                      0
  #define PIT_TCTRL_TEN_WIDTH                      1
  #define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
  #define PIT_TCTRL_TIE_MASK                       0x2u
  #define PIT_TCTRL_TIE_SHIFT                      1
  #define PIT_TCTRL_TIE_WIDTH                      1
  #define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TIE_SHIFT))&PIT_TCTRL_TIE_MASK)
  #define PIT_TCTRL_CHN_MASK                       0x4u
  #define PIT_TCTRL_CHN_SHIFT                      2
  #define PIT_TCTRL_CHN_WIDTH                      1
  #define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
  /* TFLG Bit Fields */
  #define PIT_TFLG_TIF_MASK                        0x1u
  #define PIT_TFLG_TIF_SHIFT                       0
  #define PIT_TFLG_TIF_WIDTH                       1
  #define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_TFLG_TIF_SHIFT))&PIT_TFLG_TIF_MASK)
  
  /*!
   * @}
   */ /* end of group PIT_Register_Masks */
  
  
  /* PIT - Peripheral instance base addresses */
  /** Peripheral PIT base address */
  #define PIT_BASE                                 (0x40037000u)
  /** Peripheral PIT base pointer */
  #define PIT                                      ((PIT_Type *)PIT_BASE)
  #define PIT_BASE_PTR                             (PIT)
  /** Array initializer of PIT peripheral base addresses */
  #define PIT_BASE_ADDRS                           { PIT_BASE }
  /** Array initializer of PIT peripheral base pointers */
  #define PIT_BASE_PTRS                            { PIT }
  
  /* ----------------------------------------------------------------------------
     -- PIT - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
   * @{
   */
  
  
  /* PIT - Register instance definitions */
  /* PIT */
  #define PIT_MCR                                  PIT_MCR_REG(PIT)
  #define PIT_LTMR64H                              PIT_LTMR64H_REG(PIT)
  #define PIT_LTMR64L                              PIT_LTMR64L_REG(PIT)
  #define PIT_LDVAL0                               PIT_LDVAL_REG(PIT,0)
  #define PIT_CVAL0                                PIT_CVAL_REG(PIT,0)
  #define PIT_TCTRL0                               PIT_TCTRL_REG(PIT,0)
  #define PIT_TFLG0                                PIT_TFLG_REG(PIT,0)
  #define PIT_LDVAL1                               PIT_LDVAL_REG(PIT,1)
  #define PIT_CVAL1                                PIT_CVAL_REG(PIT,1)
  #define PIT_TCTRL1                               PIT_TCTRL_REG(PIT,1)
  #define PIT_TFLG1                                PIT_TFLG_REG(PIT,1)
  #define PIT_LDVAL2                               PIT_LDVAL_REG(PIT,2)
  #define PIT_CVAL2                                PIT_CVAL_REG(PIT,2)
  #define PIT_TCTRL2                               PIT_TCTRL_REG(PIT,2)
  #define PIT_TFLG2                                PIT_TFLG_REG(PIT,2)
  #define PIT_LDVAL3                               PIT_LDVAL_REG(PIT,3)
  #define PIT_CVAL3                                PIT_CVAL_REG(PIT,3)
  #define PIT_TCTRL3                               PIT_TCTRL_REG(PIT,3)
  #define PIT_TFLG3                                PIT_TFLG_REG(PIT,3)
  
  /* PIT - Register array accessors */
  #define PIT_LDVAL(index)                         PIT_LDVAL_REG(PIT,index)
  #define PIT_CVAL(index)                          PIT_CVAL_REG(PIT,index)
  #define PIT_TCTRL(index)                         PIT_TCTRL_REG(PIT,index)
  #define PIT_TFLG(index)                          PIT_TFLG_REG(PIT,index)
  
  /*!
   * @}
   */ /* end of group PIT_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group PIT_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- PMC Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
   * @{
   */
  
  /** PMC - Register Layout Typedef */
  typedef struct {
    __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
    __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
    __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
         uint8_t RESERVED_0[8];
    __IO uint8_t HVDSC1;                             /**< High Voltage Detect Status And Control 1 register, offset: 0xB */
  } PMC_Type, *PMC_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- PMC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
   * @{
   */
  
  
  /* PMC - Register accessors */
  #define PMC_LVDSC1_REG(base)                     ((base)->LVDSC1)
  #define PMC_LVDSC2_REG(base)                     ((base)->LVDSC2)
  #define PMC_REGSC_REG(base)                      ((base)->REGSC)
  #define PMC_HVDSC1_REG(base)                     ((base)->HVDSC1)
  
  /*!
   * @}
   */ /* end of group PMC_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- PMC Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PMC_Register_Masks PMC Register Masks
   * @{
   */
  
  /* LVDSC1 Bit Fields */
  #define PMC_LVDSC1_LVDV_MASK                     0x3u
  #define PMC_LVDSC1_LVDV_SHIFT                    0
  #define PMC_LVDSC1_LVDV_WIDTH                    2
  #define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
  #define PMC_LVDSC1_LVDRE_MASK                    0x10u
  #define PMC_LVDSC1_LVDRE_SHIFT                   4
  #define PMC_LVDSC1_LVDRE_WIDTH                   1
  #define PMC_LVDSC1_LVDRE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
  #define PMC_LVDSC1_LVDIE_MASK                    0x20u
  #define PMC_LVDSC1_LVDIE_SHIFT                   5
  #define PMC_LVDSC1_LVDIE_WIDTH                   1
  #define PMC_LVDSC1_LVDIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
  #define PMC_LVDSC1_LVDACK_MASK                   0x40u
  #define PMC_LVDSC1_LVDACK_SHIFT                  6
  #define PMC_LVDSC1_LVDACK_WIDTH                  1
  #define PMC_LVDSC1_LVDACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
  #define PMC_LVDSC1_LVDF_MASK                     0x80u
  #define PMC_LVDSC1_LVDF_SHIFT                    7
  #define PMC_LVDSC1_LVDF_WIDTH                    1
  #define PMC_LVDSC1_LVDF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
  /* LVDSC2 Bit Fields */
  #define PMC_LVDSC2_LVWV_MASK                     0x3u
  #define PMC_LVDSC2_LVWV_SHIFT                    0
  #define PMC_LVDSC2_LVWV_WIDTH                    2
  #define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
  #define PMC_LVDSC2_LVWIE_MASK                    0x20u
  #define PMC_LVDSC2_LVWIE_SHIFT                   5
  #define PMC_LVDSC2_LVWIE_WIDTH                   1
  #define PMC_LVDSC2_LVWIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
  #define PMC_LVDSC2_LVWACK_MASK                   0x40u
  #define PMC_LVDSC2_LVWACK_SHIFT                  6
  #define PMC_LVDSC2_LVWACK_WIDTH                  1
  #define PMC_LVDSC2_LVWACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
  #define PMC_LVDSC2_LVWF_MASK                     0x80u
  #define PMC_LVDSC2_LVWF_SHIFT                    7
  #define PMC_LVDSC2_LVWF_WIDTH                    1
  #define PMC_LVDSC2_LVWF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
  /* REGSC Bit Fields */
  #define PMC_REGSC_BGBE_MASK                      0x1u
  #define PMC_REGSC_BGBE_SHIFT                     0
  #define PMC_REGSC_BGBE_WIDTH                     1
  #define PMC_REGSC_BGBE(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGBE_SHIFT))&PMC_REGSC_BGBE_MASK)
  #define PMC_REGSC_REGONS_MASK                    0x4u
  #define PMC_REGSC_REGONS_SHIFT                   2
  #define PMC_REGSC_REGONS_WIDTH                   1
  #define PMC_REGSC_REGONS(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGONS_SHIFT))&PMC_REGSC_REGONS_MASK)
  #define PMC_REGSC_ACKISO_MASK                    0x8u
  #define PMC_REGSC_ACKISO_SHIFT                   3
  #define PMC_REGSC_ACKISO_WIDTH                   1
  #define PMC_REGSC_ACKISO(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_ACKISO_SHIFT))&PMC_REGSC_ACKISO_MASK)
  #define PMC_REGSC_BGEN_MASK                      0x10u
  #define PMC_REGSC_BGEN_SHIFT                     4
  #define PMC_REGSC_BGEN_WIDTH                     1
  #define PMC_REGSC_BGEN(x)                        (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BGEN_SHIFT))&PMC_REGSC_BGEN_MASK)
  /* HVDSC1 Bit Fields */
  #define PMC_HVDSC1_HVDV_MASK                     0x1u
  #define PMC_HVDSC1_HVDV_SHIFT                    0
  #define PMC_HVDSC1_HVDV_WIDTH                    1
  #define PMC_HVDSC1_HVDV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_HVDSC1_HVDV_SHIFT))&PMC_HVDSC1_HVDV_MASK)
  #define PMC_HVDSC1_HVDRE_MASK                    0x10u
  #define PMC_HVDSC1_HVDRE_SHIFT                   4
  #define PMC_HVDSC1_HVDRE_WIDTH                   1
  #define PMC_HVDSC1_HVDRE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_HVDSC1_HVDRE_SHIFT))&PMC_HVDSC1_HVDRE_MASK)
  #define PMC_HVDSC1_HVDIE_MASK                    0x20u
  #define PMC_HVDSC1_HVDIE_SHIFT                   5
  #define PMC_HVDSC1_HVDIE_WIDTH                   1
  #define PMC_HVDSC1_HVDIE(x)                      (((uint8_t)(((uint8_t)(x))<<PMC_HVDSC1_HVDIE_SHIFT))&PMC_HVDSC1_HVDIE_MASK)
  #define PMC_HVDSC1_HVDACK_MASK                   0x40u
  #define PMC_HVDSC1_HVDACK_SHIFT                  6
  #define PMC_HVDSC1_HVDACK_WIDTH                  1
  #define PMC_HVDSC1_HVDACK(x)                     (((uint8_t)(((uint8_t)(x))<<PMC_HVDSC1_HVDACK_SHIFT))&PMC_HVDSC1_HVDACK_MASK)
  #define PMC_HVDSC1_HVDF_MASK                     0x80u
  #define PMC_HVDSC1_HVDF_SHIFT                    7
  #define PMC_HVDSC1_HVDF_WIDTH                    1
  #define PMC_HVDSC1_HVDF(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_HVDSC1_HVDF_SHIFT))&PMC_HVDSC1_HVDF_MASK)
  
  /*!
   * @}
   */ /* end of group PMC_Register_Masks */
  
  
  /* PMC - Peripheral instance base addresses */
  /** Peripheral PMC base address */
  #define PMC_BASE                                 (0x4007D000u)
  /** Peripheral PMC base pointer */
  #define PMC                                      ((PMC_Type *)PMC_BASE)
  #define PMC_BASE_PTR                             (PMC)
  /** Array initializer of PMC peripheral base addresses */
  #define PMC_BASE_ADDRS                           { PMC_BASE }
  /** Array initializer of PMC peripheral base pointers */
  #define PMC_BASE_PTRS                            { PMC }
  
  /* ----------------------------------------------------------------------------
     -- PMC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
   * @{
   */
  
  
  /* PMC - Register instance definitions */
  /* PMC */
  #define PMC_LVDSC1                               PMC_LVDSC1_REG(PMC)
  #define PMC_LVDSC2                               PMC_LVDSC2_REG(PMC)
  #define PMC_REGSC                                PMC_REGSC_REG(PMC)
  #define PMC_HVDSC1                               PMC_HVDSC1_REG(PMC)
  
  /*!
   * @}
   */ /* end of group PMC_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group PMC_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- PORT Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
   * @{
   */
  
  /** PORT - Register Layout Typedef */
  typedef struct {
    __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
    __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
    __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
    __O  uint32_t GICLR;                             /**< Global Interrupt Control Low Register, offset: 0x88 */
    __O  uint32_t GICHR;                             /**< Global Interrupt Control High Register, offset: 0x8C */
         uint8_t RESERVED_0[16];
    __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
         uint8_t RESERVED_1[28];
    __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
    __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
    __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
  } PORT_Type, *PORT_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- PORT - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
   * @{
   */
  
  
  /* PORT - Register accessors */
  #define PORT_PCR_REG(base,index)                 ((base)->PCR[index])
  #define PORT_PCR_COUNT                           32
  #define PORT_GPCLR_REG(base)                     ((base)->GPCLR)
  #define PORT_GPCHR_REG(base)                     ((base)->GPCHR)
  #define PORT_GICLR_REG(base)                     ((base)->GICLR)
  #define PORT_GICHR_REG(base)                     ((base)->GICHR)
  #define PORT_ISFR_REG(base)                      ((base)->ISFR)
  #define PORT_DFER_REG(base)                      ((base)->DFER)
  #define PORT_DFCR_REG(base)                      ((base)->DFCR)
  #define PORT_DFWR_REG(base)                      ((base)->DFWR)
  
  /*!
   * @}
   */ /* end of group PORT_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- PORT Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PORT_Register_Masks PORT Register Masks
   * @{
   */
  
  /* PCR Bit Fields */
  #define PORT_PCR_PS_MASK                         0x1u
  #define PORT_PCR_PS_SHIFT                        0
  #define PORT_PCR_PS_WIDTH                        1
  #define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
  #define PORT_PCR_PE_MASK                         0x2u
  #define PORT_PCR_PE_SHIFT                        1
  #define PORT_PCR_PE_WIDTH                        1
  #define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
  #define PORT_PCR_SRE_MASK                        0x4u
  #define PORT_PCR_SRE_SHIFT                       2
  #define PORT_PCR_SRE_WIDTH                       1
  #define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_SRE_SHIFT))&PORT_PCR_SRE_MASK)
  #define PORT_PCR_PFE_MASK                        0x10u
  #define PORT_PCR_PFE_SHIFT                       4
  #define PORT_PCR_PFE_WIDTH                       1
  #define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
  #define PORT_PCR_ODE_MASK                        0x20u
  #define PORT_PCR_ODE_SHIFT                       5
  #define PORT_PCR_ODE_WIDTH                       1
  #define PORT_PCR_ODE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ODE_SHIFT))&PORT_PCR_ODE_MASK)
  #define PORT_PCR_DSE_MASK                        0x40u
  #define PORT_PCR_DSE_SHIFT                       6
  #define PORT_PCR_DSE_WIDTH                       1
  #define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
  #define PORT_PCR_MUX_MASK                        0xF00u
  #define PORT_PCR_MUX_SHIFT                       8
  #define PORT_PCR_MUX_WIDTH                       4
  #define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
  #define PORT_PCR_LK_MASK                         0x8000u
  #define PORT_PCR_LK_SHIFT                        15
  #define PORT_PCR_LK_WIDTH                        1
  #define PORT_PCR_LK(x)                           (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
  #define PORT_PCR_IRQC_MASK                       0xF0000u
  #define PORT_PCR_IRQC_SHIFT                      16
  #define PORT_PCR_IRQC_WIDTH                      4
  #define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
  #define PORT_PCR_ISF_MASK                        0x1000000u
  #define PORT_PCR_ISF_SHIFT                       24
  #define PORT_PCR_ISF_WIDTH                       1
  #define PORT_PCR_ISF(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
  /* GPCLR Bit Fields */
  #define PORT_GPCLR_GPWD_MASK                     0xFFFFu
  #define PORT_GPCLR_GPWD_SHIFT                    0
  #define PORT_GPCLR_GPWD_WIDTH                    16
  #define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
  #define PORT_GPCLR_GPWE_MASK                     0xFFFF0000u
  #define PORT_GPCLR_GPWE_SHIFT                    16
  #define PORT_GPCLR_GPWE_WIDTH                    16
  #define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
  /* GPCHR Bit Fields */
  #define PORT_GPCHR_GPWD_MASK                     0xFFFFu
  #define PORT_GPCHR_GPWD_SHIFT                    0
  #define PORT_GPCHR_GPWD_WIDTH                    16
  #define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
  #define PORT_GPCHR_GPWE_MASK                     0xFFFF0000u
  #define PORT_GPCHR_GPWE_SHIFT                    16
  #define PORT_GPCHR_GPWE_WIDTH                    16
  #define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
  /* GICLR Bit Fields */
  #define PORT_GICLR_GIWE_MASK                     0xFFFFu
  #define PORT_GICLR_GIWE_SHIFT                    0
  #define PORT_GICLR_GIWE_WIDTH                    16
  #define PORT_GICLR_GIWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GICLR_GIWE_SHIFT))&PORT_GICLR_GIWE_MASK)
  #define PORT_GICLR_GIWD_MASK                     0xFFFF0000u
  #define PORT_GICLR_GIWD_SHIFT                    16
  #define PORT_GICLR_GIWD_WIDTH                    16
  #define PORT_GICLR_GIWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GICLR_GIWD_SHIFT))&PORT_GICLR_GIWD_MASK)
  /* GICHR Bit Fields */
  #define PORT_GICHR_GIWE_MASK                     0xFFFFu
  #define PORT_GICHR_GIWE_SHIFT                    0
  #define PORT_GICHR_GIWE_WIDTH                    16
  #define PORT_GICHR_GIWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GICHR_GIWE_SHIFT))&PORT_GICHR_GIWE_MASK)
  #define PORT_GICHR_GIWD_MASK                     0xFFFF0000u
  #define PORT_GICHR_GIWD_SHIFT                    16
  #define PORT_GICHR_GIWD_WIDTH                    16
  #define PORT_GICHR_GIWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GICHR_GIWD_SHIFT))&PORT_GICHR_GIWD_MASK)
  /* ISFR Bit Fields */
  #define PORT_ISFR_ISF_MASK                       0xFFFFFFFFu
  #define PORT_ISFR_ISF_SHIFT                      0
  #define PORT_ISFR_ISF_WIDTH                      32
  #define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
  /* DFER Bit Fields */
  #define PORT_DFER_DFE_MASK                       0xFFFFFFFFu
  #define PORT_DFER_DFE_SHIFT                      0
  #define PORT_DFER_DFE_WIDTH                      32
  #define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
  /* DFCR Bit Fields */
  #define PORT_DFCR_CS_MASK                        0x1u
  #define PORT_DFCR_CS_SHIFT                       0
  #define PORT_DFCR_CS_WIDTH                       1
  #define PORT_DFCR_CS(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
  /* DFWR Bit Fields */
  #define PORT_DFWR_FILT_MASK                      0x1Fu
  #define PORT_DFWR_FILT_SHIFT                     0
  #define PORT_DFWR_FILT_WIDTH                     5
  #define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
  
  /*!
   * @}
   */ /* end of group PORT_Register_Masks */
  
  
  /* PORT - Peripheral instance base addresses */
  /** Peripheral PORTA base address */
  #define PORTA_BASE                               (0x40049000u)
  /** Peripheral PORTA base pointer */
  #define PORTA                                    ((PORT_Type *)PORTA_BASE)
  #define PORTA_BASE_PTR                           (PORTA)
  /** Peripheral PORTB base address */
  #define PORTB_BASE                               (0x4004A000u)
  /** Peripheral PORTB base pointer */
  #define PORTB                                    ((PORT_Type *)PORTB_BASE)
  #define PORTB_BASE_PTR                           (PORTB)
  /** Peripheral PORTC base address */
  #define PORTC_BASE                               (0x4004B000u)
  /** Peripheral PORTC base pointer */
  #define PORTC                                    ((PORT_Type *)PORTC_BASE)
  #define PORTC_BASE_PTR                           (PORTC)
  /** Peripheral PORTD base address */
  #define PORTD_BASE                               (0x4004C000u)
  /** Peripheral PORTD base pointer */
  #define PORTD                                    ((PORT_Type *)PORTD_BASE)
  #define PORTD_BASE_PTR                           (PORTD)
  /** Peripheral PORTE base address */
  #define PORTE_BASE                               (0x4004D000u)
  /** Peripheral PORTE base pointer */
  #define PORTE                                    ((PORT_Type *)PORTE_BASE)
  #define PORTE_BASE_PTR                           (PORTE)
  /** Array initializer of PORT peripheral base addresses */
  #define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
  /** Array initializer of PORT peripheral base pointers */
  #define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD, PORTE }
  
  /* ----------------------------------------------------------------------------
     -- PORT - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
   * @{
   */
  
  
  /* PORT - Register instance definitions */
  /* PORTA */
  #define PORTA_PCR0                               PORT_PCR_REG(PORTA,0)
  #define PORTA_PCR1                               PORT_PCR_REG(PORTA,1)
  #define PORTA_PCR2                               PORT_PCR_REG(PORTA,2)
  #define PORTA_PCR3                               PORT_PCR_REG(PORTA,3)
  #define PORTA_PCR4                               PORT_PCR_REG(PORTA,4)
  #define PORTA_PCR5                               PORT_PCR_REG(PORTA,5)
  #define PORTA_PCR6                               PORT_PCR_REG(PORTA,6)
  #define PORTA_PCR7                               PORT_PCR_REG(PORTA,7)
  #define PORTA_PCR8                               PORT_PCR_REG(PORTA,8)
  #define PORTA_PCR9                               PORT_PCR_REG(PORTA,9)
  #define PORTA_PCR10                              PORT_PCR_REG(PORTA,10)
  #define PORTA_PCR11                              PORT_PCR_REG(PORTA,11)
  #define PORTA_PCR12                              PORT_PCR_REG(PORTA,12)
  #define PORTA_PCR13                              PORT_PCR_REG(PORTA,13)
  #define PORTA_PCR14                              PORT_PCR_REG(PORTA,14)
  #define PORTA_PCR15                              PORT_PCR_REG(PORTA,15)
  #define PORTA_PCR16                              PORT_PCR_REG(PORTA,16)
  #define PORTA_PCR17                              PORT_PCR_REG(PORTA,17)
  #define PORTA_PCR18                              PORT_PCR_REG(PORTA,18)
  #define PORTA_PCR19                              PORT_PCR_REG(PORTA,19)
  #define PORTA_PCR20                              PORT_PCR_REG(PORTA,20)
  #define PORTA_PCR21                              PORT_PCR_REG(PORTA,21)
  #define PORTA_PCR22                              PORT_PCR_REG(PORTA,22)
  #define PORTA_PCR23                              PORT_PCR_REG(PORTA,23)
  #define PORTA_PCR24                              PORT_PCR_REG(PORTA,24)
  #define PORTA_PCR25                              PORT_PCR_REG(PORTA,25)
  #define PORTA_PCR26                              PORT_PCR_REG(PORTA,26)
  #define PORTA_PCR27                              PORT_PCR_REG(PORTA,27)
  #define PORTA_PCR28                              PORT_PCR_REG(PORTA,28)
  #define PORTA_PCR29                              PORT_PCR_REG(PORTA,29)
  #define PORTA_PCR30                              PORT_PCR_REG(PORTA,30)
  #define PORTA_PCR31                              PORT_PCR_REG(PORTA,31)
  #define PORTA_GPCLR                              PORT_GPCLR_REG(PORTA)
  #define PORTA_GPCHR                              PORT_GPCHR_REG(PORTA)
  #define PORTA_GICLR                              PORT_GICLR_REG(PORTA)
  #define PORTA_GICHR                              PORT_GICHR_REG(PORTA)
  #define PORTA_ISFR                               PORT_ISFR_REG(PORTA)
  /* PORTB */
  #define PORTB_PCR0                               PORT_PCR_REG(PORTB,0)
  #define PORTB_PCR1                               PORT_PCR_REG(PORTB,1)
  #define PORTB_PCR2                               PORT_PCR_REG(PORTB,2)
  #define PORTB_PCR3                               PORT_PCR_REG(PORTB,3)
  #define PORTB_PCR4                               PORT_PCR_REG(PORTB,4)
  #define PORTB_PCR5                               PORT_PCR_REG(PORTB,5)
  #define PORTB_PCR6                               PORT_PCR_REG(PORTB,6)
  #define PORTB_PCR7                               PORT_PCR_REG(PORTB,7)
  #define PORTB_PCR8                               PORT_PCR_REG(PORTB,8)
  #define PORTB_PCR9                               PORT_PCR_REG(PORTB,9)
  #define PORTB_PCR10                              PORT_PCR_REG(PORTB,10)
  #define PORTB_PCR11                              PORT_PCR_REG(PORTB,11)
  #define PORTB_PCR12                              PORT_PCR_REG(PORTB,12)
  #define PORTB_PCR13                              PORT_PCR_REG(PORTB,13)
  #define PORTB_PCR14                              PORT_PCR_REG(PORTB,14)
  #define PORTB_PCR15                              PORT_PCR_REG(PORTB,15)
  #define PORTB_PCR16                              PORT_PCR_REG(PORTB,16)
  #define PORTB_PCR17                              PORT_PCR_REG(PORTB,17)
  #define PORTB_PCR18                              PORT_PCR_REG(PORTB,18)
  #define PORTB_PCR19                              PORT_PCR_REG(PORTB,19)
  #define PORTB_PCR20                              PORT_PCR_REG(PORTB,20)
  #define PORTB_PCR21                              PORT_PCR_REG(PORTB,21)
  #define PORTB_PCR22                              PORT_PCR_REG(PORTB,22)
  #define PORTB_PCR23                              PORT_PCR_REG(PORTB,23)
  #define PORTB_PCR24                              PORT_PCR_REG(PORTB,24)
  #define PORTB_PCR25                              PORT_PCR_REG(PORTB,25)
  #define PORTB_PCR26                              PORT_PCR_REG(PORTB,26)
  #define PORTB_PCR27                              PORT_PCR_REG(PORTB,27)
  #define PORTB_PCR28                              PORT_PCR_REG(PORTB,28)
  #define PORTB_PCR29                              PORT_PCR_REG(PORTB,29)
  #define PORTB_PCR30                              PORT_PCR_REG(PORTB,30)
  #define PORTB_PCR31                              PORT_PCR_REG(PORTB,31)
  #define PORTB_GPCLR                              PORT_GPCLR_REG(PORTB)
  #define PORTB_GPCHR                              PORT_GPCHR_REG(PORTB)
  #define PORTB_GICLR                              PORT_GICLR_REG(PORTB)
  #define PORTB_GICHR                              PORT_GICHR_REG(PORTB)
  #define PORTB_ISFR                               PORT_ISFR_REG(PORTB)
  /* PORTC */
  #define PORTC_PCR0                               PORT_PCR_REG(PORTC,0)
  #define PORTC_PCR1                               PORT_PCR_REG(PORTC,1)
  #define PORTC_PCR2                               PORT_PCR_REG(PORTC,2)
  #define PORTC_PCR3                               PORT_PCR_REG(PORTC,3)
  #define PORTC_PCR4                               PORT_PCR_REG(PORTC,4)
  #define PORTC_PCR5                               PORT_PCR_REG(PORTC,5)
  #define PORTC_PCR6                               PORT_PCR_REG(PORTC,6)
  #define PORTC_PCR7                               PORT_PCR_REG(PORTC,7)
  #define PORTC_PCR8                               PORT_PCR_REG(PORTC,8)
  #define PORTC_PCR9                               PORT_PCR_REG(PORTC,9)
  #define PORTC_PCR10                              PORT_PCR_REG(PORTC,10)
  #define PORTC_PCR11                              PORT_PCR_REG(PORTC,11)
  #define PORTC_PCR12                              PORT_PCR_REG(PORTC,12)
  #define PORTC_PCR13                              PORT_PCR_REG(PORTC,13)
  #define PORTC_PCR14                              PORT_PCR_REG(PORTC,14)
  #define PORTC_PCR15                              PORT_PCR_REG(PORTC,15)
  #define PORTC_PCR16                              PORT_PCR_REG(PORTC,16)
  #define PORTC_PCR17                              PORT_PCR_REG(PORTC,17)
  #define PORTC_PCR18                              PORT_PCR_REG(PORTC,18)
  #define PORTC_PCR19                              PORT_PCR_REG(PORTC,19)
  #define PORTC_PCR20                              PORT_PCR_REG(PORTC,20)
  #define PORTC_PCR21                              PORT_PCR_REG(PORTC,21)
  #define PORTC_PCR22                              PORT_PCR_REG(PORTC,22)
  #define PORTC_PCR23                              PORT_PCR_REG(PORTC,23)
  #define PORTC_PCR24                              PORT_PCR_REG(PORTC,24)
  #define PORTC_PCR25                              PORT_PCR_REG(PORTC,25)
  #define PORTC_PCR26                              PORT_PCR_REG(PORTC,26)
  #define PORTC_PCR27                              PORT_PCR_REG(PORTC,27)
  #define PORTC_PCR28                              PORT_PCR_REG(PORTC,28)
  #define PORTC_PCR29                              PORT_PCR_REG(PORTC,29)
  #define PORTC_PCR30                              PORT_PCR_REG(PORTC,30)
  #define PORTC_PCR31                              PORT_PCR_REG(PORTC,31)
  #define PORTC_GPCLR                              PORT_GPCLR_REG(PORTC)
  #define PORTC_GPCHR                              PORT_GPCHR_REG(PORTC)
  #define PORTC_GICLR                              PORT_GICLR_REG(PORTC)
  #define PORTC_GICHR                              PORT_GICHR_REG(PORTC)
  #define PORTC_ISFR                               PORT_ISFR_REG(PORTC)
  /* PORTD */
  #define PORTD_PCR0                               PORT_PCR_REG(PORTD,0)
  #define PORTD_PCR1                               PORT_PCR_REG(PORTD,1)
  #define PORTD_PCR2                               PORT_PCR_REG(PORTD,2)
  #define PORTD_PCR3                               PORT_PCR_REG(PORTD,3)
  #define PORTD_PCR4                               PORT_PCR_REG(PORTD,4)
  #define PORTD_PCR5                               PORT_PCR_REG(PORTD,5)
  #define PORTD_PCR6                               PORT_PCR_REG(PORTD,6)
  #define PORTD_PCR7                               PORT_PCR_REG(PORTD,7)
  #define PORTD_PCR8                               PORT_PCR_REG(PORTD,8)
  #define PORTD_PCR9                               PORT_PCR_REG(PORTD,9)
  #define PORTD_PCR10                              PORT_PCR_REG(PORTD,10)
  #define PORTD_PCR11                              PORT_PCR_REG(PORTD,11)
  #define PORTD_PCR12                              PORT_PCR_REG(PORTD,12)
  #define PORTD_PCR13                              PORT_PCR_REG(PORTD,13)
  #define PORTD_PCR14                              PORT_PCR_REG(PORTD,14)
  #define PORTD_PCR15                              PORT_PCR_REG(PORTD,15)
  #define PORTD_PCR16                              PORT_PCR_REG(PORTD,16)
  #define PORTD_PCR17                              PORT_PCR_REG(PORTD,17)
  #define PORTD_PCR18                              PORT_PCR_REG(PORTD,18)
  #define PORTD_PCR19                              PORT_PCR_REG(PORTD,19)
  #define PORTD_PCR20                              PORT_PCR_REG(PORTD,20)
  #define PORTD_PCR21                              PORT_PCR_REG(PORTD,21)
  #define PORTD_PCR22                              PORT_PCR_REG(PORTD,22)
  #define PORTD_PCR23                              PORT_PCR_REG(PORTD,23)
  #define PORTD_PCR24                              PORT_PCR_REG(PORTD,24)
  #define PORTD_PCR25                              PORT_PCR_REG(PORTD,25)
  #define PORTD_PCR26                              PORT_PCR_REG(PORTD,26)
  #define PORTD_PCR27                              PORT_PCR_REG(PORTD,27)
  #define PORTD_PCR28                              PORT_PCR_REG(PORTD,28)
  #define PORTD_PCR29                              PORT_PCR_REG(PORTD,29)
  #define PORTD_PCR30                              PORT_PCR_REG(PORTD,30)
  #define PORTD_PCR31                              PORT_PCR_REG(PORTD,31)
  #define PORTD_GPCLR                              PORT_GPCLR_REG(PORTD)
  #define PORTD_GPCHR                              PORT_GPCHR_REG(PORTD)
  #define PORTD_GICLR                              PORT_GICLR_REG(PORTD)
  #define PORTD_GICHR                              PORT_GICHR_REG(PORTD)
  #define PORTD_ISFR                               PORT_ISFR_REG(PORTD)
  #define PORTD_DFER                               PORT_DFER_REG(PORTD)
  #define PORTD_DFCR                               PORT_DFCR_REG(PORTD)
  #define PORTD_DFWR                               PORT_DFWR_REG(PORTD)
  /* PORTE */
  #define PORTE_PCR0                               PORT_PCR_REG(PORTE,0)
  #define PORTE_PCR1                               PORT_PCR_REG(PORTE,1)
  #define PORTE_PCR2                               PORT_PCR_REG(PORTE,2)
  #define PORTE_PCR3                               PORT_PCR_REG(PORTE,3)
  #define PORTE_PCR4                               PORT_PCR_REG(PORTE,4)
  #define PORTE_PCR5                               PORT_PCR_REG(PORTE,5)
  #define PORTE_PCR6                               PORT_PCR_REG(PORTE,6)
  #define PORTE_PCR7                               PORT_PCR_REG(PORTE,7)
  #define PORTE_PCR8                               PORT_PCR_REG(PORTE,8)
  #define PORTE_PCR9                               PORT_PCR_REG(PORTE,9)
  #define PORTE_PCR10                              PORT_PCR_REG(PORTE,10)
  #define PORTE_PCR11                              PORT_PCR_REG(PORTE,11)
  #define PORTE_PCR12                              PORT_PCR_REG(PORTE,12)
  #define PORTE_PCR13                              PORT_PCR_REG(PORTE,13)
  #define PORTE_PCR14                              PORT_PCR_REG(PORTE,14)
  #define PORTE_PCR15                              PORT_PCR_REG(PORTE,15)
  #define PORTE_PCR16                              PORT_PCR_REG(PORTE,16)
  #define PORTE_PCR17                              PORT_PCR_REG(PORTE,17)
  #define PORTE_PCR18                              PORT_PCR_REG(PORTE,18)
  #define PORTE_PCR19                              PORT_PCR_REG(PORTE,19)
  #define PORTE_PCR20                              PORT_PCR_REG(PORTE,20)
  #define PORTE_PCR21                              PORT_PCR_REG(PORTE,21)
  #define PORTE_PCR22                              PORT_PCR_REG(PORTE,22)
  #define PORTE_PCR23                              PORT_PCR_REG(PORTE,23)
  #define PORTE_PCR24                              PORT_PCR_REG(PORTE,24)
  #define PORTE_PCR25                              PORT_PCR_REG(PORTE,25)
  #define PORTE_PCR26                              PORT_PCR_REG(PORTE,26)
  #define PORTE_PCR27                              PORT_PCR_REG(PORTE,27)
  #define PORTE_PCR28                              PORT_PCR_REG(PORTE,28)
  #define PORTE_PCR29                              PORT_PCR_REG(PORTE,29)
  #define PORTE_PCR30                              PORT_PCR_REG(PORTE,30)
  #define PORTE_PCR31                              PORT_PCR_REG(PORTE,31)
  #define PORTE_GPCLR                              PORT_GPCLR_REG(PORTE)
  #define PORTE_GPCHR                              PORT_GPCHR_REG(PORTE)
  #define PORTE_GICLR                              PORT_GICLR_REG(PORTE)
  #define PORTE_GICHR                              PORT_GICHR_REG(PORTE)
  #define PORTE_ISFR                               PORT_ISFR_REG(PORTE)
  
  /* PORT - Register array accessors */
  #define PORTA_PCR(index)                         PORT_PCR_REG(PORTA,index)
  #define PORTB_PCR(index)                         PORT_PCR_REG(PORTB,index)
  #define PORTC_PCR(index)                         PORT_PCR_REG(PORTC,index)
  #define PORTD_PCR(index)                         PORT_PCR_REG(PORTD,index)
  #define PORTE_PCR(index)                         PORT_PCR_REG(PORTE,index)
  
  /*!
   * @}
   */ /* end of group PORT_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group PORT_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- RCM Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
   * @{
   */
  
  /** RCM - Register Layout Typedef */
  typedef struct {
    __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
    __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
         uint8_t RESERVED_0[2];
    __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
    __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
         uint8_t RESERVED_1[2];
    __IO uint8_t SSRS0;                              /**< Sticky System Reset Status Register 0, offset: 0x8 */
    __IO uint8_t SSRS1;                              /**< Sticky System Reset Status Register 1, offset: 0x9 */
  } RCM_Type, *RCM_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- RCM - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
   * @{
   */
  
  
  /* RCM - Register accessors */
  #define RCM_SRS0_REG(base)                       ((base)->SRS0)
  #define RCM_SRS1_REG(base)                       ((base)->SRS1)
  #define RCM_RPFC_REG(base)                       ((base)->RPFC)
  #define RCM_RPFW_REG(base)                       ((base)->RPFW)
  #define RCM_SSRS0_REG(base)                      ((base)->SSRS0)
  #define RCM_SSRS1_REG(base)                      ((base)->SSRS1)
  
  /*!
   * @}
   */ /* end of group RCM_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- RCM Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RCM_Register_Masks RCM Register Masks
   * @{
   */
  
  /* SRS0 Bit Fields */
  #define RCM_SRS0_WAKEUP_MASK                     0x1u
  #define RCM_SRS0_WAKEUP_SHIFT                    0
  #define RCM_SRS0_WAKEUP_WIDTH                    1
  #define RCM_SRS0_WAKEUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WAKEUP_SHIFT))&RCM_SRS0_WAKEUP_MASK)
  #define RCM_SRS0_LVD_MASK                        0x2u
  #define RCM_SRS0_LVD_SHIFT                       1
  #define RCM_SRS0_LVD_WIDTH                       1
  #define RCM_SRS0_LVD(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LVD_SHIFT))&RCM_SRS0_LVD_MASK)
  #define RCM_SRS0_LOC_MASK                        0x4u
  #define RCM_SRS0_LOC_SHIFT                       2
  #define RCM_SRS0_LOC_WIDTH                       1
  #define RCM_SRS0_LOC(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOC_SHIFT))&RCM_SRS0_LOC_MASK)
  #define RCM_SRS0_LOL_MASK                        0x8u
  #define RCM_SRS0_LOL_SHIFT                       3
  #define RCM_SRS0_LOL_WIDTH                       1
  #define RCM_SRS0_LOL(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_LOL_SHIFT))&RCM_SRS0_LOL_MASK)
  #define RCM_SRS0_WDOG_MASK                       0x20u
  #define RCM_SRS0_WDOG_SHIFT                      5
  #define RCM_SRS0_WDOG_WIDTH                      1
  #define RCM_SRS0_WDOG(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_WDOG_SHIFT))&RCM_SRS0_WDOG_MASK)
  #define RCM_SRS0_PIN_MASK                        0x40u
  #define RCM_SRS0_PIN_SHIFT                       6
  #define RCM_SRS0_PIN_WIDTH                       1
  #define RCM_SRS0_PIN(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_PIN_SHIFT))&RCM_SRS0_PIN_MASK)
  #define RCM_SRS0_POR_MASK                        0x80u
  #define RCM_SRS0_POR_SHIFT                       7
  #define RCM_SRS0_POR_WIDTH                       1
  #define RCM_SRS0_POR(x)                          (((uint8_t)(((uint8_t)(x))<<RCM_SRS0_POR_SHIFT))&RCM_SRS0_POR_MASK)
  /* SRS1 Bit Fields */
  #define RCM_SRS1_JTAG_MASK                       0x1u
  #define RCM_SRS1_JTAG_SHIFT                      0
  #define RCM_SRS1_JTAG_WIDTH                      1
  #define RCM_SRS1_JTAG(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_JTAG_SHIFT))&RCM_SRS1_JTAG_MASK)
  #define RCM_SRS1_LOCKUP_MASK                     0x2u
  #define RCM_SRS1_LOCKUP_SHIFT                    1
  #define RCM_SRS1_LOCKUP_WIDTH                    1
  #define RCM_SRS1_LOCKUP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_LOCKUP_SHIFT))&RCM_SRS1_LOCKUP_MASK)
  #define RCM_SRS1_SW_MASK                         0x4u
  #define RCM_SRS1_SW_SHIFT                        2
  #define RCM_SRS1_SW_WIDTH                        1
  #define RCM_SRS1_SW(x)                           (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SW_SHIFT))&RCM_SRS1_SW_MASK)
  #define RCM_SRS1_MDM_AP_MASK                     0x8u
  #define RCM_SRS1_MDM_AP_SHIFT                    3
  #define RCM_SRS1_MDM_AP_WIDTH                    1
  #define RCM_SRS1_MDM_AP(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_MDM_AP_SHIFT))&RCM_SRS1_MDM_AP_MASK)
  #define RCM_SRS1_SACKERR_MASK                    0x20u
  #define RCM_SRS1_SACKERR_SHIFT                   5
  #define RCM_SRS1_SACKERR_WIDTH                   1
  #define RCM_SRS1_SACKERR(x)                      (((uint8_t)(((uint8_t)(x))<<RCM_SRS1_SACKERR_SHIFT))&RCM_SRS1_SACKERR_MASK)
  /* RPFC Bit Fields */
  #define RCM_RPFC_RSTFLTSRW_MASK                  0x3u
  #define RCM_RPFC_RSTFLTSRW_SHIFT                 0
  #define RCM_RPFC_RSTFLTSRW_WIDTH                 2
  #define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
  #define RCM_RPFC_RSTFLTSS_MASK                   0x4u
  #define RCM_RPFC_RSTFLTSS_SHIFT                  2
  #define RCM_RPFC_RSTFLTSS_WIDTH                  1
  #define RCM_RPFC_RSTFLTSS(x)                     (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSS_SHIFT))&RCM_RPFC_RSTFLTSS_MASK)
  /* RPFW Bit Fields */
  #define RCM_RPFW_RSTFLTSEL_MASK                  0x1Fu
  #define RCM_RPFW_RSTFLTSEL_SHIFT                 0
  #define RCM_RPFW_RSTFLTSEL_WIDTH                 5
  #define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
  /* SSRS0 Bit Fields */
  #define RCM_SSRS0_SWAKEUP_MASK                   0x1u
  #define RCM_SSRS0_SWAKEUP_SHIFT                  0
  #define RCM_SSRS0_SWAKEUP_WIDTH                  1
  #define RCM_SSRS0_SWAKEUP(x)                     (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SWAKEUP_SHIFT))&RCM_SSRS0_SWAKEUP_MASK)
  #define RCM_SSRS0_SLVD_MASK                      0x2u
  #define RCM_SSRS0_SLVD_SHIFT                     1
  #define RCM_SSRS0_SLVD_WIDTH                     1
  #define RCM_SSRS0_SLVD(x)                        (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SLVD_SHIFT))&RCM_SSRS0_SLVD_MASK)
  #define RCM_SSRS0_SLOC_MASK                      0x4u
  #define RCM_SSRS0_SLOC_SHIFT                     2
  #define RCM_SSRS0_SLOC_WIDTH                     1
  #define RCM_SSRS0_SLOC(x)                        (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SLOC_SHIFT))&RCM_SSRS0_SLOC_MASK)
  #define RCM_SSRS0_SLOL_MASK                      0x8u
  #define RCM_SSRS0_SLOL_SHIFT                     3
  #define RCM_SSRS0_SLOL_WIDTH                     1
  #define RCM_SSRS0_SLOL(x)                        (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SLOL_SHIFT))&RCM_SSRS0_SLOL_MASK)
  #define RCM_SSRS0_SWDOG_MASK                     0x20u
  #define RCM_SSRS0_SWDOG_SHIFT                    5
  #define RCM_SSRS0_SWDOG_WIDTH                    1
  #define RCM_SSRS0_SWDOG(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SWDOG_SHIFT))&RCM_SSRS0_SWDOG_MASK)
  #define RCM_SSRS0_SPIN_MASK                      0x40u
  #define RCM_SSRS0_SPIN_SHIFT                     6
  #define RCM_SSRS0_SPIN_WIDTH                     1
  #define RCM_SSRS0_SPIN(x)                        (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SPIN_SHIFT))&RCM_SSRS0_SPIN_MASK)
  #define RCM_SSRS0_SPOR_MASK                      0x80u
  #define RCM_SSRS0_SPOR_SHIFT                     7
  #define RCM_SSRS0_SPOR_WIDTH                     1
  #define RCM_SSRS0_SPOR(x)                        (((uint8_t)(((uint8_t)(x))<<RCM_SSRS0_SPOR_SHIFT))&RCM_SSRS0_SPOR_MASK)
  /* SSRS1 Bit Fields */
  #define RCM_SSRS1_SJTAG_MASK                     0x1u
  #define RCM_SSRS1_SJTAG_SHIFT                    0
  #define RCM_SSRS1_SJTAG_WIDTH                    1
  #define RCM_SSRS1_SJTAG(x)                       (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SJTAG_SHIFT))&RCM_SSRS1_SJTAG_MASK)
  #define RCM_SSRS1_SLOCKUP_MASK                   0x2u
  #define RCM_SSRS1_SLOCKUP_SHIFT                  1
  #define RCM_SSRS1_SLOCKUP_WIDTH                  1
  #define RCM_SSRS1_SLOCKUP(x)                     (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SLOCKUP_SHIFT))&RCM_SSRS1_SLOCKUP_MASK)
  #define RCM_SSRS1_SSW_MASK                       0x4u
  #define RCM_SSRS1_SSW_SHIFT                      2
  #define RCM_SSRS1_SSW_WIDTH                      1
  #define RCM_SSRS1_SSW(x)                         (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SSW_SHIFT))&RCM_SSRS1_SSW_MASK)
  #define RCM_SSRS1_SMDM_AP_MASK                   0x8u
  #define RCM_SSRS1_SMDM_AP_SHIFT                  3
  #define RCM_SSRS1_SMDM_AP_WIDTH                  1
  #define RCM_SSRS1_SMDM_AP(x)                     (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SMDM_AP_SHIFT))&RCM_SSRS1_SMDM_AP_MASK)
  #define RCM_SSRS1_SSACKERR_MASK                  0x20u
  #define RCM_SSRS1_SSACKERR_SHIFT                 5
  #define RCM_SSRS1_SSACKERR_WIDTH                 1
  #define RCM_SSRS1_SSACKERR(x)                    (((uint8_t)(((uint8_t)(x))<<RCM_SSRS1_SSACKERR_SHIFT))&RCM_SSRS1_SSACKERR_MASK)
  
  /*!
   * @}
   */ /* end of group RCM_Register_Masks */
  
  
  /* RCM - Peripheral instance base addresses */
  /** Peripheral RCM base address */
  #define RCM_BASE                                 (0x4007F000u)
  /** Peripheral RCM base pointer */
  #define RCM                                      ((RCM_Type *)RCM_BASE)
  #define RCM_BASE_PTR                             (RCM)
  /** Array initializer of RCM peripheral base addresses */
  #define RCM_BASE_ADDRS                           { RCM_BASE }
  /** Array initializer of RCM peripheral base pointers */
  #define RCM_BASE_PTRS                            { RCM }
  
  /* ----------------------------------------------------------------------------
     -- RCM - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
   * @{
   */
  
  
  /* RCM - Register instance definitions */
  /* RCM */
  #define RCM_SRS0                                 RCM_SRS0_REG(RCM)
  #define RCM_SRS1                                 RCM_SRS1_REG(RCM)
  #define RCM_RPFC                                 RCM_RPFC_REG(RCM)
  #define RCM_RPFW                                 RCM_RPFW_REG(RCM)
  #define RCM_SSRS0                                RCM_SSRS0_REG(RCM)
  #define RCM_SSRS1                                RCM_SSRS1_REG(RCM)
  
  /*!
   * @}
   */ /* end of group RCM_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group RCM_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- RFSYS Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
   * @{
   */
  
  /** RFSYS - Register Layout Typedef */
  typedef struct {
    __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
  } RFSYS_Type, *RFSYS_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- RFSYS - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
   * @{
   */
  
  
  /* RFSYS - Register accessors */
  #define RFSYS_REG_REG(base,index)                ((base)->REG[index])
  #define RFSYS_REG_COUNT                          8
  
  /*!
   * @}
   */ /* end of group RFSYS_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- RFSYS Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
   * @{
   */
  
  /* REG Bit Fields */
  #define RFSYS_REG_LL_MASK                        0xFFu
  #define RFSYS_REG_LL_SHIFT                       0
  #define RFSYS_REG_LL_WIDTH                       8
  #define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
  #define RFSYS_REG_LH_MASK                        0xFF00u
  #define RFSYS_REG_LH_SHIFT                       8
  #define RFSYS_REG_LH_WIDTH                       8
  #define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
  #define RFSYS_REG_HL_MASK                        0xFF0000u
  #define RFSYS_REG_HL_SHIFT                       16
  #define RFSYS_REG_HL_WIDTH                       8
  #define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
  #define RFSYS_REG_HH_MASK                        0xFF000000u
  #define RFSYS_REG_HH_SHIFT                       24
  #define RFSYS_REG_HH_WIDTH                       8
  #define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
  
  /*!
   * @}
   */ /* end of group RFSYS_Register_Masks */
  
  
  /* RFSYS - Peripheral instance base addresses */
  /** Peripheral RFSYS base address */
  #define RFSYS_BASE                               (0x40041000u)
  /** Peripheral RFSYS base pointer */
  #define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
  #define RFSYS_BASE_PTR                           (RFSYS)
  /** Array initializer of RFSYS peripheral base addresses */
  #define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
  /** Array initializer of RFSYS peripheral base pointers */
  #define RFSYS_BASE_PTRS                          { RFSYS }
  
  /* ----------------------------------------------------------------------------
     -- RFSYS - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
   * @{
   */
  
  
  /* RFSYS - Register instance definitions */
  /* RFSYS */
  #define RFSYS_REG0                               RFSYS_REG_REG(RFSYS,0)
  #define RFSYS_REG1                               RFSYS_REG_REG(RFSYS,1)
  #define RFSYS_REG2                               RFSYS_REG_REG(RFSYS,2)
  #define RFSYS_REG3                               RFSYS_REG_REG(RFSYS,3)
  #define RFSYS_REG4                               RFSYS_REG_REG(RFSYS,4)
  #define RFSYS_REG5                               RFSYS_REG_REG(RFSYS,5)
  #define RFSYS_REG6                               RFSYS_REG_REG(RFSYS,6)
  #define RFSYS_REG7                               RFSYS_REG_REG(RFSYS,7)
  
  /* RFSYS - Register array accessors */
  #define RFSYS_REG(index)                         RFSYS_REG_REG(RFSYS,index)
  
  /*!
   * @}
   */ /* end of group RFSYS_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group RFSYS_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- RFVBAT Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
   * @{
   */
  
  /** RFVBAT - Register Layout Typedef */
  typedef struct {
    __IO uint32_t REG[8];                            /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
  } RFVBAT_Type, *RFVBAT_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- RFVBAT - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
   * @{
   */
  
  
  /* RFVBAT - Register accessors */
  #define RFVBAT_REG_REG(base,index)               ((base)->REG[index])
  #define RFVBAT_REG_COUNT                         8
  
  /*!
   * @}
   */ /* end of group RFVBAT_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- RFVBAT Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
   * @{
   */
  
  /* REG Bit Fields */
  #define RFVBAT_REG_LL_MASK                       0xFFu
  #define RFVBAT_REG_LL_SHIFT                      0
  #define RFVBAT_REG_LL_WIDTH                      8
  #define RFVBAT_REG_LL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
  #define RFVBAT_REG_LH_MASK                       0xFF00u
  #define RFVBAT_REG_LH_SHIFT                      8
  #define RFVBAT_REG_LH_WIDTH                      8
  #define RFVBAT_REG_LH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
  #define RFVBAT_REG_HL_MASK                       0xFF0000u
  #define RFVBAT_REG_HL_SHIFT                      16
  #define RFVBAT_REG_HL_WIDTH                      8
  #define RFVBAT_REG_HL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
  #define RFVBAT_REG_HH_MASK                       0xFF000000u
  #define RFVBAT_REG_HH_SHIFT                      24
  #define RFVBAT_REG_HH_WIDTH                      8
  #define RFVBAT_REG_HH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
  
  /*!
   * @}
   */ /* end of group RFVBAT_Register_Masks */
  
  
  /* RFVBAT - Peripheral instance base addresses */
  /** Peripheral RFVBAT base address */
  #define RFVBAT_BASE                              (0x4003E000u)
  /** Peripheral RFVBAT base pointer */
  #define RFVBAT                                   ((RFVBAT_Type *)RFVBAT_BASE)
  #define RFVBAT_BASE_PTR                          (RFVBAT)
  /** Array initializer of RFVBAT peripheral base addresses */
  #define RFVBAT_BASE_ADDRS                        { RFVBAT_BASE }
  /** Array initializer of RFVBAT peripheral base pointers */
  #define RFVBAT_BASE_PTRS                         { RFVBAT }
  
  /* ----------------------------------------------------------------------------
     -- RFVBAT - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
   * @{
   */
  
  
  /* RFVBAT - Register instance definitions */
  /* RFVBAT */
  #define RFVBAT_REG0                              RFVBAT_REG_REG(RFVBAT,0)
  #define RFVBAT_REG1                              RFVBAT_REG_REG(RFVBAT,1)
  #define RFVBAT_REG2                              RFVBAT_REG_REG(RFVBAT,2)
  #define RFVBAT_REG3                              RFVBAT_REG_REG(RFVBAT,3)
  #define RFVBAT_REG4                              RFVBAT_REG_REG(RFVBAT,4)
  #define RFVBAT_REG5                              RFVBAT_REG_REG(RFVBAT,5)
  #define RFVBAT_REG6                              RFVBAT_REG_REG(RFVBAT,6)
  #define RFVBAT_REG7                              RFVBAT_REG_REG(RFVBAT,7)
  
  /* RFVBAT - Register array accessors */
  #define RFVBAT_REG(index)                        RFVBAT_REG_REG(RFVBAT,index)
  
  /*!
   * @}
   */ /* end of group RFVBAT_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group RFVBAT_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- RNG Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
   * @{
   */
  
  /** RNG - Register Layout Typedef */
  typedef struct {
    __IO uint32_t CR;                                /**< RNGA Control Register, offset: 0x0 */
    __I  uint32_t SR;                                /**< RNGA Status Register, offset: 0x4 */
    __O  uint32_t ER;                                /**< RNGA Entropy Register, offset: 0x8 */
    __I  uint32_t OR;                                /**< RNGA Output Register, offset: 0xC */
  } RNG_Type, *RNG_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- RNG - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
   * @{
   */
  
  
  /* RNG - Register accessors */
  #define RNG_CR_REG(base)                         ((base)->CR)
  #define RNG_SR_REG(base)                         ((base)->SR)
  #define RNG_ER_REG(base)                         ((base)->ER)
  #define RNG_OR_REG(base)                         ((base)->OR)
  
  /*!
   * @}
   */ /* end of group RNG_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- RNG Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RNG_Register_Masks RNG Register Masks
   * @{
   */
  
  /* CR Bit Fields */
  #define RNG_CR_GO_MASK                           0x1u
  #define RNG_CR_GO_SHIFT                          0
  #define RNG_CR_GO_WIDTH                          1
  #define RNG_CR_GO(x)                             (((uint32_t)(((uint32_t)(x))<<RNG_CR_GO_SHIFT))&RNG_CR_GO_MASK)
  #define RNG_CR_HA_MASK                           0x2u
  #define RNG_CR_HA_SHIFT                          1
  #define RNG_CR_HA_WIDTH                          1
  #define RNG_CR_HA(x)                             (((uint32_t)(((uint32_t)(x))<<RNG_CR_HA_SHIFT))&RNG_CR_HA_MASK)
  #define RNG_CR_INTM_MASK                         0x4u
  #define RNG_CR_INTM_SHIFT                        2
  #define RNG_CR_INTM_WIDTH                        1
  #define RNG_CR_INTM(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_CR_INTM_SHIFT))&RNG_CR_INTM_MASK)
  #define RNG_CR_CLRI_MASK                         0x8u
  #define RNG_CR_CLRI_SHIFT                        3
  #define RNG_CR_CLRI_WIDTH                        1
  #define RNG_CR_CLRI(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_CR_CLRI_SHIFT))&RNG_CR_CLRI_MASK)
  #define RNG_CR_SLP_MASK                          0x10u
  #define RNG_CR_SLP_SHIFT                         4
  #define RNG_CR_SLP_WIDTH                         1
  #define RNG_CR_SLP(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_CR_SLP_SHIFT))&RNG_CR_SLP_MASK)
  /* SR Bit Fields */
  #define RNG_SR_SECV_MASK                         0x1u
  #define RNG_SR_SECV_SHIFT                        0
  #define RNG_SR_SECV_WIDTH                        1
  #define RNG_SR_SECV(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_SR_SECV_SHIFT))&RNG_SR_SECV_MASK)
  #define RNG_SR_LRS_MASK                          0x2u
  #define RNG_SR_LRS_SHIFT                         1
  #define RNG_SR_LRS_WIDTH                         1
  #define RNG_SR_LRS(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_LRS_SHIFT))&RNG_SR_LRS_MASK)
  #define RNG_SR_ORU_MASK                          0x4u
  #define RNG_SR_ORU_SHIFT                         2
  #define RNG_SR_ORU_WIDTH                         1
  #define RNG_SR_ORU(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_ORU_SHIFT))&RNG_SR_ORU_MASK)
  #define RNG_SR_ERRI_MASK                         0x8u
  #define RNG_SR_ERRI_SHIFT                        3
  #define RNG_SR_ERRI_WIDTH                        1
  #define RNG_SR_ERRI(x)                           (((uint32_t)(((uint32_t)(x))<<RNG_SR_ERRI_SHIFT))&RNG_SR_ERRI_MASK)
  #define RNG_SR_SLP_MASK                          0x10u
  #define RNG_SR_SLP_SHIFT                         4
  #define RNG_SR_SLP_WIDTH                         1
  #define RNG_SR_SLP(x)                            (((uint32_t)(((uint32_t)(x))<<RNG_SR_SLP_SHIFT))&RNG_SR_SLP_MASK)
  #define RNG_SR_OREG_LVL_MASK                     0xFF00u
  #define RNG_SR_OREG_LVL_SHIFT                    8
  #define RNG_SR_OREG_LVL_WIDTH                    8
  #define RNG_SR_OREG_LVL(x)                       (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
  #define RNG_SR_OREG_SIZE_MASK                    0xFF0000u
  #define RNG_SR_OREG_SIZE_SHIFT                   16
  #define RNG_SR_OREG_SIZE_WIDTH                   8
  #define RNG_SR_OREG_SIZE(x)                      (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
  /* ER Bit Fields */
  #define RNG_ER_EXT_ENT_MASK                      0xFFFFFFFFu
  #define RNG_ER_EXT_ENT_SHIFT                     0
  #define RNG_ER_EXT_ENT_WIDTH                     32
  #define RNG_ER_EXT_ENT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
  /* OR Bit Fields */
  #define RNG_OR_RANDOUT_MASK                      0xFFFFFFFFu
  #define RNG_OR_RANDOUT_SHIFT                     0
  #define RNG_OR_RANDOUT_WIDTH                     32
  #define RNG_OR_RANDOUT(x)                        (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
  
  /*!
   * @}
   */ /* end of group RNG_Register_Masks */
  
  
  /* RNG - Peripheral instance base addresses */
  /** Peripheral RNG base address */
  #define RNG_BASE                                 (0x40029000u)
  /** Peripheral RNG base pointer */
  #define RNG                                      ((RNG_Type *)RNG_BASE)
  #define RNG_BASE_PTR                             (RNG)
  /** Array initializer of RNG peripheral base addresses */
  #define RNG_BASE_ADDRS                           { RNG_BASE }
  /** Array initializer of RNG peripheral base pointers */
  #define RNG_BASE_PTRS                            { RNG }
  
  /* ----------------------------------------------------------------------------
     -- RNG - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
   * @{
   */
  
  
  /* RNG - Register instance definitions */
  /* RNG */
  #define RNG_CR                                   RNG_CR_REG(RNG)
  #define RNG_SR                                   RNG_SR_REG(RNG)
  #define RNG_ER                                   RNG_ER_REG(RNG)
  #define RNG_OR                                   RNG_OR_REG(RNG)
  
  /*!
   * @}
   */ /* end of group RNG_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group RNG_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- RTC Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
   * @{
   */
  
  /** RTC - Register Layout Typedef */
  typedef struct {
    __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
    __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
    __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
    __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
    __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
    __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
    __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
    __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
         uint8_t RESERVED_0[2016];
    __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
    __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
  } RTC_Type, *RTC_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- RTC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
   * @{
   */
  
  
  /* RTC - Register accessors */
  #define RTC_TSR_REG(base)                        ((base)->TSR)
  #define RTC_TPR_REG(base)                        ((base)->TPR)
  #define RTC_TAR_REG(base)                        ((base)->TAR)
  #define RTC_TCR_REG(base)                        ((base)->TCR)
  #define RTC_CR_REG(base)                         ((base)->CR)
  #define RTC_SR_REG(base)                         ((base)->SR)
  #define RTC_LR_REG(base)                         ((base)->LR)
  #define RTC_IER_REG(base)                        ((base)->IER)
  #define RTC_WAR_REG(base)                        ((base)->WAR)
  #define RTC_RAR_REG(base)                        ((base)->RAR)
  
  /*!
   * @}
   */ /* end of group RTC_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- RTC Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RTC_Register_Masks RTC Register Masks
   * @{
   */
  
  /* TSR Bit Fields */
  #define RTC_TSR_TSR_MASK                         0xFFFFFFFFu
  #define RTC_TSR_TSR_SHIFT                        0
  #define RTC_TSR_TSR_WIDTH                        32
  #define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
  /* TPR Bit Fields */
  #define RTC_TPR_TPR_MASK                         0xFFFFu
  #define RTC_TPR_TPR_SHIFT                        0
  #define RTC_TPR_TPR_WIDTH                        16
  #define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
  /* TAR Bit Fields */
  #define RTC_TAR_TAR_MASK                         0xFFFFFFFFu
  #define RTC_TAR_TAR_SHIFT                        0
  #define RTC_TAR_TAR_WIDTH                        32
  #define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
  /* TCR Bit Fields */
  #define RTC_TCR_TCR_MASK                         0xFFu
  #define RTC_TCR_TCR_SHIFT                        0
  #define RTC_TCR_TCR_WIDTH                        8
  #define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
  #define RTC_TCR_CIR_MASK                         0xFF00u
  #define RTC_TCR_CIR_SHIFT                        8
  #define RTC_TCR_CIR_WIDTH                        8
  #define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
  #define RTC_TCR_TCV_MASK                         0xFF0000u
  #define RTC_TCR_TCV_SHIFT                        16
  #define RTC_TCR_TCV_WIDTH                        8
  #define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
  #define RTC_TCR_CIC_MASK                         0xFF000000u
  #define RTC_TCR_CIC_SHIFT                        24
  #define RTC_TCR_CIC_WIDTH                        8
  #define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
  /* CR Bit Fields */
  #define RTC_CR_SWR_MASK                          0x1u
  #define RTC_CR_SWR_SHIFT                         0
  #define RTC_CR_SWR_WIDTH                         1
  #define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
  #define RTC_CR_WPE_MASK                          0x2u
  #define RTC_CR_WPE_SHIFT                         1
  #define RTC_CR_WPE_WIDTH                         1
  #define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPE_SHIFT))&RTC_CR_WPE_MASK)
  #define RTC_CR_SUP_MASK                          0x4u
  #define RTC_CR_SUP_SHIFT                         2
  #define RTC_CR_SUP_WIDTH                         1
  #define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
  #define RTC_CR_UM_MASK                           0x8u
  #define RTC_CR_UM_SHIFT                          3
  #define RTC_CR_UM_WIDTH                          1
  #define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
  #define RTC_CR_WPS_MASK                          0x10u
  #define RTC_CR_WPS_SHIFT                         4
  #define RTC_CR_WPS_WIDTH                         1
  #define RTC_CR_WPS(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_CR_WPS_SHIFT))&RTC_CR_WPS_MASK)
  #define RTC_CR_OSCE_MASK                         0x100u
  #define RTC_CR_OSCE_SHIFT                        8
  #define RTC_CR_OSCE_WIDTH                        1
  #define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_OSCE_SHIFT))&RTC_CR_OSCE_MASK)
  #define RTC_CR_CLKO_MASK                         0x200u
  #define RTC_CR_CLKO_SHIFT                        9
  #define RTC_CR_CLKO_WIDTH                        1
  #define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_CLKO_SHIFT))&RTC_CR_CLKO_MASK)
  #define RTC_CR_SC16P_MASK                        0x400u
  #define RTC_CR_SC16P_SHIFT                       10
  #define RTC_CR_SC16P_WIDTH                       1
  #define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC16P_SHIFT))&RTC_CR_SC16P_MASK)
  #define RTC_CR_SC8P_MASK                         0x800u
  #define RTC_CR_SC8P_SHIFT                        11
  #define RTC_CR_SC8P_WIDTH                        1
  #define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC8P_SHIFT))&RTC_CR_SC8P_MASK)
  #define RTC_CR_SC4P_MASK                         0x1000u
  #define RTC_CR_SC4P_SHIFT                        12
  #define RTC_CR_SC4P_WIDTH                        1
  #define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC4P_SHIFT))&RTC_CR_SC4P_MASK)
  #define RTC_CR_SC2P_MASK                         0x2000u
  #define RTC_CR_SC2P_SHIFT                        13
  #define RTC_CR_SC2P_WIDTH                        1
  #define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_CR_SC2P_SHIFT))&RTC_CR_SC2P_MASK)
  /* SR Bit Fields */
  #define RTC_SR_TIF_MASK                          0x1u
  #define RTC_SR_TIF_SHIFT                         0
  #define RTC_SR_TIF_WIDTH                         1
  #define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
  #define RTC_SR_TOF_MASK                          0x2u
  #define RTC_SR_TOF_SHIFT                         1
  #define RTC_SR_TOF_WIDTH                         1
  #define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
  #define RTC_SR_TAF_MASK                          0x4u
  #define RTC_SR_TAF_SHIFT                         2
  #define RTC_SR_TAF_WIDTH                         1
  #define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
  #define RTC_SR_TCE_MASK                          0x10u
  #define RTC_SR_TCE_SHIFT                         4
  #define RTC_SR_TCE_WIDTH                         1
  #define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
  /* LR Bit Fields */
  #define RTC_LR_TCL_MASK                          0x8u
  #define RTC_LR_TCL_SHIFT                         3
  #define RTC_LR_TCL_WIDTH                         1
  #define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
  #define RTC_LR_CRL_MASK                          0x10u
  #define RTC_LR_CRL_SHIFT                         4
  #define RTC_LR_CRL_WIDTH                         1
  #define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
  #define RTC_LR_SRL_MASK                          0x20u
  #define RTC_LR_SRL_SHIFT                         5
  #define RTC_LR_SRL_WIDTH                         1
  #define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
  #define RTC_LR_LRL_MASK                          0x40u
  #define RTC_LR_LRL_SHIFT                         6
  #define RTC_LR_LRL_WIDTH                         1
  #define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
  /* IER Bit Fields */
  #define RTC_IER_TIIE_MASK                        0x1u
  #define RTC_IER_TIIE_SHIFT                       0
  #define RTC_IER_TIIE_WIDTH                       1
  #define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
  #define RTC_IER_TOIE_MASK                        0x2u
  #define RTC_IER_TOIE_SHIFT                       1
  #define RTC_IER_TOIE_WIDTH                       1
  #define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
  #define RTC_IER_TAIE_MASK                        0x4u
  #define RTC_IER_TAIE_SHIFT                       2
  #define RTC_IER_TAIE_WIDTH                       1
  #define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
  #define RTC_IER_TSIE_MASK                        0x10u
  #define RTC_IER_TSIE_SHIFT                       4
  #define RTC_IER_TSIE_WIDTH                       1
  #define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
  #define RTC_IER_WPON_MASK                        0x80u
  #define RTC_IER_WPON_SHIFT                       7
  #define RTC_IER_WPON_WIDTH                       1
  #define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_IER_WPON_SHIFT))&RTC_IER_WPON_MASK)
  /* WAR Bit Fields */
  #define RTC_WAR_TSRW_MASK                        0x1u
  #define RTC_WAR_TSRW_SHIFT                       0
  #define RTC_WAR_TSRW_WIDTH                       1
  #define RTC_WAR_TSRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TSRW_SHIFT))&RTC_WAR_TSRW_MASK)
  #define RTC_WAR_TPRW_MASK                        0x2u
  #define RTC_WAR_TPRW_SHIFT                       1
  #define RTC_WAR_TPRW_WIDTH                       1
  #define RTC_WAR_TPRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TPRW_SHIFT))&RTC_WAR_TPRW_MASK)
  #define RTC_WAR_TARW_MASK                        0x4u
  #define RTC_WAR_TARW_SHIFT                       2
  #define RTC_WAR_TARW_WIDTH                       1
  #define RTC_WAR_TARW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TARW_SHIFT))&RTC_WAR_TARW_MASK)
  #define RTC_WAR_TCRW_MASK                        0x8u
  #define RTC_WAR_TCRW_SHIFT                       3
  #define RTC_WAR_TCRW_WIDTH                       1
  #define RTC_WAR_TCRW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_TCRW_SHIFT))&RTC_WAR_TCRW_MASK)
  #define RTC_WAR_CRW_MASK                         0x10u
  #define RTC_WAR_CRW_SHIFT                        4
  #define RTC_WAR_CRW_WIDTH                        1
  #define RTC_WAR_CRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_CRW_SHIFT))&RTC_WAR_CRW_MASK)
  #define RTC_WAR_SRW_MASK                         0x20u
  #define RTC_WAR_SRW_SHIFT                        5
  #define RTC_WAR_SRW_WIDTH                        1
  #define RTC_WAR_SRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_SRW_SHIFT))&RTC_WAR_SRW_MASK)
  #define RTC_WAR_LRW_MASK                         0x40u
  #define RTC_WAR_LRW_SHIFT                        6
  #define RTC_WAR_LRW_WIDTH                        1
  #define RTC_WAR_LRW(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_WAR_LRW_SHIFT))&RTC_WAR_LRW_MASK)
  #define RTC_WAR_IERW_MASK                        0x80u
  #define RTC_WAR_IERW_SHIFT                       7
  #define RTC_WAR_IERW_WIDTH                       1
  #define RTC_WAR_IERW(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_WAR_IERW_SHIFT))&RTC_WAR_IERW_MASK)
  /* RAR Bit Fields */
  #define RTC_RAR_TSRR_MASK                        0x1u
  #define RTC_RAR_TSRR_SHIFT                       0
  #define RTC_RAR_TSRR_WIDTH                       1
  #define RTC_RAR_TSRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TSRR_SHIFT))&RTC_RAR_TSRR_MASK)
  #define RTC_RAR_TPRR_MASK                        0x2u
  #define RTC_RAR_TPRR_SHIFT                       1
  #define RTC_RAR_TPRR_WIDTH                       1
  #define RTC_RAR_TPRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TPRR_SHIFT))&RTC_RAR_TPRR_MASK)
  #define RTC_RAR_TARR_MASK                        0x4u
  #define RTC_RAR_TARR_SHIFT                       2
  #define RTC_RAR_TARR_WIDTH                       1
  #define RTC_RAR_TARR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TARR_SHIFT))&RTC_RAR_TARR_MASK)
  #define RTC_RAR_TCRR_MASK                        0x8u
  #define RTC_RAR_TCRR_SHIFT                       3
  #define RTC_RAR_TCRR_WIDTH                       1
  #define RTC_RAR_TCRR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_TCRR_SHIFT))&RTC_RAR_TCRR_MASK)
  #define RTC_RAR_CRR_MASK                         0x10u
  #define RTC_RAR_CRR_SHIFT                        4
  #define RTC_RAR_CRR_WIDTH                        1
  #define RTC_RAR_CRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_CRR_SHIFT))&RTC_RAR_CRR_MASK)
  #define RTC_RAR_SRR_MASK                         0x20u
  #define RTC_RAR_SRR_SHIFT                        5
  #define RTC_RAR_SRR_WIDTH                        1
  #define RTC_RAR_SRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_SRR_SHIFT))&RTC_RAR_SRR_MASK)
  #define RTC_RAR_LRR_MASK                         0x40u
  #define RTC_RAR_LRR_SHIFT                        6
  #define RTC_RAR_LRR_WIDTH                        1
  #define RTC_RAR_LRR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_RAR_LRR_SHIFT))&RTC_RAR_LRR_MASK)
  #define RTC_RAR_IERR_MASK                        0x80u
  #define RTC_RAR_IERR_SHIFT                       7
  #define RTC_RAR_IERR_WIDTH                       1
  #define RTC_RAR_IERR(x)                          (((uint32_t)(((uint32_t)(x))<<RTC_RAR_IERR_SHIFT))&RTC_RAR_IERR_MASK)
  
  /*!
   * @}
   */ /* end of group RTC_Register_Masks */
  
  
  /* RTC - Peripheral instance base addresses */
  /** Peripheral RTC base address */
  #define RTC_BASE                                 (0x4003D000u)
  /** Peripheral RTC base pointer */
  #define RTC                                      ((RTC_Type *)RTC_BASE)
  #define RTC_BASE_PTR                             (RTC)
  /** Array initializer of RTC peripheral base addresses */
  #define RTC_BASE_ADDRS                           { RTC_BASE }
  /** Array initializer of RTC peripheral base pointers */
  #define RTC_BASE_PTRS                            { RTC }
  
  /* ----------------------------------------------------------------------------
     -- RTC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
   * @{
   */
  
  
  /* RTC - Register instance definitions */
  /* RTC */
  #define RTC_TSR                                  RTC_TSR_REG(RTC)
  #define RTC_TPR                                  RTC_TPR_REG(RTC)
  #define RTC_TAR                                  RTC_TAR_REG(RTC)
  #define RTC_TCR                                  RTC_TCR_REG(RTC)
  #define RTC_CR                                   RTC_CR_REG(RTC)
  #define RTC_SR                                   RTC_SR_REG(RTC)
  #define RTC_LR                                   RTC_LR_REG(RTC)
  #define RTC_IER                                  RTC_IER_REG(RTC)
  #define RTC_WAR                                  RTC_WAR_REG(RTC)
  #define RTC_RAR                                  RTC_RAR_REG(RTC)
  
  /*!
   * @}
   */ /* end of group RTC_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group RTC_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- SIM Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
   * @{
   */
  
  /** SIM - Register Layout Typedef */
  typedef struct {
    __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
         uint8_t RESERVED_0[4096];
    __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
         uint8_t RESERVED_1[8];
    __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
         uint8_t RESERVED_2[4];
    __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
         uint8_t RESERVED_3[4];
    __IO uint32_t SOPT9;                             /**< System Options Register 9, offset: 0x1020 */
    __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
         uint8_t RESERVED_4[12];
    __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
    __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
    __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
    __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
    __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
    __IO uint32_t CLKDIV2;                           /**< System Clock Divider Register 2, offset: 0x1048 */
    __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
    __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
    __I  uint32_t UIDH;                              /**< Unique Identification Register High, offset: 0x1054 */
    __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
    __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
    __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
    __IO uint32_t CLKDIV3;                           /**< System Clock Divider Register 3, offset: 0x1064 */
         uint8_t RESERVED_5[4];
    __IO uint32_t MISCCTL;                           /**< Miscellaneous Control Register, offset: 0x106C */
  } SIM_Type, *SIM_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- SIM - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
   * @{
   */
  
  
  /* SIM - Register accessors */
  #define SIM_SOPT1_REG(base)                      ((base)->SOPT1)
  #define SIM_SOPT2_REG(base)                      ((base)->SOPT2)
  #define SIM_SOPT5_REG(base)                      ((base)->SOPT5)
  #define SIM_SOPT7_REG(base)                      ((base)->SOPT7)
  #define SIM_SOPT9_REG(base)                      ((base)->SOPT9)
  #define SIM_SDID_REG(base)                       ((base)->SDID)
  #define SIM_SCGC4_REG(base)                      ((base)->SCGC4)
  #define SIM_SCGC5_REG(base)                      ((base)->SCGC5)
  #define SIM_SCGC6_REG(base)                      ((base)->SCGC6)
  #define SIM_SCGC7_REG(base)                      ((base)->SCGC7)
  #define SIM_CLKDIV1_REG(base)                    ((base)->CLKDIV1)
  #define SIM_CLKDIV2_REG(base)                    ((base)->CLKDIV2)
  #define SIM_FCFG1_REG(base)                      ((base)->FCFG1)
  #define SIM_FCFG2_REG(base)                      ((base)->FCFG2)
  #define SIM_UIDH_REG(base)                       ((base)->UIDH)
  #define SIM_UIDMH_REG(base)                      ((base)->UIDMH)
  #define SIM_UIDML_REG(base)                      ((base)->UIDML)
  #define SIM_UIDL_REG(base)                       ((base)->UIDL)
  #define SIM_CLKDIV3_REG(base)                    ((base)->CLKDIV3)
  #define SIM_MISCCTL_REG(base)                    ((base)->MISCCTL)
  
  /*!
   * @}
   */ /* end of group SIM_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- SIM Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SIM_Register_Masks SIM Register Masks
   * @{
   */
  
  /* SOPT1 Bit Fields */
  #define SIM_SOPT1_RAMSIZE_MASK                   0xF000u
  #define SIM_SOPT1_RAMSIZE_SHIFT                  12
  #define SIM_SOPT1_RAMSIZE_WIDTH                  4
  #define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
  #define SIM_SOPT1_OSC32KOUT_MASK                 0x30000u
  #define SIM_SOPT1_OSC32KOUT_SHIFT                16
  #define SIM_SOPT1_OSC32KOUT_WIDTH                2
  #define SIM_SOPT1_OSC32KOUT(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
  #define SIM_SOPT1_OSC32KSEL_MASK                 0xC0000u
  #define SIM_SOPT1_OSC32KSEL_SHIFT                18
  #define SIM_SOPT1_OSC32KSEL_WIDTH                2
  #define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
  /* SOPT2 Bit Fields */
  #define SIM_SOPT2_LPI2C1SRC_MASK                 0xCu
  #define SIM_SOPT2_LPI2C1SRC_SHIFT                2
  #define SIM_SOPT2_LPI2C1SRC_WIDTH                2
  #define SIM_SOPT2_LPI2C1SRC(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPI2C1SRC_SHIFT))&SIM_SOPT2_LPI2C1SRC_MASK)
  #define SIM_SOPT2_RTCCLKOUTSEL_MASK              0x10u
  #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             4
  #define SIM_SOPT2_RTCCLKOUTSEL_WIDTH             1
  #define SIM_SOPT2_RTCCLKOUTSEL(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_RTCCLKOUTSEL_SHIFT))&SIM_SOPT2_RTCCLKOUTSEL_MASK)
  #define SIM_SOPT2_CLKOUTSEL_MASK                 0xE0u
  #define SIM_SOPT2_CLKOUTSEL_SHIFT                5
  #define SIM_SOPT2_CLKOUTSEL_WIDTH                3
  #define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
  #define SIM_SOPT2_LPI2C0SRC_MASK                 0xC00u
  #define SIM_SOPT2_LPI2C0SRC_SHIFT                10
  #define SIM_SOPT2_LPI2C0SRC_WIDTH                2
  #define SIM_SOPT2_LPI2C0SRC(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPI2C0SRC_SHIFT))&SIM_SOPT2_LPI2C0SRC_MASK)
  #define SIM_SOPT2_TRACECLKSEL_MASK               0x1000u
  #define SIM_SOPT2_TRACECLKSEL_SHIFT              12
  #define SIM_SOPT2_TRACECLKSEL_WIDTH              1
  #define SIM_SOPT2_TRACECLKSEL(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TRACECLKSEL_SHIFT))&SIM_SOPT2_TRACECLKSEL_MASK)
  #define SIM_SOPT2_PLLFLLSEL_MASK                 0x30000u
  #define SIM_SOPT2_PLLFLLSEL_SHIFT                16
  #define SIM_SOPT2_PLLFLLSEL_WIDTH                2
  #define SIM_SOPT2_PLLFLLSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
  #define SIM_SOPT2_USBSRC_MASK                    0x40000u
  #define SIM_SOPT2_USBSRC_SHIFT                   18
  #define SIM_SOPT2_USBSRC_WIDTH                   1
  #define SIM_SOPT2_USBSRC(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_USBSRC_SHIFT))&SIM_SOPT2_USBSRC_MASK)
  #define SIM_SOPT2_FLEXIOSRC_MASK                 0xC00000u
  #define SIM_SOPT2_FLEXIOSRC_SHIFT                22
  #define SIM_SOPT2_FLEXIOSRC_WIDTH                2
  #define SIM_SOPT2_FLEXIOSRC(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FLEXIOSRC_SHIFT))&SIM_SOPT2_FLEXIOSRC_MASK)
  #define SIM_SOPT2_TPMSRC_MASK                    0x3000000u
  #define SIM_SOPT2_TPMSRC_SHIFT                   24
  #define SIM_SOPT2_TPMSRC_WIDTH                   2
  #define SIM_SOPT2_TPMSRC(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
  #define SIM_SOPT2_LPUARTSRC_MASK                 0xC000000u
  #define SIM_SOPT2_LPUARTSRC_SHIFT                26
  #define SIM_SOPT2_LPUARTSRC_WIDTH                2
  #define SIM_SOPT2_LPUARTSRC(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUARTSRC_SHIFT))&SIM_SOPT2_LPUARTSRC_MASK)
  /* SOPT5 Bit Fields */
  #define SIM_SOPT5_UART0TXSRC_MASK                0x3u
  #define SIM_SOPT5_UART0TXSRC_SHIFT               0
  #define SIM_SOPT5_UART0TXSRC_WIDTH               2
  #define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
  #define SIM_SOPT5_UART0RXSRC_MASK                0xCu
  #define SIM_SOPT5_UART0RXSRC_SHIFT               2
  #define SIM_SOPT5_UART0RXSRC_WIDTH               2
  #define SIM_SOPT5_UART0RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
  #define SIM_SOPT5_UART1TXSRC_MASK                0x30u
  #define SIM_SOPT5_UART1TXSRC_SHIFT               4
  #define SIM_SOPT5_UART1TXSRC_WIDTH               2
  #define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
  #define SIM_SOPT5_UART1RXSRC_MASK                0xC0u
  #define SIM_SOPT5_UART1RXSRC_SHIFT               6
  #define SIM_SOPT5_UART1RXSRC_WIDTH               2
  #define SIM_SOPT5_UART1RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
  #define SIM_SOPT5_LPUART0TXSRC_MASK              0x30000u
  #define SIM_SOPT5_LPUART0TXSRC_SHIFT             16
  #define SIM_SOPT5_LPUART0TXSRC_WIDTH             2
  #define SIM_SOPT5_LPUART0TXSRC(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0TXSRC_SHIFT))&SIM_SOPT5_LPUART0TXSRC_MASK)
  #define SIM_SOPT5_LPUART0RXSRC_MASK              0xC0000u
  #define SIM_SOPT5_LPUART0RXSRC_SHIFT             18
  #define SIM_SOPT5_LPUART0RXSRC_WIDTH             2
  #define SIM_SOPT5_LPUART0RXSRC(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0RXSRC_SHIFT))&SIM_SOPT5_LPUART0RXSRC_MASK)
  /* SOPT7 Bit Fields */
  #define SIM_SOPT7_ADC0TRGSEL_MASK                0xFu
  #define SIM_SOPT7_ADC0TRGSEL_SHIFT               0
  #define SIM_SOPT7_ADC0TRGSEL_WIDTH               4
  #define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
  #define SIM_SOPT7_ADC0PRETRGSEL_MASK             0x10u
  #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            4
  #define SIM_SOPT7_ADC0PRETRGSEL_WIDTH            1
  #define SIM_SOPT7_ADC0PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0PRETRGSEL_SHIFT))&SIM_SOPT7_ADC0PRETRGSEL_MASK)
  #define SIM_SOPT7_ADC0ALTTRGEN_MASK              0x80u
  #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             7
  #define SIM_SOPT7_ADC0ALTTRGEN_WIDTH             1
  #define SIM_SOPT7_ADC0ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0ALTTRGEN_SHIFT))&SIM_SOPT7_ADC0ALTTRGEN_MASK)
  /* SOPT9 Bit Fields */
  #define SIM_SOPT9_TPM1CH0SRC_MASK                0xC0000u
  #define SIM_SOPT9_TPM1CH0SRC_SHIFT               18
  #define SIM_SOPT9_TPM1CH0SRC_WIDTH               2
  #define SIM_SOPT9_TPM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT9_TPM1CH0SRC_SHIFT))&SIM_SOPT9_TPM1CH0SRC_MASK)
  #define SIM_SOPT9_TPM2CH0SRC_MASK                0x300000u
  #define SIM_SOPT9_TPM2CH0SRC_SHIFT               20
  #define SIM_SOPT9_TPM2CH0SRC_WIDTH               2
  #define SIM_SOPT9_TPM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT9_TPM2CH0SRC_SHIFT))&SIM_SOPT9_TPM2CH0SRC_MASK)
  #define SIM_SOPT9_TPM0CLKSEL_MASK                0x1000000u
  #define SIM_SOPT9_TPM0CLKSEL_SHIFT               24
  #define SIM_SOPT9_TPM0CLKSEL_WIDTH               1
  #define SIM_SOPT9_TPM0CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT9_TPM0CLKSEL_SHIFT))&SIM_SOPT9_TPM0CLKSEL_MASK)
  #define SIM_SOPT9_TPM1CLKSEL_MASK                0x2000000u
  #define SIM_SOPT9_TPM1CLKSEL_SHIFT               25
  #define SIM_SOPT9_TPM1CLKSEL_WIDTH               1
  #define SIM_SOPT9_TPM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT9_TPM1CLKSEL_SHIFT))&SIM_SOPT9_TPM1CLKSEL_MASK)
  #define SIM_SOPT9_TPM2CLKSEL_MASK                0x4000000u
  #define SIM_SOPT9_TPM2CLKSEL_SHIFT               26
  #define SIM_SOPT9_TPM2CLKSEL_WIDTH               1
  #define SIM_SOPT9_TPM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT9_TPM2CLKSEL_SHIFT))&SIM_SOPT9_TPM2CLKSEL_MASK)
  /* SDID Bit Fields */
  #define SIM_SDID_PINID_MASK                      0xFu
  #define SIM_SDID_PINID_SHIFT                     0
  #define SIM_SDID_PINID_WIDTH                     4
  #define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
  #define SIM_SDID_FAMID_MASK                      0x70u
  #define SIM_SDID_FAMID_SHIFT                     4
  #define SIM_SDID_FAMID_WIDTH                     3
  #define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
  #define SIM_SDID_DIEID_MASK                      0xF80u
  #define SIM_SDID_DIEID_SHIFT                     7
  #define SIM_SDID_DIEID_WIDTH                     5
  #define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
  #define SIM_SDID_REVID_MASK                      0xF000u
  #define SIM_SDID_REVID_SHIFT                     12
  #define SIM_SDID_REVID_WIDTH                     4
  #define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
  #define SIM_SDID_SERIESID_MASK                   0xF00000u
  #define SIM_SDID_SERIESID_SHIFT                  20
  #define SIM_SDID_SERIESID_WIDTH                  4
  #define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
  #define SIM_SDID_SUBFAMID_MASK                   0xF000000u
  #define SIM_SDID_SUBFAMID_SHIFT                  24
  #define SIM_SDID_SUBFAMID_WIDTH                  4
  #define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
  #define SIM_SDID_FAMILYID_MASK                   0xF0000000u
  #define SIM_SDID_FAMILYID_SHIFT                  28
  #define SIM_SDID_FAMILYID_WIDTH                  4
  #define SIM_SDID_FAMILYID(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
  /* SCGC4 Bit Fields */
  #define SIM_SCGC4_EWM_MASK                       0x2u
  #define SIM_SCGC4_EWM_SHIFT                      1
  #define SIM_SCGC4_EWM_WIDTH                      1
  #define SIM_SCGC4_EWM(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_EWM_SHIFT))&SIM_SCGC4_EWM_MASK)
  #define SIM_SCGC4_LPI2C0_MASK                    0x40u
  #define SIM_SCGC4_LPI2C0_SHIFT                   6
  #define SIM_SCGC4_LPI2C0_WIDTH                   1
  #define SIM_SCGC4_LPI2C0(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_LPI2C0_SHIFT))&SIM_SCGC4_LPI2C0_MASK)
  #define SIM_SCGC4_LPI2C1_MASK                    0x80u
  #define SIM_SCGC4_LPI2C1_SHIFT                   7
  #define SIM_SCGC4_LPI2C1_WIDTH                   1
  #define SIM_SCGC4_LPI2C1(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_LPI2C1_SHIFT))&SIM_SCGC4_LPI2C1_MASK)
  #define SIM_SCGC4_UART0_MASK                     0x400u
  #define SIM_SCGC4_UART0_SHIFT                    10
  #define SIM_SCGC4_UART0_WIDTH                    1
  #define SIM_SCGC4_UART0(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART0_SHIFT))&SIM_SCGC4_UART0_MASK)
  #define SIM_SCGC4_UART1_MASK                     0x800u
  #define SIM_SCGC4_UART1_SHIFT                    11
  #define SIM_SCGC4_UART1_WIDTH                    1
  #define SIM_SCGC4_UART1(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART1_SHIFT))&SIM_SCGC4_UART1_MASK)
  #define SIM_SCGC4_UART2_MASK                     0x1000u
  #define SIM_SCGC4_UART2_SHIFT                    12
  #define SIM_SCGC4_UART2_WIDTH                    1
  #define SIM_SCGC4_UART2(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_UART2_SHIFT))&SIM_SCGC4_UART2_MASK)
  #define SIM_SCGC4_USBOTG_MASK                    0x40000u
  #define SIM_SCGC4_USBOTG_SHIFT                   18
  #define SIM_SCGC4_USBOTG_WIDTH                   1
  #define SIM_SCGC4_USBOTG(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_USBOTG_SHIFT))&SIM_SCGC4_USBOTG_MASK)
  #define SIM_SCGC4_CMP_MASK                       0x80000u
  #define SIM_SCGC4_CMP_SHIFT                      19
  #define SIM_SCGC4_CMP_WIDTH                      1
  #define SIM_SCGC4_CMP(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP_SHIFT))&SIM_SCGC4_CMP_MASK)
  /* SCGC5 Bit Fields */
  #define SIM_SCGC5_LPTMR_MASK                     0x1u
  #define SIM_SCGC5_LPTMR_SHIFT                    0
  #define SIM_SCGC5_LPTMR_WIDTH                    1
  #define SIM_SCGC5_LPTMR(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPTMR_SHIFT))&SIM_SCGC5_LPTMR_MASK)
  #define SIM_SCGC5_PORTA_MASK                     0x200u
  #define SIM_SCGC5_PORTA_SHIFT                    9
  #define SIM_SCGC5_PORTA_WIDTH                    1
  #define SIM_SCGC5_PORTA(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTA_SHIFT))&SIM_SCGC5_PORTA_MASK)
  #define SIM_SCGC5_PORTB_MASK                     0x400u
  #define SIM_SCGC5_PORTB_SHIFT                    10
  #define SIM_SCGC5_PORTB_WIDTH                    1
  #define SIM_SCGC5_PORTB(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTB_SHIFT))&SIM_SCGC5_PORTB_MASK)
  #define SIM_SCGC5_PORTC_MASK                     0x800u
  #define SIM_SCGC5_PORTC_SHIFT                    11
  #define SIM_SCGC5_PORTC_WIDTH                    1
  #define SIM_SCGC5_PORTC(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
  #define SIM_SCGC5_PORTD_MASK                     0x1000u
  #define SIM_SCGC5_PORTD_SHIFT                    12
  #define SIM_SCGC5_PORTD_WIDTH                    1
  #define SIM_SCGC5_PORTD(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTD_SHIFT))&SIM_SCGC5_PORTD_MASK)
  #define SIM_SCGC5_PORTE_MASK                     0x2000u
  #define SIM_SCGC5_PORTE_SHIFT                    13
  #define SIM_SCGC5_PORTE_WIDTH                    1
  #define SIM_SCGC5_PORTE(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTE_SHIFT))&SIM_SCGC5_PORTE_MASK)
  #define SIM_SCGC5_FLEXIO_MASK                    0x80000000u
  #define SIM_SCGC5_FLEXIO_SHIFT                   31
  #define SIM_SCGC5_FLEXIO_WIDTH                   1
  #define SIM_SCGC5_FLEXIO(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_FLEXIO_SHIFT))&SIM_SCGC5_FLEXIO_MASK)
  /* SCGC6 Bit Fields */
  #define SIM_SCGC6_FTF_MASK                       0x1u
  #define SIM_SCGC6_FTF_SHIFT                      0
  #define SIM_SCGC6_FTF_WIDTH                      1
  #define SIM_SCGC6_FTF(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTF_SHIFT))&SIM_SCGC6_FTF_MASK)
  #define SIM_SCGC6_DMAMUX_MASK                    0x2u
  #define SIM_SCGC6_DMAMUX_SHIFT                   1
  #define SIM_SCGC6_DMAMUX_WIDTH                   1
  #define SIM_SCGC6_DMAMUX(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DMAMUX_SHIFT))&SIM_SCGC6_DMAMUX_MASK)
  #define SIM_SCGC6_FLEXCAN0_MASK                  0x10u
  #define SIM_SCGC6_FLEXCAN0_SHIFT                 4
  #define SIM_SCGC6_FLEXCAN0_WIDTH                 1
  #define SIM_SCGC6_FLEXCAN0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FLEXCAN0_SHIFT))&SIM_SCGC6_FLEXCAN0_MASK)
  #define SIM_SCGC6_FLEXCAN1_MASK                  0x20u
  #define SIM_SCGC6_FLEXCAN1_SHIFT                 5
  #define SIM_SCGC6_FLEXCAN1_WIDTH                 1
  #define SIM_SCGC6_FLEXCAN1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FLEXCAN1_SHIFT))&SIM_SCGC6_FLEXCAN1_MASK)
  #define SIM_SCGC6_RNGA_MASK                      0x200u
  #define SIM_SCGC6_RNGA_SHIFT                     9
  #define SIM_SCGC6_RNGA_WIDTH                     1
  #define SIM_SCGC6_RNGA(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RNGA_SHIFT))&SIM_SCGC6_RNGA_MASK)
  #define SIM_SCGC6_LPUART0_MASK                   0x400u
  #define SIM_SCGC6_LPUART0_SHIFT                  10
  #define SIM_SCGC6_LPUART0_WIDTH                  1
  #define SIM_SCGC6_LPUART0(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_LPUART0_SHIFT))&SIM_SCGC6_LPUART0_MASK)
  #define SIM_SCGC6_SPI0_MASK                      0x1000u
  #define SIM_SCGC6_SPI0_SHIFT                     12
  #define SIM_SCGC6_SPI0_WIDTH                     1
  #define SIM_SCGC6_SPI0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI0_SHIFT))&SIM_SCGC6_SPI0_MASK)
  #define SIM_SCGC6_SPI1_MASK                      0x2000u
  #define SIM_SCGC6_SPI1_SHIFT                     13
  #define SIM_SCGC6_SPI1_WIDTH                     1
  #define SIM_SCGC6_SPI1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_SPI1_SHIFT))&SIM_SCGC6_SPI1_MASK)
  #define SIM_SCGC6_I2S0_MASK                      0x8000u
  #define SIM_SCGC6_I2S0_SHIFT                     15
  #define SIM_SCGC6_I2S0_WIDTH                     1
  #define SIM_SCGC6_I2S0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_I2S0_SHIFT))&SIM_SCGC6_I2S0_MASK)
  #define SIM_SCGC6_I2S1_MASK                      0x10000u
  #define SIM_SCGC6_I2S1_SHIFT                     16
  #define SIM_SCGC6_I2S1_WIDTH                     1
  #define SIM_SCGC6_I2S1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_I2S1_SHIFT))&SIM_SCGC6_I2S1_MASK)
  #define SIM_SCGC6_CRC_MASK                       0x40000u
  #define SIM_SCGC6_CRC_SHIFT                      18
  #define SIM_SCGC6_CRC_WIDTH                      1
  #define SIM_SCGC6_CRC(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_CRC_SHIFT))&SIM_SCGC6_CRC_MASK)
  #define SIM_SCGC6_PDB_MASK                       0x400000u
  #define SIM_SCGC6_PDB_SHIFT                      22
  #define SIM_SCGC6_PDB_WIDTH                      1
  #define SIM_SCGC6_PDB(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PDB_SHIFT))&SIM_SCGC6_PDB_MASK)
  #define SIM_SCGC6_PIT_MASK                       0x800000u
  #define SIM_SCGC6_PIT_SHIFT                      23
  #define SIM_SCGC6_PIT_WIDTH                      1
  #define SIM_SCGC6_PIT(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_PIT_SHIFT))&SIM_SCGC6_PIT_MASK)
  #define SIM_SCGC6_TPM0_MASK                      0x1000000u
  #define SIM_SCGC6_TPM0_SHIFT                     24
  #define SIM_SCGC6_TPM0_WIDTH                     1
  #define SIM_SCGC6_TPM0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM0_SHIFT))&SIM_SCGC6_TPM0_MASK)
  #define SIM_SCGC6_TPM1_MASK                      0x2000000u
  #define SIM_SCGC6_TPM1_SHIFT                     25
  #define SIM_SCGC6_TPM1_WIDTH                     1
  #define SIM_SCGC6_TPM1(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM1_SHIFT))&SIM_SCGC6_TPM1_MASK)
  #define SIM_SCGC6_TPM2_MASK                      0x4000000u
  #define SIM_SCGC6_TPM2_SHIFT                     26
  #define SIM_SCGC6_TPM2_WIDTH                     1
  #define SIM_SCGC6_TPM2(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM2_SHIFT))&SIM_SCGC6_TPM2_MASK)
  #define SIM_SCGC6_ADC0_MASK                      0x8000000u
  #define SIM_SCGC6_ADC0_SHIFT                     27
  #define SIM_SCGC6_ADC0_WIDTH                     1
  #define SIM_SCGC6_ADC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC0_SHIFT))&SIM_SCGC6_ADC0_MASK)
  #define SIM_SCGC6_RTC_MASK                       0x20000000u
  #define SIM_SCGC6_RTC_SHIFT                      29
  #define SIM_SCGC6_RTC_WIDTH                      1
  #define SIM_SCGC6_RTC(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_RTC_SHIFT))&SIM_SCGC6_RTC_MASK)
  #define SIM_SCGC6_DAC0_MASK                      0x80000000u
  #define SIM_SCGC6_DAC0_SHIFT                     31
  #define SIM_SCGC6_DAC0_WIDTH                     1
  #define SIM_SCGC6_DAC0(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_DAC0_SHIFT))&SIM_SCGC6_DAC0_MASK)
  /* SCGC7 Bit Fields */
  #define SIM_SCGC7_DMA_MASK                       0x2u
  #define SIM_SCGC7_DMA_SHIFT                      1
  #define SIM_SCGC7_DMA_WIDTH                      1
  #define SIM_SCGC7_DMA(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_SCGC7_DMA_SHIFT))&SIM_SCGC7_DMA_MASK)
  /* CLKDIV1 Bit Fields */
  #define SIM_CLKDIV1_OUTDIV4_MASK                 0xF0000u
  #define SIM_CLKDIV1_OUTDIV4_SHIFT                16
  #define SIM_CLKDIV1_OUTDIV4_WIDTH                4
  #define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
  #define SIM_CLKDIV1_OUTDIV2_MASK                 0xF000000u
  #define SIM_CLKDIV1_OUTDIV2_SHIFT                24
  #define SIM_CLKDIV1_OUTDIV2_WIDTH                4
  #define SIM_CLKDIV1_OUTDIV2(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
  #define SIM_CLKDIV1_OUTDIV1_MASK                 0xF0000000u
  #define SIM_CLKDIV1_OUTDIV1_SHIFT                28
  #define SIM_CLKDIV1_OUTDIV1_WIDTH                4
  #define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
  /* CLKDIV2 Bit Fields */
  #define SIM_CLKDIV2_USBFRAC_MASK                 0x1u
  #define SIM_CLKDIV2_USBFRAC_SHIFT                0
  #define SIM_CLKDIV2_USBFRAC_WIDTH                1
  #define SIM_CLKDIV2_USBFRAC(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBFRAC_SHIFT))&SIM_CLKDIV2_USBFRAC_MASK)
  #define SIM_CLKDIV2_USBDIV_MASK                  0xEu
  #define SIM_CLKDIV2_USBDIV_SHIFT                 1
  #define SIM_CLKDIV2_USBDIV_WIDTH                 3
  #define SIM_CLKDIV2_USBDIV(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
  /* FCFG1 Bit Fields */
  #define SIM_FCFG1_FLASHDIS_MASK                  0x1u
  #define SIM_FCFG1_FLASHDIS_SHIFT                 0
  #define SIM_FCFG1_FLASHDIS_WIDTH                 1
  #define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDIS_SHIFT))&SIM_FCFG1_FLASHDIS_MASK)
  #define SIM_FCFG1_FLASHDOZE_MASK                 0x2u
  #define SIM_FCFG1_FLASHDOZE_SHIFT                1
  #define SIM_FCFG1_FLASHDOZE_WIDTH                1
  #define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FLASHDOZE_SHIFT))&SIM_FCFG1_FLASHDOZE_MASK)
  #define SIM_FCFG1_PFSIZE_MASK                    0xF000000u
  #define SIM_FCFG1_PFSIZE_SHIFT                   24
  #define SIM_FCFG1_PFSIZE_WIDTH                   4
  #define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
  /* FCFG2 Bit Fields */
  #define SIM_FCFG2_MAXADDR0_MASK                  0x7F000000u
  #define SIM_FCFG2_MAXADDR0_SHIFT                 24
  #define SIM_FCFG2_MAXADDR0_WIDTH                 7
  #define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
  /* UIDH Bit Fields */
  #define SIM_UIDH_UID_MASK                        0xFFFFFFFFu
  #define SIM_UIDH_UID_SHIFT                       0
  #define SIM_UIDH_UID_WIDTH                       32
  #define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
  /* UIDMH Bit Fields */
  #define SIM_UIDMH_UID_MASK                       0xFFFFFFFFu
  #define SIM_UIDMH_UID_SHIFT                      0
  #define SIM_UIDMH_UID_WIDTH                      32
  #define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
  /* UIDML Bit Fields */
  #define SIM_UIDML_UID_MASK                       0xFFFFFFFFu
  #define SIM_UIDML_UID_SHIFT                      0
  #define SIM_UIDML_UID_WIDTH                      32
  #define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
  /* UIDL Bit Fields */
  #define SIM_UIDL_UID_MASK                        0xFFFFFFFFu
  #define SIM_UIDL_UID_SHIFT                       0
  #define SIM_UIDL_UID_WIDTH                       32
  #define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
  /* CLKDIV3 Bit Fields */
  #define SIM_CLKDIV3_PLLFLLFRAC_MASK              0x1u
  #define SIM_CLKDIV3_PLLFLLFRAC_SHIFT             0
  #define SIM_CLKDIV3_PLLFLLFRAC_WIDTH             1
  #define SIM_CLKDIV3_PLLFLLFRAC(x)                (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV3_PLLFLLFRAC_SHIFT))&SIM_CLKDIV3_PLLFLLFRAC_MASK)
  #define SIM_CLKDIV3_PLLFLLDIV_MASK               0xEu
  #define SIM_CLKDIV3_PLLFLLDIV_SHIFT              1
  #define SIM_CLKDIV3_PLLFLLDIV_WIDTH              3
  #define SIM_CLKDIV3_PLLFLLDIV(x)                 (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV3_PLLFLLDIV_SHIFT))&SIM_CLKDIV3_PLLFLLDIV_MASK)
  /* MISCCTL Bit Fields */
  #define SIM_MISCCTL_UARTSELONUSB_MASK            0x3u
  #define SIM_MISCCTL_UARTSELONUSB_SHIFT           0
  #define SIM_MISCCTL_UARTSELONUSB_WIDTH           2
  #define SIM_MISCCTL_UARTSELONUSB(x)              (((uint32_t)(((uint32_t)(x))<<SIM_MISCCTL_UARTSELONUSB_SHIFT))&SIM_MISCCTL_UARTSELONUSB_MASK)
  #define SIM_MISCCTL_FlexIOS0_MASK                0x4u
  #define SIM_MISCCTL_FlexIOS0_SHIFT               2
  #define SIM_MISCCTL_FlexIOS0_WIDTH               1
  #define SIM_MISCCTL_FlexIOS0(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_MISCCTL_FlexIOS0_SHIFT))&SIM_MISCCTL_FlexIOS0_MASK)
  
  /*!
   * @}
   */ /* end of group SIM_Register_Masks */
  
  
  /* SIM - Peripheral instance base addresses */
  /** Peripheral SIM base address */
  #define SIM_BASE                                 (0x40047000u)
  /** Peripheral SIM base pointer */
  #define SIM                                      ((SIM_Type *)SIM_BASE)
  #define SIM_BASE_PTR                             (SIM)
  /** Array initializer of SIM peripheral base addresses */
  #define SIM_BASE_ADDRS                           { SIM_BASE }
  /** Array initializer of SIM peripheral base pointers */
  #define SIM_BASE_PTRS                            { SIM }
  
  /* ----------------------------------------------------------------------------
     -- SIM - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
   * @{
   */
  
  
  /* SIM - Register instance definitions */
  /* SIM */
  #define SIM_SOPT1                                SIM_SOPT1_REG(SIM)
  #define SIM_SOPT2                                SIM_SOPT2_REG(SIM)
  #define SIM_SOPT5                                SIM_SOPT5_REG(SIM)
  #define SIM_SOPT7                                SIM_SOPT7_REG(SIM)
  #define SIM_SOPT9                                SIM_SOPT9_REG(SIM)
  #define SIM_SDID                                 SIM_SDID_REG(SIM)
  #define SIM_SCGC4                                SIM_SCGC4_REG(SIM)
  #define SIM_SCGC5                                SIM_SCGC5_REG(SIM)
  #define SIM_SCGC6                                SIM_SCGC6_REG(SIM)
  #define SIM_SCGC7                                SIM_SCGC7_REG(SIM)
  #define SIM_CLKDIV1                              SIM_CLKDIV1_REG(SIM)
  #define SIM_CLKDIV2                              SIM_CLKDIV2_REG(SIM)
  #define SIM_FCFG1                                SIM_FCFG1_REG(SIM)
  #define SIM_FCFG2                                SIM_FCFG2_REG(SIM)
  #define SIM_UIDH                                 SIM_UIDH_REG(SIM)
  #define SIM_UIDMH                                SIM_UIDMH_REG(SIM)
  #define SIM_UIDML                                SIM_UIDML_REG(SIM)
  #define SIM_UIDL                                 SIM_UIDL_REG(SIM)
  #define SIM_CLKDIV3                              SIM_CLKDIV3_REG(SIM)
  #define SIM_MISCCTL                              SIM_MISCCTL_REG(SIM)
  
  /*!
   * @}
   */ /* end of group SIM_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group SIM_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- SMC Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
   * @{
   */
  
  /** SMC - Register Layout Typedef */
  typedef struct {
    __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
    __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
    __IO uint8_t STOPCTRL;                           /**< Stop Control Register, offset: 0x2 */
    __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
  } SMC_Type, *SMC_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- SMC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
   * @{
   */
  
  
  /* SMC - Register accessors */
  #define SMC_PMPROT_REG(base)                     ((base)->PMPROT)
  #define SMC_PMCTRL_REG(base)                     ((base)->PMCTRL)
  #define SMC_STOPCTRL_REG(base)                   ((base)->STOPCTRL)
  #define SMC_PMSTAT_REG(base)                     ((base)->PMSTAT)
  
  /*!
   * @}
   */ /* end of group SMC_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- SMC Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SMC_Register_Masks SMC Register Masks
   * @{
   */
  
  /* PMPROT Bit Fields */
  #define SMC_PMPROT_AVLLS_MASK                    0x2u
  #define SMC_PMPROT_AVLLS_SHIFT                   1
  #define SMC_PMPROT_AVLLS_WIDTH                   1
  #define SMC_PMPROT_AVLLS(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLLS_SHIFT))&SMC_PMPROT_AVLLS_MASK)
  #define SMC_PMPROT_ALLS_MASK                     0x8u
  #define SMC_PMPROT_ALLS_SHIFT                    3
  #define SMC_PMPROT_ALLS_WIDTH                    1
  #define SMC_PMPROT_ALLS(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_ALLS_SHIFT))&SMC_PMPROT_ALLS_MASK)
  #define SMC_PMPROT_AVLP_MASK                     0x20u
  #define SMC_PMPROT_AVLP_SHIFT                    5
  #define SMC_PMPROT_AVLP_WIDTH                    1
  #define SMC_PMPROT_AVLP(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
  #define SMC_PMPROT_AHSRUN_MASK                   0x80u
  #define SMC_PMPROT_AHSRUN_SHIFT                  7
  #define SMC_PMPROT_AHSRUN_WIDTH                  1
  #define SMC_PMPROT_AHSRUN(x)                     (((uint8_t)(((uint8_t)(x))<<SMC_PMPROT_AHSRUN_SHIFT))&SMC_PMPROT_AHSRUN_MASK)
  /* PMCTRL Bit Fields */
  #define SMC_PMCTRL_STOPM_MASK                    0x7u
  #define SMC_PMCTRL_STOPM_SHIFT                   0
  #define SMC_PMCTRL_STOPM_WIDTH                   3
  #define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
  #define SMC_PMCTRL_STOPA_MASK                    0x8u
  #define SMC_PMCTRL_STOPA_SHIFT                   3
  #define SMC_PMCTRL_STOPA_WIDTH                   1
  #define SMC_PMCTRL_STOPA(x)                      (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPA_SHIFT))&SMC_PMCTRL_STOPA_MASK)
  #define SMC_PMCTRL_RUNM_MASK                     0x60u
  #define SMC_PMCTRL_RUNM_SHIFT                    5
  #define SMC_PMCTRL_RUNM_WIDTH                    2
  #define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
  /* STOPCTRL Bit Fields */
  #define SMC_STOPCTRL_LLSM_MASK                   0x7u
  #define SMC_STOPCTRL_LLSM_SHIFT                  0
  #define SMC_STOPCTRL_LLSM_WIDTH                  3
  #define SMC_STOPCTRL_LLSM(x)                     (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_LLSM_SHIFT))&SMC_STOPCTRL_LLSM_MASK)
  #define SMC_STOPCTRL_LPOPO_MASK                  0x8u
  #define SMC_STOPCTRL_LPOPO_SHIFT                 3
  #define SMC_STOPCTRL_LPOPO_WIDTH                 1
  #define SMC_STOPCTRL_LPOPO(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_LPOPO_SHIFT))&SMC_STOPCTRL_LPOPO_MASK)
  #define SMC_STOPCTRL_PORPO_MASK                  0x20u
  #define SMC_STOPCTRL_PORPO_SHIFT                 5
  #define SMC_STOPCTRL_PORPO_WIDTH                 1
  #define SMC_STOPCTRL_PORPO(x)                    (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PORPO_SHIFT))&SMC_STOPCTRL_PORPO_MASK)
  #define SMC_STOPCTRL_PSTOPO_MASK                 0xC0u
  #define SMC_STOPCTRL_PSTOPO_SHIFT                6
  #define SMC_STOPCTRL_PSTOPO_WIDTH                2
  #define SMC_STOPCTRL_PSTOPO(x)                   (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
  /* PMSTAT Bit Fields */
  #define SMC_PMSTAT_PMSTAT_MASK                   0xFFu
  #define SMC_PMSTAT_PMSTAT_SHIFT                  0
  #define SMC_PMSTAT_PMSTAT_WIDTH                  8
  #define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
  
  /*!
   * @}
   */ /* end of group SMC_Register_Masks */
  
  
  /* SMC - Peripheral instance base addresses */
  /** Peripheral SMC base address */
  #define SMC_BASE                                 (0x4007E000u)
  /** Peripheral SMC base pointer */
  #define SMC                                      ((SMC_Type *)SMC_BASE)
  #define SMC_BASE_PTR                             (SMC)
  /** Array initializer of SMC peripheral base addresses */
  #define SMC_BASE_ADDRS                           { SMC_BASE }
  /** Array initializer of SMC peripheral base pointers */
  #define SMC_BASE_PTRS                            { SMC }
  
  /* ----------------------------------------------------------------------------
     -- SMC - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
   * @{
   */
  
  
  /* SMC - Register instance definitions */
  /* SMC */
  #define SMC_PMPROT                               SMC_PMPROT_REG(SMC)
  #define SMC_PMCTRL                               SMC_PMCTRL_REG(SMC)
  #define SMC_STOPCTRL                             SMC_STOPCTRL_REG(SMC)
  #define SMC_PMSTAT                               SMC_PMSTAT_REG(SMC)
  
  /*!
   * @}
   */ /* end of group SMC_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group SMC_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- SPI Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
   * @{
   */
  
  /** SPI - Register Layout Typedef */
  typedef struct {
    __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
         uint8_t RESERVED_0[4];
    __IO uint32_t TCR;                               /**< Transfer Count Register, offset: 0x8 */
    union {                                          /* offset: 0xC */
      __IO uint32_t CTAR[2];                           /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
      __IO uint32_t CTAR_SLAVE[1];                     /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
    };
         uint8_t RESERVED_1[24];
    __IO uint32_t SR;                                /**< Status Register, offset: 0x2C */
    __IO uint32_t RSER;                              /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
    union {                                          /* offset: 0x34 */
      __IO uint32_t PUSHR;                             /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
      __IO uint32_t PUSHR_SLAVE;                       /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
    };
    __I  uint32_t POPR;                              /**< POP RX FIFO Register, offset: 0x38 */
    __I  uint32_t TXFR0;                             /**< Transmit FIFO Registers, offset: 0x3C */
    __I  uint32_t TXFR1;                             /**< Transmit FIFO Registers, offset: 0x40 */
    __I  uint32_t TXFR2;                             /**< Transmit FIFO Registers, offset: 0x44 */
    __I  uint32_t TXFR3;                             /**< Transmit FIFO Registers, offset: 0x48 */
         uint8_t RESERVED_2[48];
    __I  uint32_t RXFR0;                             /**< Receive FIFO Registers, offset: 0x7C */
    __I  uint32_t RXFR1;                             /**< Receive FIFO Registers, offset: 0x80 */
    __I  uint32_t RXFR2;                             /**< Receive FIFO Registers, offset: 0x84 */
    __I  uint32_t RXFR3;                             /**< Receive FIFO Registers, offset: 0x88 */
  } SPI_Type, *SPI_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- SPI - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
   * @{
   */
  
  
  /* SPI - Register accessors */
  #define SPI_MCR_REG(base)                        ((base)->MCR)
  #define SPI_TCR_REG(base)                        ((base)->TCR)
  #define SPI_CTAR_REG(base,index2)                ((base)->CTAR[index2])
  #define SPI_CTAR_COUNT                           2
  #define SPI_CTAR_SLAVE_REG(base,index2)          ((base)->CTAR_SLAVE[index2])
  #define SPI_CTAR_SLAVE_COUNT                     1
  #define SPI_SR_REG(base)                         ((base)->SR)
  #define SPI_RSER_REG(base)                       ((base)->RSER)
  #define SPI_PUSHR_REG(base)                      ((base)->PUSHR)
  #define SPI_PUSHR_SLAVE_REG(base)                ((base)->PUSHR_SLAVE)
  #define SPI_POPR_REG(base)                       ((base)->POPR)
  #define SPI_TXFR0_REG(base)                      ((base)->TXFR0)
  #define SPI_TXFR1_REG(base)                      ((base)->TXFR1)
  #define SPI_TXFR2_REG(base)                      ((base)->TXFR2)
  #define SPI_TXFR3_REG(base)                      ((base)->TXFR3)
  #define SPI_RXFR0_REG(base)                      ((base)->RXFR0)
  #define SPI_RXFR1_REG(base)                      ((base)->RXFR1)
  #define SPI_RXFR2_REG(base)                      ((base)->RXFR2)
  #define SPI_RXFR3_REG(base)                      ((base)->RXFR3)
  
  /*!
   * @}
   */ /* end of group SPI_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- SPI Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SPI_Register_Masks SPI Register Masks
   * @{
   */
  
  /* MCR Bit Fields */
  #define SPI_MCR_HALT_MASK                        0x1u
  #define SPI_MCR_HALT_SHIFT                       0
  #define SPI_MCR_HALT_WIDTH                       1
  #define SPI_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_HALT_SHIFT))&SPI_MCR_HALT_MASK)
  #define SPI_MCR_SMPL_PT_MASK                     0x300u
  #define SPI_MCR_SMPL_PT_SHIFT                    8
  #define SPI_MCR_SMPL_PT_WIDTH                    2
  #define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
  #define SPI_MCR_CLR_RXF_MASK                     0x400u
  #define SPI_MCR_CLR_RXF_SHIFT                    10
  #define SPI_MCR_CLR_RXF_WIDTH                    1
  #define SPI_MCR_CLR_RXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_RXF_SHIFT))&SPI_MCR_CLR_RXF_MASK)
  #define SPI_MCR_CLR_TXF_MASK                     0x800u
  #define SPI_MCR_CLR_TXF_SHIFT                    11
  #define SPI_MCR_CLR_TXF_WIDTH                    1
  #define SPI_MCR_CLR_TXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CLR_TXF_SHIFT))&SPI_MCR_CLR_TXF_MASK)
  #define SPI_MCR_DIS_RXF_MASK                     0x1000u
  #define SPI_MCR_DIS_RXF_SHIFT                    12
  #define SPI_MCR_DIS_RXF_WIDTH                    1
  #define SPI_MCR_DIS_RXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_RXF_SHIFT))&SPI_MCR_DIS_RXF_MASK)
  #define SPI_MCR_DIS_TXF_MASK                     0x2000u
  #define SPI_MCR_DIS_TXF_SHIFT                    13
  #define SPI_MCR_DIS_TXF_WIDTH                    1
  #define SPI_MCR_DIS_TXF(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DIS_TXF_SHIFT))&SPI_MCR_DIS_TXF_MASK)
  #define SPI_MCR_MDIS_MASK                        0x4000u
  #define SPI_MCR_MDIS_SHIFT                       14
  #define SPI_MCR_MDIS_WIDTH                       1
  #define SPI_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MDIS_SHIFT))&SPI_MCR_MDIS_MASK)
  #define SPI_MCR_DOZE_MASK                        0x8000u
  #define SPI_MCR_DOZE_SHIFT                       15
  #define SPI_MCR_DOZE_WIDTH                       1
  #define SPI_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DOZE_SHIFT))&SPI_MCR_DOZE_MASK)
  #define SPI_MCR_PCSIS_MASK                       0x3F0000u
  #define SPI_MCR_PCSIS_SHIFT                      16
  #define SPI_MCR_PCSIS_WIDTH                      6
  #define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
  #define SPI_MCR_ROOE_MASK                        0x1000000u
  #define SPI_MCR_ROOE_SHIFT                       24
  #define SPI_MCR_ROOE_WIDTH                       1
  #define SPI_MCR_ROOE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_ROOE_SHIFT))&SPI_MCR_ROOE_MASK)
  #define SPI_MCR_PCSSE_MASK                       0x2000000u
  #define SPI_MCR_PCSSE_SHIFT                      25
  #define SPI_MCR_PCSSE_WIDTH                      1
  #define SPI_MCR_PCSSE(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSSE_SHIFT))&SPI_MCR_PCSSE_MASK)
  #define SPI_MCR_MTFE_MASK                        0x4000000u
  #define SPI_MCR_MTFE_SHIFT                       26
  #define SPI_MCR_MTFE_WIDTH                       1
  #define SPI_MCR_MTFE(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MTFE_SHIFT))&SPI_MCR_MTFE_MASK)
  #define SPI_MCR_FRZ_MASK                         0x8000000u
  #define SPI_MCR_FRZ_SHIFT                        27
  #define SPI_MCR_FRZ_WIDTH                        1
  #define SPI_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_MCR_FRZ_SHIFT))&SPI_MCR_FRZ_MASK)
  #define SPI_MCR_DCONF_MASK                       0x30000000u
  #define SPI_MCR_DCONF_SHIFT                      28
  #define SPI_MCR_DCONF_WIDTH                      2
  #define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
  #define SPI_MCR_CONT_SCKE_MASK                   0x40000000u
  #define SPI_MCR_CONT_SCKE_SHIFT                  30
  #define SPI_MCR_CONT_SCKE_WIDTH                  1
  #define SPI_MCR_CONT_SCKE(x)                     (((uint32_t)(((uint32_t)(x))<<SPI_MCR_CONT_SCKE_SHIFT))&SPI_MCR_CONT_SCKE_MASK)
  #define SPI_MCR_MSTR_MASK                        0x80000000u
  #define SPI_MCR_MSTR_SHIFT                       31
  #define SPI_MCR_MSTR_WIDTH                       1
  #define SPI_MCR_MSTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_MCR_MSTR_SHIFT))&SPI_MCR_MSTR_MASK)
  /* TCR Bit Fields */
  #define SPI_TCR_SPI_TCNT_MASK                    0xFFFF0000u
  #define SPI_TCR_SPI_TCNT_SHIFT                   16
  #define SPI_TCR_SPI_TCNT_WIDTH                   16
  #define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
  /* CTAR Bit Fields */
  #define SPI_CTAR_BR_MASK                         0xFu
  #define SPI_CTAR_BR_SHIFT                        0
  #define SPI_CTAR_BR_WIDTH                        4
  #define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
  #define SPI_CTAR_DT_MASK                         0xF0u
  #define SPI_CTAR_DT_SHIFT                        4
  #define SPI_CTAR_DT_WIDTH                        4
  #define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
  #define SPI_CTAR_ASC_MASK                        0xF00u
  #define SPI_CTAR_ASC_SHIFT                       8
  #define SPI_CTAR_ASC_WIDTH                       4
  #define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
  #define SPI_CTAR_CSSCK_MASK                      0xF000u
  #define SPI_CTAR_CSSCK_SHIFT                     12
  #define SPI_CTAR_CSSCK_WIDTH                     4
  #define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
  #define SPI_CTAR_PBR_MASK                        0x30000u
  #define SPI_CTAR_PBR_SHIFT                       16
  #define SPI_CTAR_PBR_WIDTH                       2
  #define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
  #define SPI_CTAR_PDT_MASK                        0xC0000u
  #define SPI_CTAR_PDT_SHIFT                       18
  #define SPI_CTAR_PDT_WIDTH                       2
  #define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
  #define SPI_CTAR_PASC_MASK                       0x300000u
  #define SPI_CTAR_PASC_SHIFT                      20
  #define SPI_CTAR_PASC_WIDTH                      2
  #define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
  #define SPI_CTAR_PCSSCK_MASK                     0xC00000u
  #define SPI_CTAR_PCSSCK_SHIFT                    22
  #define SPI_CTAR_PCSSCK_WIDTH                    2
  #define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
  #define SPI_CTAR_LSBFE_MASK                      0x1000000u
  #define SPI_CTAR_LSBFE_SHIFT                     24
  #define SPI_CTAR_LSBFE_WIDTH                     1
  #define SPI_CTAR_LSBFE(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_LSBFE_SHIFT))&SPI_CTAR_LSBFE_MASK)
  #define SPI_CTAR_CPHA_MASK                       0x2000000u
  #define SPI_CTAR_CPHA_SHIFT                      25
  #define SPI_CTAR_CPHA_WIDTH                      1
  #define SPI_CTAR_CPHA(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPHA_SHIFT))&SPI_CTAR_CPHA_MASK)
  #define SPI_CTAR_CPOL_MASK                       0x4000000u
  #define SPI_CTAR_CPOL_SHIFT                      26
  #define SPI_CTAR_CPOL_WIDTH                      1
  #define SPI_CTAR_CPOL(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CPOL_SHIFT))&SPI_CTAR_CPOL_MASK)
  #define SPI_CTAR_FMSZ_MASK                       0x78000000u
  #define SPI_CTAR_FMSZ_SHIFT                      27
  #define SPI_CTAR_FMSZ_WIDTH                      4
  #define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
  #define SPI_CTAR_DBR_MASK                        0x80000000u
  #define SPI_CTAR_DBR_SHIFT                       31
  #define SPI_CTAR_DBR_WIDTH                       1
  #define SPI_CTAR_DBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DBR_SHIFT))&SPI_CTAR_DBR_MASK)
  /* CTAR_SLAVE Bit Fields */
  #define SPI_CTAR_SLAVE_CPHA_MASK                 0x2000000u
  #define SPI_CTAR_SLAVE_CPHA_SHIFT                25
  #define SPI_CTAR_SLAVE_CPHA_WIDTH                1
  #define SPI_CTAR_SLAVE_CPHA(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPHA_SHIFT))&SPI_CTAR_SLAVE_CPHA_MASK)
  #define SPI_CTAR_SLAVE_CPOL_MASK                 0x4000000u
  #define SPI_CTAR_SLAVE_CPOL_SHIFT                26
  #define SPI_CTAR_SLAVE_CPOL_WIDTH                1
  #define SPI_CTAR_SLAVE_CPOL(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_CPOL_SHIFT))&SPI_CTAR_SLAVE_CPOL_MASK)
  #define SPI_CTAR_SLAVE_FMSZ_MASK                 0x78000000u
  #define SPI_CTAR_SLAVE_FMSZ_SHIFT                27
  #define SPI_CTAR_SLAVE_FMSZ_WIDTH                4
  #define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
  /* SR Bit Fields */
  #define SPI_SR_POPNXTPTR_MASK                    0xFu
  #define SPI_SR_POPNXTPTR_SHIFT                   0
  #define SPI_SR_POPNXTPTR_WIDTH                   4
  #define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
  #define SPI_SR_RXCTR_MASK                        0xF0u
  #define SPI_SR_RXCTR_SHIFT                       4
  #define SPI_SR_RXCTR_WIDTH                       4
  #define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
  #define SPI_SR_TXNXTPTR_MASK                     0xF00u
  #define SPI_SR_TXNXTPTR_SHIFT                    8
  #define SPI_SR_TXNXTPTR_WIDTH                    4
  #define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
  #define SPI_SR_TXCTR_MASK                        0xF000u
  #define SPI_SR_TXCTR_SHIFT                       12
  #define SPI_SR_TXCTR_WIDTH                       4
  #define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
  #define SPI_SR_RFDF_MASK                         0x20000u
  #define SPI_SR_RFDF_SHIFT                        17
  #define SPI_SR_RFDF_WIDTH                        1
  #define SPI_SR_RFDF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFDF_SHIFT))&SPI_SR_RFDF_MASK)
  #define SPI_SR_RFOF_MASK                         0x80000u
  #define SPI_SR_RFOF_SHIFT                        19
  #define SPI_SR_RFOF_WIDTH                        1
  #define SPI_SR_RFOF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_RFOF_SHIFT))&SPI_SR_RFOF_MASK)
  #define SPI_SR_TFFF_MASK                         0x2000000u
  #define SPI_SR_TFFF_SHIFT                        25
  #define SPI_SR_TFFF_WIDTH                        1
  #define SPI_SR_TFFF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFFF_SHIFT))&SPI_SR_TFFF_MASK)
  #define SPI_SR_TFUF_MASK                         0x8000000u
  #define SPI_SR_TFUF_SHIFT                        27
  #define SPI_SR_TFUF_WIDTH                        1
  #define SPI_SR_TFUF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_TFUF_SHIFT))&SPI_SR_TFUF_MASK)
  #define SPI_SR_EOQF_MASK                         0x10000000u
  #define SPI_SR_EOQF_SHIFT                        28
  #define SPI_SR_EOQF_WIDTH                        1
  #define SPI_SR_EOQF(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_SR_EOQF_SHIFT))&SPI_SR_EOQF_MASK)
  #define SPI_SR_TXRXS_MASK                        0x40000000u
  #define SPI_SR_TXRXS_SHIFT                       30
  #define SPI_SR_TXRXS_WIDTH                       1
  #define SPI_SR_TXRXS(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXRXS_SHIFT))&SPI_SR_TXRXS_MASK)
  #define SPI_SR_TCF_MASK                          0x80000000u
  #define SPI_SR_TCF_SHIFT                         31
  #define SPI_SR_TCF_WIDTH                         1
  #define SPI_SR_TCF(x)                            (((uint32_t)(((uint32_t)(x))<<SPI_SR_TCF_SHIFT))&SPI_SR_TCF_MASK)
  /* RSER Bit Fields */
  #define SPI_RSER_RFDF_DIRS_MASK                  0x10000u
  #define SPI_RSER_RFDF_DIRS_SHIFT                 16
  #define SPI_RSER_RFDF_DIRS_WIDTH                 1
  #define SPI_RSER_RFDF_DIRS(x)                    (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_DIRS_SHIFT))&SPI_RSER_RFDF_DIRS_MASK)
  #define SPI_RSER_RFDF_RE_MASK                    0x20000u
  #define SPI_RSER_RFDF_RE_SHIFT                   17
  #define SPI_RSER_RFDF_RE_WIDTH                   1
  #define SPI_RSER_RFDF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFDF_RE_SHIFT))&SPI_RSER_RFDF_RE_MASK)
  #define SPI_RSER_RFOF_RE_MASK                    0x80000u
  #define SPI_RSER_RFOF_RE_SHIFT                   19
  #define SPI_RSER_RFOF_RE_WIDTH                   1
  #define SPI_RSER_RFOF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_RFOF_RE_SHIFT))&SPI_RSER_RFOF_RE_MASK)
  #define SPI_RSER_TFFF_DIRS_MASK                  0x1000000u
  #define SPI_RSER_TFFF_DIRS_SHIFT                 24
  #define SPI_RSER_TFFF_DIRS_WIDTH                 1
  #define SPI_RSER_TFFF_DIRS(x)                    (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_DIRS_SHIFT))&SPI_RSER_TFFF_DIRS_MASK)
  #define SPI_RSER_TFFF_RE_MASK                    0x2000000u
  #define SPI_RSER_TFFF_RE_SHIFT                   25
  #define SPI_RSER_TFFF_RE_WIDTH                   1
  #define SPI_RSER_TFFF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFFF_RE_SHIFT))&SPI_RSER_TFFF_RE_MASK)
  #define SPI_RSER_TFUF_RE_MASK                    0x8000000u
  #define SPI_RSER_TFUF_RE_SHIFT                   27
  #define SPI_RSER_TFUF_RE_WIDTH                   1
  #define SPI_RSER_TFUF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TFUF_RE_SHIFT))&SPI_RSER_TFUF_RE_MASK)
  #define SPI_RSER_EOQF_RE_MASK                    0x10000000u
  #define SPI_RSER_EOQF_RE_SHIFT                   28
  #define SPI_RSER_EOQF_RE_WIDTH                   1
  #define SPI_RSER_EOQF_RE(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RSER_EOQF_RE_SHIFT))&SPI_RSER_EOQF_RE_MASK)
  #define SPI_RSER_TCF_RE_MASK                     0x80000000u
  #define SPI_RSER_TCF_RE_SHIFT                    31
  #define SPI_RSER_TCF_RE_WIDTH                    1
  #define SPI_RSER_TCF_RE(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_RSER_TCF_RE_SHIFT))&SPI_RSER_TCF_RE_MASK)
  /* PUSHR Bit Fields */
  #define SPI_PUSHR_TXDATA_MASK                    0xFFFFu
  #define SPI_PUSHR_TXDATA_SHIFT                   0
  #define SPI_PUSHR_TXDATA_WIDTH                   16
  #define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
  #define SPI_PUSHR_PCS_MASK                       0x3F0000u
  #define SPI_PUSHR_PCS_SHIFT                      16
  #define SPI_PUSHR_PCS_WIDTH                      6
  #define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
  #define SPI_PUSHR_CTCNT_MASK                     0x4000000u
  #define SPI_PUSHR_CTCNT_SHIFT                    26
  #define SPI_PUSHR_CTCNT_WIDTH                    1
  #define SPI_PUSHR_CTCNT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTCNT_SHIFT))&SPI_PUSHR_CTCNT_MASK)
  #define SPI_PUSHR_EOQ_MASK                       0x8000000u
  #define SPI_PUSHR_EOQ_SHIFT                      27
  #define SPI_PUSHR_EOQ_WIDTH                      1
  #define SPI_PUSHR_EOQ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_EOQ_SHIFT))&SPI_PUSHR_EOQ_MASK)
  #define SPI_PUSHR_CTAS_MASK                      0x70000000u
  #define SPI_PUSHR_CTAS_SHIFT                     28
  #define SPI_PUSHR_CTAS_WIDTH                     3
  #define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
  #define SPI_PUSHR_CONT_MASK                      0x80000000u
  #define SPI_PUSHR_CONT_SHIFT                     31
  #define SPI_PUSHR_CONT_WIDTH                     1
  #define SPI_PUSHR_CONT(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CONT_SHIFT))&SPI_PUSHR_CONT_MASK)
  /* PUSHR_SLAVE Bit Fields */
  #define SPI_PUSHR_SLAVE_TXDATA_MASK              0xFFFFu
  #define SPI_PUSHR_SLAVE_TXDATA_SHIFT             0
  #define SPI_PUSHR_SLAVE_TXDATA_WIDTH             16
  #define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
  /* POPR Bit Fields */
  #define SPI_POPR_RXDATA_MASK                     0xFFFFFFFFu
  #define SPI_POPR_RXDATA_SHIFT                    0
  #define SPI_POPR_RXDATA_WIDTH                    32
  #define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
  /* TXFR0 Bit Fields */
  #define SPI_TXFR0_TXDATA_MASK                    0xFFFFu
  #define SPI_TXFR0_TXDATA_SHIFT                   0
  #define SPI_TXFR0_TXDATA_WIDTH                   16
  #define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
  #define SPI_TXFR0_TXCMD_TXDATA_MASK              0xFFFF0000u
  #define SPI_TXFR0_TXCMD_TXDATA_SHIFT             16
  #define SPI_TXFR0_TXCMD_TXDATA_WIDTH             16
  #define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
  /* TXFR1 Bit Fields */
  #define SPI_TXFR1_TXDATA_MASK                    0xFFFFu
  #define SPI_TXFR1_TXDATA_SHIFT                   0
  #define SPI_TXFR1_TXDATA_WIDTH                   16
  #define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
  #define SPI_TXFR1_TXCMD_TXDATA_MASK              0xFFFF0000u
  #define SPI_TXFR1_TXCMD_TXDATA_SHIFT             16
  #define SPI_TXFR1_TXCMD_TXDATA_WIDTH             16
  #define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
  /* TXFR2 Bit Fields */
  #define SPI_TXFR2_TXDATA_MASK                    0xFFFFu
  #define SPI_TXFR2_TXDATA_SHIFT                   0
  #define SPI_TXFR2_TXDATA_WIDTH                   16
  #define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
  #define SPI_TXFR2_TXCMD_TXDATA_MASK              0xFFFF0000u
  #define SPI_TXFR2_TXCMD_TXDATA_SHIFT             16
  #define SPI_TXFR2_TXCMD_TXDATA_WIDTH             16
  #define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
  /* TXFR3 Bit Fields */
  #define SPI_TXFR3_TXDATA_MASK                    0xFFFFu
  #define SPI_TXFR3_TXDATA_SHIFT                   0
  #define SPI_TXFR3_TXDATA_WIDTH                   16
  #define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
  #define SPI_TXFR3_TXCMD_TXDATA_MASK              0xFFFF0000u
  #define SPI_TXFR3_TXCMD_TXDATA_SHIFT             16
  #define SPI_TXFR3_TXCMD_TXDATA_WIDTH             16
  #define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
  /* RXFR0 Bit Fields */
  #define SPI_RXFR0_RXDATA_MASK                    0xFFFFFFFFu
  #define SPI_RXFR0_RXDATA_SHIFT                   0
  #define SPI_RXFR0_RXDATA_WIDTH                   32
  #define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
  /* RXFR1 Bit Fields */
  #define SPI_RXFR1_RXDATA_MASK                    0xFFFFFFFFu
  #define SPI_RXFR1_RXDATA_SHIFT                   0
  #define SPI_RXFR1_RXDATA_WIDTH                   32
  #define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
  /* RXFR2 Bit Fields */
  #define SPI_RXFR2_RXDATA_MASK                    0xFFFFFFFFu
  #define SPI_RXFR2_RXDATA_SHIFT                   0
  #define SPI_RXFR2_RXDATA_WIDTH                   32
  #define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
  /* RXFR3 Bit Fields */
  #define SPI_RXFR3_RXDATA_MASK                    0xFFFFFFFFu
  #define SPI_RXFR3_RXDATA_SHIFT                   0
  #define SPI_RXFR3_RXDATA_WIDTH                   32
  #define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
  
  /*!
   * @}
   */ /* end of group SPI_Register_Masks */
  
  
  /* SPI - Peripheral instance base addresses */
  /** Peripheral SPI0 base address */
  #define SPI0_BASE                                (0x4002C000u)
  /** Peripheral SPI0 base pointer */
  #define SPI0                                     ((SPI_Type *)SPI0_BASE)
  #define SPI0_BASE_PTR                            (SPI0)
  /** Peripheral SPI1 base address */
  #define SPI1_BASE                                (0x4002D000u)
  /** Peripheral SPI1 base pointer */
  #define SPI1                                     ((SPI_Type *)SPI1_BASE)
  #define SPI1_BASE_PTR                            (SPI1)
  /** Array initializer of SPI peripheral base addresses */
  #define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE }
  /** Array initializer of SPI peripheral base pointers */
  #define SPI_BASE_PTRS                            { SPI0, SPI1 }
  
  /* ----------------------------------------------------------------------------
     -- SPI - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
   * @{
   */
  
  
  /* SPI - Register instance definitions */
  /* SPI0 */
  #define SPI0_MCR                                 SPI_MCR_REG(SPI0)
  #define SPI0_TCR                                 SPI_TCR_REG(SPI0)
  #define SPI0_CTAR0                               SPI_CTAR_REG(SPI0,0)
  #define SPI0_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI0,0)
  #define SPI0_CTAR1                               SPI_CTAR_REG(SPI0,1)
  #define SPI0_SR                                  SPI_SR_REG(SPI0)
  #define SPI0_RSER                                SPI_RSER_REG(SPI0)
  #define SPI0_PUSHR                               SPI_PUSHR_REG(SPI0)
  #define SPI0_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI0)
  #define SPI0_POPR                                SPI_POPR_REG(SPI0)
  #define SPI0_TXFR0                               SPI_TXFR0_REG(SPI0)
  #define SPI0_TXFR1                               SPI_TXFR1_REG(SPI0)
  #define SPI0_TXFR2                               SPI_TXFR2_REG(SPI0)
  #define SPI0_TXFR3                               SPI_TXFR3_REG(SPI0)
  #define SPI0_RXFR0                               SPI_RXFR0_REG(SPI0)
  #define SPI0_RXFR1                               SPI_RXFR1_REG(SPI0)
  #define SPI0_RXFR2                               SPI_RXFR2_REG(SPI0)
  #define SPI0_RXFR3                               SPI_RXFR3_REG(SPI0)
  /* SPI1 */
  #define SPI1_MCR                                 SPI_MCR_REG(SPI1)
  #define SPI1_TCR                                 SPI_TCR_REG(SPI1)
  #define SPI1_CTAR0                               SPI_CTAR_REG(SPI1,0)
  #define SPI1_CTAR0_SLAVE                         SPI_CTAR_SLAVE_REG(SPI1,0)
  #define SPI1_CTAR1                               SPI_CTAR_REG(SPI1,1)
  #define SPI1_SR                                  SPI_SR_REG(SPI1)
  #define SPI1_RSER                                SPI_RSER_REG(SPI1)
  #define SPI1_PUSHR                               SPI_PUSHR_REG(SPI1)
  #define SPI1_PUSHR_SLAVE                         SPI_PUSHR_SLAVE_REG(SPI1)
  #define SPI1_POPR                                SPI_POPR_REG(SPI1)
  #define SPI1_TXFR0                               SPI_TXFR0_REG(SPI1)
  #define SPI1_TXFR1                               SPI_TXFR1_REG(SPI1)
  #define SPI1_TXFR2                               SPI_TXFR2_REG(SPI1)
  #define SPI1_TXFR3                               SPI_TXFR3_REG(SPI1)
  #define SPI1_RXFR0                               SPI_RXFR0_REG(SPI1)
  #define SPI1_RXFR1                               SPI_RXFR1_REG(SPI1)
  #define SPI1_RXFR2                               SPI_RXFR2_REG(SPI1)
  #define SPI1_RXFR3                               SPI_RXFR3_REG(SPI1)
  
  /* SPI - Register array accessors */
  #define SPI0_CTAR(index2)                        SPI_CTAR_REG(SPI0,index2)
  #define SPI1_CTAR(index2)                        SPI_CTAR_REG(SPI1,index2)
  #define SPI0_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI0,index2)
  #define SPI1_CTAR_SLAVE(index2)                  SPI_CTAR_SLAVE_REG(SPI1,index2)
  
  /*!
   * @}
   */ /* end of group SPI_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group SPI_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- TPM Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
   * @{
   */
  
  /** TPM - Register Layout Typedef */
  typedef struct {
    __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
    __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
    __IO uint32_t GLOBAL;                            /**< TPM Global Register, offset: 0x8 */
         uint8_t RESERVED_0[4];
    __IO uint32_t SC;                                /**< Status and Control, offset: 0x10 */
    __IO uint32_t CNT;                               /**< Counter, offset: 0x14 */
    __IO uint32_t MOD;                               /**< Modulo, offset: 0x18 */
    __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x1C */
    struct {                                         /* offset: 0x20, array step: 0x8 */
      __IO uint32_t CnSC;                              /**< Channel (n) Status and Control, array offset: 0x20, array step: 0x8 */
      __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x24, array step: 0x8 */
    } CONTROLS[6];
         uint8_t RESERVED_1[20];
    __IO uint32_t COMBINE;                           /**< Combine Channel Register, offset: 0x64 */
         uint8_t RESERVED_2[4];
    __IO uint32_t TRIG;                              /**< Channel Trigger, offset: 0x6C */
    __IO uint32_t POL;                               /**< Channel Polarity, offset: 0x70 */
         uint8_t RESERVED_3[4];
    __IO uint32_t FILTER;                            /**< Filter Control, offset: 0x78 */
         uint8_t RESERVED_4[4];
    __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control and Status, offset: 0x80 */
    __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
  } TPM_Type, *TPM_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- TPM - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
   * @{
   */
  
  
  /* TPM - Register accessors */
  #define TPM_VERID_REG(base)                      ((base)->VERID)
  #define TPM_PARAM_REG(base)                      ((base)->PARAM)
  #define TPM_GLOBAL_REG(base)                     ((base)->GLOBAL)
  #define TPM_SC_REG(base)                         ((base)->SC)
  #define TPM_CNT_REG(base)                        ((base)->CNT)
  #define TPM_MOD_REG(base)                        ((base)->MOD)
  #define TPM_STATUS_REG(base)                     ((base)->STATUS)
  #define TPM_CnSC_REG(base,index)                 ((base)->CONTROLS[index].CnSC)
  #define TPM_CnSC_COUNT                           6
  #define TPM_CnV_REG(base,index)                  ((base)->CONTROLS[index].CnV)
  #define TPM_CnV_COUNT                            6
  #define TPM_COMBINE_REG(base)                    ((base)->COMBINE)
  #define TPM_TRIG_REG(base)                       ((base)->TRIG)
  #define TPM_POL_REG(base)                        ((base)->POL)
  #define TPM_FILTER_REG(base)                     ((base)->FILTER)
  #define TPM_QDCTRL_REG(base)                     ((base)->QDCTRL)
  #define TPM_CONF_REG(base)                       ((base)->CONF)
  
  /*!
   * @}
   */ /* end of group TPM_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- TPM Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup TPM_Register_Masks TPM Register Masks
   * @{
   */
  
  /* VERID Bit Fields */
  #define TPM_VERID_FEATURE_MASK                   0xFFFFu
  #define TPM_VERID_FEATURE_SHIFT                  0
  #define TPM_VERID_FEATURE_WIDTH                  16
  #define TPM_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x))<<TPM_VERID_FEATURE_SHIFT))&TPM_VERID_FEATURE_MASK)
  #define TPM_VERID_MINOR_MASK                     0xFF0000u
  #define TPM_VERID_MINOR_SHIFT                    16
  #define TPM_VERID_MINOR_WIDTH                    8
  #define TPM_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_VERID_MINOR_SHIFT))&TPM_VERID_MINOR_MASK)
  #define TPM_VERID_MAJOR_MASK                     0xFF000000u
  #define TPM_VERID_MAJOR_SHIFT                    24
  #define TPM_VERID_MAJOR_WIDTH                    8
  #define TPM_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_VERID_MAJOR_SHIFT))&TPM_VERID_MAJOR_MASK)
  /* PARAM Bit Fields */
  #define TPM_PARAM_CHAN_MASK                      0xFFu
  #define TPM_PARAM_CHAN_SHIFT                     0
  #define TPM_PARAM_CHAN_WIDTH                     8
  #define TPM_PARAM_CHAN(x)                        (((uint32_t)(((uint32_t)(x))<<TPM_PARAM_CHAN_SHIFT))&TPM_PARAM_CHAN_MASK)
  #define TPM_PARAM_TRIG_MASK                      0xFF00u
  #define TPM_PARAM_TRIG_SHIFT                     8
  #define TPM_PARAM_TRIG_WIDTH                     8
  #define TPM_PARAM_TRIG(x)                        (((uint32_t)(((uint32_t)(x))<<TPM_PARAM_TRIG_SHIFT))&TPM_PARAM_TRIG_MASK)
  #define TPM_PARAM_WIDTH_MASK                     0xFF0000u
  #define TPM_PARAM_WIDTH_SHIFT                    16
  #define TPM_PARAM_WIDTH_WIDTH                    8
  #define TPM_PARAM_WIDTH(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_PARAM_WIDTH_SHIFT))&TPM_PARAM_WIDTH_MASK)
  /* GLOBAL Bit Fields */
  #define TPM_GLOBAL_RST_MASK                      0x2u
  #define TPM_GLOBAL_RST_SHIFT                     1
  #define TPM_GLOBAL_RST_WIDTH                     1
  #define TPM_GLOBAL_RST(x)                        (((uint32_t)(((uint32_t)(x))<<TPM_GLOBAL_RST_SHIFT))&TPM_GLOBAL_RST_MASK)
  /* SC Bit Fields */
  #define TPM_SC_PS_MASK                           0x7u
  #define TPM_SC_PS_SHIFT                          0
  #define TPM_SC_PS_WIDTH                          3
  #define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
  #define TPM_SC_CMOD_MASK                         0x18u
  #define TPM_SC_CMOD_SHIFT                        3
  #define TPM_SC_CMOD_WIDTH                        2
  #define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
  #define TPM_SC_CPWMS_MASK                        0x20u
  #define TPM_SC_CPWMS_SHIFT                       5
  #define TPM_SC_CPWMS_WIDTH                       1
  #define TPM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_SC_CPWMS_SHIFT))&TPM_SC_CPWMS_MASK)
  #define TPM_SC_TOIE_MASK                         0x40u
  #define TPM_SC_TOIE_SHIFT                        6
  #define TPM_SC_TOIE_WIDTH                        1
  #define TPM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_SC_TOIE_SHIFT))&TPM_SC_TOIE_MASK)
  #define TPM_SC_TOF_MASK                          0x80u
  #define TPM_SC_TOF_SHIFT                         7
  #define TPM_SC_TOF_WIDTH                         1
  #define TPM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x))<<TPM_SC_TOF_SHIFT))&TPM_SC_TOF_MASK)
  #define TPM_SC_DMA_MASK                          0x100u
  #define TPM_SC_DMA_SHIFT                         8
  #define TPM_SC_DMA_WIDTH                         1
  #define TPM_SC_DMA(x)                            (((uint32_t)(((uint32_t)(x))<<TPM_SC_DMA_SHIFT))&TPM_SC_DMA_MASK)
  /* CNT Bit Fields */
  #define TPM_CNT_COUNT_MASK                       0xFFFFu
  #define TPM_CNT_COUNT_SHIFT                      0
  #define TPM_CNT_COUNT_WIDTH                      16
  #define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
  /* MOD Bit Fields */
  #define TPM_MOD_MOD_MASK                         0xFFFFu
  #define TPM_MOD_MOD_SHIFT                        0
  #define TPM_MOD_MOD_WIDTH                        16
  #define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
  /* STATUS Bit Fields */
  #define TPM_STATUS_CH0F_MASK                     0x1u
  #define TPM_STATUS_CH0F_SHIFT                    0
  #define TPM_STATUS_CH0F_WIDTH                    1
  #define TPM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH0F_SHIFT))&TPM_STATUS_CH0F_MASK)
  #define TPM_STATUS_CH1F_MASK                     0x2u
  #define TPM_STATUS_CH1F_SHIFT                    1
  #define TPM_STATUS_CH1F_WIDTH                    1
  #define TPM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH1F_SHIFT))&TPM_STATUS_CH1F_MASK)
  #define TPM_STATUS_CH2F_MASK                     0x4u
  #define TPM_STATUS_CH2F_SHIFT                    2
  #define TPM_STATUS_CH2F_WIDTH                    1
  #define TPM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH2F_SHIFT))&TPM_STATUS_CH2F_MASK)
  #define TPM_STATUS_CH3F_MASK                     0x8u
  #define TPM_STATUS_CH3F_SHIFT                    3
  #define TPM_STATUS_CH3F_WIDTH                    1
  #define TPM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH3F_SHIFT))&TPM_STATUS_CH3F_MASK)
  #define TPM_STATUS_CH4F_MASK                     0x10u
  #define TPM_STATUS_CH4F_SHIFT                    4
  #define TPM_STATUS_CH4F_WIDTH                    1
  #define TPM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH4F_SHIFT))&TPM_STATUS_CH4F_MASK)
  #define TPM_STATUS_CH5F_MASK                     0x20u
  #define TPM_STATUS_CH5F_SHIFT                    5
  #define TPM_STATUS_CH5F_WIDTH                    1
  #define TPM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_CH5F_SHIFT))&TPM_STATUS_CH5F_MASK)
  #define TPM_STATUS_TOF_MASK                      0x100u
  #define TPM_STATUS_TOF_SHIFT                     8
  #define TPM_STATUS_TOF_WIDTH                     1
  #define TPM_STATUS_TOF(x)                        (((uint32_t)(((uint32_t)(x))<<TPM_STATUS_TOF_SHIFT))&TPM_STATUS_TOF_MASK)
  /* CnSC Bit Fields */
  #define TPM_CnSC_DMA_MASK                        0x1u
  #define TPM_CnSC_DMA_SHIFT                       0
  #define TPM_CnSC_DMA_WIDTH                       1
  #define TPM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_DMA_SHIFT))&TPM_CnSC_DMA_MASK)
  #define TPM_CnSC_ELSA_MASK                       0x4u
  #define TPM_CnSC_ELSA_SHIFT                      2
  #define TPM_CnSC_ELSA_WIDTH                      1
  #define TPM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_ELSA_SHIFT))&TPM_CnSC_ELSA_MASK)
  #define TPM_CnSC_ELSB_MASK                       0x8u
  #define TPM_CnSC_ELSB_SHIFT                      3
  #define TPM_CnSC_ELSB_WIDTH                      1
  #define TPM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_ELSB_SHIFT))&TPM_CnSC_ELSB_MASK)
  #define TPM_CnSC_MSA_MASK                        0x10u
  #define TPM_CnSC_MSA_SHIFT                       4
  #define TPM_CnSC_MSA_WIDTH                       1
  #define TPM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_MSA_SHIFT))&TPM_CnSC_MSA_MASK)
  #define TPM_CnSC_MSB_MASK                        0x20u
  #define TPM_CnSC_MSB_SHIFT                       5
  #define TPM_CnSC_MSB_WIDTH                       1
  #define TPM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_MSB_SHIFT))&TPM_CnSC_MSB_MASK)
  #define TPM_CnSC_CHIE_MASK                       0x40u
  #define TPM_CnSC_CHIE_SHIFT                      6
  #define TPM_CnSC_CHIE_WIDTH                      1
  #define TPM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_CHIE_SHIFT))&TPM_CnSC_CHIE_MASK)
  #define TPM_CnSC_CHF_MASK                        0x80u
  #define TPM_CnSC_CHF_SHIFT                       7
  #define TPM_CnSC_CHF_WIDTH                       1
  #define TPM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_CnSC_CHF_SHIFT))&TPM_CnSC_CHF_MASK)
  /* CnV Bit Fields */
  #define TPM_CnV_VAL_MASK                         0xFFFFu
  #define TPM_CnV_VAL_SHIFT                        0
  #define TPM_CnV_VAL_WIDTH                        16
  #define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
  /* COMBINE Bit Fields */
  #define TPM_COMBINE_COMBINE0_MASK                0x1u
  #define TPM_COMBINE_COMBINE0_SHIFT               0
  #define TPM_COMBINE_COMBINE0_WIDTH               1
  #define TPM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMBINE0_SHIFT))&TPM_COMBINE_COMBINE0_MASK)
  #define TPM_COMBINE_COMSWAP0_MASK                0x2u
  #define TPM_COMBINE_COMSWAP0_SHIFT               1
  #define TPM_COMBINE_COMSWAP0_WIDTH               1
  #define TPM_COMBINE_COMSWAP0(x)                  (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMSWAP0_SHIFT))&TPM_COMBINE_COMSWAP0_MASK)
  #define TPM_COMBINE_COMBINE1_MASK                0x100u
  #define TPM_COMBINE_COMBINE1_SHIFT               8
  #define TPM_COMBINE_COMBINE1_WIDTH               1
  #define TPM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMBINE1_SHIFT))&TPM_COMBINE_COMBINE1_MASK)
  #define TPM_COMBINE_COMSWAP1_MASK                0x200u
  #define TPM_COMBINE_COMSWAP1_SHIFT               9
  #define TPM_COMBINE_COMSWAP1_WIDTH               1
  #define TPM_COMBINE_COMSWAP1(x)                  (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMSWAP1_SHIFT))&TPM_COMBINE_COMSWAP1_MASK)
  #define TPM_COMBINE_COMBINE2_MASK                0x10000u
  #define TPM_COMBINE_COMBINE2_SHIFT               16
  #define TPM_COMBINE_COMBINE2_WIDTH               1
  #define TPM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMBINE2_SHIFT))&TPM_COMBINE_COMBINE2_MASK)
  #define TPM_COMBINE_COMSWAP2_MASK                0x20000u
  #define TPM_COMBINE_COMSWAP2_SHIFT               17
  #define TPM_COMBINE_COMSWAP2_WIDTH               1
  #define TPM_COMBINE_COMSWAP2(x)                  (((uint32_t)(((uint32_t)(x))<<TPM_COMBINE_COMSWAP2_SHIFT))&TPM_COMBINE_COMSWAP2_MASK)
  /* TRIG Bit Fields */
  #define TPM_TRIG_TRIG0_MASK                      0x1u
  #define TPM_TRIG_TRIG0_SHIFT                     0
  #define TPM_TRIG_TRIG0_WIDTH                     1
  #define TPM_TRIG_TRIG0(x)                        (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG0_SHIFT))&TPM_TRIG_TRIG0_MASK)
  #define TPM_TRIG_TRIG1_MASK                      0x2u
  #define TPM_TRIG_TRIG1_SHIFT                     1
  #define TPM_TRIG_TRIG1_WIDTH                     1
  #define TPM_TRIG_TRIG1(x)                        (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG1_SHIFT))&TPM_TRIG_TRIG1_MASK)
  #define TPM_TRIG_TRIG2_MASK                      0x4u
  #define TPM_TRIG_TRIG2_SHIFT                     2
  #define TPM_TRIG_TRIG2_WIDTH                     1
  #define TPM_TRIG_TRIG2(x)                        (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG2_SHIFT))&TPM_TRIG_TRIG2_MASK)
  #define TPM_TRIG_TRIG3_MASK                      0x8u
  #define TPM_TRIG_TRIG3_SHIFT                     3
  #define TPM_TRIG_TRIG3_WIDTH                     1
  #define TPM_TRIG_TRIG3(x)                        (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG3_SHIFT))&TPM_TRIG_TRIG3_MASK)
  #define TPM_TRIG_TRIG4_MASK                      0x10u
  #define TPM_TRIG_TRIG4_SHIFT                     4
  #define TPM_TRIG_TRIG4_WIDTH                     1
  #define TPM_TRIG_TRIG4(x)                        (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG4_SHIFT))&TPM_TRIG_TRIG4_MASK)
  #define TPM_TRIG_TRIG5_MASK                      0x20u
  #define TPM_TRIG_TRIG5_SHIFT                     5
  #define TPM_TRIG_TRIG5_WIDTH                     1
  #define TPM_TRIG_TRIG5(x)                        (((uint32_t)(((uint32_t)(x))<<TPM_TRIG_TRIG5_SHIFT))&TPM_TRIG_TRIG5_MASK)
  /* POL Bit Fields */
  #define TPM_POL_POL0_MASK                        0x1u
  #define TPM_POL_POL0_SHIFT                       0
  #define TPM_POL_POL0_WIDTH                       1
  #define TPM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL0_SHIFT))&TPM_POL_POL0_MASK)
  #define TPM_POL_POL1_MASK                        0x2u
  #define TPM_POL_POL1_SHIFT                       1
  #define TPM_POL_POL1_WIDTH                       1
  #define TPM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL1_SHIFT))&TPM_POL_POL1_MASK)
  #define TPM_POL_POL2_MASK                        0x4u
  #define TPM_POL_POL2_SHIFT                       2
  #define TPM_POL_POL2_WIDTH                       1
  #define TPM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL2_SHIFT))&TPM_POL_POL2_MASK)
  #define TPM_POL_POL3_MASK                        0x8u
  #define TPM_POL_POL3_SHIFT                       3
  #define TPM_POL_POL3_WIDTH                       1
  #define TPM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL3_SHIFT))&TPM_POL_POL3_MASK)
  #define TPM_POL_POL4_MASK                        0x10u
  #define TPM_POL_POL4_SHIFT                       4
  #define TPM_POL_POL4_WIDTH                       1
  #define TPM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL4_SHIFT))&TPM_POL_POL4_MASK)
  #define TPM_POL_POL5_MASK                        0x20u
  #define TPM_POL_POL5_SHIFT                       5
  #define TPM_POL_POL5_WIDTH                       1
  #define TPM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x))<<TPM_POL_POL5_SHIFT))&TPM_POL_POL5_MASK)
  /* FILTER Bit Fields */
  #define TPM_FILTER_CH0FVAL_MASK                  0xFu
  #define TPM_FILTER_CH0FVAL_SHIFT                 0
  #define TPM_FILTER_CH0FVAL_WIDTH                 4
  #define TPM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH0FVAL_SHIFT))&TPM_FILTER_CH0FVAL_MASK)
  #define TPM_FILTER_CH1FVAL_MASK                  0xF0u
  #define TPM_FILTER_CH1FVAL_SHIFT                 4
  #define TPM_FILTER_CH1FVAL_WIDTH                 4
  #define TPM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH1FVAL_SHIFT))&TPM_FILTER_CH1FVAL_MASK)
  #define TPM_FILTER_CH2FVAL_MASK                  0xF00u
  #define TPM_FILTER_CH2FVAL_SHIFT                 8
  #define TPM_FILTER_CH2FVAL_WIDTH                 4
  #define TPM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH2FVAL_SHIFT))&TPM_FILTER_CH2FVAL_MASK)
  #define TPM_FILTER_CH3FVAL_MASK                  0xF000u
  #define TPM_FILTER_CH3FVAL_SHIFT                 12
  #define TPM_FILTER_CH3FVAL_WIDTH                 4
  #define TPM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH3FVAL_SHIFT))&TPM_FILTER_CH3FVAL_MASK)
  #define TPM_FILTER_CH4FVAL_MASK                  0xF0000u
  #define TPM_FILTER_CH4FVAL_SHIFT                 16
  #define TPM_FILTER_CH4FVAL_WIDTH                 4
  #define TPM_FILTER_CH4FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH4FVAL_SHIFT))&TPM_FILTER_CH4FVAL_MASK)
  #define TPM_FILTER_CH5FVAL_MASK                  0xF00000u
  #define TPM_FILTER_CH5FVAL_SHIFT                 20
  #define TPM_FILTER_CH5FVAL_WIDTH                 4
  #define TPM_FILTER_CH5FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<TPM_FILTER_CH5FVAL_SHIFT))&TPM_FILTER_CH5FVAL_MASK)
  /* QDCTRL Bit Fields */
  #define TPM_QDCTRL_QUADEN_MASK                   0x1u
  #define TPM_QDCTRL_QUADEN_SHIFT                  0
  #define TPM_QDCTRL_QUADEN_WIDTH                  1
  #define TPM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x))<<TPM_QDCTRL_QUADEN_SHIFT))&TPM_QDCTRL_QUADEN_MASK)
  #define TPM_QDCTRL_TOFDIR_MASK                   0x2u
  #define TPM_QDCTRL_TOFDIR_SHIFT                  1
  #define TPM_QDCTRL_TOFDIR_WIDTH                  1
  #define TPM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x))<<TPM_QDCTRL_TOFDIR_SHIFT))&TPM_QDCTRL_TOFDIR_MASK)
  #define TPM_QDCTRL_QUADIR_MASK                   0x4u
  #define TPM_QDCTRL_QUADIR_SHIFT                  2
  #define TPM_QDCTRL_QUADIR_WIDTH                  1
  #define TPM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x))<<TPM_QDCTRL_QUADIR_SHIFT))&TPM_QDCTRL_QUADIR_MASK)
  #define TPM_QDCTRL_QUADMODE_MASK                 0x8u
  #define TPM_QDCTRL_QUADMODE_SHIFT                3
  #define TPM_QDCTRL_QUADMODE_WIDTH                1
  #define TPM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x))<<TPM_QDCTRL_QUADMODE_SHIFT))&TPM_QDCTRL_QUADMODE_MASK)
  /* CONF Bit Fields */
  #define TPM_CONF_DOZEEN_MASK                     0x20u
  #define TPM_CONF_DOZEEN_SHIFT                    5
  #define TPM_CONF_DOZEEN_WIDTH                    1
  #define TPM_CONF_DOZEEN(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DOZEEN_SHIFT))&TPM_CONF_DOZEEN_MASK)
  #define TPM_CONF_DBGMODE_MASK                    0xC0u
  #define TPM_CONF_DBGMODE_SHIFT                   6
  #define TPM_CONF_DBGMODE_WIDTH                   2
  #define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
  #define TPM_CONF_GTBSYNC_MASK                    0x100u
  #define TPM_CONF_GTBSYNC_SHIFT                   8
  #define TPM_CONF_GTBSYNC_WIDTH                   1
  #define TPM_CONF_GTBSYNC(x)                      (((uint32_t)(((uint32_t)(x))<<TPM_CONF_GTBSYNC_SHIFT))&TPM_CONF_GTBSYNC_MASK)
  #define TPM_CONF_GTBEEN_MASK                     0x200u
  #define TPM_CONF_GTBEEN_SHIFT                    9
  #define TPM_CONF_GTBEEN_WIDTH                    1
  #define TPM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_CONF_GTBEEN_SHIFT))&TPM_CONF_GTBEEN_MASK)
  #define TPM_CONF_CSOT_MASK                       0x10000u
  #define TPM_CONF_CSOT_SHIFT                      16
  #define TPM_CONF_CSOT_WIDTH                      1
  #define TPM_CONF_CSOT(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CSOT_SHIFT))&TPM_CONF_CSOT_MASK)
  #define TPM_CONF_CSOO_MASK                       0x20000u
  #define TPM_CONF_CSOO_SHIFT                      17
  #define TPM_CONF_CSOO_WIDTH                      1
  #define TPM_CONF_CSOO(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CSOO_SHIFT))&TPM_CONF_CSOO_MASK)
  #define TPM_CONF_CROT_MASK                       0x40000u
  #define TPM_CONF_CROT_SHIFT                      18
  #define TPM_CONF_CROT_WIDTH                      1
  #define TPM_CONF_CROT(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CROT_SHIFT))&TPM_CONF_CROT_MASK)
  #define TPM_CONF_CPOT_MASK                       0x80000u
  #define TPM_CONF_CPOT_SHIFT                      19
  #define TPM_CONF_CPOT_WIDTH                      1
  #define TPM_CONF_CPOT(x)                         (((uint32_t)(((uint32_t)(x))<<TPM_CONF_CPOT_SHIFT))&TPM_CONF_CPOT_MASK)
  #define TPM_CONF_TRGPOL_MASK                     0x400000u
  #define TPM_CONF_TRGPOL_SHIFT                    22
  #define TPM_CONF_TRGPOL_WIDTH                    1
  #define TPM_CONF_TRGPOL(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGPOL_SHIFT))&TPM_CONF_TRGPOL_MASK)
  #define TPM_CONF_TRGSRC_MASK                     0x800000u
  #define TPM_CONF_TRGSRC_SHIFT                    23
  #define TPM_CONF_TRGSRC_WIDTH                    1
  #define TPM_CONF_TRGSRC(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSRC_SHIFT))&TPM_CONF_TRGSRC_MASK)
  #define TPM_CONF_TRGSEL_MASK                     0xF000000u
  #define TPM_CONF_TRGSEL_SHIFT                    24
  #define TPM_CONF_TRGSEL_WIDTH                    4
  #define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
  
  /*!
   * @}
   */ /* end of group TPM_Register_Masks */
  
  
  /* TPM - Peripheral instance base addresses */
  /** Peripheral TPM0 base address */
  #define TPM0_BASE                                (0x40038000u)
  /** Peripheral TPM0 base pointer */
  #define TPM0                                     ((TPM_Type *)TPM0_BASE)
  #define TPM0_BASE_PTR                            (TPM0)
  /** Peripheral TPM1 base address */
  #define TPM1_BASE                                (0x40039000u)
  /** Peripheral TPM1 base pointer */
  #define TPM1                                     ((TPM_Type *)TPM1_BASE)
  #define TPM1_BASE_PTR                            (TPM1)
  /** Peripheral TPM2 base address */
  #define TPM2_BASE                                (0x4003A000u)
  /** Peripheral TPM2 base pointer */
  #define TPM2                                     ((TPM_Type *)TPM2_BASE)
  #define TPM2_BASE_PTR                            (TPM2)
  /** Array initializer of TPM peripheral base addresses */
  #define TPM_BASE_ADDRS                           { TPM0_BASE, TPM1_BASE, TPM2_BASE }
  /** Array initializer of TPM peripheral base pointers */
  #define TPM_BASE_PTRS                            { TPM0, TPM1, TPM2 }
  
  /* ----------------------------------------------------------------------------
     -- TPM - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
   * @{
   */
  
  
  /* TPM - Register instance definitions */
  /* TPM0 */
  #define TPM0_VERID                               TPM_VERID_REG(TPM0)
  #define TPM0_PARAM                               TPM_PARAM_REG(TPM0)
  #define TPM0_GLOBAL                              TPM_GLOBAL_REG(TPM0)
  #define TPM0_SC                                  TPM_SC_REG(TPM0)
  #define TPM0_CNT                                 TPM_CNT_REG(TPM0)
  #define TPM0_MOD                                 TPM_MOD_REG(TPM0)
  #define TPM0_STATUS                              TPM_STATUS_REG(TPM0)
  #define TPM0_C0SC                                TPM_CnSC_REG(TPM0,0)
  #define TPM0_C0V                                 TPM_CnV_REG(TPM0,0)
  #define TPM0_C1SC                                TPM_CnSC_REG(TPM0,1)
  #define TPM0_C1V                                 TPM_CnV_REG(TPM0,1)
  #define TPM0_C2SC                                TPM_CnSC_REG(TPM0,2)
  #define TPM0_C2V                                 TPM_CnV_REG(TPM0,2)
  #define TPM0_C3SC                                TPM_CnSC_REG(TPM0,3)
  #define TPM0_C3V                                 TPM_CnV_REG(TPM0,3)
  #define TPM0_C4SC                                TPM_CnSC_REG(TPM0,4)
  #define TPM0_C4V                                 TPM_CnV_REG(TPM0,4)
  #define TPM0_C5SC                                TPM_CnSC_REG(TPM0,5)
  #define TPM0_C5V                                 TPM_CnV_REG(TPM0,5)
  #define TPM0_COMBINE                             TPM_COMBINE_REG(TPM0)
  #define TPM0_TRIG                                TPM_TRIG_REG(TPM0)
  #define TPM0_POL                                 TPM_POL_REG(TPM0)
  #define TPM0_FILTER                              TPM_FILTER_REG(TPM0)
  #define TPM0_QDCTRL                              TPM_QDCTRL_REG(TPM0)
  #define TPM0_CONF                                TPM_CONF_REG(TPM0)
  /* TPM1 */
  #define TPM1_VERID                               TPM_VERID_REG(TPM1)
  #define TPM1_PARAM                               TPM_PARAM_REG(TPM1)
  #define TPM1_GLOBAL                              TPM_GLOBAL_REG(TPM1)
  #define TPM1_SC                                  TPM_SC_REG(TPM1)
  #define TPM1_CNT                                 TPM_CNT_REG(TPM1)
  #define TPM1_MOD                                 TPM_MOD_REG(TPM1)
  #define TPM1_STATUS                              TPM_STATUS_REG(TPM1)
  #define TPM1_C0SC                                TPM_CnSC_REG(TPM1,0)
  #define TPM1_C0V                                 TPM_CnV_REG(TPM1,0)
  #define TPM1_C1SC                                TPM_CnSC_REG(TPM1,1)
  #define TPM1_C1V                                 TPM_CnV_REG(TPM1,1)
  #define TPM1_C2SC                                TPM_CnSC_REG(TPM1,2)
  #define TPM1_C2V                                 TPM_CnV_REG(TPM1,2)
  #define TPM1_C3SC                                TPM_CnSC_REG(TPM1,3)
  #define TPM1_C3V                                 TPM_CnV_REG(TPM1,3)
  #define TPM1_C4SC                                TPM_CnSC_REG(TPM1,4)
  #define TPM1_C4V                                 TPM_CnV_REG(TPM1,4)
  #define TPM1_C5SC                                TPM_CnSC_REG(TPM1,5)
  #define TPM1_C5V                                 TPM_CnV_REG(TPM1,5)
  #define TPM1_COMBINE                             TPM_COMBINE_REG(TPM1)
  #define TPM1_TRIG                                TPM_TRIG_REG(TPM1)
  #define TPM1_POL                                 TPM_POL_REG(TPM1)
  #define TPM1_FILTER                              TPM_FILTER_REG(TPM1)
  #define TPM1_QDCTRL                              TPM_QDCTRL_REG(TPM1)
  #define TPM1_CONF                                TPM_CONF_REG(TPM1)
  /* TPM2 */
  #define TPM2_VERID                               TPM_VERID_REG(TPM2)
  #define TPM2_PARAM                               TPM_PARAM_REG(TPM2)
  #define TPM2_GLOBAL                              TPM_GLOBAL_REG(TPM2)
  #define TPM2_SC                                  TPM_SC_REG(TPM2)
  #define TPM2_CNT                                 TPM_CNT_REG(TPM2)
  #define TPM2_MOD                                 TPM_MOD_REG(TPM2)
  #define TPM2_STATUS                              TPM_STATUS_REG(TPM2)
  #define TPM2_C0SC                                TPM_CnSC_REG(TPM2,0)
  #define TPM2_C0V                                 TPM_CnV_REG(TPM2,0)
  #define TPM2_C1SC                                TPM_CnSC_REG(TPM2,1)
  #define TPM2_C1V                                 TPM_CnV_REG(TPM2,1)
  #define TPM2_C2SC                                TPM_CnSC_REG(TPM2,2)
  #define TPM2_C2V                                 TPM_CnV_REG(TPM2,2)
  #define TPM2_C3SC                                TPM_CnSC_REG(TPM2,3)
  #define TPM2_C3V                                 TPM_CnV_REG(TPM2,3)
  #define TPM2_C4SC                                TPM_CnSC_REG(TPM2,4)
  #define TPM2_C4V                                 TPM_CnV_REG(TPM2,4)
  #define TPM2_C5SC                                TPM_CnSC_REG(TPM2,5)
  #define TPM2_C5V                                 TPM_CnV_REG(TPM2,5)
  #define TPM2_COMBINE                             TPM_COMBINE_REG(TPM2)
  #define TPM2_TRIG                                TPM_TRIG_REG(TPM2)
  #define TPM2_POL                                 TPM_POL_REG(TPM2)
  #define TPM2_FILTER                              TPM_FILTER_REG(TPM2)
  #define TPM2_QDCTRL                              TPM_QDCTRL_REG(TPM2)
  #define TPM2_CONF                                TPM_CONF_REG(TPM2)
  
  /* TPM - Register array accessors */
  #define TPM0_CnSC(index)                         TPM_CnSC_REG(TPM0,index)
  #define TPM1_CnSC(index)                         TPM_CnSC_REG(TPM1,index)
  #define TPM2_CnSC(index)                         TPM_CnSC_REG(TPM2,index)
  #define TPM0_CnV(index)                          TPM_CnV_REG(TPM0,index)
  #define TPM1_CnV(index)                          TPM_CnV_REG(TPM1,index)
  #define TPM2_CnV(index)                          TPM_CnV_REG(TPM2,index)
  
  /*!
   * @}
   */ /* end of group TPM_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group TPM_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- UART Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
   * @{
   */
  
  /** UART - Register Layout Typedef */
  typedef struct {
    __IO uint8_t BDH;                                /**< UART Baud Rate Registers: High, offset: 0x0 */
    __IO uint8_t BDL;                                /**< UART Baud Rate Registers: Low, offset: 0x1 */
    __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
    __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
    __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
    __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
    __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
    __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
    __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
    __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
    __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
    __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
    __I  uint8_t ED;                                 /**< UART Extended Data Register, offset: 0xC */
    __IO uint8_t MODEM;                              /**< UART Modem Register, offset: 0xD */
    __IO uint8_t IR;                                 /**< UART Infrared Register, offset: 0xE */
         uint8_t RESERVED_0[1];
    __IO uint8_t PFIFO;                              /**< UART FIFO Parameters, offset: 0x10 */
    __IO uint8_t CFIFO;                              /**< UART FIFO Control Register, offset: 0x11 */
    __IO uint8_t SFIFO;                              /**< UART FIFO Status Register, offset: 0x12 */
    __IO uint8_t TWFIFO;                             /**< UART FIFO Transmit Watermark, offset: 0x13 */
    __I  uint8_t TCFIFO;                             /**< UART FIFO Transmit Count, offset: 0x14 */
    __IO uint8_t RWFIFO;                             /**< UART FIFO Receive Watermark, offset: 0x15 */
    __I  uint8_t RCFIFO;                             /**< UART FIFO Receive Count, offset: 0x16 */
         uint8_t RESERVED_1[1];
    __IO uint8_t C7816;                              /**< UART 7816 Control Register, offset: 0x18 */
    __IO uint8_t IE7816;                             /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
    __IO uint8_t IS7816;                             /**< UART 7816 Interrupt Status Register, offset: 0x1A */
    __IO uint8_t WP7816;                             /**< UART 7816 Wait Parameter Register, offset: 0x1B */
    __IO uint8_t WN7816;                             /**< UART 7816 Wait N Register, offset: 0x1C */
    __IO uint8_t WF7816;                             /**< UART 7816 Wait FD Register, offset: 0x1D */
    __IO uint8_t ET7816;                             /**< UART 7816 Error Threshold Register, offset: 0x1E */
    __IO uint8_t TL7816;                             /**< UART 7816 Transmit Length Register, offset: 0x1F */
         uint8_t RESERVED_2[26];
    __IO uint8_t AP7816A_T0;                         /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
    __IO uint8_t AP7816B_T0;                         /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
    union {                                          /* offset: 0x3C */
      struct {                                         /* offset: 0x3C */
        __IO uint8_t WP7816A_T0;                         /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
        __IO uint8_t WP7816B_T0;                         /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
      } TYPE0;
      struct {                                         /* offset: 0x3C */
        __IO uint8_t WP7816A_T1;                         /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
        __IO uint8_t WP7816B_T1;                         /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
      } TYPE1;
    };
    __IO uint8_t WGP7816_T1;                         /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
    __IO uint8_t WP7816C_T1;                         /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
  } UART_Type, *UART_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- UART - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
   * @{
   */
  
  
  /* UART - Register accessors */
  #define UART_BDH_REG(base)                       ((base)->BDH)
  #define UART_BDL_REG(base)                       ((base)->BDL)
  #define UART_C1_REG(base)                        ((base)->C1)
  #define UART_C2_REG(base)                        ((base)->C2)
  #define UART_S1_REG(base)                        ((base)->S1)
  #define UART_S2_REG(base)                        ((base)->S2)
  #define UART_C3_REG(base)                        ((base)->C3)
  #define UART_D_REG(base)                         ((base)->D)
  #define UART_MA1_REG(base)                       ((base)->MA1)
  #define UART_MA2_REG(base)                       ((base)->MA2)
  #define UART_C4_REG(base)                        ((base)->C4)
  #define UART_C5_REG(base)                        ((base)->C5)
  #define UART_ED_REG(base)                        ((base)->ED)
  #define UART_MODEM_REG(base)                     ((base)->MODEM)
  #define UART_IR_REG(base)                        ((base)->IR)
  #define UART_PFIFO_REG(base)                     ((base)->PFIFO)
  #define UART_CFIFO_REG(base)                     ((base)->CFIFO)
  #define UART_SFIFO_REG(base)                     ((base)->SFIFO)
  #define UART_TWFIFO_REG(base)                    ((base)->TWFIFO)
  #define UART_TCFIFO_REG(base)                    ((base)->TCFIFO)
  #define UART_RWFIFO_REG(base)                    ((base)->RWFIFO)
  #define UART_RCFIFO_REG(base)                    ((base)->RCFIFO)
  #define UART_C7816_REG(base)                     ((base)->C7816)
  #define UART_IE7816_REG(base)                    ((base)->IE7816)
  #define UART_IS7816_REG(base)                    ((base)->IS7816)
  #define UART_WP7816_REG(base)                    ((base)->WP7816)
  #define UART_WN7816_REG(base)                    ((base)->WN7816)
  #define UART_WF7816_REG(base)                    ((base)->WF7816)
  #define UART_ET7816_REG(base)                    ((base)->ET7816)
  #define UART_TL7816_REG(base)                    ((base)->TL7816)
  #define UART_AP7816A_T0_REG(base)                ((base)->AP7816A_T0)
  #define UART_AP7816B_T0_REG(base)                ((base)->AP7816B_T0)
  #define UART_WP7816A_T0_REG(base)                ((base)->TYPE0.WP7816A_T0)
  #define UART_WP7816B_T0_REG(base)                ((base)->TYPE0.WP7816B_T0)
  #define UART_WP7816A_T1_REG(base)                ((base)->TYPE1.WP7816A_T1)
  #define UART_WP7816B_T1_REG(base)                ((base)->TYPE1.WP7816B_T1)
  #define UART_WGP7816_T1_REG(base)                ((base)->WGP7816_T1)
  #define UART_WP7816C_T1_REG(base)                ((base)->WP7816C_T1)
  
  /*!
   * @}
   */ /* end of group UART_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- UART Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup UART_Register_Masks UART Register Masks
   * @{
   */
  
  /* BDH Bit Fields */
  #define UART_BDH_SBR_MASK                        0x1Fu
  #define UART_BDH_SBR_SHIFT                       0
  #define UART_BDH_SBR_WIDTH                       5
  #define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
  #define UART_BDH_SBNS_MASK                       0x20u
  #define UART_BDH_SBNS_SHIFT                      5
  #define UART_BDH_SBNS_WIDTH                      1
  #define UART_BDH_SBNS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBNS_SHIFT))&UART_BDH_SBNS_MASK)
  #define UART_BDH_RXEDGIE_MASK                    0x40u
  #define UART_BDH_RXEDGIE_SHIFT                   6
  #define UART_BDH_RXEDGIE_WIDTH                   1
  #define UART_BDH_RXEDGIE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_BDH_RXEDGIE_SHIFT))&UART_BDH_RXEDGIE_MASK)
  #define UART_BDH_LBKDIE_MASK                     0x80u
  #define UART_BDH_LBKDIE_SHIFT                    7
  #define UART_BDH_LBKDIE_WIDTH                    1
  #define UART_BDH_LBKDIE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_BDH_LBKDIE_SHIFT))&UART_BDH_LBKDIE_MASK)
  /* BDL Bit Fields */
  #define UART_BDL_SBR_MASK                        0xFFu
  #define UART_BDL_SBR_SHIFT                       0
  #define UART_BDL_SBR_WIDTH                       8
  #define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
  /* C1 Bit Fields */
  #define UART_C1_PT_MASK                          0x1u
  #define UART_C1_PT_SHIFT                         0
  #define UART_C1_PT_WIDTH                         1
  #define UART_C1_PT(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PT_SHIFT))&UART_C1_PT_MASK)
  #define UART_C1_PE_MASK                          0x2u
  #define UART_C1_PE_SHIFT                         1
  #define UART_C1_PE_WIDTH                         1
  #define UART_C1_PE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C1_PE_SHIFT))&UART_C1_PE_MASK)
  #define UART_C1_ILT_MASK                         0x4u
  #define UART_C1_ILT_SHIFT                        2
  #define UART_C1_ILT_WIDTH                        1
  #define UART_C1_ILT(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C1_ILT_SHIFT))&UART_C1_ILT_MASK)
  #define UART_C1_WAKE_MASK                        0x8u
  #define UART_C1_WAKE_SHIFT                       3
  #define UART_C1_WAKE_WIDTH                       1
  #define UART_C1_WAKE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_WAKE_SHIFT))&UART_C1_WAKE_MASK)
  #define UART_C1_M_MASK                           0x10u
  #define UART_C1_M_SHIFT                          4
  #define UART_C1_M_WIDTH                          1
  #define UART_C1_M(x)                             (((uint8_t)(((uint8_t)(x))<<UART_C1_M_SHIFT))&UART_C1_M_MASK)
  #define UART_C1_RSRC_MASK                        0x20u
  #define UART_C1_RSRC_SHIFT                       5
  #define UART_C1_RSRC_WIDTH                       1
  #define UART_C1_RSRC(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C1_RSRC_SHIFT))&UART_C1_RSRC_MASK)
  #define UART_C1_UARTSWAI_MASK                    0x40u
  #define UART_C1_UARTSWAI_SHIFT                   6
  #define UART_C1_UARTSWAI_WIDTH                   1
  #define UART_C1_UARTSWAI(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C1_UARTSWAI_SHIFT))&UART_C1_UARTSWAI_MASK)
  #define UART_C1_LOOPS_MASK                       0x80u
  #define UART_C1_LOOPS_SHIFT                      7
  #define UART_C1_LOOPS_WIDTH                      1
  #define UART_C1_LOOPS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C1_LOOPS_SHIFT))&UART_C1_LOOPS_MASK)
  /* C2 Bit Fields */
  #define UART_C2_SBK_MASK                         0x1u
  #define UART_C2_SBK_SHIFT                        0
  #define UART_C2_SBK_WIDTH                        1
  #define UART_C2_SBK(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_SBK_SHIFT))&UART_C2_SBK_MASK)
  #define UART_C2_RWU_MASK                         0x2u
  #define UART_C2_RWU_SHIFT                        1
  #define UART_C2_RWU_WIDTH                        1
  #define UART_C2_RWU(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RWU_SHIFT))&UART_C2_RWU_MASK)
  #define UART_C2_RE_MASK                          0x4u
  #define UART_C2_RE_SHIFT                         2
  #define UART_C2_RE_WIDTH                         1
  #define UART_C2_RE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_RE_SHIFT))&UART_C2_RE_MASK)
  #define UART_C2_TE_MASK                          0x8u
  #define UART_C2_TE_SHIFT                         3
  #define UART_C2_TE_WIDTH                         1
  #define UART_C2_TE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C2_TE_SHIFT))&UART_C2_TE_MASK)
  #define UART_C2_ILIE_MASK                        0x10u
  #define UART_C2_ILIE_SHIFT                       4
  #define UART_C2_ILIE_WIDTH                       1
  #define UART_C2_ILIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_ILIE_SHIFT))&UART_C2_ILIE_MASK)
  #define UART_C2_RIE_MASK                         0x20u
  #define UART_C2_RIE_SHIFT                        5
  #define UART_C2_RIE_WIDTH                        1
  #define UART_C2_RIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_RIE_SHIFT))&UART_C2_RIE_MASK)
  #define UART_C2_TCIE_MASK                        0x40u
  #define UART_C2_TCIE_SHIFT                       6
  #define UART_C2_TCIE_WIDTH                       1
  #define UART_C2_TCIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C2_TCIE_SHIFT))&UART_C2_TCIE_MASK)
  #define UART_C2_TIE_MASK                         0x80u
  #define UART_C2_TIE_SHIFT                        7
  #define UART_C2_TIE_WIDTH                        1
  #define UART_C2_TIE(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C2_TIE_SHIFT))&UART_C2_TIE_MASK)
  /* S1 Bit Fields */
  #define UART_S1_PF_MASK                          0x1u
  #define UART_S1_PF_SHIFT                         0
  #define UART_S1_PF_WIDTH                         1
  #define UART_S1_PF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_PF_SHIFT))&UART_S1_PF_MASK)
  #define UART_S1_FE_MASK                          0x2u
  #define UART_S1_FE_SHIFT                         1
  #define UART_S1_FE_WIDTH                         1
  #define UART_S1_FE(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_FE_SHIFT))&UART_S1_FE_MASK)
  #define UART_S1_NF_MASK                          0x4u
  #define UART_S1_NF_SHIFT                         2
  #define UART_S1_NF_WIDTH                         1
  #define UART_S1_NF(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_NF_SHIFT))&UART_S1_NF_MASK)
  #define UART_S1_OR_MASK                          0x8u
  #define UART_S1_OR_SHIFT                         3
  #define UART_S1_OR_WIDTH                         1
  #define UART_S1_OR(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_OR_SHIFT))&UART_S1_OR_MASK)
  #define UART_S1_IDLE_MASK                        0x10u
  #define UART_S1_IDLE_SHIFT                       4
  #define UART_S1_IDLE_WIDTH                       1
  #define UART_S1_IDLE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_IDLE_SHIFT))&UART_S1_IDLE_MASK)
  #define UART_S1_RDRF_MASK                        0x20u
  #define UART_S1_RDRF_SHIFT                       5
  #define UART_S1_RDRF_WIDTH                       1
  #define UART_S1_RDRF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_RDRF_SHIFT))&UART_S1_RDRF_MASK)
  #define UART_S1_TC_MASK                          0x40u
  #define UART_S1_TC_SHIFT                         6
  #define UART_S1_TC_WIDTH                         1
  #define UART_S1_TC(x)                            (((uint8_t)(((uint8_t)(x))<<UART_S1_TC_SHIFT))&UART_S1_TC_MASK)
  #define UART_S1_TDRE_MASK                        0x80u
  #define UART_S1_TDRE_SHIFT                       7
  #define UART_S1_TDRE_WIDTH                       1
  #define UART_S1_TDRE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S1_TDRE_SHIFT))&UART_S1_TDRE_MASK)
  /* S2 Bit Fields */
  #define UART_S2_RAF_MASK                         0x1u
  #define UART_S2_RAF_SHIFT                        0
  #define UART_S2_RAF_WIDTH                        1
  #define UART_S2_RAF(x)                           (((uint8_t)(((uint8_t)(x))<<UART_S2_RAF_SHIFT))&UART_S2_RAF_MASK)
  #define UART_S2_LBKDE_MASK                       0x2u
  #define UART_S2_LBKDE_SHIFT                      1
  #define UART_S2_LBKDE_WIDTH                      1
  #define UART_S2_LBKDE(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDE_SHIFT))&UART_S2_LBKDE_MASK)
  #define UART_S2_BRK13_MASK                       0x4u
  #define UART_S2_BRK13_SHIFT                      2
  #define UART_S2_BRK13_WIDTH                      1
  #define UART_S2_BRK13(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_BRK13_SHIFT))&UART_S2_BRK13_MASK)
  #define UART_S2_RWUID_MASK                       0x8u
  #define UART_S2_RWUID_SHIFT                      3
  #define UART_S2_RWUID_WIDTH                      1
  #define UART_S2_RWUID(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RWUID_SHIFT))&UART_S2_RWUID_MASK)
  #define UART_S2_RXINV_MASK                       0x10u
  #define UART_S2_RXINV_SHIFT                      4
  #define UART_S2_RXINV_WIDTH                      1
  #define UART_S2_RXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_S2_RXINV_SHIFT))&UART_S2_RXINV_MASK)
  #define UART_S2_MSBF_MASK                        0x20u
  #define UART_S2_MSBF_SHIFT                       5
  #define UART_S2_MSBF_WIDTH                       1
  #define UART_S2_MSBF(x)                          (((uint8_t)(((uint8_t)(x))<<UART_S2_MSBF_SHIFT))&UART_S2_MSBF_MASK)
  #define UART_S2_RXEDGIF_MASK                     0x40u
  #define UART_S2_RXEDGIF_SHIFT                    6
  #define UART_S2_RXEDGIF_WIDTH                    1
  #define UART_S2_RXEDGIF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_S2_RXEDGIF_SHIFT))&UART_S2_RXEDGIF_MASK)
  #define UART_S2_LBKDIF_MASK                      0x80u
  #define UART_S2_LBKDIF_SHIFT                     7
  #define UART_S2_LBKDIF_WIDTH                     1
  #define UART_S2_LBKDIF(x)                        (((uint8_t)(((uint8_t)(x))<<UART_S2_LBKDIF_SHIFT))&UART_S2_LBKDIF_MASK)
  /* C3 Bit Fields */
  #define UART_C3_PEIE_MASK                        0x1u
  #define UART_C3_PEIE_SHIFT                       0
  #define UART_C3_PEIE_WIDTH                       1
  #define UART_C3_PEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_PEIE_SHIFT))&UART_C3_PEIE_MASK)
  #define UART_C3_FEIE_MASK                        0x2u
  #define UART_C3_FEIE_SHIFT                       1
  #define UART_C3_FEIE_WIDTH                       1
  #define UART_C3_FEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_FEIE_SHIFT))&UART_C3_FEIE_MASK)
  #define UART_C3_NEIE_MASK                        0x4u
  #define UART_C3_NEIE_SHIFT                       2
  #define UART_C3_NEIE_WIDTH                       1
  #define UART_C3_NEIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_NEIE_SHIFT))&UART_C3_NEIE_MASK)
  #define UART_C3_ORIE_MASK                        0x8u
  #define UART_C3_ORIE_SHIFT                       3
  #define UART_C3_ORIE_WIDTH                       1
  #define UART_C3_ORIE(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C3_ORIE_SHIFT))&UART_C3_ORIE_MASK)
  #define UART_C3_TXINV_MASK                       0x10u
  #define UART_C3_TXINV_SHIFT                      4
  #define UART_C3_TXINV_WIDTH                      1
  #define UART_C3_TXINV(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXINV_SHIFT))&UART_C3_TXINV_MASK)
  #define UART_C3_TXDIR_MASK                       0x20u
  #define UART_C3_TXDIR_SHIFT                      5
  #define UART_C3_TXDIR_WIDTH                      1
  #define UART_C3_TXDIR(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C3_TXDIR_SHIFT))&UART_C3_TXDIR_MASK)
  #define UART_C3_T8_MASK                          0x40u
  #define UART_C3_T8_SHIFT                         6
  #define UART_C3_T8_WIDTH                         1
  #define UART_C3_T8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_T8_SHIFT))&UART_C3_T8_MASK)
  #define UART_C3_R8_MASK                          0x80u
  #define UART_C3_R8_SHIFT                         7
  #define UART_C3_R8_WIDTH                         1
  #define UART_C3_R8(x)                            (((uint8_t)(((uint8_t)(x))<<UART_C3_R8_SHIFT))&UART_C3_R8_MASK)
  /* D Bit Fields */
  #define UART_D_RT_MASK                           0xFFu
  #define UART_D_RT_SHIFT                          0
  #define UART_D_RT_WIDTH                          8
  #define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
  /* MA1 Bit Fields */
  #define UART_MA1_MA_MASK                         0xFFu
  #define UART_MA1_MA_SHIFT                        0
  #define UART_MA1_MA_WIDTH                        8
  #define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
  /* MA2 Bit Fields */
  #define UART_MA2_MA_MASK                         0xFFu
  #define UART_MA2_MA_SHIFT                        0
  #define UART_MA2_MA_WIDTH                        8
  #define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
  /* C4 Bit Fields */
  #define UART_C4_BRFA_MASK                        0x1Fu
  #define UART_C4_BRFA_SHIFT                       0
  #define UART_C4_BRFA_WIDTH                       5
  #define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
  #define UART_C4_M10_MASK                         0x20u
  #define UART_C4_M10_SHIFT                        5
  #define UART_C4_M10_WIDTH                        1
  #define UART_C4_M10(x)                           (((uint8_t)(((uint8_t)(x))<<UART_C4_M10_SHIFT))&UART_C4_M10_MASK)
  #define UART_C4_MAEN2_MASK                       0x40u
  #define UART_C4_MAEN2_SHIFT                      6
  #define UART_C4_MAEN2_WIDTH                      1
  #define UART_C4_MAEN2(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN2_SHIFT))&UART_C4_MAEN2_MASK)
  #define UART_C4_MAEN1_MASK                       0x80u
  #define UART_C4_MAEN1_SHIFT                      7
  #define UART_C4_MAEN1_WIDTH                      1
  #define UART_C4_MAEN1(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C4_MAEN1_SHIFT))&UART_C4_MAEN1_MASK)
  /* C5 Bit Fields */
  #define UART_C5_LBKDDMAS_MASK                    0x8u
  #define UART_C5_LBKDDMAS_SHIFT                   3
  #define UART_C5_LBKDDMAS_WIDTH                   1
  #define UART_C5_LBKDDMAS(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C5_LBKDDMAS_SHIFT))&UART_C5_LBKDDMAS_MASK)
  #define UART_C5_RDMAS_MASK                       0x20u
  #define UART_C5_RDMAS_SHIFT                      5
  #define UART_C5_RDMAS_WIDTH                      1
  #define UART_C5_RDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_RDMAS_SHIFT))&UART_C5_RDMAS_MASK)
  #define UART_C5_TDMAS_MASK                       0x80u
  #define UART_C5_TDMAS_SHIFT                      7
  #define UART_C5_TDMAS_WIDTH                      1
  #define UART_C5_TDMAS(x)                         (((uint8_t)(((uint8_t)(x))<<UART_C5_TDMAS_SHIFT))&UART_C5_TDMAS_MASK)
  /* ED Bit Fields */
  #define UART_ED_PARITYE_MASK                     0x40u
  #define UART_ED_PARITYE_SHIFT                    6
  #define UART_ED_PARITYE_WIDTH                    1
  #define UART_ED_PARITYE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_ED_PARITYE_SHIFT))&UART_ED_PARITYE_MASK)
  #define UART_ED_NOISY_MASK                       0x80u
  #define UART_ED_NOISY_SHIFT                      7
  #define UART_ED_NOISY_WIDTH                      1
  #define UART_ED_NOISY(x)                         (((uint8_t)(((uint8_t)(x))<<UART_ED_NOISY_SHIFT))&UART_ED_NOISY_MASK)
  /* MODEM Bit Fields */
  #define UART_MODEM_TXCTSE_MASK                   0x1u
  #define UART_MODEM_TXCTSE_SHIFT                  0
  #define UART_MODEM_TXCTSE_WIDTH                  1
  #define UART_MODEM_TXCTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXCTSE_SHIFT))&UART_MODEM_TXCTSE_MASK)
  #define UART_MODEM_TXRTSE_MASK                   0x2u
  #define UART_MODEM_TXRTSE_SHIFT                  1
  #define UART_MODEM_TXRTSE_WIDTH                  1
  #define UART_MODEM_TXRTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSE_SHIFT))&UART_MODEM_TXRTSE_MASK)
  #define UART_MODEM_TXRTSPOL_MASK                 0x4u
  #define UART_MODEM_TXRTSPOL_SHIFT                2
  #define UART_MODEM_TXRTSPOL_WIDTH                1
  #define UART_MODEM_TXRTSPOL(x)                   (((uint8_t)(((uint8_t)(x))<<UART_MODEM_TXRTSPOL_SHIFT))&UART_MODEM_TXRTSPOL_MASK)
  #define UART_MODEM_RXRTSE_MASK                   0x8u
  #define UART_MODEM_RXRTSE_SHIFT                  3
  #define UART_MODEM_RXRTSE_WIDTH                  1
  #define UART_MODEM_RXRTSE(x)                     (((uint8_t)(((uint8_t)(x))<<UART_MODEM_RXRTSE_SHIFT))&UART_MODEM_RXRTSE_MASK)
  /* IR Bit Fields */
  #define UART_IR_TNP_MASK                         0x3u
  #define UART_IR_TNP_SHIFT                        0
  #define UART_IR_TNP_WIDTH                        2
  #define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
  #define UART_IR_IREN_MASK                        0x4u
  #define UART_IR_IREN_SHIFT                       2
  #define UART_IR_IREN_WIDTH                       1
  #define UART_IR_IREN(x)                          (((uint8_t)(((uint8_t)(x))<<UART_IR_IREN_SHIFT))&UART_IR_IREN_MASK)
  /* PFIFO Bit Fields */
  #define UART_PFIFO_RXFIFOSIZE_MASK               0x7u
  #define UART_PFIFO_RXFIFOSIZE_SHIFT              0
  #define UART_PFIFO_RXFIFOSIZE_WIDTH              3
  #define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
  #define UART_PFIFO_RXFE_MASK                     0x8u
  #define UART_PFIFO_RXFE_SHIFT                    3
  #define UART_PFIFO_RXFE_WIDTH                    1
  #define UART_PFIFO_RXFE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFE_SHIFT))&UART_PFIFO_RXFE_MASK)
  #define UART_PFIFO_TXFIFOSIZE_MASK               0x70u
  #define UART_PFIFO_TXFIFOSIZE_SHIFT              4
  #define UART_PFIFO_TXFIFOSIZE_WIDTH              3
  #define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
  #define UART_PFIFO_TXFE_MASK                     0x80u
  #define UART_PFIFO_TXFE_SHIFT                    7
  #define UART_PFIFO_TXFE_WIDTH                    1
  #define UART_PFIFO_TXFE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFE_SHIFT))&UART_PFIFO_TXFE_MASK)
  /* CFIFO Bit Fields */
  #define UART_CFIFO_RXUFE_MASK                    0x1u
  #define UART_CFIFO_RXUFE_SHIFT                   0
  #define UART_CFIFO_RXUFE_WIDTH                   1
  #define UART_CFIFO_RXUFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXUFE_SHIFT))&UART_CFIFO_RXUFE_MASK)
  #define UART_CFIFO_TXOFE_MASK                    0x2u
  #define UART_CFIFO_TXOFE_SHIFT                   1
  #define UART_CFIFO_TXOFE_WIDTH                   1
  #define UART_CFIFO_TXOFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXOFE_SHIFT))&UART_CFIFO_TXOFE_MASK)
  #define UART_CFIFO_RXOFE_MASK                    0x4u
  #define UART_CFIFO_RXOFE_SHIFT                   2
  #define UART_CFIFO_RXOFE_WIDTH                   1
  #define UART_CFIFO_RXOFE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXOFE_SHIFT))&UART_CFIFO_RXOFE_MASK)
  #define UART_CFIFO_RXFLUSH_MASK                  0x40u
  #define UART_CFIFO_RXFLUSH_SHIFT                 6
  #define UART_CFIFO_RXFLUSH_WIDTH                 1
  #define UART_CFIFO_RXFLUSH(x)                    (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_RXFLUSH_SHIFT))&UART_CFIFO_RXFLUSH_MASK)
  #define UART_CFIFO_TXFLUSH_MASK                  0x80u
  #define UART_CFIFO_TXFLUSH_SHIFT                 7
  #define UART_CFIFO_TXFLUSH_WIDTH                 1
  #define UART_CFIFO_TXFLUSH(x)                    (((uint8_t)(((uint8_t)(x))<<UART_CFIFO_TXFLUSH_SHIFT))&UART_CFIFO_TXFLUSH_MASK)
  /* SFIFO Bit Fields */
  #define UART_SFIFO_RXUF_MASK                     0x1u
  #define UART_SFIFO_RXUF_SHIFT                    0
  #define UART_SFIFO_RXUF_WIDTH                    1
  #define UART_SFIFO_RXUF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXUF_SHIFT))&UART_SFIFO_RXUF_MASK)
  #define UART_SFIFO_TXOF_MASK                     0x2u
  #define UART_SFIFO_TXOF_SHIFT                    1
  #define UART_SFIFO_TXOF_WIDTH                    1
  #define UART_SFIFO_TXOF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXOF_SHIFT))&UART_SFIFO_TXOF_MASK)
  #define UART_SFIFO_RXOF_MASK                     0x4u
  #define UART_SFIFO_RXOF_SHIFT                    2
  #define UART_SFIFO_RXOF_WIDTH                    1
  #define UART_SFIFO_RXOF(x)                       (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXOF_SHIFT))&UART_SFIFO_RXOF_MASK)
  #define UART_SFIFO_RXEMPT_MASK                   0x40u
  #define UART_SFIFO_RXEMPT_SHIFT                  6
  #define UART_SFIFO_RXEMPT_WIDTH                  1
  #define UART_SFIFO_RXEMPT(x)                     (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_RXEMPT_SHIFT))&UART_SFIFO_RXEMPT_MASK)
  #define UART_SFIFO_TXEMPT_MASK                   0x80u
  #define UART_SFIFO_TXEMPT_SHIFT                  7
  #define UART_SFIFO_TXEMPT_WIDTH                  1
  #define UART_SFIFO_TXEMPT(x)                     (((uint8_t)(((uint8_t)(x))<<UART_SFIFO_TXEMPT_SHIFT))&UART_SFIFO_TXEMPT_MASK)
  /* TWFIFO Bit Fields */
  #define UART_TWFIFO_TXWATER_MASK                 0xFFu
  #define UART_TWFIFO_TXWATER_SHIFT                0
  #define UART_TWFIFO_TXWATER_WIDTH                8
  #define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
  /* TCFIFO Bit Fields */
  #define UART_TCFIFO_TXCOUNT_MASK                 0xFFu
  #define UART_TCFIFO_TXCOUNT_SHIFT                0
  #define UART_TCFIFO_TXCOUNT_WIDTH                8
  #define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
  /* RWFIFO Bit Fields */
  #define UART_RWFIFO_RXWATER_MASK                 0xFFu
  #define UART_RWFIFO_RXWATER_SHIFT                0
  #define UART_RWFIFO_RXWATER_WIDTH                8
  #define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
  /* RCFIFO Bit Fields */
  #define UART_RCFIFO_RXCOUNT_MASK                 0xFFu
  #define UART_RCFIFO_RXCOUNT_SHIFT                0
  #define UART_RCFIFO_RXCOUNT_WIDTH                8
  #define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
  /* C7816 Bit Fields */
  #define UART_C7816_ISO_7816E_MASK                0x1u
  #define UART_C7816_ISO_7816E_SHIFT               0
  #define UART_C7816_ISO_7816E_WIDTH               1
  #define UART_C7816_ISO_7816E(x)                  (((uint8_t)(((uint8_t)(x))<<UART_C7816_ISO_7816E_SHIFT))&UART_C7816_ISO_7816E_MASK)
  #define UART_C7816_TTYPE_MASK                    0x2u
  #define UART_C7816_TTYPE_SHIFT                   1
  #define UART_C7816_TTYPE_WIDTH                   1
  #define UART_C7816_TTYPE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_TTYPE_SHIFT))&UART_C7816_TTYPE_MASK)
  #define UART_C7816_INIT_MASK                     0x4u
  #define UART_C7816_INIT_SHIFT                    2
  #define UART_C7816_INIT_WIDTH                    1
  #define UART_C7816_INIT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_C7816_INIT_SHIFT))&UART_C7816_INIT_MASK)
  #define UART_C7816_ANACK_MASK                    0x8u
  #define UART_C7816_ANACK_SHIFT                   3
  #define UART_C7816_ANACK_WIDTH                   1
  #define UART_C7816_ANACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ANACK_SHIFT))&UART_C7816_ANACK_MASK)
  #define UART_C7816_ONACK_MASK                    0x10u
  #define UART_C7816_ONACK_SHIFT                   4
  #define UART_C7816_ONACK_WIDTH                   1
  #define UART_C7816_ONACK(x)                      (((uint8_t)(((uint8_t)(x))<<UART_C7816_ONACK_SHIFT))&UART_C7816_ONACK_MASK)
  /* IE7816 Bit Fields */
  #define UART_IE7816_RXTE_MASK                    0x1u
  #define UART_IE7816_RXTE_SHIFT                   0
  #define UART_IE7816_RXTE_WIDTH                   1
  #define UART_IE7816_RXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_RXTE_SHIFT))&UART_IE7816_RXTE_MASK)
  #define UART_IE7816_TXTE_MASK                    0x2u
  #define UART_IE7816_TXTE_SHIFT                   1
  #define UART_IE7816_TXTE_WIDTH                   1
  #define UART_IE7816_TXTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_TXTE_SHIFT))&UART_IE7816_TXTE_MASK)
  #define UART_IE7816_GTVE_MASK                    0x4u
  #define UART_IE7816_GTVE_SHIFT                   2
  #define UART_IE7816_GTVE_WIDTH                   1
  #define UART_IE7816_GTVE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_GTVE_SHIFT))&UART_IE7816_GTVE_MASK)
  #define UART_IE7816_ADTE_MASK                    0x8u
  #define UART_IE7816_ADTE_SHIFT                   3
  #define UART_IE7816_ADTE_WIDTH                   1
  #define UART_IE7816_ADTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_ADTE_SHIFT))&UART_IE7816_ADTE_MASK)
  #define UART_IE7816_INITDE_MASK                  0x10u
  #define UART_IE7816_INITDE_SHIFT                 4
  #define UART_IE7816_INITDE_WIDTH                 1
  #define UART_IE7816_INITDE(x)                    (((uint8_t)(((uint8_t)(x))<<UART_IE7816_INITDE_SHIFT))&UART_IE7816_INITDE_MASK)
  #define UART_IE7816_BWTE_MASK                    0x20u
  #define UART_IE7816_BWTE_SHIFT                   5
  #define UART_IE7816_BWTE_WIDTH                   1
  #define UART_IE7816_BWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_BWTE_SHIFT))&UART_IE7816_BWTE_MASK)
  #define UART_IE7816_CWTE_MASK                    0x40u
  #define UART_IE7816_CWTE_SHIFT                   6
  #define UART_IE7816_CWTE_WIDTH                   1
  #define UART_IE7816_CWTE(x)                      (((uint8_t)(((uint8_t)(x))<<UART_IE7816_CWTE_SHIFT))&UART_IE7816_CWTE_MASK)
  #define UART_IE7816_WTE_MASK                     0x80u
  #define UART_IE7816_WTE_SHIFT                    7
  #define UART_IE7816_WTE_WIDTH                    1
  #define UART_IE7816_WTE(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IE7816_WTE_SHIFT))&UART_IE7816_WTE_MASK)
  /* IS7816 Bit Fields */
  #define UART_IS7816_RXT_MASK                     0x1u
  #define UART_IS7816_RXT_SHIFT                    0
  #define UART_IS7816_RXT_WIDTH                    1
  #define UART_IS7816_RXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_RXT_SHIFT))&UART_IS7816_RXT_MASK)
  #define UART_IS7816_TXT_MASK                     0x2u
  #define UART_IS7816_TXT_SHIFT                    1
  #define UART_IS7816_TXT_WIDTH                    1
  #define UART_IS7816_TXT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_TXT_SHIFT))&UART_IS7816_TXT_MASK)
  #define UART_IS7816_GTV_MASK                     0x4u
  #define UART_IS7816_GTV_SHIFT                    2
  #define UART_IS7816_GTV_WIDTH                    1
  #define UART_IS7816_GTV(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_GTV_SHIFT))&UART_IS7816_GTV_MASK)
  #define UART_IS7816_ADT_MASK                     0x8u
  #define UART_IS7816_ADT_SHIFT                    3
  #define UART_IS7816_ADT_WIDTH                    1
  #define UART_IS7816_ADT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_ADT_SHIFT))&UART_IS7816_ADT_MASK)
  #define UART_IS7816_INITD_MASK                   0x10u
  #define UART_IS7816_INITD_SHIFT                  4
  #define UART_IS7816_INITD_WIDTH                  1
  #define UART_IS7816_INITD(x)                     (((uint8_t)(((uint8_t)(x))<<UART_IS7816_INITD_SHIFT))&UART_IS7816_INITD_MASK)
  #define UART_IS7816_BWT_MASK                     0x20u
  #define UART_IS7816_BWT_SHIFT                    5
  #define UART_IS7816_BWT_WIDTH                    1
  #define UART_IS7816_BWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_BWT_SHIFT))&UART_IS7816_BWT_MASK)
  #define UART_IS7816_CWT_MASK                     0x40u
  #define UART_IS7816_CWT_SHIFT                    6
  #define UART_IS7816_CWT_WIDTH                    1
  #define UART_IS7816_CWT(x)                       (((uint8_t)(((uint8_t)(x))<<UART_IS7816_CWT_SHIFT))&UART_IS7816_CWT_MASK)
  #define UART_IS7816_WT_MASK                      0x80u
  #define UART_IS7816_WT_SHIFT                     7
  #define UART_IS7816_WT_WIDTH                     1
  #define UART_IS7816_WT(x)                        (((uint8_t)(((uint8_t)(x))<<UART_IS7816_WT_SHIFT))&UART_IS7816_WT_MASK)
  /* WP7816 Bit Fields */
  #define UART_WP7816_WTX_MASK                     0xFFu
  #define UART_WP7816_WTX_SHIFT                    0
  #define UART_WP7816_WTX_WIDTH                    8
  #define UART_WP7816_WTX(x)                       (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
  /* WN7816 Bit Fields */
  #define UART_WN7816_GTN_MASK                     0xFFu
  #define UART_WN7816_GTN_SHIFT                    0
  #define UART_WN7816_GTN_WIDTH                    8
  #define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
  /* WF7816 Bit Fields */
  #define UART_WF7816_GTFD_MASK                    0xFFu
  #define UART_WF7816_GTFD_SHIFT                   0
  #define UART_WF7816_GTFD_WIDTH                   8
  #define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
  /* ET7816 Bit Fields */
  #define UART_ET7816_RXTHRESHOLD_MASK             0xFu
  #define UART_ET7816_RXTHRESHOLD_SHIFT            0
  #define UART_ET7816_RXTHRESHOLD_WIDTH            4
  #define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
  #define UART_ET7816_TXTHRESHOLD_MASK             0xF0u
  #define UART_ET7816_TXTHRESHOLD_SHIFT            4
  #define UART_ET7816_TXTHRESHOLD_WIDTH            4
  #define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
  /* TL7816 Bit Fields */
  #define UART_TL7816_TLEN_MASK                    0xFFu
  #define UART_TL7816_TLEN_SHIFT                   0
  #define UART_TL7816_TLEN_WIDTH                   8
  #define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
  /* AP7816A_T0 Bit Fields */
  #define UART_AP7816A_T0_ADTI_H_MASK              0xFFu
  #define UART_AP7816A_T0_ADTI_H_SHIFT             0
  #define UART_AP7816A_T0_ADTI_H_WIDTH             8
  #define UART_AP7816A_T0_ADTI_H(x)                (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
  /* AP7816B_T0 Bit Fields */
  #define UART_AP7816B_T0_ADTI_L_MASK              0xFFu
  #define UART_AP7816B_T0_ADTI_L_SHIFT             0
  #define UART_AP7816B_T0_ADTI_L_WIDTH             8
  #define UART_AP7816B_T0_ADTI_L(x)                (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
  /* WP7816A_T0 Bit Fields */
  #define UART_WP7816A_T0_WI_H_MASK                0xFFu
  #define UART_WP7816A_T0_WI_H_SHIFT               0
  #define UART_WP7816A_T0_WI_H_WIDTH               8
  #define UART_WP7816A_T0_WI_H(x)                  (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
  /* WP7816B_T0 Bit Fields */
  #define UART_WP7816B_T0_WI_L_MASK                0xFFu
  #define UART_WP7816B_T0_WI_L_SHIFT               0
  #define UART_WP7816B_T0_WI_L_WIDTH               8
  #define UART_WP7816B_T0_WI_L(x)                  (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
  /* WP7816A_T1 Bit Fields */
  #define UART_WP7816A_T1_BWI_H_MASK               0xFFu
  #define UART_WP7816A_T1_BWI_H_SHIFT              0
  #define UART_WP7816A_T1_BWI_H_WIDTH              8
  #define UART_WP7816A_T1_BWI_H(x)                 (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
  /* WP7816B_T1 Bit Fields */
  #define UART_WP7816B_T1_BWI_L_MASK               0xFFu
  #define UART_WP7816B_T1_BWI_L_SHIFT              0
  #define UART_WP7816B_T1_BWI_L_WIDTH              8
  #define UART_WP7816B_T1_BWI_L(x)                 (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
  /* WGP7816_T1 Bit Fields */
  #define UART_WGP7816_T1_BGI_MASK                 0xFu
  #define UART_WGP7816_T1_BGI_SHIFT                0
  #define UART_WGP7816_T1_BGI_WIDTH                4
  #define UART_WGP7816_T1_BGI(x)                   (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
  #define UART_WGP7816_T1_CWI1_MASK                0xF0u
  #define UART_WGP7816_T1_CWI1_SHIFT               4
  #define UART_WGP7816_T1_CWI1_WIDTH               4
  #define UART_WGP7816_T1_CWI1(x)                  (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
  /* WP7816C_T1 Bit Fields */
  #define UART_WP7816C_T1_CWI2_MASK                0x1Fu
  #define UART_WP7816C_T1_CWI2_SHIFT               0
  #define UART_WP7816C_T1_CWI2_WIDTH               5
  #define UART_WP7816C_T1_CWI2(x)                  (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
  
  /*!
   * @}
   */ /* end of group UART_Register_Masks */
  
  
  /* UART - Peripheral instance base addresses */
  /** Peripheral UART0 base address */
  #define UART0_BASE                               (0x4006A000u)
  /** Peripheral UART0 base pointer */
  #define UART0                                    ((UART_Type *)UART0_BASE)
  #define UART0_BASE_PTR                           (UART0)
  /** Peripheral UART1 base address */
  #define UART1_BASE                               (0x4006B000u)
  /** Peripheral UART1 base pointer */
  #define UART1                                    ((UART_Type *)UART1_BASE)
  #define UART1_BASE_PTR                           (UART1)
  /** Peripheral UART2 base address */
  #define UART2_BASE                               (0x4006C000u)
  /** Peripheral UART2 base pointer */
  #define UART2                                    ((UART_Type *)UART2_BASE)
  #define UART2_BASE_PTR                           (UART2)
  /** Array initializer of UART peripheral base addresses */
  #define UART_BASE_ADDRS                          { UART0_BASE, UART1_BASE, UART2_BASE }
  /** Array initializer of UART peripheral base pointers */
  #define UART_BASE_PTRS                           { UART0, UART1, UART2 }
  
  /* ----------------------------------------------------------------------------
     -- UART - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
   * @{
   */
  
  
  /* UART - Register instance definitions */
  /* UART0 */
  #define UART0_BDH                                UART_BDH_REG(UART0)
  #define UART0_BDL                                UART_BDL_REG(UART0)
  #define UART0_C1                                 UART_C1_REG(UART0)
  #define UART0_C2                                 UART_C2_REG(UART0)
  #define UART0_S1                                 UART_S1_REG(UART0)
  #define UART0_S2                                 UART_S2_REG(UART0)
  #define UART0_C3                                 UART_C3_REG(UART0)
  #define UART0_D                                  UART_D_REG(UART0)
  #define UART0_MA1                                UART_MA1_REG(UART0)
  #define UART0_MA2                                UART_MA2_REG(UART0)
  #define UART0_C4                                 UART_C4_REG(UART0)
  #define UART0_C5                                 UART_C5_REG(UART0)
  #define UART0_ED                                 UART_ED_REG(UART0)
  #define UART0_MODEM                              UART_MODEM_REG(UART0)
  #define UART0_IR                                 UART_IR_REG(UART0)
  #define UART0_PFIFO                              UART_PFIFO_REG(UART0)
  #define UART0_CFIFO                              UART_CFIFO_REG(UART0)
  #define UART0_SFIFO                              UART_SFIFO_REG(UART0)
  #define UART0_TWFIFO                             UART_TWFIFO_REG(UART0)
  #define UART0_TCFIFO                             UART_TCFIFO_REG(UART0)
  #define UART0_RWFIFO                             UART_RWFIFO_REG(UART0)
  #define UART0_RCFIFO                             UART_RCFIFO_REG(UART0)
  #define UART0_C7816                              UART_C7816_REG(UART0)
  #define UART0_IE7816                             UART_IE7816_REG(UART0)
  #define UART0_IS7816                             UART_IS7816_REG(UART0)
  #define UART0_WP7816                             UART_WP7816_REG(UART0)
  #define UART0_WN7816                             UART_WN7816_REG(UART0)
  #define UART0_WF7816                             UART_WF7816_REG(UART0)
  #define UART0_ET7816                             UART_ET7816_REG(UART0)
  #define UART0_TL7816                             UART_TL7816_REG(UART0)
  #define UART0_AP7816A_T0                         UART_AP7816A_T0_REG(UART0)
  #define UART0_AP7816B_T0                         UART_AP7816B_T0_REG(UART0)
  #define UART0_WP7816A_T0                         UART_WP7816A_T0_REG(UART0)
  #define UART0_WP7816A_T1                         UART_WP7816A_T1_REG(UART0)
  #define UART0_WP7816B_T0                         UART_WP7816B_T0_REG(UART0)
  #define UART0_WP7816B_T1                         UART_WP7816B_T1_REG(UART0)
  #define UART0_WGP7816_T1                         UART_WGP7816_T1_REG(UART0)
  #define UART0_WP7816C_T1                         UART_WP7816C_T1_REG(UART0)
  /* UART1 */
  #define UART1_BDH                                UART_BDH_REG(UART1)
  #define UART1_BDL                                UART_BDL_REG(UART1)
  #define UART1_C1                                 UART_C1_REG(UART1)
  #define UART1_C2                                 UART_C2_REG(UART1)
  #define UART1_S1                                 UART_S1_REG(UART1)
  #define UART1_S2                                 UART_S2_REG(UART1)
  #define UART1_C3                                 UART_C3_REG(UART1)
  #define UART1_D                                  UART_D_REG(UART1)
  #define UART1_MA1                                UART_MA1_REG(UART1)
  #define UART1_MA2                                UART_MA2_REG(UART1)
  #define UART1_C4                                 UART_C4_REG(UART1)
  #define UART1_C5                                 UART_C5_REG(UART1)
  #define UART1_ED                                 UART_ED_REG(UART1)
  #define UART1_MODEM                              UART_MODEM_REG(UART1)
  #define UART1_IR                                 UART_IR_REG(UART1)
  #define UART1_PFIFO                              UART_PFIFO_REG(UART1)
  #define UART1_CFIFO                              UART_CFIFO_REG(UART1)
  #define UART1_SFIFO                              UART_SFIFO_REG(UART1)
  #define UART1_TWFIFO                             UART_TWFIFO_REG(UART1)
  #define UART1_TCFIFO                             UART_TCFIFO_REG(UART1)
  #define UART1_RWFIFO                             UART_RWFIFO_REG(UART1)
  #define UART1_RCFIFO                             UART_RCFIFO_REG(UART1)
  /* UART2 */
  #define UART2_BDH                                UART_BDH_REG(UART2)
  #define UART2_BDL                                UART_BDL_REG(UART2)
  #define UART2_C1                                 UART_C1_REG(UART2)
  #define UART2_C2                                 UART_C2_REG(UART2)
  #define UART2_S1                                 UART_S1_REG(UART2)
  #define UART2_S2                                 UART_S2_REG(UART2)
  #define UART2_C3                                 UART_C3_REG(UART2)
  #define UART2_D                                  UART_D_REG(UART2)
  #define UART2_MA1                                UART_MA1_REG(UART2)
  #define UART2_MA2                                UART_MA2_REG(UART2)
  #define UART2_C4                                 UART_C4_REG(UART2)
  #define UART2_C5                                 UART_C5_REG(UART2)
  #define UART2_ED                                 UART_ED_REG(UART2)
  #define UART2_MODEM                              UART_MODEM_REG(UART2)
  #define UART2_IR                                 UART_IR_REG(UART2)
  #define UART2_PFIFO                              UART_PFIFO_REG(UART2)
  #define UART2_CFIFO                              UART_CFIFO_REG(UART2)
  #define UART2_SFIFO                              UART_SFIFO_REG(UART2)
  #define UART2_TWFIFO                             UART_TWFIFO_REG(UART2)
  #define UART2_TCFIFO                             UART_TCFIFO_REG(UART2)
  #define UART2_RWFIFO                             UART_RWFIFO_REG(UART2)
  #define UART2_RCFIFO                             UART_RCFIFO_REG(UART2)
  
  /*!
   * @}
   */ /* end of group UART_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group UART_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- USB Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
   * @{
   */
  
  /** USB - Register Layout Typedef */
  typedef struct {
    __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
         uint8_t RESERVED_0[3];
    __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
         uint8_t RESERVED_1[3];
    __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
         uint8_t RESERVED_2[3];
    __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
         uint8_t RESERVED_3[3];
    __IO uint8_t OTGISTAT;                           /**< OTG Interrupt Status register, offset: 0x10 */
         uint8_t RESERVED_4[3];
    __IO uint8_t OTGICR;                             /**< OTG Interrupt Control register, offset: 0x14 */
         uint8_t RESERVED_5[3];
    __IO uint8_t OTGSTAT;                            /**< OTG Status register, offset: 0x18 */
         uint8_t RESERVED_6[3];
    __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
         uint8_t RESERVED_7[99];
    __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
         uint8_t RESERVED_8[3];
    __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
         uint8_t RESERVED_9[3];
    __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
         uint8_t RESERVED_10[3];
    __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
         uint8_t RESERVED_11[3];
    __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
         uint8_t RESERVED_12[3];
    __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
         uint8_t RESERVED_13[3];
    __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
         uint8_t RESERVED_14[3];
    __IO uint8_t BDTPAGE1;                           /**< BDT Page register 1, offset: 0x9C */
         uint8_t RESERVED_15[3];
    __IO uint8_t FRMNUML;                            /**< Frame Number register Low, offset: 0xA0 */
         uint8_t RESERVED_16[3];
    __IO uint8_t FRMNUMH;                            /**< Frame Number register High, offset: 0xA4 */
         uint8_t RESERVED_17[3];
    __IO uint8_t TOKEN;                              /**< Token register, offset: 0xA8 */
         uint8_t RESERVED_18[3];
    __IO uint8_t SOFTHLD;                            /**< SOF Threshold register, offset: 0xAC */
         uint8_t RESERVED_19[3];
    __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
         uint8_t RESERVED_20[3];
    __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
         uint8_t RESERVED_21[11];
    struct {                                         /* offset: 0xC0, array step: 0x4 */
      __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
           uint8_t RESERVED_0[3];
    } ENDPOINT[16];
    __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
         uint8_t RESERVED_22[3];
    __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
         uint8_t RESERVED_23[3];
    __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
         uint8_t RESERVED_24[3];
    __IO uint8_t USBTRC0;                            /**< USB Transceiver Control register 0, offset: 0x10C */
         uint8_t RESERVED_25[7];
    __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust Register, offset: 0x114 */
         uint8_t RESERVED_26[23];
    __IO uint8_t MISCCTRL;                           /**< Miscellaneous Control register, offset: 0x12C */
         uint8_t RESERVED_27[3];
    __IO uint8_t STALL_IL_DIS;                       /**< Peripheral mode stall disable for endpoints 7 to 0 in IN direction, offset: 0x130 */
         uint8_t RESERVED_28[3];
    __IO uint8_t STALL_IH_DIS;                       /**< Peripheral mode stall disable for endpoints 15 to 8 in IN direction, offset: 0x134 */
         uint8_t RESERVED_29[3];
    __IO uint8_t STALL_OL_DIS;                       /**< Peripheral mode stall disable for endpoints 7 to 0 in OUT direction, offset: 0x138 */
         uint8_t RESERVED_30[3];
    __IO uint8_t STALL_OH_DIS;                       /**< Peripheral mode stall disable for endpoints 15 to 8 in OUT direction, offset: 0x13C */
         uint8_t RESERVED_31[3];
    __IO uint8_t CLK_RECOVER_CTRL;                   /**< USB Clock recovery control, offset: 0x140 */
         uint8_t RESERVED_32[3];
    __IO uint8_t CLK_RECOVER_IRC_EN;                 /**< IRC48M oscillator enable register, offset: 0x144 */
         uint8_t RESERVED_33[15];
    __IO uint8_t CLK_RECOVER_INT_EN;                 /**< Clock recovery combined interrupt enable, offset: 0x154 */
         uint8_t RESERVED_34[7];
    __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock recovery separated interrupt status, offset: 0x15C */
  } USB_Type, *USB_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- USB - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
   * @{
   */
  
  
  /* USB - Register accessors */
  #define USB_PERID_REG(base)                      ((base)->PERID)
  #define USB_IDCOMP_REG(base)                     ((base)->IDCOMP)
  #define USB_REV_REG(base)                        ((base)->REV)
  #define USB_ADDINFO_REG(base)                    ((base)->ADDINFO)
  #define USB_OTGISTAT_REG(base)                   ((base)->OTGISTAT)
  #define USB_OTGICR_REG(base)                     ((base)->OTGICR)
  #define USB_OTGSTAT_REG(base)                    ((base)->OTGSTAT)
  #define USB_OTGCTL_REG(base)                     ((base)->OTGCTL)
  #define USB_ISTAT_REG(base)                      ((base)->ISTAT)
  #define USB_INTEN_REG(base)                      ((base)->INTEN)
  #define USB_ERRSTAT_REG(base)                    ((base)->ERRSTAT)
  #define USB_ERREN_REG(base)                      ((base)->ERREN)
  #define USB_STAT_REG(base)                       ((base)->STAT)
  #define USB_CTL_REG(base)                        ((base)->CTL)
  #define USB_ADDR_REG(base)                       ((base)->ADDR)
  #define USB_BDTPAGE1_REG(base)                   ((base)->BDTPAGE1)
  #define USB_FRMNUML_REG(base)                    ((base)->FRMNUML)
  #define USB_FRMNUMH_REG(base)                    ((base)->FRMNUMH)
  #define USB_TOKEN_REG(base)                      ((base)->TOKEN)
  #define USB_SOFTHLD_REG(base)                    ((base)->SOFTHLD)
  #define USB_BDTPAGE2_REG(base)                   ((base)->BDTPAGE2)
  #define USB_BDTPAGE3_REG(base)                   ((base)->BDTPAGE3)
  #define USB_ENDPT_REG(base,index)                ((base)->ENDPOINT[index].ENDPT)
  #define USB_ENDPT_COUNT                          16
  #define USB_USBCTRL_REG(base)                    ((base)->USBCTRL)
  #define USB_OBSERVE_REG(base)                    ((base)->OBSERVE)
  #define USB_CONTROL_REG(base)                    ((base)->CONTROL)
  #define USB_USBTRC0_REG(base)                    ((base)->USBTRC0)
  #define USB_USBFRMADJUST_REG(base)               ((base)->USBFRMADJUST)
  #define USB_MISCCTRL_REG(base)                   ((base)->MISCCTRL)
  #define USB_STALL_IL_DIS_REG(base)               ((base)->STALL_IL_DIS)
  #define USB_STALL_IH_DIS_REG(base)               ((base)->STALL_IH_DIS)
  #define USB_STALL_OL_DIS_REG(base)               ((base)->STALL_OL_DIS)
  #define USB_STALL_OH_DIS_REG(base)               ((base)->STALL_OH_DIS)
  #define USB_CLK_RECOVER_CTRL_REG(base)           ((base)->CLK_RECOVER_CTRL)
  #define USB_CLK_RECOVER_IRC_EN_REG(base)         ((base)->CLK_RECOVER_IRC_EN)
  #define USB_CLK_RECOVER_INT_EN_REG(base)         ((base)->CLK_RECOVER_INT_EN)
  #define USB_CLK_RECOVER_INT_STATUS_REG(base)     ((base)->CLK_RECOVER_INT_STATUS)
  
  /*!
   * @}
   */ /* end of group USB_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- USB Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup USB_Register_Masks USB Register Masks
   * @{
   */
  
  /* PERID Bit Fields */
  #define USB_PERID_ID_MASK                        0x3Fu
  #define USB_PERID_ID_SHIFT                       0
  #define USB_PERID_ID_WIDTH                       6
  #define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
  /* IDCOMP Bit Fields */
  #define USB_IDCOMP_NID_MASK                      0x3Fu
  #define USB_IDCOMP_NID_SHIFT                     0
  #define USB_IDCOMP_NID_WIDTH                     6
  #define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
  /* REV Bit Fields */
  #define USB_REV_REV_MASK                         0xFFu
  #define USB_REV_REV_SHIFT                        0
  #define USB_REV_REV_WIDTH                        8
  #define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
  /* ADDINFO Bit Fields */
  #define USB_ADDINFO_IEHOST_MASK                  0x1u
  #define USB_ADDINFO_IEHOST_SHIFT                 0
  #define USB_ADDINFO_IEHOST_WIDTH                 1
  #define USB_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IEHOST_SHIFT))&USB_ADDINFO_IEHOST_MASK)
  /* OTGISTAT Bit Fields */
  #define USB_OTGISTAT_LINE_STATE_CHG_MASK         0x20u
  #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        5
  #define USB_OTGISTAT_LINE_STATE_CHG_WIDTH        1
  #define USB_OTGISTAT_LINE_STATE_CHG(x)           (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_LINE_STATE_CHG_SHIFT))&USB_OTGISTAT_LINE_STATE_CHG_MASK)
  #define USB_OTGISTAT_ONEMSEC_MASK                0x40u
  #define USB_OTGISTAT_ONEMSEC_SHIFT               6
  #define USB_OTGISTAT_ONEMSEC_WIDTH               1
  #define USB_OTGISTAT_ONEMSEC(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGISTAT_ONEMSEC_SHIFT))&USB_OTGISTAT_ONEMSEC_MASK)
  /* OTGICR Bit Fields */
  #define USB_OTGICR_LINESTATEEN_MASK              0x20u
  #define USB_OTGICR_LINESTATEEN_SHIFT             5
  #define USB_OTGICR_LINESTATEEN_WIDTH             1
  #define USB_OTGICR_LINESTATEEN(x)                (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_LINESTATEEN_SHIFT))&USB_OTGICR_LINESTATEEN_MASK)
  #define USB_OTGICR_ONEMSECEN_MASK                0x40u
  #define USB_OTGICR_ONEMSECEN_SHIFT               6
  #define USB_OTGICR_ONEMSECEN_WIDTH               1
  #define USB_OTGICR_ONEMSECEN(x)                  (((uint8_t)(((uint8_t)(x))<<USB_OTGICR_ONEMSECEN_SHIFT))&USB_OTGICR_ONEMSECEN_MASK)
  /* OTGSTAT Bit Fields */
  #define USB_OTGSTAT_LINESTATESTABLE_MASK         0x20u
  #define USB_OTGSTAT_LINESTATESTABLE_SHIFT        5
  #define USB_OTGSTAT_LINESTATESTABLE_WIDTH        1
  #define USB_OTGSTAT_LINESTATESTABLE(x)           (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_LINESTATESTABLE_SHIFT))&USB_OTGSTAT_LINESTATESTABLE_MASK)
  #define USB_OTGSTAT_ONEMSECEN_MASK               0x40u
  #define USB_OTGSTAT_ONEMSECEN_SHIFT              6
  #define USB_OTGSTAT_ONEMSECEN_WIDTH              1
  #define USB_OTGSTAT_ONEMSECEN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_OTGSTAT_ONEMSECEN_SHIFT))&USB_OTGSTAT_ONEMSECEN_MASK)
  /* OTGCTL Bit Fields */
  #define USB_OTGCTL_OTGEN_MASK                    0x4u
  #define USB_OTGCTL_OTGEN_SHIFT                   2
  #define USB_OTGCTL_OTGEN_WIDTH                   1
  #define USB_OTGCTL_OTGEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_OTGEN_SHIFT))&USB_OTGCTL_OTGEN_MASK)
  #define USB_OTGCTL_DMLOW_MASK                    0x10u
  #define USB_OTGCTL_DMLOW_SHIFT                   4
  #define USB_OTGCTL_DMLOW_WIDTH                   1
  #define USB_OTGCTL_DMLOW(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DMLOW_SHIFT))&USB_OTGCTL_DMLOW_MASK)
  #define USB_OTGCTL_DPLOW_MASK                    0x20u
  #define USB_OTGCTL_DPLOW_SHIFT                   5
  #define USB_OTGCTL_DPLOW_WIDTH                   1
  #define USB_OTGCTL_DPLOW(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPLOW_SHIFT))&USB_OTGCTL_DPLOW_MASK)
  #define USB_OTGCTL_DPHIGH_MASK                   0x80u
  #define USB_OTGCTL_DPHIGH_SHIFT                  7
  #define USB_OTGCTL_DPHIGH_WIDTH                  1
  #define USB_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x))<<USB_OTGCTL_DPHIGH_SHIFT))&USB_OTGCTL_DPHIGH_MASK)
  /* ISTAT Bit Fields */
  #define USB_ISTAT_USBRST_MASK                    0x1u
  #define USB_ISTAT_USBRST_SHIFT                   0
  #define USB_ISTAT_USBRST_WIDTH                   1
  #define USB_ISTAT_USBRST(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_USBRST_SHIFT))&USB_ISTAT_USBRST_MASK)
  #define USB_ISTAT_ERROR_MASK                     0x2u
  #define USB_ISTAT_ERROR_SHIFT                    1
  #define USB_ISTAT_ERROR_WIDTH                    1
  #define USB_ISTAT_ERROR(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ERROR_SHIFT))&USB_ISTAT_ERROR_MASK)
  #define USB_ISTAT_SOFTOK_MASK                    0x4u
  #define USB_ISTAT_SOFTOK_SHIFT                   2
  #define USB_ISTAT_SOFTOK_WIDTH                   1
  #define USB_ISTAT_SOFTOK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SOFTOK_SHIFT))&USB_ISTAT_SOFTOK_MASK)
  #define USB_ISTAT_TOKDNE_MASK                    0x8u
  #define USB_ISTAT_TOKDNE_SHIFT                   3
  #define USB_ISTAT_TOKDNE_WIDTH                   1
  #define USB_ISTAT_TOKDNE(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_TOKDNE_SHIFT))&USB_ISTAT_TOKDNE_MASK)
  #define USB_ISTAT_SLEEP_MASK                     0x10u
  #define USB_ISTAT_SLEEP_SHIFT                    4
  #define USB_ISTAT_SLEEP_WIDTH                    1
  #define USB_ISTAT_SLEEP(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_SLEEP_SHIFT))&USB_ISTAT_SLEEP_MASK)
  #define USB_ISTAT_RESUME_MASK                    0x20u
  #define USB_ISTAT_RESUME_SHIFT                   5
  #define USB_ISTAT_RESUME_WIDTH                   1
  #define USB_ISTAT_RESUME(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_RESUME_SHIFT))&USB_ISTAT_RESUME_MASK)
  #define USB_ISTAT_ATTACH_MASK                    0x40u
  #define USB_ISTAT_ATTACH_SHIFT                   6
  #define USB_ISTAT_ATTACH_WIDTH                   1
  #define USB_ISTAT_ATTACH(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_ATTACH_SHIFT))&USB_ISTAT_ATTACH_MASK)
  #define USB_ISTAT_STALL_MASK                     0x80u
  #define USB_ISTAT_STALL_SHIFT                    7
  #define USB_ISTAT_STALL_WIDTH                    1
  #define USB_ISTAT_STALL(x)                       (((uint8_t)(((uint8_t)(x))<<USB_ISTAT_STALL_SHIFT))&USB_ISTAT_STALL_MASK)
  /* INTEN Bit Fields */
  #define USB_INTEN_USBRSTEN_MASK                  0x1u
  #define USB_INTEN_USBRSTEN_SHIFT                 0
  #define USB_INTEN_USBRSTEN_WIDTH                 1
  #define USB_INTEN_USBRSTEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_USBRSTEN_SHIFT))&USB_INTEN_USBRSTEN_MASK)
  #define USB_INTEN_ERROREN_MASK                   0x2u
  #define USB_INTEN_ERROREN_SHIFT                  1
  #define USB_INTEN_ERROREN_WIDTH                  1
  #define USB_INTEN_ERROREN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ERROREN_SHIFT))&USB_INTEN_ERROREN_MASK)
  #define USB_INTEN_SOFTOKEN_MASK                  0x4u
  #define USB_INTEN_SOFTOKEN_SHIFT                 2
  #define USB_INTEN_SOFTOKEN_WIDTH                 1
  #define USB_INTEN_SOFTOKEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SOFTOKEN_SHIFT))&USB_INTEN_SOFTOKEN_MASK)
  #define USB_INTEN_TOKDNEEN_MASK                  0x8u
  #define USB_INTEN_TOKDNEEN_SHIFT                 3
  #define USB_INTEN_TOKDNEEN_WIDTH                 1
  #define USB_INTEN_TOKDNEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_TOKDNEEN_SHIFT))&USB_INTEN_TOKDNEEN_MASK)
  #define USB_INTEN_SLEEPEN_MASK                   0x10u
  #define USB_INTEN_SLEEPEN_SHIFT                  4
  #define USB_INTEN_SLEEPEN_WIDTH                  1
  #define USB_INTEN_SLEEPEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_SLEEPEN_SHIFT))&USB_INTEN_SLEEPEN_MASK)
  #define USB_INTEN_RESUMEEN_MASK                  0x20u
  #define USB_INTEN_RESUMEEN_SHIFT                 5
  #define USB_INTEN_RESUMEEN_WIDTH                 1
  #define USB_INTEN_RESUMEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_RESUMEEN_SHIFT))&USB_INTEN_RESUMEEN_MASK)
  #define USB_INTEN_ATTACHEN_MASK                  0x40u
  #define USB_INTEN_ATTACHEN_SHIFT                 6
  #define USB_INTEN_ATTACHEN_WIDTH                 1
  #define USB_INTEN_ATTACHEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_INTEN_ATTACHEN_SHIFT))&USB_INTEN_ATTACHEN_MASK)
  #define USB_INTEN_STALLEN_MASK                   0x80u
  #define USB_INTEN_STALLEN_SHIFT                  7
  #define USB_INTEN_STALLEN_WIDTH                  1
  #define USB_INTEN_STALLEN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_INTEN_STALLEN_SHIFT))&USB_INTEN_STALLEN_MASK)
  /* ERRSTAT Bit Fields */
  #define USB_ERRSTAT_PIDERR_MASK                  0x1u
  #define USB_ERRSTAT_PIDERR_SHIFT                 0
  #define USB_ERRSTAT_PIDERR_WIDTH                 1
  #define USB_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_PIDERR_SHIFT))&USB_ERRSTAT_PIDERR_MASK)
  #define USB_ERRSTAT_CRC5EOF_MASK                 0x2u
  #define USB_ERRSTAT_CRC5EOF_SHIFT                1
  #define USB_ERRSTAT_CRC5EOF_WIDTH                1
  #define USB_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC5EOF_SHIFT))&USB_ERRSTAT_CRC5EOF_MASK)
  #define USB_ERRSTAT_CRC16_MASK                   0x4u
  #define USB_ERRSTAT_CRC16_SHIFT                  2
  #define USB_ERRSTAT_CRC16_WIDTH                  1
  #define USB_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_CRC16_SHIFT))&USB_ERRSTAT_CRC16_MASK)
  #define USB_ERRSTAT_DFN8_MASK                    0x8u
  #define USB_ERRSTAT_DFN8_SHIFT                   3
  #define USB_ERRSTAT_DFN8_WIDTH                   1
  #define USB_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DFN8_SHIFT))&USB_ERRSTAT_DFN8_MASK)
  #define USB_ERRSTAT_BTOERR_MASK                  0x10u
  #define USB_ERRSTAT_BTOERR_SHIFT                 4
  #define USB_ERRSTAT_BTOERR_WIDTH                 1
  #define USB_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTOERR_SHIFT))&USB_ERRSTAT_BTOERR_MASK)
  #define USB_ERRSTAT_DMAERR_MASK                  0x20u
  #define USB_ERRSTAT_DMAERR_SHIFT                 5
  #define USB_ERRSTAT_DMAERR_WIDTH                 1
  #define USB_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_DMAERR_SHIFT))&USB_ERRSTAT_DMAERR_MASK)
  #define USB_ERRSTAT_OWNERR_MASK                  0x40u
  #define USB_ERRSTAT_OWNERR_SHIFT                 6
  #define USB_ERRSTAT_OWNERR_WIDTH                 1
  #define USB_ERRSTAT_OWNERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_OWNERR_SHIFT))&USB_ERRSTAT_OWNERR_MASK)
  #define USB_ERRSTAT_BTSERR_MASK                  0x80u
  #define USB_ERRSTAT_BTSERR_SHIFT                 7
  #define USB_ERRSTAT_BTSERR_WIDTH                 1
  #define USB_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERRSTAT_BTSERR_SHIFT))&USB_ERRSTAT_BTSERR_MASK)
  /* ERREN Bit Fields */
  #define USB_ERREN_PIDERREN_MASK                  0x1u
  #define USB_ERREN_PIDERREN_SHIFT                 0
  #define USB_ERREN_PIDERREN_WIDTH                 1
  #define USB_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_PIDERREN_SHIFT))&USB_ERREN_PIDERREN_MASK)
  #define USB_ERREN_CRC5EOFEN_MASK                 0x2u
  #define USB_ERREN_CRC5EOFEN_SHIFT                1
  #define USB_ERREN_CRC5EOFEN_WIDTH                1
  #define USB_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC5EOFEN_SHIFT))&USB_ERREN_CRC5EOFEN_MASK)
  #define USB_ERREN_CRC16EN_MASK                   0x4u
  #define USB_ERREN_CRC16EN_SHIFT                  2
  #define USB_ERREN_CRC16EN_WIDTH                  1
  #define USB_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ERREN_CRC16EN_SHIFT))&USB_ERREN_CRC16EN_MASK)
  #define USB_ERREN_DFN8EN_MASK                    0x8u
  #define USB_ERREN_DFN8EN_SHIFT                   3
  #define USB_ERREN_DFN8EN_WIDTH                   1
  #define USB_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DFN8EN_SHIFT))&USB_ERREN_DFN8EN_MASK)
  #define USB_ERREN_BTOERREN_MASK                  0x10u
  #define USB_ERREN_BTOERREN_SHIFT                 4
  #define USB_ERREN_BTOERREN_WIDTH                 1
  #define USB_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTOERREN_SHIFT))&USB_ERREN_BTOERREN_MASK)
  #define USB_ERREN_DMAERREN_MASK                  0x20u
  #define USB_ERREN_DMAERREN_SHIFT                 5
  #define USB_ERREN_DMAERREN_WIDTH                 1
  #define USB_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_DMAERREN_SHIFT))&USB_ERREN_DMAERREN_MASK)
  #define USB_ERREN_OWNERREN_MASK                  0x40u
  #define USB_ERREN_OWNERREN_SHIFT                 6
  #define USB_ERREN_OWNERREN_WIDTH                 1
  #define USB_ERREN_OWNERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_OWNERREN_SHIFT))&USB_ERREN_OWNERREN_MASK)
  #define USB_ERREN_BTSERREN_MASK                  0x80u
  #define USB_ERREN_BTSERREN_SHIFT                 7
  #define USB_ERREN_BTSERREN_WIDTH                 1
  #define USB_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ERREN_BTSERREN_SHIFT))&USB_ERREN_BTSERREN_MASK)
  /* STAT Bit Fields */
  #define USB_STAT_ODD_MASK                        0x4u
  #define USB_STAT_ODD_SHIFT                       2
  #define USB_STAT_ODD_WIDTH                       1
  #define USB_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x))<<USB_STAT_ODD_SHIFT))&USB_STAT_ODD_MASK)
  #define USB_STAT_TX_MASK                         0x8u
  #define USB_STAT_TX_SHIFT                        3
  #define USB_STAT_TX_WIDTH                        1
  #define USB_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x))<<USB_STAT_TX_SHIFT))&USB_STAT_TX_MASK)
  #define USB_STAT_ENDP_MASK                       0xF0u
  #define USB_STAT_ENDP_SHIFT                      4
  #define USB_STAT_ENDP_WIDTH                      4
  #define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
  /* CTL Bit Fields */
  #define USB_CTL_USBENSOFEN_MASK                  0x1u
  #define USB_CTL_USBENSOFEN_SHIFT                 0
  #define USB_CTL_USBENSOFEN_WIDTH                 1
  #define USB_CTL_USBENSOFEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_CTL_USBENSOFEN_SHIFT))&USB_CTL_USBENSOFEN_MASK)
  #define USB_CTL_ODDRST_MASK                      0x2u
  #define USB_CTL_ODDRST_SHIFT                     1
  #define USB_CTL_ODDRST_WIDTH                     1
  #define USB_CTL_ODDRST(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_ODDRST_SHIFT))&USB_CTL_ODDRST_MASK)
  #define USB_CTL_RESUME_MASK                      0x4u
  #define USB_CTL_RESUME_SHIFT                     2
  #define USB_CTL_RESUME_WIDTH                     1
  #define USB_CTL_RESUME(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESUME_SHIFT))&USB_CTL_RESUME_MASK)
  #define USB_CTL_HOSTMODEEN_MASK                  0x8u
  #define USB_CTL_HOSTMODEEN_SHIFT                 3
  #define USB_CTL_HOSTMODEEN_WIDTH                 1
  #define USB_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x))<<USB_CTL_HOSTMODEEN_SHIFT))&USB_CTL_HOSTMODEEN_MASK)
  #define USB_CTL_RESET_MASK                       0x10u
  #define USB_CTL_RESET_SHIFT                      4
  #define USB_CTL_RESET_WIDTH                      1
  #define USB_CTL_RESET(x)                         (((uint8_t)(((uint8_t)(x))<<USB_CTL_RESET_SHIFT))&USB_CTL_RESET_MASK)
  #define USB_CTL_TXSUSPENDTOKENBUSY_MASK          0x20u
  #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         5
  #define USB_CTL_TXSUSPENDTOKENBUSY_WIDTH         1
  #define USB_CTL_TXSUSPENDTOKENBUSY(x)            (((uint8_t)(((uint8_t)(x))<<USB_CTL_TXSUSPENDTOKENBUSY_SHIFT))&USB_CTL_TXSUSPENDTOKENBUSY_MASK)
  #define USB_CTL_SE0_MASK                         0x40u
  #define USB_CTL_SE0_SHIFT                        6
  #define USB_CTL_SE0_WIDTH                        1
  #define USB_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x))<<USB_CTL_SE0_SHIFT))&USB_CTL_SE0_MASK)
  #define USB_CTL_JSTATE_MASK                      0x80u
  #define USB_CTL_JSTATE_SHIFT                     7
  #define USB_CTL_JSTATE_WIDTH                     1
  #define USB_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x))<<USB_CTL_JSTATE_SHIFT))&USB_CTL_JSTATE_MASK)
  /* ADDR Bit Fields */
  #define USB_ADDR_ADDR_MASK                       0x7Fu
  #define USB_ADDR_ADDR_SHIFT                      0
  #define USB_ADDR_ADDR_WIDTH                      7
  #define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
  #define USB_ADDR_LSEN_MASK                       0x80u
  #define USB_ADDR_LSEN_SHIFT                      7
  #define USB_ADDR_LSEN_WIDTH                      1
  #define USB_ADDR_LSEN(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_LSEN_SHIFT))&USB_ADDR_LSEN_MASK)
  /* BDTPAGE1 Bit Fields */
  #define USB_BDTPAGE1_BDTBA_MASK                  0xFEu
  #define USB_BDTPAGE1_BDTBA_SHIFT                 1
  #define USB_BDTPAGE1_BDTBA_WIDTH                 7
  #define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
  /* FRMNUML Bit Fields */
  #define USB_FRMNUML_FRM_MASK                     0xFFu
  #define USB_FRMNUML_FRM_SHIFT                    0
  #define USB_FRMNUML_FRM_WIDTH                    8
  #define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
  /* FRMNUMH Bit Fields */
  #define USB_FRMNUMH_FRM_MASK                     0x7u
  #define USB_FRMNUMH_FRM_SHIFT                    0
  #define USB_FRMNUMH_FRM_WIDTH                    3
  #define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
  /* TOKEN Bit Fields */
  #define USB_TOKEN_TOKENENDPT_MASK                0xFu
  #define USB_TOKEN_TOKENENDPT_SHIFT               0
  #define USB_TOKEN_TOKENENDPT_WIDTH               4
  #define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
  #define USB_TOKEN_TOKENPID_MASK                  0xF0u
  #define USB_TOKEN_TOKENPID_SHIFT                 4
  #define USB_TOKEN_TOKENPID_WIDTH                 4
  #define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
  /* SOFTHLD Bit Fields */
  #define USB_SOFTHLD_CNT_MASK                     0xFFu
  #define USB_SOFTHLD_CNT_SHIFT                    0
  #define USB_SOFTHLD_CNT_WIDTH                    8
  #define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
  /* BDTPAGE2 Bit Fields */
  #define USB_BDTPAGE2_BDTBA_MASK                  0xFFu
  #define USB_BDTPAGE2_BDTBA_SHIFT                 0
  #define USB_BDTPAGE2_BDTBA_WIDTH                 8
  #define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
  /* BDTPAGE3 Bit Fields */
  #define USB_BDTPAGE3_BDTBA_MASK                  0xFFu
  #define USB_BDTPAGE3_BDTBA_SHIFT                 0
  #define USB_BDTPAGE3_BDTBA_WIDTH                 8
  #define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
  /* ENDPT Bit Fields */
  #define USB_ENDPT_EPHSHK_MASK                    0x1u
  #define USB_ENDPT_EPHSHK_SHIFT                   0
  #define USB_ENDPT_EPHSHK_WIDTH                   1
  #define USB_ENDPT_EPHSHK(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPHSHK_SHIFT))&USB_ENDPT_EPHSHK_MASK)
  #define USB_ENDPT_EPSTALL_MASK                   0x2u
  #define USB_ENDPT_EPSTALL_SHIFT                  1
  #define USB_ENDPT_EPSTALL_WIDTH                  1
  #define USB_ENDPT_EPSTALL(x)                     (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPSTALL_SHIFT))&USB_ENDPT_EPSTALL_MASK)
  #define USB_ENDPT_EPTXEN_MASK                    0x4u
  #define USB_ENDPT_EPTXEN_SHIFT                   2
  #define USB_ENDPT_EPTXEN_WIDTH                   1
  #define USB_ENDPT_EPTXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPTXEN_SHIFT))&USB_ENDPT_EPTXEN_MASK)
  #define USB_ENDPT_EPRXEN_MASK                    0x8u
  #define USB_ENDPT_EPRXEN_SHIFT                   3
  #define USB_ENDPT_EPRXEN_WIDTH                   1
  #define USB_ENDPT_EPRXEN(x)                      (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPRXEN_SHIFT))&USB_ENDPT_EPRXEN_MASK)
  #define USB_ENDPT_EPCTLDIS_MASK                  0x10u
  #define USB_ENDPT_EPCTLDIS_SHIFT                 4
  #define USB_ENDPT_EPCTLDIS_WIDTH                 1
  #define USB_ENDPT_EPCTLDIS(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_EPCTLDIS_SHIFT))&USB_ENDPT_EPCTLDIS_MASK)
  #define USB_ENDPT_RETRYDIS_MASK                  0x40u
  #define USB_ENDPT_RETRYDIS_SHIFT                 6
  #define USB_ENDPT_RETRYDIS_WIDTH                 1
  #define USB_ENDPT_RETRYDIS(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_RETRYDIS_SHIFT))&USB_ENDPT_RETRYDIS_MASK)
  #define USB_ENDPT_HOSTWOHUB_MASK                 0x80u
  #define USB_ENDPT_HOSTWOHUB_SHIFT                7
  #define USB_ENDPT_HOSTWOHUB_WIDTH                1
  #define USB_ENDPT_HOSTWOHUB(x)                   (((uint8_t)(((uint8_t)(x))<<USB_ENDPT_HOSTWOHUB_SHIFT))&USB_ENDPT_HOSTWOHUB_MASK)
  /* USBCTRL Bit Fields */
  #define USB_USBCTRL_UARTSEL_MASK                 0x10u
  #define USB_USBCTRL_UARTSEL_SHIFT                4
  #define USB_USBCTRL_UARTSEL_WIDTH                1
  #define USB_USBCTRL_UARTSEL(x)                   (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_UARTSEL_SHIFT))&USB_USBCTRL_UARTSEL_MASK)
  #define USB_USBCTRL_UARTCHLS_MASK                0x20u
  #define USB_USBCTRL_UARTCHLS_SHIFT               5
  #define USB_USBCTRL_UARTCHLS_WIDTH               1
  #define USB_USBCTRL_UARTCHLS(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_UARTCHLS_SHIFT))&USB_USBCTRL_UARTCHLS_MASK)
  #define USB_USBCTRL_PDE_MASK                     0x40u
  #define USB_USBCTRL_PDE_SHIFT                    6
  #define USB_USBCTRL_PDE_WIDTH                    1
  #define USB_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_PDE_SHIFT))&USB_USBCTRL_PDE_MASK)
  #define USB_USBCTRL_SUSP_MASK                    0x80u
  #define USB_USBCTRL_SUSP_SHIFT                   7
  #define USB_USBCTRL_SUSP_WIDTH                   1
  #define USB_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x))<<USB_USBCTRL_SUSP_SHIFT))&USB_USBCTRL_SUSP_MASK)
  /* OBSERVE Bit Fields */
  #define USB_OBSERVE_DMPD_MASK                    0x10u
  #define USB_OBSERVE_DMPD_SHIFT                   4
  #define USB_OBSERVE_DMPD_WIDTH                   1
  #define USB_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DMPD_SHIFT))&USB_OBSERVE_DMPD_MASK)
  #define USB_OBSERVE_DPPD_MASK                    0x40u
  #define USB_OBSERVE_DPPD_SHIFT                   6
  #define USB_OBSERVE_DPPD_WIDTH                   1
  #define USB_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPD_SHIFT))&USB_OBSERVE_DPPD_MASK)
  #define USB_OBSERVE_DPPU_MASK                    0x80u
  #define USB_OBSERVE_DPPU_SHIFT                   7
  #define USB_OBSERVE_DPPU_WIDTH                   1
  #define USB_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x))<<USB_OBSERVE_DPPU_SHIFT))&USB_OBSERVE_DPPU_MASK)
  /* CONTROL Bit Fields */
  #define USB_CONTROL_DPPULLUPNONOTG_MASK          0x10u
  #define USB_CONTROL_DPPULLUPNONOTG_SHIFT         4
  #define USB_CONTROL_DPPULLUPNONOTG_WIDTH         1
  #define USB_CONTROL_DPPULLUPNONOTG(x)            (((uint8_t)(((uint8_t)(x))<<USB_CONTROL_DPPULLUPNONOTG_SHIFT))&USB_CONTROL_DPPULLUPNONOTG_MASK)
  /* USBTRC0 Bit Fields */
  #define USB_USBTRC0_USB_RESUME_INT_MASK          0x1u
  #define USB_USBTRC0_USB_RESUME_INT_SHIFT         0
  #define USB_USBTRC0_USB_RESUME_INT_WIDTH         1
  #define USB_USBTRC0_USB_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_RESUME_INT_SHIFT))&USB_USBTRC0_USB_RESUME_INT_MASK)
  #define USB_USBTRC0_SYNC_DET_MASK                0x2u
  #define USB_USBTRC0_SYNC_DET_SHIFT               1
  #define USB_USBTRC0_SYNC_DET_WIDTH               1
  #define USB_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_SYNC_DET_SHIFT))&USB_USBTRC0_SYNC_DET_MASK)
  #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK    0x4u
  #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT   2
  #define USB_USBTRC0_USB_CLK_RECOVERY_INT_WIDTH   1
  #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT))&USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
  #define USB_USBTRC0_VREDG_DET_MASK               0x8u
  #define USB_USBTRC0_VREDG_DET_SHIFT              3
  #define USB_USBTRC0_VREDG_DET_WIDTH              1
  #define USB_USBTRC0_VREDG_DET(x)                 (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_VREDG_DET_SHIFT))&USB_USBTRC0_VREDG_DET_MASK)
  #define USB_USBTRC0_VFEDG_DET_MASK               0x10u
  #define USB_USBTRC0_VFEDG_DET_SHIFT              4
  #define USB_USBTRC0_VFEDG_DET_WIDTH              1
  #define USB_USBTRC0_VFEDG_DET(x)                 (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_VFEDG_DET_SHIFT))&USB_USBTRC0_VFEDG_DET_MASK)
  #define USB_USBTRC0_USBRESMEN_MASK               0x20u
  #define USB_USBTRC0_USBRESMEN_SHIFT              5
  #define USB_USBTRC0_USBRESMEN_WIDTH              1
  #define USB_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESMEN_SHIFT))&USB_USBTRC0_USBRESMEN_MASK)
  #define USB_USBTRC0_USBRESET_MASK                0x80u
  #define USB_USBTRC0_USBRESET_SHIFT               7
  #define USB_USBTRC0_USBRESET_WIDTH               1
  #define USB_USBTRC0_USBRESET(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBTRC0_USBRESET_SHIFT))&USB_USBTRC0_USBRESET_MASK)
  /* USBFRMADJUST Bit Fields */
  #define USB_USBFRMADJUST_ADJ_MASK                0xFFu
  #define USB_USBFRMADJUST_ADJ_SHIFT               0
  #define USB_USBFRMADJUST_ADJ_WIDTH               8
  #define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
  /* MISCCTRL Bit Fields */
  #define USB_MISCCTRL_SOFDYNTHLD_MASK             0x1u
  #define USB_MISCCTRL_SOFDYNTHLD_SHIFT            0
  #define USB_MISCCTRL_SOFDYNTHLD_WIDTH            1
  #define USB_MISCCTRL_SOFDYNTHLD(x)               (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_SOFDYNTHLD_SHIFT))&USB_MISCCTRL_SOFDYNTHLD_MASK)
  #define USB_MISCCTRL_SOFBUSSET_MASK              0x2u
  #define USB_MISCCTRL_SOFBUSSET_SHIFT             1
  #define USB_MISCCTRL_SOFBUSSET_WIDTH             1
  #define USB_MISCCTRL_SOFBUSSET(x)                (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_SOFBUSSET_SHIFT))&USB_MISCCTRL_SOFBUSSET_MASK)
  #define USB_MISCCTRL_OWNERRISODIS_MASK           0x4u
  #define USB_MISCCTRL_OWNERRISODIS_SHIFT          2
  #define USB_MISCCTRL_OWNERRISODIS_WIDTH          1
  #define USB_MISCCTRL_OWNERRISODIS(x)             (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_OWNERRISODIS_SHIFT))&USB_MISCCTRL_OWNERRISODIS_MASK)
  #define USB_MISCCTRL_VREDG_EN_MASK               0x8u
  #define USB_MISCCTRL_VREDG_EN_SHIFT              3
  #define USB_MISCCTRL_VREDG_EN_WIDTH              1
  #define USB_MISCCTRL_VREDG_EN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_VREDG_EN_SHIFT))&USB_MISCCTRL_VREDG_EN_MASK)
  #define USB_MISCCTRL_VFEDG_EN_MASK               0x10u
  #define USB_MISCCTRL_VFEDG_EN_SHIFT              4
  #define USB_MISCCTRL_VFEDG_EN_WIDTH              1
  #define USB_MISCCTRL_VFEDG_EN(x)                 (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_VFEDG_EN_SHIFT))&USB_MISCCTRL_VFEDG_EN_MASK)
  #define USB_MISCCTRL_STL_ADJ_EN_MASK             0x80u
  #define USB_MISCCTRL_STL_ADJ_EN_SHIFT            7
  #define USB_MISCCTRL_STL_ADJ_EN_WIDTH            1
  #define USB_MISCCTRL_STL_ADJ_EN(x)               (((uint8_t)(((uint8_t)(x))<<USB_MISCCTRL_STL_ADJ_EN_SHIFT))&USB_MISCCTRL_STL_ADJ_EN_MASK)
  /* STALL_IL_DIS Bit Fields */
  #define USB_STALL_IL_DIS_STALL_I_DIS0_MASK       0x1u
  #define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT      0
  #define USB_STALL_IL_DIS_STALL_I_DIS0_WIDTH      1
  #define USB_STALL_IL_DIS_STALL_I_DIS0(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS0_MASK)
  #define USB_STALL_IL_DIS_STALL_I_DIS1_MASK       0x2u
  #define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT      1
  #define USB_STALL_IL_DIS_STALL_I_DIS1_WIDTH      1
  #define USB_STALL_IL_DIS_STALL_I_DIS1(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS1_MASK)
  #define USB_STALL_IL_DIS_STALL_I_DIS2_MASK       0x4u
  #define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT      2
  #define USB_STALL_IL_DIS_STALL_I_DIS2_WIDTH      1
  #define USB_STALL_IL_DIS_STALL_I_DIS2(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS2_MASK)
  #define USB_STALL_IL_DIS_STALL_I_DIS3_MASK       0x8u
  #define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT      3
  #define USB_STALL_IL_DIS_STALL_I_DIS3_WIDTH      1
  #define USB_STALL_IL_DIS_STALL_I_DIS3(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS3_MASK)
  #define USB_STALL_IL_DIS_STALL_I_DIS4_MASK       0x10u
  #define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT      4
  #define USB_STALL_IL_DIS_STALL_I_DIS4_WIDTH      1
  #define USB_STALL_IL_DIS_STALL_I_DIS4(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS4_MASK)
  #define USB_STALL_IL_DIS_STALL_I_DIS5_MASK       0x20u
  #define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT      5
  #define USB_STALL_IL_DIS_STALL_I_DIS5_WIDTH      1
  #define USB_STALL_IL_DIS_STALL_I_DIS5(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS5_MASK)
  #define USB_STALL_IL_DIS_STALL_I_DIS6_MASK       0x40u
  #define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT      6
  #define USB_STALL_IL_DIS_STALL_I_DIS6_WIDTH      1
  #define USB_STALL_IL_DIS_STALL_I_DIS6(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS6_MASK)
  #define USB_STALL_IL_DIS_STALL_I_DIS7_MASK       0x80u
  #define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT      7
  #define USB_STALL_IL_DIS_STALL_I_DIS7_WIDTH      1
  #define USB_STALL_IL_DIS_STALL_I_DIS7(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT))&USB_STALL_IL_DIS_STALL_I_DIS7_MASK)
  /* STALL_IH_DIS Bit Fields */
  #define USB_STALL_IH_DIS_STALL_I_DIS8_MASK       0x1u
  #define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT      0
  #define USB_STALL_IH_DIS_STALL_I_DIS8_WIDTH      1
  #define USB_STALL_IH_DIS_STALL_I_DIS8(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS8_MASK)
  #define USB_STALL_IH_DIS_STALL_I_DIS9_MASK       0x2u
  #define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT      1
  #define USB_STALL_IH_DIS_STALL_I_DIS9_WIDTH      1
  #define USB_STALL_IH_DIS_STALL_I_DIS9(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS9_MASK)
  #define USB_STALL_IH_DIS_STALL_I_DIS10_MASK      0x4u
  #define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT     2
  #define USB_STALL_IH_DIS_STALL_I_DIS10_WIDTH     1
  #define USB_STALL_IH_DIS_STALL_I_DIS10(x)        (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS10_MASK)
  #define USB_STALL_IH_DIS_STALL_I_DIS11_MASK      0x8u
  #define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT     3
  #define USB_STALL_IH_DIS_STALL_I_DIS11_WIDTH     1
  #define USB_STALL_IH_DIS_STALL_I_DIS11(x)        (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS11_MASK)
  #define USB_STALL_IH_DIS_STALL_I_DIS12_MASK      0x10u
  #define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT     4
  #define USB_STALL_IH_DIS_STALL_I_DIS12_WIDTH     1
  #define USB_STALL_IH_DIS_STALL_I_DIS12(x)        (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS12_MASK)
  #define USB_STALL_IH_DIS_STALL_I_DIS13_MASK      0x20u
  #define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT     5
  #define USB_STALL_IH_DIS_STALL_I_DIS13_WIDTH     1
  #define USB_STALL_IH_DIS_STALL_I_DIS13(x)        (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS13_MASK)
  #define USB_STALL_IH_DIS_STALL_I_DIS14_MASK      0x40u
  #define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT     6
  #define USB_STALL_IH_DIS_STALL_I_DIS14_WIDTH     1
  #define USB_STALL_IH_DIS_STALL_I_DIS14(x)        (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS14_MASK)
  #define USB_STALL_IH_DIS_STALL_I_DIS15_MASK      0x80u
  #define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT     7
  #define USB_STALL_IH_DIS_STALL_I_DIS15_WIDTH     1
  #define USB_STALL_IH_DIS_STALL_I_DIS15(x)        (((uint8_t)(((uint8_t)(x))<<USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT))&USB_STALL_IH_DIS_STALL_I_DIS15_MASK)
  /* STALL_OL_DIS Bit Fields */
  #define USB_STALL_OL_DIS_STALL_O_DIS0_MASK       0x1u
  #define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT      0
  #define USB_STALL_OL_DIS_STALL_O_DIS0_WIDTH      1
  #define USB_STALL_OL_DIS_STALL_O_DIS0(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS0_MASK)
  #define USB_STALL_OL_DIS_STALL_O_DIS1_MASK       0x2u
  #define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT      1
  #define USB_STALL_OL_DIS_STALL_O_DIS1_WIDTH      1
  #define USB_STALL_OL_DIS_STALL_O_DIS1(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS1_MASK)
  #define USB_STALL_OL_DIS_STALL_O_DIS2_MASK       0x4u
  #define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT      2
  #define USB_STALL_OL_DIS_STALL_O_DIS2_WIDTH      1
  #define USB_STALL_OL_DIS_STALL_O_DIS2(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS2_MASK)
  #define USB_STALL_OL_DIS_STALL_O_DIS3_MASK       0x8u
  #define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT      3
  #define USB_STALL_OL_DIS_STALL_O_DIS3_WIDTH      1
  #define USB_STALL_OL_DIS_STALL_O_DIS3(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS3_MASK)
  #define USB_STALL_OL_DIS_STALL_O_DIS4_MASK       0x10u
  #define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT      4
  #define USB_STALL_OL_DIS_STALL_O_DIS4_WIDTH      1
  #define USB_STALL_OL_DIS_STALL_O_DIS4(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS4_MASK)
  #define USB_STALL_OL_DIS_STALL_O_DIS5_MASK       0x20u
  #define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT      5
  #define USB_STALL_OL_DIS_STALL_O_DIS5_WIDTH      1
  #define USB_STALL_OL_DIS_STALL_O_DIS5(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS5_MASK)
  #define USB_STALL_OL_DIS_STALL_O_DIS6_MASK       0x40u
  #define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT      6
  #define USB_STALL_OL_DIS_STALL_O_DIS6_WIDTH      1
  #define USB_STALL_OL_DIS_STALL_O_DIS6(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS6_MASK)
  #define USB_STALL_OL_DIS_STALL_O_DIS7_MASK       0x80u
  #define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT      7
  #define USB_STALL_OL_DIS_STALL_O_DIS7_WIDTH      1
  #define USB_STALL_OL_DIS_STALL_O_DIS7(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT))&USB_STALL_OL_DIS_STALL_O_DIS7_MASK)
  /* STALL_OH_DIS Bit Fields */
  #define USB_STALL_OH_DIS_STALL_O_DIS8_MASK       0x1u
  #define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT      0
  #define USB_STALL_OH_DIS_STALL_O_DIS8_WIDTH      1
  #define USB_STALL_OH_DIS_STALL_O_DIS8(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS8_MASK)
  #define USB_STALL_OH_DIS_STALL_O_DIS9_MASK       0x2u
  #define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT      1
  #define USB_STALL_OH_DIS_STALL_O_DIS9_WIDTH      1
  #define USB_STALL_OH_DIS_STALL_O_DIS9(x)         (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS9_MASK)
  #define USB_STALL_OH_DIS_STALL_O_DIS10_MASK      0x4u
  #define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT     2
  #define USB_STALL_OH_DIS_STALL_O_DIS10_WIDTH     1
  #define USB_STALL_OH_DIS_STALL_O_DIS10(x)        (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS10_MASK)
  #define USB_STALL_OH_DIS_STALL_O_DIS11_MASK      0x8u
  #define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT     3
  #define USB_STALL_OH_DIS_STALL_O_DIS11_WIDTH     1
  #define USB_STALL_OH_DIS_STALL_O_DIS11(x)        (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS11_MASK)
  #define USB_STALL_OH_DIS_STALL_O_DIS12_MASK      0x10u
  #define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT     4
  #define USB_STALL_OH_DIS_STALL_O_DIS12_WIDTH     1
  #define USB_STALL_OH_DIS_STALL_O_DIS12(x)        (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS12_MASK)
  #define USB_STALL_OH_DIS_STALL_O_DIS13_MASK      0x20u
  #define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT     5
  #define USB_STALL_OH_DIS_STALL_O_DIS13_WIDTH     1
  #define USB_STALL_OH_DIS_STALL_O_DIS13(x)        (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS13_MASK)
  #define USB_STALL_OH_DIS_STALL_O_DIS14_MASK      0x40u
  #define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT     6
  #define USB_STALL_OH_DIS_STALL_O_DIS14_WIDTH     1
  #define USB_STALL_OH_DIS_STALL_O_DIS14(x)        (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS14_MASK)
  #define USB_STALL_OH_DIS_STALL_O_DIS15_MASK      0x80u
  #define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT     7
  #define USB_STALL_OH_DIS_STALL_O_DIS15_WIDTH     1
  #define USB_STALL_OH_DIS_STALL_O_DIS15(x)        (((uint8_t)(((uint8_t)(x))<<USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT))&USB_STALL_OH_DIS_STALL_O_DIS15_MASK)
  /* CLK_RECOVER_CTRL Bit Fields */
  #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
  #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
  #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_WIDTH 1
  #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
  #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
  #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
  #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_WIDTH 1
  #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT))&USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
  #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
  #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
  #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_WIDTH 1
  #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT))&USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
  /* CLK_RECOVER_IRC_EN Bit Fields */
  #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK       0x1u
  #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT      0
  #define USB_CLK_RECOVER_IRC_EN_REG_EN_WIDTH      1
  #define USB_CLK_RECOVER_IRC_EN_REG_EN(x)         (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
  #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK       0x2u
  #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      1
  #define USB_CLK_RECOVER_IRC_EN_IRC_EN_WIDTH      1
  #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x)         (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT))&USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
  /* CLK_RECOVER_INT_EN Bit Fields */
  #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK 0x10u
  #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT 4
  #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_WIDTH 1
  #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x)   (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT))&USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
  /* CLK_RECOVER_INT_STATUS Bit Fields */
  #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
  #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
  #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_WIDTH 1
  #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x))<<USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT))&USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
  
  /*!
   * @}
   */ /* end of group USB_Register_Masks */
  
  
  /* USB - Peripheral instance base addresses */
  /** Peripheral USB0 base address */
  #define USB0_BASE                                (0x40072000u)
  /** Peripheral USB0 base pointer */
  #define USB0                                     ((USB_Type *)USB0_BASE)
  #define USB0_BASE_PTR                            (USB0)
  /** Array initializer of USB peripheral base addresses */
  #define USB_BASE_ADDRS                           { USB0_BASE }
  /** Array initializer of USB peripheral base pointers */
  #define USB_BASE_PTRS                            { USB0 }
  
  /* ----------------------------------------------------------------------------
     -- USB - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
   * @{
   */
  
  
  /* USB - Register instance definitions */
  /* USB0 */
  #define USB0_PERID                               USB_PERID_REG(USB0)
  #define USB0_IDCOMP                              USB_IDCOMP_REG(USB0)
  #define USB0_REV                                 USB_REV_REG(USB0)
  #define USB0_ADDINFO                             USB_ADDINFO_REG(USB0)
  #define USB0_OTGISTAT                            USB_OTGISTAT_REG(USB0)
  #define USB0_OTGICR                              USB_OTGICR_REG(USB0)
  #define USB0_OTGSTAT                             USB_OTGSTAT_REG(USB0)
  #define USB0_OTGCTL                              USB_OTGCTL_REG(USB0)
  #define USB0_ISTAT                               USB_ISTAT_REG(USB0)
  #define USB0_INTEN                               USB_INTEN_REG(USB0)
  #define USB0_ERRSTAT                             USB_ERRSTAT_REG(USB0)
  #define USB0_ERREN                               USB_ERREN_REG(USB0)
  #define USB0_STAT                                USB_STAT_REG(USB0)
  #define USB0_CTL                                 USB_CTL_REG(USB0)
  #define USB0_ADDR                                USB_ADDR_REG(USB0)
  #define USB0_BDTPAGE1                            USB_BDTPAGE1_REG(USB0)
  #define USB0_FRMNUML                             USB_FRMNUML_REG(USB0)
  #define USB0_FRMNUMH                             USB_FRMNUMH_REG(USB0)
  #define USB0_TOKEN                               USB_TOKEN_REG(USB0)
  #define USB0_SOFTHLD                             USB_SOFTHLD_REG(USB0)
  #define USB0_BDTPAGE2                            USB_BDTPAGE2_REG(USB0)
  #define USB0_BDTPAGE3                            USB_BDTPAGE3_REG(USB0)
  #define USB0_ENDPT0                              USB_ENDPT_REG(USB0,0)
  #define USB0_ENDPT1                              USB_ENDPT_REG(USB0,1)
  #define USB0_ENDPT2                              USB_ENDPT_REG(USB0,2)
  #define USB0_ENDPT3                              USB_ENDPT_REG(USB0,3)
  #define USB0_ENDPT4                              USB_ENDPT_REG(USB0,4)
  #define USB0_ENDPT5                              USB_ENDPT_REG(USB0,5)
  #define USB0_ENDPT6                              USB_ENDPT_REG(USB0,6)
  #define USB0_ENDPT7                              USB_ENDPT_REG(USB0,7)
  #define USB0_ENDPT8                              USB_ENDPT_REG(USB0,8)
  #define USB0_ENDPT9                              USB_ENDPT_REG(USB0,9)
  #define USB0_ENDPT10                             USB_ENDPT_REG(USB0,10)
  #define USB0_ENDPT11                             USB_ENDPT_REG(USB0,11)
  #define USB0_ENDPT12                             USB_ENDPT_REG(USB0,12)
  #define USB0_ENDPT13                             USB_ENDPT_REG(USB0,13)
  #define USB0_ENDPT14                             USB_ENDPT_REG(USB0,14)
  #define USB0_ENDPT15                             USB_ENDPT_REG(USB0,15)
  #define USB0_USBCTRL                             USB_USBCTRL_REG(USB0)
  #define USB0_OBSERVE                             USB_OBSERVE_REG(USB0)
  #define USB0_CONTROL                             USB_CONTROL_REG(USB0)
  #define USB0_USBTRC0                             USB_USBTRC0_REG(USB0)
  #define USB0_USBFRMADJUST                        USB_USBFRMADJUST_REG(USB0)
  #define USB0_MISCCTRL                            USB_MISCCTRL_REG(USB0)
  #define USB0_STALL_IL_DIS                        USB_STALL_IL_DIS_REG(USB0)
  #define USB0_STALL_IH_DIS                        USB_STALL_IH_DIS_REG(USB0)
  #define USB0_STALL_OL_DIS                        USB_STALL_OL_DIS_REG(USB0)
  #define USB0_STALL_OH_DIS                        USB_STALL_OH_DIS_REG(USB0)
  #define USB0_CLK_RECOVER_CTRL                    USB_CLK_RECOVER_CTRL_REG(USB0)
  #define USB0_CLK_RECOVER_IRC_EN                  USB_CLK_RECOVER_IRC_EN_REG(USB0)
  #define USB0_CLK_RECOVER_INT_EN                  USB_CLK_RECOVER_INT_EN_REG(USB0)
  #define USB0_CLK_RECOVER_INT_STATUS              USB_CLK_RECOVER_INT_STATUS_REG(USB0)
  
  /* USB - Register array accessors */
  #define USB0_ENDPT(index)                        USB_ENDPT_REG(USB0,index)
  
  /*!
   * @}
   */ /* end of group USB_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group USB_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- WDOG Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
   * @{
   */
  
  /** WDOG - Register Layout Typedef */
  typedef struct {
    __IO uint16_t STCTRLH;                           /**< Watchdog Status and Control Register High, offset: 0x0 */
    __IO uint16_t STCTRLL;                           /**< Watchdog Status and Control Register Low, offset: 0x2 */
    __IO uint16_t TOVALH;                            /**< Watchdog Time-out Value Register High, offset: 0x4 */
    __IO uint16_t TOVALL;                            /**< Watchdog Time-out Value Register Low, offset: 0x6 */
    __IO uint16_t WINH;                              /**< Watchdog Window Register High, offset: 0x8 */
    __IO uint16_t WINL;                              /**< Watchdog Window Register Low, offset: 0xA */
    __IO uint16_t REFRESH;                           /**< Watchdog Refresh register, offset: 0xC */
    __IO uint16_t UNLOCK;                            /**< Watchdog Unlock register, offset: 0xE */
    __IO uint16_t TMROUTH;                           /**< Watchdog Timer Output Register High, offset: 0x10 */
    __IO uint16_t TMROUTL;                           /**< Watchdog Timer Output Register Low, offset: 0x12 */
    __IO uint16_t RSTCNT;                            /**< Watchdog Reset Count register, offset: 0x14 */
    __IO uint16_t PRESC;                             /**< Watchdog Prescaler register, offset: 0x16 */
  } WDOG_Type, *WDOG_MemMapPtr;
  
  /* ----------------------------------------------------------------------------
     -- WDOG - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
   * @{
   */
  
  
  /* WDOG - Register accessors */
  #define WDOG_STCTRLH_REG(base)                   ((base)->STCTRLH)
  #define WDOG_STCTRLL_REG(base)                   ((base)->STCTRLL)
  #define WDOG_TOVALH_REG(base)                    ((base)->TOVALH)
  #define WDOG_TOVALL_REG(base)                    ((base)->TOVALL)
  #define WDOG_WINH_REG(base)                      ((base)->WINH)
  #define WDOG_WINL_REG(base)                      ((base)->WINL)
  #define WDOG_REFRESH_REG(base)                   ((base)->REFRESH)
  #define WDOG_UNLOCK_REG(base)                    ((base)->UNLOCK)
  #define WDOG_TMROUTH_REG(base)                   ((base)->TMROUTH)
  #define WDOG_TMROUTL_REG(base)                   ((base)->TMROUTL)
  #define WDOG_RSTCNT_REG(base)                    ((base)->RSTCNT)
  #define WDOG_PRESC_REG(base)                     ((base)->PRESC)
  
  /*!
   * @}
   */ /* end of group WDOG_Register_Accessor_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- WDOG Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup WDOG_Register_Masks WDOG Register Masks
   * @{
   */
  
  /* STCTRLH Bit Fields */
  #define WDOG_STCTRLH_WDOGEN_MASK                 0x1u
  #define WDOG_STCTRLH_WDOGEN_SHIFT                0
  #define WDOG_STCTRLH_WDOGEN_WIDTH                1
  #define WDOG_STCTRLH_WDOGEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WDOGEN_SHIFT))&WDOG_STCTRLH_WDOGEN_MASK)
  #define WDOG_STCTRLH_CLKSRC_MASK                 0x2u
  #define WDOG_STCTRLH_CLKSRC_SHIFT                1
  #define WDOG_STCTRLH_CLKSRC_WIDTH                1
  #define WDOG_STCTRLH_CLKSRC(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_CLKSRC_SHIFT))&WDOG_STCTRLH_CLKSRC_MASK)
  #define WDOG_STCTRLH_IRQRSTEN_MASK               0x4u
  #define WDOG_STCTRLH_IRQRSTEN_SHIFT              2
  #define WDOG_STCTRLH_IRQRSTEN_WIDTH              1
  #define WDOG_STCTRLH_IRQRSTEN(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_IRQRSTEN_SHIFT))&WDOG_STCTRLH_IRQRSTEN_MASK)
  #define WDOG_STCTRLH_WINEN_MASK                  0x8u
  #define WDOG_STCTRLH_WINEN_SHIFT                 3
  #define WDOG_STCTRLH_WINEN_WIDTH                 1
  #define WDOG_STCTRLH_WINEN(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WINEN_SHIFT))&WDOG_STCTRLH_WINEN_MASK)
  #define WDOG_STCTRLH_ALLOWUPDATE_MASK            0x10u
  #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT           4
  #define WDOG_STCTRLH_ALLOWUPDATE_WIDTH           1
  #define WDOG_STCTRLH_ALLOWUPDATE(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_ALLOWUPDATE_SHIFT))&WDOG_STCTRLH_ALLOWUPDATE_MASK)
  #define WDOG_STCTRLH_DBGEN_MASK                  0x20u
  #define WDOG_STCTRLH_DBGEN_SHIFT                 5
  #define WDOG_STCTRLH_DBGEN_WIDTH                 1
  #define WDOG_STCTRLH_DBGEN(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DBGEN_SHIFT))&WDOG_STCTRLH_DBGEN_MASK)
  #define WDOG_STCTRLH_STOPEN_MASK                 0x40u
  #define WDOG_STCTRLH_STOPEN_SHIFT                6
  #define WDOG_STCTRLH_STOPEN_WIDTH                1
  #define WDOG_STCTRLH_STOPEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_STOPEN_SHIFT))&WDOG_STCTRLH_STOPEN_MASK)
  #define WDOG_STCTRLH_WAITEN_MASK                 0x80u
  #define WDOG_STCTRLH_WAITEN_SHIFT                7
  #define WDOG_STCTRLH_WAITEN_WIDTH                1
  #define WDOG_STCTRLH_WAITEN(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_WAITEN_SHIFT))&WDOG_STCTRLH_WAITEN_MASK)
  #define WDOG_STCTRLH_TESTWDOG_MASK               0x400u
  #define WDOG_STCTRLH_TESTWDOG_SHIFT              10
  #define WDOG_STCTRLH_TESTWDOG_WIDTH              1
  #define WDOG_STCTRLH_TESTWDOG(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTWDOG_SHIFT))&WDOG_STCTRLH_TESTWDOG_MASK)
  #define WDOG_STCTRLH_TESTSEL_MASK                0x800u
  #define WDOG_STCTRLH_TESTSEL_SHIFT               11
  #define WDOG_STCTRLH_TESTSEL_WIDTH               1
  #define WDOG_STCTRLH_TESTSEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_TESTSEL_SHIFT))&WDOG_STCTRLH_TESTSEL_MASK)
  #define WDOG_STCTRLH_BYTESEL_MASK                0x3000u
  #define WDOG_STCTRLH_BYTESEL_SHIFT               12
  #define WDOG_STCTRLH_BYTESEL_WIDTH               2
  #define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
  #define WDOG_STCTRLH_DISTESTWDOG_MASK            0x4000u
  #define WDOG_STCTRLH_DISTESTWDOG_SHIFT           14
  #define WDOG_STCTRLH_DISTESTWDOG_WIDTH           1
  #define WDOG_STCTRLH_DISTESTWDOG(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_DISTESTWDOG_SHIFT))&WDOG_STCTRLH_DISTESTWDOG_MASK)
  /* STCTRLL Bit Fields */
  #define WDOG_STCTRLL_INTFLG_MASK                 0x8000u
  #define WDOG_STCTRLL_INTFLG_SHIFT                15
  #define WDOG_STCTRLL_INTFLG_WIDTH                1
  #define WDOG_STCTRLL_INTFLG(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLL_INTFLG_SHIFT))&WDOG_STCTRLL_INTFLG_MASK)
  /* TOVALH Bit Fields */
  #define WDOG_TOVALH_TOVALHIGH_MASK               0xFFFFu
  #define WDOG_TOVALH_TOVALHIGH_SHIFT              0
  #define WDOG_TOVALH_TOVALHIGH_WIDTH              16
  #define WDOG_TOVALH_TOVALHIGH(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
  /* TOVALL Bit Fields */
  #define WDOG_TOVALL_TOVALLOW_MASK                0xFFFFu
  #define WDOG_TOVALL_TOVALLOW_SHIFT               0
  #define WDOG_TOVALL_TOVALLOW_WIDTH               16
  #define WDOG_TOVALL_TOVALLOW(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
  /* WINH Bit Fields */
  #define WDOG_WINH_WINHIGH_MASK                   0xFFFFu
  #define WDOG_WINH_WINHIGH_SHIFT                  0
  #define WDOG_WINH_WINHIGH_WIDTH                  16
  #define WDOG_WINH_WINHIGH(x)                     (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
  /* WINL Bit Fields */
  #define WDOG_WINL_WINLOW_MASK                    0xFFFFu
  #define WDOG_WINL_WINLOW_SHIFT                   0
  #define WDOG_WINL_WINLOW_WIDTH                   16
  #define WDOG_WINL_WINLOW(x)                      (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
  /* REFRESH Bit Fields */
  #define WDOG_REFRESH_WDOGREFRESH_MASK            0xFFFFu
  #define WDOG_REFRESH_WDOGREFRESH_SHIFT           0
  #define WDOG_REFRESH_WDOGREFRESH_WIDTH           16
  #define WDOG_REFRESH_WDOGREFRESH(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
  /* UNLOCK Bit Fields */
  #define WDOG_UNLOCK_WDOGUNLOCK_MASK              0xFFFFu
  #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT             0
  #define WDOG_UNLOCK_WDOGUNLOCK_WIDTH             16
  #define WDOG_UNLOCK_WDOGUNLOCK(x)                (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
  /* TMROUTH Bit Fields */
  #define WDOG_TMROUTH_TIMEROUTHIGH_MASK           0xFFFFu
  #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT          0
  #define WDOG_TMROUTH_TIMEROUTHIGH_WIDTH          16
  #define WDOG_TMROUTH_TIMEROUTHIGH(x)             (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
  /* TMROUTL Bit Fields */
  #define WDOG_TMROUTL_TIMEROUTLOW_MASK            0xFFFFu
  #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT           0
  #define WDOG_TMROUTL_TIMEROUTLOW_WIDTH           16
  #define WDOG_TMROUTL_TIMEROUTLOW(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
  /* RSTCNT Bit Fields */
  #define WDOG_RSTCNT_RSTCNT_MASK                  0xFFFFu
  #define WDOG_RSTCNT_RSTCNT_SHIFT                 0
  #define WDOG_RSTCNT_RSTCNT_WIDTH                 16
  #define WDOG_RSTCNT_RSTCNT(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
  /* PRESC Bit Fields */
  #define WDOG_PRESC_PRESCVAL_MASK                 0x700u
  #define WDOG_PRESC_PRESCVAL_SHIFT                8
  #define WDOG_PRESC_PRESCVAL_WIDTH                3
  #define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
  
  /*!
   * @}
   */ /* end of group WDOG_Register_Masks */
  
  
  /* WDOG - Peripheral instance base addresses */
  /** Peripheral WDOG base address */
  #define WDOG_BASE                                (0x40052000u)
  /** Peripheral WDOG base pointer */
  #define WDOG                                     ((WDOG_Type *)WDOG_BASE)
  #define WDOG_BASE_PTR                            (WDOG)
  /** Array initializer of WDOG peripheral base addresses */
  #define WDOG_BASE_ADDRS                          { WDOG_BASE }
  /** Array initializer of WDOG peripheral base pointers */
  #define WDOG_BASE_PTRS                           { WDOG }
  
  /* ----------------------------------------------------------------------------
     -- WDOG - Register accessor macros
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
   * @{
   */
  
  
  /* WDOG - Register instance definitions */
  /* WDOG */
  #define WDOG_STCTRLH                             WDOG_STCTRLH_REG(WDOG)
  #define WDOG_STCTRLL                             WDOG_STCTRLL_REG(WDOG)
  #define WDOG_TOVALH                              WDOG_TOVALH_REG(WDOG)
  #define WDOG_TOVALL                              WDOG_TOVALL_REG(WDOG)
  #define WDOG_WINH                                WDOG_WINH_REG(WDOG)
  #define WDOG_WINL                                WDOG_WINL_REG(WDOG)
  #define WDOG_REFRESH                             WDOG_REFRESH_REG(WDOG)
  #define WDOG_UNLOCK                              WDOG_UNLOCK_REG(WDOG)
  #define WDOG_TMROUTH                             WDOG_TMROUTH_REG(WDOG)
  #define WDOG_TMROUTL                             WDOG_TMROUTL_REG(WDOG)
  #define WDOG_RSTCNT                              WDOG_RSTCNT_REG(WDOG)
  #define WDOG_PRESC                               WDOG_PRESC_REG(WDOG)
  
  /*!
   * @}
   */ /* end of group WDOG_Register_Accessor_Macros */
  
  
  /*!
   * @}
   */ /* end of group WDOG_Peripheral_Access_Layer */
  
  
  /*
  ** End of section using anonymous unions
  */
  
  #if defined(__ARMCC_VERSION)
    #pragma pop
  #elif defined(__CWCC__)
    #pragma pop
  #elif defined(__GNUC__)
    /* leave anonymous unions enabled */
  #elif defined(__IAR_SYSTEMS_ICC__)
    #pragma language=default
  #else
    #error Not supported compiler type
  #endif
  
  /*!
   * @}
   */ /* end of group Peripheral_access_layer */
  
  
  /* ----------------------------------------------------------------------------
     -- Backward Compatibility
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
   * @{
   */
  
  #define  MCG_C2_EREFS0_MASK          MCG_C2_EREFS_MASK
  #define  MCG_C2_EREFS0_SHIFT         MCG_C2_EREFS_SHIFT
  #define  MCG_C2_HGO0_MASK            MCG_C2_HGO_MASK
  #define  MCG_C2_HGO0_SHIFT           MCG_C2_HGO_SHIFT
  #define  MCG_C2_RANGE0_MASK          MCG_C2_RANGE_MASK
  #define  MCG_C2_RANGE0_SHIFT         MCG_C2_RANGE_SHIFT
  #define  MCG_C2_RANGE0(x)            MCG_C2_RANGE(x)
  #define ADC_BASES                    ADC_BASE_PTRS
  #define CMP_BASES                    CMP_BASE_PTRS
  #define CRC_BASES                    CRC_BASE_PTRS
  #define DAC_BASES                    DAC_BASE_PTRS
  #define DMA_BASES                    DMA_BASE_PTRS
  #define DMAMUX_BASES                 DMAMUX_BASE_PTRS
  #define EWM_BASES                    EWM_BASE_PTRS
  #define FMC_BASES                    FMC_BASE_PTRS
  #define FTFA_BASES                   FTFA_BASE_PTRS
  #define FTM_BASES                    FTM_BASE_PTRS
  #define GPIO_BASES                   GPIO_BASE_PTRS
  #define I2C_BASES                    I2C_BASE_PTRS
  #define I2S_BASES                    I2S_BASE_PTRS
  #define LLWU_BASES                   LLWU_BASE_PTRS
  #define LPTMR_BASES                  LPTMR_BASE_PTRS
  #define LPUART_BASES                 LPUART_BASE_PTRS
  #define MCG_BASES                    MCG_BASE_PTRS
  #define MCM_BASES                    MCM_BASE_PTRS
  #define NV_BASES                     NV_BASE_PTRS
  #define OSC_BASES                    OSC_BASE_PTRS
  #define PDB_BASES                    PDB_BASE_PTRS
  #define PIT_BASES                    PIT_BASE_PTRS
  #define PMC_BASES                    PMC_BASE_PTRS
  #define PORT_BASES                   PORT_BASE_PTRS
  #define RCM_BASES                    RCM_BASE_PTRS
  #define RFSYS_BASES                  RFSYS_BASE_PTRS
  #define RFVBAT_BASES                 RFVBAT_BASE_PTRS
  #define RNG_BASES                    RNG_BASE_PTRS
  #define RTC_BASES                    RTC_BASE_PTRS
  #define SIM_BASES                    SIM_BASE_PTRS
  #define SMC_BASES                    SMC_BASE_PTRS
  #define SPI_BASES                    SPI_BASE_PTRS
  #define UART_BASES                   UART_BASE_PTRS
  #define USB_BASES                    USB_BASE_PTRS
  #define VREF_BASES                   VREF_BASE_PTRS
  #define WDOG_BASES                   WDOG_BASE_PTRS
  #define USB_ADDINFO_IRQNUM_MASK      This_symbol_has_been_deprecated
  #define USB_ADDINFO_IRQNUM_SHIFT     This_symbol_has_been_deprecated
  #define USB_ADDINFO_IRQNUM(x)        This_symbol_has_been_deprecated
  #define Watchdog_IRQn                WDOG_EWM_IRQn
  #define Watchdog_IRQHandler          WDOG_EWM_IRQHandler
  #define LPTimer_IRQn                 LPTMR0_IRQn
  #define LPTimer_IRQHandler           LPTMR0_IRQHandler
  #define LLW_IRQn                     LLWU_IRQn
  #define LLW_IRQHandler               LLWU_IRQHandler
  
  /*!
   * @}
   */ /* end of group Backward_Compatibility_Symbols */
  
  
  #else /* #if !defined(MKS22F25612_H_) */
    /* There is already included the same memory map. Check if it is compatible (has the same major version) */
    #if (MCU_MEM_MAP_VERSION != 0x0200u)
      #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
        #warning There are included two not compatible versions of memory maps. Please check possible differences.
      #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
    #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
  #endif  /* #if !defined(MKS22F25612_H_) */
  
  /* MKS22F25612.h, eof. */
  