text: /*
      ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
                   2011,2012,2013 Giovanni Di Sirio.
  
      This file is part of ChibiOS/RT.
  
      ChibiOS/RT is free software; you can redistribute it and/or modify
      it under the terms of the GNU General Public License as published by
      the Free Software Foundation; either version 3 of the License, or
      (at your option) any later version.
  
      ChibiOS/RT is distributed in the hope that it will be useful,
      but WITHOUT ANY WARRANTY; without even the implied warranty of
      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
      GNU General Public License for more details.
  
      You should have received a copy of the GNU General Public License
      along with this program.  If not, see <http://www.gnu.org/licenses/>.
  
                                        ---
  
      A special exception to the GPL can be applied should you wish to distribute
      a combined work that includes ChibiOS/RT, without being obliged to provide
      the source code for any proprietary components. See the file exception.txt
      for full details of how and when the exception can be applied.
  */
  
  /**
   * @file    RVCT/ARMCMx/chcore_v6m.h
   * @brief   ARMv6-M architecture port macros and structures.
   *
   * @addtogroup RVCT_ARMCMx_V6M_CORE
   * @{
   */
  
  #ifndef _CHCORE_V6M_H_
  #define _CHCORE_V6M_H_
  
  /*===========================================================================*/
  /* Port constants.                                                           */
  /*===========================================================================*/
  
  /**
   * @brief   PendSV priority level.
   * @note    This priority is enforced to be equal to @p 0,
   *          this handler always has the highest priority that cannot preempt
   *          the kernel.
   */
  #define CORTEX_PRIORITY_PENDSV          0
  
  /*===========================================================================*/
  /* Port macros.                                                              */
  /*===========================================================================*/
  
  /*===========================================================================*/
  /* Port configurable parameters.                                             */
  /*===========================================================================*/
  
  /**
   * @brief   Stack size for the system idle thread.
   * @details This size depends on the idle thread implementation, usually
   *          the idle thread should take no more space than those reserved
   *          by @p PORT_INT_REQUIRED_STACK.
   * @note    In this port it is set to 16 because the idle thread does have
   *          a stack frame when compiling without optimizations. You may
   *          reduce this value to zero when compiling with optimizations.
   */
  #if !defined(PORT_IDLE_THREAD_STACK_SIZE)
  #define PORT_IDLE_THREAD_STACK_SIZE     16
  #endif
  
  /**
   * @brief   Per-thread stack overhead for interrupts servicing.
   * @details This constant is used in the calculation of the correct working
   *          area size.
   * @note    In this port this value is conservatively set to 32 because the
   *          function @p chSchDoReschedule() can have a stack frame, especially
   *          with compiler optimizations disabled. The value can be reduced
   *          when compiler optimizations are enabled.
   */
  #if !defined(PORT_INT_REQUIRED_STACK)
  #define PORT_INT_REQUIRED_STACK         32
  #endif
  
  /**
   * @brief   Enables the use of the WFI instruction in the idle thread loop.
   */
  #if !defined(CORTEX_ENABLE_WFI_IDLE)
  #define CORTEX_ENABLE_WFI_IDLE          FALSE
  #endif
  
  /**
   * @brief   SYSTICK handler priority.
   * @note    The default SYSTICK handler priority is calculated as the priority
   *          level in the middle of the numeric priorities range.
   */
  #if !defined(CORTEX_PRIORITY_SYSTICK)
  #define CORTEX_PRIORITY_SYSTICK         (CORTEX_PRIORITY_LEVELS >> 1)
  #elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
  /* If it is externally redefined then better perform a validity check on it.*/
  #error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
  #endif
  
  /**
   * @brief   Alternate preemption method.
   * @details Activating this option will make the Kernel use the PendSV
   *          handler for preemption instead of the NMI handler.
   */
  #ifndef CORTEX_ALTERNATE_SWITCH
  #define CORTEX_ALTERNATE_SWITCH         FALSE
  #endif
  
  /*===========================================================================*/
  /* Port derived parameters.                                                  */
  /*===========================================================================*/
  
  /**
   * @brief   Maximum usable priority for normal ISRs.
   */
  #if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
  #define CORTEX_MAX_KERNEL_PRIORITY      1
  #else
  #define CORTEX_MAX_KERNEL_PRIORITY      0
  #endif
  
  /*===========================================================================*/
  /* Port exported info.                                                       */
  /*===========================================================================*/
  
  /**
   * @brief   Macro defining the specific ARM architecture.
   */
  #define CH_ARCHITECTURE_ARM_v6M
  
  /**
   * @brief   Name of the implemented architecture.
   */
  #define CH_ARCHITECTURE_NAME            "ARMv6-M"
  
  /**
   * @brief   Name of the architecture variant.
   */
  #if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)
  #define CH_CORE_VARIANT_NAME            "Cortex-M0"
  #elif (CORTEX_MODEL == CORTEX_M1)
  #define CH_CORE_VARIANT_NAME            "Cortex-M1"
  #endif
  
  /**
   * @brief   Port-specific information string.
   */
  #if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)
  #define CH_PORT_INFO                    "Preemption through NMI"
  #else
  #define CH_PORT_INFO                    "Preemption through PendSV"
  #endif
  
  /*===========================================================================*/
  /* Port implementation part.                                                 */
  /*===========================================================================*/
  
  #if !defined(_FROM_ASM_)
  
  /**
   * @brief   Generic ARM register.
   */
  typedef void *regarm_t;
  
  /**
   * @brief   Stack and memory alignment enforcement.
   * @note    In this architecture the stack alignment is enforced to 64 bits,
   *          32 bits alignment is supported by hardware but deprecated by ARM,
   *          the implementation choice is to not offer the option.
   */
  typedef uint64_t stkalign_t;
  
   /* The documentation of the following declarations is in chconf.h in order
      to not have duplicated structure names into the documentation.*/
  #if !defined(__DOXYGEN__)
  
  struct extctx {
    regarm_t      r0;
    regarm_t      r1;
    regarm_t      r2;
    regarm_t      r3;
    regarm_t      r12;
    regarm_t      lr_thd;
    regarm_t      pc;
    regarm_t      xpsr;
  };
  
  struct intctx {
    regarm_t      r8;
    regarm_t      r9;
    regarm_t      r10;
    regarm_t      r11;
    regarm_t      r4;
    regarm_t      r5;
    regarm_t      r6;
    regarm_t      r7;
    regarm_t      lr;
  };
  
  #endif /* !defined(__DOXYGEN__) */
  
  /**
   * @brief   Platform dependent part of the @p Thread structure.
   * @details In this port the structure just holds a pointer to the @p intctx
   *          structure representing the stack pointer at context switch time.
   */
  struct context {
    struct intctx *r13;
  };
  
  /**
   * @brief   Platform dependent part of the @p chThdCreateI() API.
   * @details This code usually setup the context switching frame represented
   *          by an @p intctx structure.
   */
  #define SETUP_CONTEXT(workspace, wsize, pf, arg) {                          \
    tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace +                  \
                                       wsize -                                \
                                       sizeof(struct intctx));                \
    tp->p_ctx.r13->r4 = (regarm_t)pf;                                         \
    tp->p_ctx.r13->r5 = (regarm_t)arg;                                        \
    tp->p_ctx.r13->lr = (regarm_t)_port_thread_start;                         \
  }
  
  /**
   * @brief   Enforces a correct alignment for a stack area size value.
   */
  #define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
  
  /**
   * @brief   Computes the thread working area global size.
   */
  #define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) +                         \
                                     sizeof(struct intctx) +                  \
                                     sizeof(struct extctx) +                  \
                                     (n) + (PORT_INT_REQUIRED_STACK))
  
  /**
   * @brief   Static working area allocation.
   * @details This macro is used to allocate a static thread working area
   *          aligned as both position and size.
   */
  #define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
  
  /**
   * @brief   IRQ prologue code.
   * @details This macro must be inserted at the start of all IRQ handlers
   *          enabled to invoke system APIs.
   */
  #define PORT_IRQ_PROLOGUE() regarm_t _saved_lr = (regarm_t)__return_address()
  
  /**
   * @brief   IRQ epilogue code.
   * @details This macro must be inserted at the end of all IRQ handlers
   *          enabled to invoke system APIs.
   */
  #define PORT_IRQ_EPILOGUE() _port_irq_epilogue(_saved_lr)
  
  /**
   * @brief   IRQ handler function declaration.
   * @note    @p id can be a function name or a vector number depending on the
   *          port implementation.
   */
  #define PORT_IRQ_HANDLER(id) void id(void)
  
  /**
   * @brief   Fast IRQ handler function declaration.
   * @note    @p id can be a function name or a vector number depending on the
   *          port implementation.
   */
  #define PORT_FAST_IRQ_HANDLER(id) void id(void)
  
  /**
   * @brief   Port-related initialization code.
   */
  #define port_init() {                                                       \
    SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0);                            \
    nvicSetSystemHandlerPriority(HANDLER_PENDSV,                              \
      CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV));                          \
    nvicSetSystemHandlerPriority(HANDLER_SYSTICK,                             \
      CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK));                         \
  }
  
  /**
   * @brief   Kernel-lock action.
   * @details Usually this function just disables interrupts but may perform
   *          more actions.
   */
  #define port_lock() __disable_irq()
  
  /**
   * @brief   Kernel-unlock action.
   * @details Usually this function just enables interrupts but may perform
   *          more actions.
   */
  #define port_unlock() __enable_irq()
  
  /**
   * @brief   Kernel-lock action from an interrupt handler.
   * @details This function is invoked before invoking I-class APIs from
   *          interrupt handlers. The implementation is architecture dependent,
   *          in its simplest form it is void.
   * @note    Same as @p port_lock() in this port.
   */
  #define port_lock_from_isr() port_lock()
  
  /**
   * @brief   Kernel-unlock action from an interrupt handler.
   * @details This function is invoked after invoking I-class APIs from interrupt
   *          handlers. The implementation is architecture dependent, in its
   *          simplest form it is void.
   * @note    Same as @p port_lock() in this port.
   */
  #define port_unlock_from_isr() port_unlock()
  
  /**
   * @brief   Disables all the interrupt sources.
   */
  #define port_disable() __disable_irq()
  
  /**
   * @brief   Disables the interrupt sources below kernel-level priority.
   */
  #define port_suspend() __disable_irq()
  
  /**
   * @brief   Enables all the interrupt sources.
   */
  #define port_enable() __enable_irq()
  
  /**
   * @brief   Enters an architecture-dependent IRQ-waiting mode.
   * @details The function is meant to return when an interrupt becomes pending.
   *          The simplest implementation is an empty function or macro but this
   *          would not take advantage of architecture-specific power saving
   *          modes.
   * @note    Implemented as an inlined @p WFI instruction.
   */
  #if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
  #define port_wait_for_interrupt() __wfi()
  #else
  #define port_wait_for_interrupt()
  #endif
  
  /**
   * @brief   Performs a context switch between two threads.
   * @details This is the most critical code in any port, this function
   *          is responsible for the context switch between 2 threads.
   * @note    The implementation of this code affects <b>directly</b> the context
   *          switch performance so optimize here as much as you can.
   *
   * @param[in] ntp       the thread to be switched in
   * @param[in] otp       the thread to be switched out
   */
  #if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
  #define port_switch(ntp, otp) _port_switch(ntp, otp)
  #else
  #define port_switch(ntp, otp) {                                             \
    uint8_t *r13 = (uint8_t *)__current_sp();                                 \
    if ((stkalign_t *)(r13 - sizeof(struct intctx)) < otp->p_stklimit)        \
      chDbgPanic("stack overflow");                                           \
    _port_switch(ntp, otp);                                                   \
  }
  #endif
  
  #ifdef __cplusplus
  extern "C" {
  #endif
    void port_halt(void);
    void _port_irq_epilogue(regarm_t lr);
    void _port_switch_from_isr(void);
    void _port_exit_from_isr(void);
    void _port_switch(Thread *ntp, Thread *otp);
    void _port_thread_start(void);
  #ifdef __cplusplus
  }
  #endif
  
  #endif /* _FROM_ASM_ */
  
  #endif /* _CHCORE_V6M_H_ */
  
  /** @} */
  