text: #ifndef _SYSREGS_H
  #define _SYSREGS_H
  
  // ***************************************
  // HCR_EL2, Hypervisor Configuration Register (EL2), Page 2487 of AArch64-Reference-Manual.
  // ***************************************
  
  #define HCR_RW	    			(1 << 31)
  #define HCR_VALUE			HCR_RW
  
  // ***************************************
  // SPSR_EL2, Saved Program Status Register (EL2) Page 389 of AArch64-Reference-Manual.
  // ***************************************
  
  #define SPSR_MASK_ALL 			(7 << 6)
  #define SPSR_EL1h			(5 << 0)
  #define SPSR_VALUE			(SPSR_MASK_ALL | SPSR_EL1h)
  
  // ***************************************
  // SCTLR_EL1, System Control Register (EL1), Page 2654 of AArch64-Reference-Manual.
  // ***************************************
  
  #define SCTLR_RESERVED                  (3 << 28) | (3 << 22) | (1 << 20) | (1 << 11)
  #define SCTLR_EE_LITTLE_ENDIAN          (0 << 25)
  #define SCTLR_EOE_LITTLE_ENDIAN         (0 << 24)
  #define SCTLR_I_CACHE_DISABLED          (0 << 12)
  #define SCTLR_D_CACHE_DISABLED          (0 << 2)
  #define SCTLR_MMU_DISABLED              (0 << 0)
  #define SCTLR_MMU_ENABLED               (1 << 0)
  
  #define SCTLR_VALUE_MMU_DISABLED	(SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_I_CACHE_DISABLED | SCTLR_D_CACHE_DISABLED | SCTLR_MMU_DISABLED)
  
  #define ICC_SRE_EL2_SRE			(1 << 0)
  #define ICC_SRE_EL2_ENABLE		(1 << 3)
  
  #define ICC_SRE_EL2_VAL			(ICC_SRE_EL2_SRE|ICC_SRE_EL2_ENABLE)
  #define ICC_SRE_EL2			S3_4_C12_C9_5
  
  #endif /* SYSREGS.h */
  