text: #pragma once 
  #include <Register/Utility.hpp>
  namespace Kvasir {
  //General purpose timers
      namespace Tim12Cr1{    ///<control register 1
          using Addr = Register::Address<0x40001800,0xfffffc70,0x00000000,unsigned>;
          ///Clock division
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(9,8),Register::ReadWriteAccess,unsigned> ckd{}; 
          ///Auto-reload preload enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,7),Register::ReadWriteAccess,unsigned> arpe{}; 
          ///One-pulse mode
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(3,3),Register::ReadWriteAccess,unsigned> opm{}; 
          ///Update request source
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(2,2),Register::ReadWriteAccess,unsigned> urs{}; 
          ///Update disable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,1),Register::ReadWriteAccess,unsigned> udis{}; 
          ///Counter enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(0,0),Register::ReadWriteAccess,unsigned> cen{}; 
      }
      namespace Tim12Smcr{    ///<slave mode control register
          using Addr = Register::Address<0x40001808,0xffffff08,0x00000000,unsigned>;
          ///Master/Slave mode
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,7),Register::ReadWriteAccess,unsigned> msm{}; 
          ///Trigger selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(6,4),Register::ReadWriteAccess,unsigned> ts{}; 
          ///Slave mode selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(2,0),Register::ReadWriteAccess,unsigned> sms{}; 
      }
      namespace Tim12Dier{    ///<DMA/Interrupt enable register
          using Addr = Register::Address<0x4000180c,0xffffffb8,0x00000000,unsigned>;
          ///Trigger interrupt enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(6,6),Register::ReadWriteAccess,unsigned> tie{}; 
          ///Capture/Compare 2 interrupt              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(2,2),Register::ReadWriteAccess,unsigned> cc2ie{}; 
          ///Capture/Compare 1 interrupt              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,1),Register::ReadWriteAccess,unsigned> cc1ie{}; 
          ///Update interrupt enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(0,0),Register::ReadWriteAccess,unsigned> uie{}; 
      }
      namespace Tim12Sr{    ///<status register
          using Addr = Register::Address<0x40001810,0xfffff9b8,0x00000000,unsigned>;
          ///Capture/compare 2 overcapture              flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(10,10),Register::ReadWriteAccess,unsigned> cc2of{}; 
          ///Capture/Compare 1 overcapture              flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(9,9),Register::ReadWriteAccess,unsigned> cc1of{}; 
          ///Trigger interrupt flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(6,6),Register::ReadWriteAccess,unsigned> tif{}; 
          ///Capture/Compare 2 interrupt              flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(2,2),Register::ReadWriteAccess,unsigned> cc2if{}; 
          ///Capture/compare 1 interrupt              flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,1),Register::ReadWriteAccess,unsigned> cc1if{}; 
          ///Update interrupt flag
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(0,0),Register::ReadWriteAccess,unsigned> uif{}; 
      }
      namespace Tim12Egr{    ///<event generation register
          using Addr = Register::Address<0x40001814,0xffffffb8,0x00000000,unsigned>;
          ///Trigger generation
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(6,6),Register::ReadWriteAccess,unsigned> tg{}; 
          ///Capture/compare 2              generation
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(2,2),Register::ReadWriteAccess,unsigned> cc2g{}; 
          ///Capture/compare 1              generation
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,1),Register::ReadWriteAccess,unsigned> cc1g{}; 
          ///Update generation
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(0,0),Register::ReadWriteAccess,unsigned> ug{}; 
      }
      namespace Tim12Ccmr1Output{    ///<capture/compare mode register (output          mode)
          using Addr = Register::Address<0x40001818,0xffff8080,0x00000000,unsigned>;
          ///Output Compare 2 mode
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(14,12),Register::ReadWriteAccess,unsigned> oc2m{}; 
          ///Output Compare 2 preload              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(11,11),Register::ReadWriteAccess,unsigned> oc2pe{}; 
          ///Output Compare 2 fast              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(10,10),Register::ReadWriteAccess,unsigned> oc2fe{}; 
          ///Capture/Compare 2              selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(9,8),Register::ReadWriteAccess,unsigned> cc2s{}; 
          ///Output Compare 1 mode
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(6,4),Register::ReadWriteAccess,unsigned> oc1m{}; 
          ///Output Compare 1 preload              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(3,3),Register::ReadWriteAccess,unsigned> oc1pe{}; 
          ///Output Compare 1 fast              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(2,2),Register::ReadWriteAccess,unsigned> oc1fe{}; 
          ///Capture/Compare 1              selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,0),Register::ReadWriteAccess,unsigned> cc1s{}; 
      }
      namespace Tim12Ccmr1Input{    ///<capture/compare mode register 1 (input          mode)
          using Addr = Register::Address<0x40001818,0xffff0080,0x00000000,unsigned>;
          ///Input capture 2 filter
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,12),Register::ReadWriteAccess,unsigned> ic2f{}; 
          ///Input capture 2 prescaler
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(11,10),Register::ReadWriteAccess,unsigned> ic2psc{}; 
          ///Capture/Compare 2              selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(9,8),Register::ReadWriteAccess,unsigned> cc2s{}; 
          ///Input capture 1 filter
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(6,4),Register::ReadWriteAccess,unsigned> ic1f{}; 
          ///Input capture 1 prescaler
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(3,2),Register::ReadWriteAccess,unsigned> ic1psc{}; 
          ///Capture/Compare 1              selection
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,0),Register::ReadWriteAccess,unsigned> cc1s{}; 
      }
      namespace Tim12Ccer{    ///<capture/compare enable          register
          using Addr = Register::Address<0x40001820,0xffffff44,0x00000000,unsigned>;
          ///Capture/Compare 2 output              Polarity
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(7,7),Register::ReadWriteAccess,unsigned> cc2np{}; 
          ///Capture/Compare 2 output              Polarity
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(5,5),Register::ReadWriteAccess,unsigned> cc2p{}; 
          ///Capture/Compare 2 output              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(4,4),Register::ReadWriteAccess,unsigned> cc2e{}; 
          ///Capture/Compare 1 output              Polarity
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(3,3),Register::ReadWriteAccess,unsigned> cc1np{}; 
          ///Capture/Compare 1 output              Polarity
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(1,1),Register::ReadWriteAccess,unsigned> cc1p{}; 
          ///Capture/Compare 1 output              enable
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(0,0),Register::ReadWriteAccess,unsigned> cc1e{}; 
      }
      namespace Tim12Cnt{    ///<counter
          using Addr = Register::Address<0x40001824,0xffff0000,0x00000000,unsigned>;
          ///counter value
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,0),Register::ReadWriteAccess,unsigned> cnt{}; 
      }
      namespace Tim12Psc{    ///<prescaler
          using Addr = Register::Address<0x40001828,0xffff0000,0x00000000,unsigned>;
          ///Prescaler value
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,0),Register::ReadWriteAccess,unsigned> psc{}; 
      }
      namespace Tim12Arr{    ///<auto-reload register
          using Addr = Register::Address<0x4000182c,0xffff0000,0x00000000,unsigned>;
          ///Auto-reload value
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,0),Register::ReadWriteAccess,unsigned> arr{}; 
      }
      namespace Tim12Ccr1{    ///<capture/compare register 1
          using Addr = Register::Address<0x40001834,0xffff0000,0x00000000,unsigned>;
          ///Capture/Compare 1 value
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,0),Register::ReadWriteAccess,unsigned> ccr1{}; 
      }
      namespace Tim12Ccr2{    ///<capture/compare register 2
          using Addr = Register::Address<0x40001838,0xffff0000,0x00000000,unsigned>;
          ///Capture/Compare 2 value
          constexpr Register::FieldLocation<Addr,Register::maskFromRange(15,0),Register::ReadWriteAccess,unsigned> ccr2{}; 
      }
  }
  