text: /*
   * Copyright (c) 2006-2018, RT-Thread Development Team
   *
   * SPDX-License-Identifier: Apache-2.0
   *
   * Change Logs:
   * Date           Author       Notes
   * 2009-01-05     Bernard      first implementation
   */
  
  #include <rthw.h>
  #include <rtthread.h>
  #include "board.h"
  #include "pin_mux.h"
  
  /* MPU configuration. */
  static void BOARD_ConfigMPU(void)
  {
      /* Disable I cache and D cache */
      SCB_DisableICache();
      SCB_DisableDCache();
  
      /* Disable MPU */
      ARM_MPU_Disable();
  
      /* Region 0 setting */
      MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
      MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
  
      /* Region 1 setting */
      MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
      MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
  
      /* Region 2 setting */
      // spi flash: normal type, cacheable, no bufferable, no shareable
      MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
      MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB);
  
      /* Region 3 setting */
      MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
      MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
  
      /* Region 4 setting */
      MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
      MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
  
      /* Region 5 setting */
      MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
      MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
  
      /* Region 6 setting */
      MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
      MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
  
  #if defined(SDRAM_MPU_INIT)
      /* Region 7 setting */
      MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
      MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
  
      /* Region 8 setting */
      MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
      MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
  #endif
  
      /* Enable MPU */
      ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
  
      /* Enable I cache and D cache */
      SCB_EnableDCache();
      SCB_EnableICache();
  }
  
  
  /* This is the timer interrupt service routine. */
  void SysTick_Handler(void)
  {
      /* enter interrupt */
      rt_interrupt_enter();
  
      rt_tick_increase();
  
      /* leave interrupt */
      rt_interrupt_leave();
  }
  
  /* This function will initial STM32 board. */
  void rt_hw_board_init()
  {
      BOARD_ConfigMPU();
      BOARD_InitPins();
      BOARD_BootClockRUN();
  
      SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
  
  #ifdef RT_USING_HEAP
      rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
  #endif
  
  #ifdef RT_USING_COMPONENTS_INIT
      rt_components_board_init();
  #endif
  
  #ifdef RT_USING_CONSOLE
      rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
  #endif
  }
  