text: // Copyright (c) 2021 PaddlePaddle Authors. All Rights Reserved.
  //
  // Licensed under the Apache License, Version 2.0 (the "License");
  // you may not use this file except in compliance with the License.
  // You may obtain a copy of the License at
  //
  //     http://www.apache.org/licenses/LICENSE-2.0
  //
  // Unless required by applicable law or agreed to in writing, software
  // distributed under the License is distributed on an "AS IS" BASIS,
  // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  // See the License for the specific language governing permissions and
  // limitations under the License.
  
  #include "operation/squeeze.h"
  #include "driver/verisilicon_timvx/converter/converter.h"
  #include "utility/debug.h"
  #include "utility/logging.h"
  
  namespace nnadapter {
  namespace verisilicon_timvx {
  
  int ConvertSqueeze(Converter* converter, core::Operation* operation) {
    SQUEEZE_OPERATION_EXTRACT_INPUTS_OUTPUTS
  
    // Convert to tim-vx tensors and operators
    std::vector<uint32_t> mapped_axes;
    if (axes.size() == 0) {
      for (int i = input_operand->type.dimensions.count - 1; i >= 0; i--) {
        if (input_operand->type.dimensions.data[i] == 1) {
          mapped_axes.push_back(ConvertToTimVXAxis(
              i, input_operand->type.dimensions.count)); /* WHCN */
        }
      }
    } else {
      for (int i = axes.size() - 1; i >= 0; i--) {
        int axis = ConvertToTimVXAxis(
            axes[i], input_operand->type.dimensions.count); /* WHCN */
        mapped_axes.push_back(axis);
      }
    }
  
    auto input_tensor = converter->GetMappedTensor(input_operand);
    if (!input_tensor) {
      input_tensor = converter->ConvertOperand(input_operand);
    }
    auto output_tensor = converter->ConvertOperand(output_operand);
    auto squeeze_op =
        converter->graph()->CreateOperation<tim::vx::ops::Squeeze>(mapped_axes);
    squeeze_op->BindInputs({input_tensor});
    squeeze_op->BindOutputs({output_tensor});
    return NNADAPTER_NO_ERROR;
  }
  
  }  // namespace verisilicon_timvx
  }  // namespace nnadapter
  