text: /**************************************************************************//**
   * @file     core_cm3.h
   * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
   * @version  V2.01
   * @date     06. December 2010
   *
   * @note
   * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
   *
   * @par
   * ARM Limited (ARM) is supplying this software for use with Cortex-M
   * processor based microcontrollers.  This file can be freely distributed
   * within development tools that are supporting such ARM based processors.
   *
   * @par
   * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
   * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
   * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
   * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
   * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
   *
   ******************************************************************************/
  #if defined ( __ICCARM__ )
   #pragma system_include  /* treat file as system include file for MISRA check */
  #endif
  
  #ifdef __cplusplus
   extern "C" {
  #endif
  
  #ifndef __CORE_CM3_H_GENERIC
  #define __CORE_CM3_H_GENERIC
  
  /** @addtogroup CMSIS_core_LintCinfiguration CMSIS Core Lint Configuration
    List of Lint messages which will be suppressed and not shown:
      - not yet checked
    .
    Note:  To re-enable a Message, insert a space before 'lint' *
  
   */
  
  
  /*******************************************************************************
   *                 CMSIS definitions
   ******************************************************************************/
  /** @addtogroup CMSIS_core_definitions CMSIS Core Definitions
    This file defines all structures and symbols for CMSIS core:
     - CMSIS version number
     - Cortex-M core
     - Cortex-M core Revision Number
    @{
   */
  
  /*  CMSIS CM3 definitions */
  #define __CM3_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
  #define __CM3_CMSIS_VERSION_SUB   (0x00)                                                       /*!< [15:0]  CMSIS HAL sub version  */
  #define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
  
  #define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
  
  
  #if defined ( __CC_ARM   )
    #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
    #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
  
  #elif defined ( __ICCARM__ )
    #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
    #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
  
  #elif defined   (  __GNUC__  )
    #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
    #define __INLINE __attribute__((always_inline)) inline                                     /*!< inline keyword for GNU Compiler       */
  
  #elif defined   (  __TASKING__  )
    #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
    #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
  
  #endif
  
  #include <stdint.h>                      /*!< standard types definitions                      */
  #include "core_cmInstr.h"                /*!< Core Instruction Access                         */
  #include "core_cmFunc.h"                 /*!< Core Function Access                            */
  
  #endif /* __CORE_CM3_H_GENERIC */
  
  
  #ifndef __CMSIS_GENERIC
  
  #ifndef __CORE_CM3_H_DEPENDANT
  #define __CORE_CM3_H_DEPENDANT
  
  /* IO definitions (access restrictions to peripheral registers) */
  #ifdef __cplusplus
    #define     __I     volatile           /*!< defines 'read only' permissions                 */
  #else
    #define     __I     volatile const     /*!< defines 'read only' permissions                 */
  #endif
  #define     __O     volatile             /*!< defines 'write only' permissions                */
  #define     __IO    volatile             /*!< defines 'read / write' permissions              */
  
  /*@} end of group CMSIS_core_definitions */
  
  
  
  /*******************************************************************************
   *                 Register Abstraction
   ******************************************************************************/
  /** @addtogroup CMSIS_core_register CMSIS Core Register
    Core Register contain:
    - Core Register
    - Core NVIC Register
    - Core SCB Register
    - Core SysTick Register
    - Core Debug Register
    - Core MPU Register
  */
  
  /** \ingroup  CMSIS_core_register
      \defgroup CMSIS_CORE CMSIS Core
    Type definitions for the Cortex-M Core Registers
    @{
   */
  
  /** \brief  Union type to access the Application Program Status Register (APSR).
   */
  typedef union
  {
    struct
    {
  #if (__CORTEX_M != 0x04)
      uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
  #else
      uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
      uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
      uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
  #endif
      uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
      uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
      uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
      uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
      uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
    } b;                                   /*!< Structure used for bit  access                  */
    uint32_t w;                            /*!< Type      used for word access                  */
  } APSR_Type;
  
  
  /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
   */
  typedef union
  {
    struct
    {
      uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
      uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
    } b;                                   /*!< Structure used for bit  access                  */
    uint32_t w;                            /*!< Type      used for word access                  */
  } IPSR_Type;
  
  
  /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
   */
  typedef union
  {
    struct
    {
      uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
  #if (__CORTEX_M != 0x04)
      uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
  #else
      uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
      uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
      uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
  #endif
      uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
      uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
      uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
      uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
      uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
      uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
      uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
    } b;                                   /*!< Structure used for bit  access                  */
    uint32_t w;                            /*!< Type      used for word access                  */
  } xPSR_Type;
  
  
  /** \brief  Union type to access the Control Registers (CONTROL).
   */
  typedef union
  {
    struct
    {
      uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
      uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
      uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
      uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
    } b;                                   /*!< Structure used for bit  access                  */
    uint32_t w;                            /*!< Type      used for word access                  */
  } CONTROL_Type;
  
  /*@} end of group CMSIS_CORE */
  
  
  /** \ingroup  CMSIS_core_register
      \defgroup CMSIS_NVIC CMSIS NVIC
    Type definitions for the Cortex-M NVIC Registers
    @{
   */
  
  /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
   */
  typedef struct
  {
    __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
         uint32_t RESERVED0[24];
    __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
         uint32_t RSERVED1[24];
    __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
         uint32_t RESERVED2[24];
    __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
         uint32_t RESERVED3[24];
    __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
         uint32_t RESERVED4[56];
    __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
         uint32_t RESERVED5[644];
    __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
  }  NVIC_Type;
  
  /*@} end of group CMSIS_NVIC */
  
  
  /** \ingroup  CMSIS_core_register
      \defgroup CMSIS_SCB CMSIS SCB
    Type definitions for the Cortex-M System Control Block Registers
    @{
   */
  
  /** \brief  Structure type to access the System Control Block (SCB).
   */
  typedef struct
  {
    __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPU ID Base Register                                  */
    __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control State Register                      */
    __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
    __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt / Reset Control Register        */
    __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
    __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
    __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
    __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
    __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
    __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  Hard Fault Status Register                            */
    __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
    __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  Mem Manage Address Register                           */
    __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  Bus Fault Address Register                            */
    __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
    __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
    __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
    __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
    __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
    __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  ISA Feature Register                                  */
  } SCB_Type;
  
  /* SCB CPUID Register Definitions */
  #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
  #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
  
  #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
  #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
  
  #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
  #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
  
  #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
  #define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
  
  /* SCB Interrupt Control State Register Definitions */
  #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
  #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
  
  #define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
  #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
  
  #define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
  #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
  
  #define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
  #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
  
  #define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
  #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
  
  #define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
  #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
  
  #define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
  #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
  
  #define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
  #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
  
  #define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
  #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
  
  #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
  #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
  
  /* SCB Interrupt Control State Register Definitions */
  #define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
  #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
  
  #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
  #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
  
  /* SCB Application Interrupt and Reset Control Register Definitions */
  #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
  #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
  
  #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
  #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
  
  #define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
  #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
  
  #define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
  #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
  
  #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
  #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
  
  #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
  #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
  
  #define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
  #define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
  
  /* SCB System Control Register Definitions */
  #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
  #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
  
  #define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
  #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
  
  #define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
  #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
  
  /* SCB Configuration Control Register Definitions */
  #define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
  #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
  
  #define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
  #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
  
  #define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
  #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
  
  #define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
  #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
  
  #define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
  #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
  
  #define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
  #define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
  
  /* SCB System Handler Control and State Register Definitions */
  #define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
  #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
  
  #define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
  #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
  
  #define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
  #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
  
  #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
  #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
  
  #define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
  #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
  
  #define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
  #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
  
  #define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
  #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
  
  #define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
  #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
  
  #define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
  #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
  
  #define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
  #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
  
  #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
  #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
  
  #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
  #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
  
  #define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
  #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
  
  #define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
  #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
  
  /* SCB Configurable Fault Status Registers Definitions */
  #define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
  #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
  
  #define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
  #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
  
  #define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
  #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
  
  /* SCB Hard Fault Status Registers Definitions */
  #define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
  #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
  
  #define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
  #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
  
  #define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
  #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
  
  /* SCB Debug Fault Status Register Definitions */
  #define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
  #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
  
  #define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
  #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
  
  #define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
  #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
  
  #define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
  #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
  
  #define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
  #define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
  
  /*@} end of group CMSIS_SCB */
  
  
  /** \ingroup  CMSIS_core_register
      \defgroup CMSIS_SysTick CMSIS SysTick
    Type definitions for the Cortex-M System Timer Registers
    @{
   */
  
  /** \brief  Structure type to access the System Timer (SysTick).
   */
  typedef struct
  {
    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
    __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
    __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
    __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
  } SysTick_Type;
  
  /* SysTick Control / Status Register Definitions */
  #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
  #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
  
  #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
  #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
  
  #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
  #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
  
  #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
  #define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
  
  /* SysTick Reload Register Definitions */
  #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
  #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
  
  /* SysTick Current Register Definitions */
  #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
  #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
  
  /* SysTick Calibration Register Definitions */
  #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
  #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
  
  #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
  #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
  
  #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
  #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
  
  /*@} end of group CMSIS_SysTick */
  
  
  /** \ingroup  CMSIS_core_register
      \defgroup CMSIS_ITM CMSIS ITM
    Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
    @{
   */
  
  /** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
   */
  typedef struct
  {
    __O  union
    {
      __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
      __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
      __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
    }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
         uint32_t RESERVED0[864];
    __IO uint32_t TER;                     /*!< Offset:       (R/W)  ITM Trace Enable Register                 */
         uint32_t RESERVED1[15];
    __IO uint32_t TPR;                     /*!< Offset:       (R/W)  ITM Trace Privilege Register              */
         uint32_t RESERVED2[15];
    __IO uint32_t TCR;                     /*!< Offset:       (R/W)  ITM Trace Control Register                */
         uint32_t RESERVED3[29];
    __IO uint32_t IWR;                     /*!< Offset:       (R/W)  ITM Integration Write Register            */
    __IO uint32_t IRR;                     /*!< Offset:       (R/W)  ITM Integration Read Register             */
    __IO uint32_t IMCR;                    /*!< Offset:       (R/W)  ITM Integration Mode Control Register     */
         uint32_t RESERVED4[43];
    __IO uint32_t LAR;                     /*!< Offset:       (R/W)  ITM Lock Access Register                  */
    __IO uint32_t LSR;                     /*!< Offset:       (R/W)  ITM Lock Status Register                  */
         uint32_t RESERVED5[6];
    __I  uint32_t PID4;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #4 */
    __I  uint32_t PID5;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #5 */
    __I  uint32_t PID6;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #6 */
    __I  uint32_t PID7;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #7 */
    __I  uint32_t PID0;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #0 */
    __I  uint32_t PID1;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #1 */
    __I  uint32_t PID2;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #2 */
    __I  uint32_t PID3;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #3 */
    __I  uint32_t CID0;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #0 */
    __I  uint32_t CID1;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #1 */
    __I  uint32_t CID2;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #2 */
    __I  uint32_t CID3;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #3 */
  } ITM_Type;
  
  /* ITM Trace Privilege Register Definitions */
  #define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
  #define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
  
  /* ITM Trace Control Register Definitions */
  #define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
  #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
  
  #define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
  #define ITM_TCR_ATBID_Msk                  (0x7FUL << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
  
  #define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
  #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
  
  #define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
  #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
  
  #define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
  #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
  
  #define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
  #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
  
  #define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
  #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
  
  #define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
  #define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
  
  /* ITM Integration Write Register Definitions */
  #define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
  #define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
  
  /* ITM Integration Read Register Definitions */
  #define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
  #define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
  
  /* ITM Integration Mode Control Register Definitions */
  #define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
  #define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
  
  /* ITM Lock Status Register Definitions */
  #define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
  #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
  
  #define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
  #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
  
  #define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
  #define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
  
  /*@}*/ /* end of group CMSIS_ITM */
  
  
  /** \ingroup  CMSIS_core_register
      \defgroup CMSIS_InterruptType CMSIS Interrupt Type
    Type definitions for the Cortex-M Interrupt Type Register
    @{
   */
  
  /** \brief  Structure type to access the Interrupt Type Register.
   */
  typedef struct
  {
         uint32_t RESERVED0;
    __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Control Type Register */
  #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
    __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
  #else
         uint32_t RESERVED1;
  #endif
  } InterruptType_Type;
  
  /* Interrupt Controller Type Register Definitions */
  #define IntType_ICTR_INTLINESNUM_Pos  0                                                   /*!< InterruptType ICTR: INTLINESNUM Position */
  #define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos)             /*!< InterruptType ICTR: INTLINESNUM Mask */
  
  /* Auxiliary Control Register Definitions */
  #define IntType_ACTLR_DISFOLD_Pos     2                                                   /*!< InterruptType ACTLR: DISFOLD Position */
  #define IntType_ACTLR_DISFOLD_Msk    (1UL << IntType_ACTLR_DISFOLD_Pos)                   /*!< InterruptType ACTLR: DISFOLD Mask */
  
  #define IntType_ACTLR_DISDEFWBUF_Pos  1                                                   /*!< InterruptType ACTLR: DISDEFWBUF Position */
  #define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos)                /*!< InterruptType ACTLR: DISDEFWBUF Mask */
  
  #define IntType_ACTLR_DISMCYCINT_Pos  0                                                   /*!< InterruptType ACTLR: DISMCYCINT Position */
  #define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos)                /*!< InterruptType ACTLR: DISMCYCINT Mask */
  
  /*@}*/ /* end of group CMSIS_InterruptType */
  
  
  #if (__MPU_PRESENT == 1)
  /** \ingroup  CMSIS_core_register
      \defgroup CMSIS_MPU CMSIS MPU
    Type definitions for the Cortex-M Memory Protection Unit (MPU)
    @{
   */
  
  /** \brief  Structure type to access the Memory Protection Unit (MPU).
   */
  typedef struct
  {
    __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
    __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
    __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
    __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
    __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
    __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
    __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
    __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
    __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
    __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
    __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
  } MPU_Type;
  
  /* MPU Type Register */
  #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
  #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
  
  #define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
  #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
  
  #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
  #define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
  
  /* MPU Control Register */
  #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
  #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
  
  #define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
  #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
  
  #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
  #define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
  
  /* MPU Region Number Register */
  #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
  #define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
  
  /* MPU Region Base Address Register */
  #define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
  #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
  
  #define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
  #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
  
  #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
  #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
  
  /* MPU Region Attribute and Size Register */
  #define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
  #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
  
  #define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
  #define MPU_RASR_AP_Msk                    (7UL << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
  
  #define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
  #define MPU_RASR_TEX_Msk                   (7UL << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
  
  #define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
  #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
  
  #define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
  #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
  
  #define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
  #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
  
  #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
  #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
  
  #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
  #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
  
  #define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
  #define MPU_RASR_ENA_Msk                    (0x1UL << MPU_RASR_ENA_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
  
  /*@} end of group CMSIS_MPU */
  #endif
  
  
  /** \ingroup  CMSIS_core_register
      \defgroup CMSIS_CoreDebug CMSIS Core Debug
    Type definitions for the Cortex-M Core Debug Registers
    @{
   */
  
  /** \brief  Structure type to access the Core Debug Register (CoreDebug).
   */
  typedef struct
  {
    __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
    __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
    __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
    __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
  } CoreDebug_Type;
  
  /* Debug Halting Control and Status Register */
  #define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
  #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
  
  #define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
  #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
  
  #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
  #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
  
  #define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
  #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
  
  #define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
  #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
  
  #define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
  #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
  
  #define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
  #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
  
  #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
  #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
  
  #define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
  #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
  
  #define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
  #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
  
  #define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
  #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
  
  #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
  #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
  
  /* Debug Core Register Selector Register */
  #define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
  #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
  
  #define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
  #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
  
  /* Debug Exception and Monitor Control Register */
  #define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
  #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
  
  #define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
  #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
  
  #define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
  #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
  
  #define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
  #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
  
  #define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
  #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
  
  #define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
  #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
  
  #define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
  #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
  
  #define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
  #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
  
  #define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
  #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
  
  #define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
  #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
  
  #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
  #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
  
  #define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
  #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
  
  #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
  #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
  
  /*@} end of group CMSIS_CoreDebug */
  
  
  /** \ingroup  CMSIS_core_register
    @{
   */
  
  /* Memory mapping of Cortex-M3 Hardware */
  #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
  #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                  */
  #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
  
  #define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
  #define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
  #define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
  #define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
  #define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
  
  #if (__MPU_PRESENT == 1)
    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit            */
    #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
  #endif
  
  /*@} */
  
  
  
  /*******************************************************************************
   *                Hardware Abstraction Layer
   ******************************************************************************/
  /** \addtogroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
    Core Function Interface contains:
    - Core NVIC Functions
    - Core SysTick Functions
    - Core Debug Functions
    - Core Register Access Functions
  */
  
  
  
  /* ##########################   NVIC functions  #################################### */
  /** \ingroup  CMSIS_Core_FunctionInterface
      \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
    @{
   */
  /** @addtogroup CMSIS_Core_NVICFunctions
   * @{
   */
  /** \brief  Set Priority Grouping
  
    This function sets the priority grouping field using the required unlock sequence.
    The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
    Only values from 0..7 are used.
    In case of a conflict between priority grouping and available
    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
  
      \param [in]      PriorityGroup  Priority grouping field
   */
  static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
  {
    uint32_t reg_value;
    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
  
    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
    reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
    reg_value  =  (reg_value                       |
                  (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
                  (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
    SCB->AIRCR =  reg_value;
  }
  
  
  /** \brief  Get Priority Grouping
  
    This function gets the priority grouping from NVIC Interrupt Controller.
    Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
  
      \return                Priority grouping field
   */
  static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
  {
    return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
  }
  
  
  /** \brief  Enable External Interrupt
  
      This function enables a device specific interupt in the NVIC interrupt controller.
      The interrupt number cannot be a negative value.
  
      \param [in]      IRQn  Number of the external interrupt to enable
   */
  static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
  {
    NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
  }
  
  
  /** \brief  Disable External Interrupt
  
      This function disables a device specific interupt in the NVIC interrupt controller.
      The interrupt number cannot be a negative value.
  
      \param [in]      IRQn  Number of the external interrupt to disable
   */
  static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
  {
    NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
  }
  
  
  /** \brief  Get Pending Interrupt
  
      This function reads the pending register in the NVIC and returns the pending bit
      for the specified interrupt.
  
      \param [in]      IRQn  Number of the interrupt for get pending
      \return             0  Interrupt status is not pending
      \return             1  Interrupt status is pending
   */
  static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
  {
    return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
  }
  
  
  /** \brief  Set Pending Interrupt
  
      This function sets the pending bit for the specified interrupt.
      The interrupt number cannot be a negative value.
  
      \param [in]      IRQn  Number of the interrupt for set pending
   */
  static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
  {
    NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
  }
  
  
  /** \brief  Clear Pending Interrupt
  
      This function clears the pending bit for the specified interrupt.
      The interrupt number cannot be a negative value.
  
      \param [in]      IRQn  Number of the interrupt for clear pending
   */
  static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  {
    NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
  }
  
  
  /** \brief  Get Active Interrupt
  
      This function reads the active register in NVIC and returns the active bit.
      \param [in]      IRQn  Number of the interrupt for get active
      \return             0  Interrupt status is not active
      \return             1  Interrupt status is active
   */
  static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
  {
    return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
  }
  
  
  /** \brief  Set Interrupt Priority
  
      This function sets the priority for the specified interrupt. The interrupt
      number can be positive to specify an external (device specific)
      interrupt, or negative to specify an internal (core) interrupt.
  
      Note: The priority cannot be set for every core interrupt.
  
      \param [in]      IRQn  Number of the interrupt for set priority
      \param [in]  priority  Priority to set
   */
  static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
  {
    if(IRQn < 0) {
      SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
    else {
      NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
  }
  
  
  /** \brief  Get Interrupt Priority
  
      This function reads the priority for the specified interrupt. The interrupt
      number can be positive to specify an external (device specific)
      interrupt, or negative to specify an internal (core) interrupt.
  
      The returned priority value is automatically aligned to the implemented
      priority bits of the microcontroller.
  
      \param [in]   IRQn  Number of the interrupt for get priority
      \return             Interrupt Priority
   */
  static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
  {
  
    if(IRQn < 0) {
      return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
    else {
      return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
  }
  
  
  /** \brief  Encode Priority
  
      This function encodes the priority for an interrupt with the given priority group,
      preemptive priority value and sub priority value.
      In case of a conflict between priority grouping and available
      priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
  
      The returned priority value can be used for NVIC_SetPriority(...) function
  
      \param [in]     PriorityGroup  Used priority group
      \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
      \param [in]       SubPriority  Sub priority value (starting from 0)
      \return                        Encoded priority for the interrupt
   */
  static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
  {
    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
    uint32_t PreemptPriorityBits;
    uint32_t SubPriorityBits;
  
    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
  
    return (
             ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
             ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
           );
  }
  
  
  /** \brief  Decode Priority
  
      This function decodes an interrupt priority value with the given priority group to
      preemptive priority value and sub priority value.
      In case of a conflict between priority grouping and available
      priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
  
      The priority value can be retrieved with NVIC_GetPriority(...) function
  
      \param [in]         Priority   Priority value
      \param [in]     PriorityGroup  Used priority group
      \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
      \param [out]     pSubPriority  Sub priority value (starting from 0)
   */
  static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
  {
    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
    uint32_t PreemptPriorityBits;
    uint32_t SubPriorityBits;
  
    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
  
    *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
    *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
  }
  
  
  /** \brief  System Reset
  
      This function initiate a system reset request to reset the MCU.
   */
  static __INLINE void NVIC_SystemReset(void)
  {
    __DSB();                                                     /* Ensure all outstanding memory accesses included
                                                                    buffered write are completed before reset */
    SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
                   (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                   SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
    __DSB();                                                     /* Ensure completion of memory access */
    while(1);                                                    /* wait until reset */
  }
  
  /*@} end of CMSIS_Core_NVICFunctions */
  
  
  /**
   * @}
   */
  /* ##################################    SysTick function  ############################################ */
  /** \ingroup  CMSIS_Core_FunctionInterface
      \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
    @{
   */
  /** @addtogroup CMSIS_Core_SysTickFunctions
   * @{
   */
  #if (__Vendor_SysTickConfig == 0)
  
  /** \brief  System Tick Configuration
  
      This function initialises the system tick timer and its interrupt and start the system tick timer.
      Counter is in free running mode to generate periodical interrupts.
  
      \param [in]  ticks  Number of ticks between two interrupts
      \return          0  Function succeeded
      \return          1  Function failed
   */
  static __INLINE uint32_t SysTick_Config(uint32_t ticks)
  {
    if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
  
    SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
    NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
    SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
                     SysTick_CTRL_TICKINT_Msk   |
                     SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
    return (0);                                                  /* Function successful */
  }
  
  #endif
  
  /*@} end of CMSIS_Core_SysTickFunctions */
  
  
  
  /* ##################################### Debug In/Output function ########################################### */
  /** \ingroup  CMSIS_Core_FunctionInterface
      \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
    @{
   */
  
  extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
  #define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
  
  
  /** \brief  ITM Send Character
  
      This function transmits a character via the ITM channel 0.
      It just returns when no debugger is connected that has booked the output.
      It is blocking when a debugger is connected, but the previous character send is not transmitted.
  
      \param [in]     ch  Character to transmit
      \return             Character to transmit
   */
  static __INLINE uint32_t ITM_SendChar (uint32_t ch)
  {
    if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
        (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
        (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
    {
      while (ITM->PORT[0].u32 == 0);
      ITM->PORT[0].u8 = (uint8_t) ch;
    }
    return (ch);
  }
  
  
  /** \brief  ITM Receive Character
  
      This function inputs a character via external variable ITM_RxBuffer.
      It just returns when no debugger is connected that has booked the output.
      It is blocking when a debugger is connected, but the previous character send is not transmitted.
  
      \return             Received character
      \return         -1  No character received
   */
  static __INLINE int32_t ITM_ReceiveChar (void) {
    int32_t ch = -1;                           /* no character available */
  
    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
      ch = ITM_RxBuffer;
      ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
    }
  
    return (ch);
  }
  
  
  /** \brief  ITM Check Character
  
      This function checks external variable ITM_RxBuffer whether a character is available or not.
      It returns '1' if a character is available and '0' if no character is available.
  
      \return          0  No character available
      \return          1  Character available
   */
  static __INLINE int32_t ITM_CheckChar (void) {
  
    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
      return (0);                                 /* no character available */
    } else {
      return (1);                                 /*    character available */
    }
  }
  
  /*@} end of CMSIS_core_DebugFunctions */
  /**
   * @}
   */
  
  #endif /* __CORE_CM3_H_DEPENDANT */
  
  #endif /* __CMSIS_GENERIC */
  
  #ifdef __cplusplus
  }
  #endif
  
  /*lint -restore */
  