text: #ifndef IP_BASE_M00_REGSLICE_29_H_
  #define IP_BASE_M00_REGSLICE_29_H_
  
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  #ifndef XTLM
  #include "xtlm.h"
  #endif
  
  #ifndef SYSTEMC_INCLUDED
  #include <systemc>
  #endif
  
  #if defined(_MSC_VER)
  #define DllExport __declspec(dllexport)
  #elif defined(__GNUC__)
  #define DllExport __attribute__ ((visibility("default")))
  #else
  #define DllExport
  #endif
  
  #include "base_m00_regslice_29_sc.h"
  
  class DllExport base_m00_regslice_29 : public base_m00_regslice_29_sc
  {
  public:
  
    base_m00_regslice_29(const sc_core::sc_module_name& nm);
    virtual ~base_m00_regslice_29();
  
  public: // module pin-to-pin RTL interface
  
    sc_core::sc_in< bool > aclk;
    sc_core::sc_in< bool > aresetn;
    sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_awid;
    sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_awaddr;
    sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_awlen;
    sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awsize;
    sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_awburst;
    sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_awlock;
    sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awcache;
    sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
    sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awregion;
    sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_awqos;
    sc_core::sc_in< bool > s_axi_awvalid;
    sc_core::sc_out< bool > s_axi_awready;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
    sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
    sc_core::sc_in< bool > s_axi_wlast;
    sc_core::sc_in< bool > s_axi_wvalid;
    sc_core::sc_out< bool > s_axi_wready;
    sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_bid;
    sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
    sc_core::sc_out< bool > s_axi_bvalid;
    sc_core::sc_in< bool > s_axi_bready;
    sc_core::sc_in< sc_dt::sc_bv<12> > s_axi_arid;
    sc_core::sc_in< sc_dt::sc_bv<16> > s_axi_araddr;
    sc_core::sc_in< sc_dt::sc_bv<8> > s_axi_arlen;
    sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arsize;
    sc_core::sc_in< sc_dt::sc_bv<2> > s_axi_arburst;
    sc_core::sc_in< sc_dt::sc_bv<1> > s_axi_arlock;
    sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arcache;
    sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
    sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arregion;
    sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_arqos;
    sc_core::sc_in< bool > s_axi_arvalid;
    sc_core::sc_out< bool > s_axi_arready;
    sc_core::sc_out< sc_dt::sc_bv<12> > s_axi_rid;
    sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
    sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
    sc_core::sc_out< bool > s_axi_rlast;
    sc_core::sc_out< bool > s_axi_rvalid;
    sc_core::sc_in< bool > s_axi_rready;
    sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_awid;
    sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_awaddr;
    sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_awlen;
    sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awsize;
    sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_awburst;
    sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_awlock;
    sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awcache;
    sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
    sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awregion;
    sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_awqos;
    sc_core::sc_out< bool > m_axi_awvalid;
    sc_core::sc_in< bool > m_axi_awready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
    sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
    sc_core::sc_out< bool > m_axi_wlast;
    sc_core::sc_out< bool > m_axi_wvalid;
    sc_core::sc_in< bool > m_axi_wready;
    sc_core::sc_in< sc_dt::sc_bv<12> > m_axi_bid;
    sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
    sc_core::sc_in< bool > m_axi_bvalid;
    sc_core::sc_out< bool > m_axi_bready;
    sc_core::sc_out< sc_dt::sc_bv<12> > m_axi_arid;
    sc_core::sc_out< sc_dt::sc_bv<16> > m_axi_araddr;
    sc_core::sc_out< sc_dt::sc_bv<8> > m_axi_arlen;
    sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arsize;
    sc_core::sc_out< sc_dt::sc_bv<2> > m_axi_arburst;
    sc_core::sc_out< sc_dt::sc_bv<1> > m_axi_arlock;
    sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arcache;
    sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
    sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arregion;
    sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_arqos;
    sc_core::sc_out< bool > m_axi_arvalid;
    sc_core::sc_in< bool > m_axi_arready;
    sc_core::sc_in< sc_dt::sc_bv<12> > m_axi_rid;
    sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
    sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
    sc_core::sc_in< bool > m_axi_rlast;
    sc_core::sc_in< bool > m_axi_rvalid;
    sc_core::sc_out< bool > m_axi_rready;
  
  protected:
  
    virtual void before_end_of_elaboration();
  
  private:
  
    xtlm::xaximm_xtlm2pin_t<32,16,12,1,1,1,1,1>* mp_M_AXI_transactor;
    xsc::common::scalar2vector_converter* mp_m_axi_arlock_converter;
    sc_signal< bool > m_m_axi_arlock_converter_signal;
    xsc::common::scalar2vector_converter* mp_m_axi_awlock_converter;
    sc_signal< bool > m_m_axi_awlock_converter_signal;
    sc_signal< bool > m_M_AXI_transactor_rst_signal;
  
    xtlm::xaximm_pin2xtlm_t<32,16,12,1,1,1,1,1>* mp_S_AXI_transactor;
    xsc::common::vector2scalar_converter* mp_s_axi_arlock_converter;
    sc_signal< bool > m_s_axi_arlock_converter_signal;
    xsc::common::vector2scalar_converter* mp_s_axi_awlock_converter;
    sc_signal< bool > m_s_axi_awlock_converter_signal;
    sc_signal< bool > m_S_AXI_transactor_rst_signal;
  
  };
  
  #endif // IP_BASE_M00_REGSLICE_29_H_
  