text: // Copyright 2017 Espressif Systems (Shanghai) PTE LTD
  //
  // Licensed under the Apache License, Version 2.0 (the "License");
  // you may not use this file except in compliance with the License.
  // You may obtain a copy of the License at
  //
  //     http://www.apache.org/licenses/LICENSE-2.0
  //
  // Unless required by applicable law or agreed to in writing, software
  // distributed under the License is distributed on an "AS IS" BASIS,
  // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  // See the License for the specific language governing permissions and
  // limitations under the License.
  #include "sdkconfig.h"
  #include "soc/soc.h"
  #include "soc/rtc.h"
  #include "soc/dport_reg.h"
  #include "soc/efuse_periph.h"
  #include "soc/rtc_cntl_reg.h"
  
  #ifdef CONFIG_IDF_TARGET_ESP32
  #include "esp32/rom/rtc.h"
  #define CPU_RESET_REASON SW_CPU_RESET
  #elif CONFIG_IDF_TARGET_ESP32S2
  #include "esp32s2/rom/rtc.h"
  #define CPU_RESET_REASON RTC_SW_CPU_RESET
  #endif
  #include "esp_rom_uart.h"
  
  void bootloader_clock_configure(void)
  {
      // ROM bootloader may have put a lot of text into UART0 FIFO.
      // Wait for it to be printed.
      // This is not needed on power on reset, when ROM bootloader is running at
      // 40 MHz. But in case of TG WDT reset, CPU may still be running at >80 MHZ,
      // and will be done with the bootloader much earlier than UART FIFO is empty.
      esp_rom_uart_tx_wait_idle(0);
  
      /* Set CPU to 80MHz. Keep other clocks unmodified. */
      int cpu_freq_mhz = 80;
      
  #if CONFIG_IDF_TARGET_ESP32
      /* On ESP32 rev 0, switching to 80/160 MHz if clock was previously set to
       * 240 MHz may cause the chip to lock up (see section 3.5 of the errata
       * document). For rev. 0, switch to 240 instead if it has been enabled
       * previously.
       */
      uint32_t chip_ver_reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
      if ((chip_ver_reg & EFUSE_RD_CHIP_VER_REV1_M) == 0 &&
              DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL) == DPORT_CPUPERIOD_SEL_240) {
          cpu_freq_mhz = 240;
      }
  #endif
      if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) {
          rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
      #if CONFIG_IDF_TARGET_ESP32
          clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ;
      #endif
          /* ESP32-S2 doesn't have XTAL_FREQ choice, always 40MHz */
          clk_cfg.cpu_freq_mhz = cpu_freq_mhz;
          clk_cfg.slow_freq = rtc_clk_slow_freq_get();
          clk_cfg.fast_freq = rtc_clk_fast_freq_get();
          rtc_clk_init(clk_cfg);
          /* As a slight optimization, if 32k XTAL was enabled in sdkconfig, we enable
          * it here. Usually it needs some time to start up, so we amortize at least
          * part of the start up time by enabling 32k XTAL early.
          * App startup code will wait until the oscillator has started up.
          */
      }
  
  #if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
      if (!rtc_clk_32k_enabled()) {
          rtc_clk_32k_bootstrap(CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES);
      }
  #endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
  }
  
  #ifdef BOOTLOADER_BUILD
  
  int esp_clk_apb_freq(void)
  {
      return rtc_clk_apb_freq_get();
  }
  
  #endif // BOOTLOADER_BUILD
  