text: /*
   *	Intel SMP support routines.
   *
   *	(c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
   *	(c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
   *      (c) 2002,2003 Andi Kleen, SuSE Labs.
   *
   *	i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
   *
   *	This code is released under the GNU General Public License version 2 or
   *	later.
   */
  
  #include <linux/init.h>
  
  #include <linux/mm.h>
  #include <linux/delay.h>
  #include <linux/spinlock.h>
  #include <linux/export.h>
  #include <linux/kernel_stat.h>
  #include <linux/mc146818rtc.h>
  #include <linux/cache.h>
  #include <linux/interrupt.h>
  #include <linux/cpu.h>
  #include <linux/gfp.h>
  
  #include <asm/mtrr.h>
  #include <asm/tlbflush.h>
  #include <asm/mmu_context.h>
  #include <asm/proto.h>
  #include <asm/apic.h>
  #include <asm/nmi.h>
  /*
   *	Some notes on x86 processor bugs affecting SMP operation:
   *
   *	Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
   *	The Linux implications for SMP are handled as follows:
   *
   *	Pentium III / [Xeon]
   *		None of the E1AP-E3AP errata are visible to the user.
   *
   *	E1AP.	see PII A1AP
   *	E2AP.	see PII A2AP
   *	E3AP.	see PII A3AP
   *
   *	Pentium II / [Xeon]
   *		None of the A1AP-A3AP errata are visible to the user.
   *
   *	A1AP.	see PPro 1AP
   *	A2AP.	see PPro 2AP
   *	A3AP.	see PPro 7AP
   *
   *	Pentium Pro
   *		None of 1AP-9AP errata are visible to the normal user,
   *	except occasional delivery of 'spurious interrupt' as trap #15.
   *	This is very rare and a non-problem.
   *
   *	1AP.	Linux maps APIC as non-cacheable
   *	2AP.	worked around in hardware
   *	3AP.	fixed in C0 and above steppings microcode update.
   *		Linux does not use excessive STARTUP_IPIs.
   *	4AP.	worked around in hardware
   *	5AP.	symmetric IO mode (normal Linux operation) not affected.
   *		'noapic' mode has vector 0xf filled out properly.
   *	6AP.	'noapic' mode might be affected - fixed in later steppings
   *	7AP.	We do not assume writes to the LVT deassering IRQs
   *	8AP.	We do not enable low power mode (deep sleep) during MP bootup
   *	9AP.	We do not use mixed mode
   *
   *	Pentium
   *		There is a marginal case where REP MOVS on 100MHz SMP
   *	machines with B stepping processors can fail. XXX should provide
   *	an L1cache=Writethrough or L1cache=off option.
   *
   *		B stepping CPUs may hang. There are hardware work arounds
   *	for this. We warn about it in case your board doesn't have the work
   *	arounds. Basically that's so I can tell anyone with a B stepping
   *	CPU and SMP problems "tough".
   *
   *	Specific items [From Pentium Processor Specification Update]
   *
   *	1AP.	Linux doesn't use remote read
   *	2AP.	Linux doesn't trust APIC errors
   *	3AP.	We work around this
   *	4AP.	Linux never generated 3 interrupts of the same priority
   *		to cause a lost local interrupt.
   *	5AP.	Remote read is never used
   *	6AP.	not affected - worked around in hardware
   *	7AP.	not affected - worked around in hardware
   *	8AP.	worked around in hardware - we get explicit CS errors if not
   *	9AP.	only 'noapic' mode affected. Might generate spurious
   *		interrupts, we log only the first one and count the
   *		rest silently.
   *	10AP.	not affected - worked around in hardware
   *	11AP.	Linux reads the APIC between writes to avoid this, as per
   *		the documentation. Make sure you preserve this as it affects
   *		the C stepping chips too.
   *	12AP.	not affected - worked around in hardware
   *	13AP.	not affected - worked around in hardware
   *	14AP.	we always deassert INIT during bootup
   *	15AP.	not affected - worked around in hardware
   *	16AP.	not affected - worked around in hardware
   *	17AP.	not affected - worked around in hardware
   *	18AP.	not affected - worked around in hardware
   *	19AP.	not affected - worked around in BIOS
   *
   *	If this sounds worrying believe me these bugs are either ___RARE___,
   *	or are signal timing bugs worked around in hardware and there's
   *	about nothing of note with C stepping upwards.
   */
  
  /*
   * this function sends a 'reschedule' IPI to another CPU.
   * it goes straight through and wastes no time serializing
   * anything. Worst case is that we lose a reschedule ...
   */
  static void native_smp_send_reschedule(int cpu)
  {
  	if (unlikely(cpu_is_offline(cpu))) {
  		WARN_ON(1);
  		return;
  	}
  	apic->send_IPI_mask(cpumask_of(cpu), RESCHEDULE_VECTOR);
  }
  
  void native_send_call_func_single_ipi(int cpu)
  {
  	apic->send_IPI_mask(cpumask_of(cpu), CALL_FUNCTION_SINGLE_VECTOR);
  }
  
  void native_send_call_func_ipi(const struct cpumask *mask)
  {
  	cpumask_var_t allbutself;
  
  	if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) {
  		apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
  		return;
  	}
  
  	cpumask_copy(allbutself, cpu_online_mask);
  	cpumask_clear_cpu(smp_processor_id(), allbutself);
  
  	if (cpumask_equal(mask, allbutself) &&
  	    cpumask_equal(cpu_online_mask, cpu_callout_mask))
  		apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR);
  	else
  		apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
  
  	free_cpumask_var(allbutself);
  }
  
  static atomic_t stopping_cpu = ATOMIC_INIT(-1);
  
  static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
  {
  	/* We are registered on stopping cpu too, avoid spurious NMI */
  	if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
  		return NMI_HANDLED;
  
  	stop_this_cpu(NULL);
  
  	return NMI_HANDLED;
  }
  
  static void native_nmi_stop_other_cpus(int wait)
  {
  	unsigned long flags;
  	unsigned long timeout;
  
  	if (reboot_force)
  		return;
  
  	/*
  	 * Use an own vector here because smp_call_function
  	 * does lots of things not suitable in a panic situation.
  	 */
  	if (num_online_cpus() > 1) {
  		/* did someone beat us here? */
  		if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1)
  			return;
  
  		if (register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
  					 NMI_FLAG_FIRST, "smp_stop"))
  			/* Note: we ignore failures here */
  			return;
  
  		/* sync above data before sending NMI */
  		wmb();
  
  		apic->send_IPI_allbutself(NMI_VECTOR);
  
  		/*
  		 * Don't wait longer than a second if the caller
  		 * didn't ask us to wait.
  		 */
  		timeout = USEC_PER_SEC;
  		while (num_online_cpus() > 1 && (wait || timeout--))
  			udelay(1);
  	}
  
  	local_irq_save(flags);
  	disable_local_APIC();
  	local_irq_restore(flags);
  }
  
  /*
   * this function calls the 'stop' function on all other CPUs in the system.
   */
  
  asmlinkage void smp_reboot_interrupt(void)
  {
  	ack_APIC_irq();
  	irq_enter();
  	stop_this_cpu(NULL);
  	irq_exit();
  }
  
  static void native_irq_stop_other_cpus(int wait)
  {
  	unsigned long flags;
  	unsigned long timeout;
  
  	if (reboot_force)
  		return;
  
  	/*
  	 * Use an own vector here because smp_call_function
  	 * does lots of things not suitable in a panic situation.
  	 * On most systems we could also use an NMI here,
  	 * but there are a few systems around where NMI
  	 * is problematic so stay with an non NMI for now
  	 * (this implies we cannot stop CPUs spinning with irq off
  	 * currently)
  	 */
  	if (num_online_cpus() > 1) {
  		apic->send_IPI_allbutself(REBOOT_VECTOR);
  
  		/*
  		 * Don't wait longer than a second if the caller
  		 * didn't ask us to wait.
  		 */
  		timeout = USEC_PER_SEC;
  		while (num_online_cpus() > 1 && (wait || timeout--))
  			udelay(1);
  	}
  
  	local_irq_save(flags);
  	disable_local_APIC();
  	local_irq_restore(flags);
  }
  
  static void native_smp_disable_nmi_ipi(void)
  {
  	smp_ops.stop_other_cpus = native_irq_stop_other_cpus;
  }
  
  /*
   * Reschedule call back.
   */
  void smp_reschedule_interrupt(struct pt_regs *regs)
  {
  	ack_APIC_irq();
  	inc_irq_stat(irq_resched_count);
  	scheduler_ipi();
  	/*
  	 * KVM uses this interrupt to force a cpu out of guest mode
  	 */
  }
  
  void smp_call_function_interrupt(struct pt_regs *regs)
  {
  	ack_APIC_irq();
  	irq_enter();
  	generic_smp_call_function_interrupt();
  	inc_irq_stat(irq_call_count);
  	irq_exit();
  }
  
  void smp_call_function_single_interrupt(struct pt_regs *regs)
  {
  	ack_APIC_irq();
  	irq_enter();
  	generic_smp_call_function_single_interrupt();
  	inc_irq_stat(irq_call_count);
  	irq_exit();
  }
  
  static int __init nonmi_ipi_setup(char *str)
  {
          native_smp_disable_nmi_ipi();
          return 1;
  }
  
  __setup("nonmi_ipi", nonmi_ipi_setup);
  
  struct smp_ops smp_ops = {
  	.smp_prepare_boot_cpu	= native_smp_prepare_boot_cpu,
  	.smp_prepare_cpus	= native_smp_prepare_cpus,
  	.smp_cpus_done		= native_smp_cpus_done,
  
  	.stop_other_cpus	= native_nmi_stop_other_cpus,
  	.smp_send_reschedule	= native_smp_send_reschedule,
  
  	.cpu_up			= native_cpu_up,
  	.cpu_die		= native_cpu_die,
  	.cpu_disable		= native_cpu_disable,
  	.play_dead		= native_play_dead,
  
  	.send_call_func_ipi	= native_send_call_func_ipi,
  	.send_call_func_single_ipi = native_send_call_func_single_ipi,
  };
  EXPORT_SYMBOL_GPL(smp_ops);
  