text: /**
   * @brief Registers for configuring the watchdog
   */
  
  #pragma once
  
  #include "registers/register_helpers.h"
  
  
  // WDT Register offsets
  #define WDT_LOAD_OFFSET      0x00000000
  #define WDT_VALUE_OFFSET     0x00000004
  #define WDT_CTL_OFFSET       0x00000008
  #define WDT_ICR_OFFSET       0x0000000C
  #define WDT_RIS_OFFSET       0x00000010
  #define WDT_MIS_OFFSET       0x00000014
  #define WDT_TEST_OFFSET      0x00000418
  #define WDT_LOCK_OFFSET      0x00000C00
  #define WDT_PeriphID4_OFFSET 0x00000FD0
  #define WDT_PeriphID5_OFFSET 0x00000FD4
  #define WDT_PeriphID6_OFFSET 0x00000FD8
  #define WDT_PeriphID7_OFFSET 0x00000FDC
  #define WDT_PeriphID0_OFFSET 0x00000FE0
  #define WDT_PeriphID1_OFFSET 0x00000FE4
  #define WDT_PeriphID2_OFFSET 0x00000FE8
  #define WDT_PeriphID3_OFFSET 0x00000FEC
  #define WDT_PCellID0_OFFSET  0x00000FF0
  #define WDT_PCellID1_OFFSET  0x00000FF4
  #define WDT_PCellID2_OFFSET  0x00000FF8
  #define WDT_PCellID3_OFFSET  0x00000FFC
  
  
  // WDT0 Base
  #define WDT0_BASE 0x40000000
  
  // WDT0 Registers
  #define WDT0_LOAD      REGISTER(WDT0_BASE + WDT_LOAD_OFFSET)
  #define WDT0_VALUE     REGISTER(WDT0_BASE + WDT_VALUE_OFFSET)
  #define WDT0_CTL       REGISTER(WDT0_BASE + WDT_CTL_OFFSET)
  #define WDT0_ICR       REGISTER(WDT0_BASE + WDT_ICR_OFFSET)
  #define WDT0_RIS       REGISTER(WDT0_BASE + WDT_RIS_OFFSET)
  #define WDT0_MIS       REGISTER(WDT0_BASE + WDT_MIS_OFFSET)
  #define WDT0_TEST      REGISTER(WDT0_BASE + WDT_TEST_OFFSET)
  #define WDT0_LOCK      REGISTER(WDT0_BASE + WDT_LOCK_OFFSET)
  #define WDT0_PeriphID4 REGISTER(WDT0_BASE + WDT_PeriphID4_OFFSET)
  #define WDT0_PeriphID5 REGISTER(WDT0_BASE + WDT_PeriphID5_OFFSET)
  #define WDT0_PeriphID6 REGISTER(WDT0_BASE + WDT_PeriphID6_OFFSET)
  #define WDT0_PeriphID7 REGISTER(WDT0_BASE + WDT_PeriphID7_OFFSET)
  #define WDT0_PeriphID0 REGISTER(WDT0_BASE + WDT_PeriphID0_OFFSET)
  #define WDT0_PeriphID1 REGISTER(WDT0_BASE + WDT_PeriphID1_OFFSET)
  #define WDT0_PeriphID2 REGISTER(WDT0_BASE + WDT_PeriphID2_OFFSET)
  #define WDT0_PeriphID3 REGISTER(WDT0_BASE + WDT_PeriphID3_OFFSET)
  #define WDT0_PCellID0  REGISTER(WDT0_BASE + WDT_PCellID0_OFFSET)
  #define WDT0_PCellID1  REGISTER(WDT0_BASE + WDT_PCellID1_OFFSET)
  #define WDT0_PCellID2  REGISTER(WDT0_BASE + WDT_PCellID2_OFFSET)
  #define WDT0_PCellID3  REGISTER(WDT0_BASE + WDT_PCellID3_OFFSET)
  
  
  // WDT1 Base
  #define WDT1_BASE 0x40001000
  
  // WDT1 Registers
  #define WDT1_LOAD      REGISTER(WDT1_BASE + WDT_LOAD_OFFSET)
  #define WDT1_VALUE     REGISTER(WDT1_BASE + WDT_VALUE_OFFSET)
  #define WDT1_CTL       REGISTER(WDT1_BASE + WDT_CTL_OFFSET)
  #define WDT1_ICR       REGISTER(WDT1_BASE + WDT_ICR_OFFSET)
  #define WDT1_RIS       REGISTER(WDT1_BASE + WDT_RIS_OFFSET)
  #define WDT1_MIS       REGISTER(WDT1_BASE + WDT_MIS_OFFSET)
  #define WDT1_TEST      REGISTER(WDT1_BASE + WDT_TEST_OFFSET)
  #define WDT1_LOCK      REGISTER(WDT1_BASE + WDT_LOCK_OFFSET)
  #define WDT1_PeriphID4 REGISTER(WDT1_BASE + WDT_PeriphID4_OFFSET)
  #define WDT1_PeriphID5 REGISTER(WDT1_BASE + WDT_PeriphID5_OFFSET)
  #define WDT1_PeriphID6 REGISTER(WDT1_BASE + WDT_PeriphID6_OFFSET)
  #define WDT1_PeriphID7 REGISTER(WDT1_BASE + WDT_PeriphID7_OFFSET)
  #define WDT1_PeriphID0 REGISTER(WDT1_BASE + WDT_PeriphID0_OFFSET)
  #define WDT1_PeriphID1 REGISTER(WDT1_BASE + WDT_PeriphID1_OFFSET)
  #define WDT1_PeriphID2 REGISTER(WDT1_BASE + WDT_PeriphID2_OFFSET)
  #define WDT1_PeriphID3 REGISTER(WDT1_BASE + WDT_PeriphID3_OFFSET)
  #define WDT1_PCellID0  REGISTER(WDT1_BASE + WDT_PCellID0_OFFSET)
  #define WDT1_PCellID1  REGISTER(WDT1_BASE + WDT_PCellID1_OFFSET)
  #define WDT1_PCellID2  REGISTER(WDT1_BASE + WDT_PCellID2_OFFSET)
  #define WDT1_PCellID3  REGISTER(WDT1_BASE + WDT_PCellID3_OFFSET)
  
  