text: /* Generated automatically by the program `gencodes'
     from the machine description file `md'.  */
  
  #ifndef GCC_INSN_CODES_H
  #define GCC_INSN_CODES_H
  
  enum insn_code {
    CODE_FOR_nothing = 0,
  
    CODE_FOR_x86_fnstsw_1 = 47,
    CODE_FOR_x86_sahf_1 = 48,
    CODE_FOR_kmovw = 84,
    CODE_FOR_movsi_insv_1 = 109,
  #define CODE_FOR_movdi_insv_1 CODE_FOR_nothing
    CODE_FOR_swapxf = 119,
  #define CODE_FOR_zero_extendqidi2 CODE_FOR_nothing
  #define CODE_FOR_zero_extendhidi2 CODE_FOR_nothing
    CODE_FOR_zero_extendqisi2_and = 123,
    CODE_FOR_zero_extendhisi2_and = 124,
    CODE_FOR_zero_extendqihi2_and = 127,
    CODE_FOR_extendsidi2_1 = 129,
  #define CODE_FOR_extendqidi2 CODE_FOR_nothing
  #define CODE_FOR_extendhidi2 CODE_FOR_nothing
    CODE_FOR_extendhisi2 = 130,
    CODE_FOR_extendqisi2 = 131,
    CODE_FOR_extendqihi2 = 132,
    CODE_FOR_truncxfsf2_i387_noop = 146,
    CODE_FOR_truncxfdf2_i387_noop = 147,
    CODE_FOR_fix_truncsfsi_sse = 152,
  #define CODE_FOR_fix_truncsfdi_sse CODE_FOR_nothing
    CODE_FOR_fix_truncdfsi_sse = 153,
  #define CODE_FOR_fix_truncdfdi_sse CODE_FOR_nothing
    CODE_FOR_fix_trunchi_fisttp_i387_1 = 154,
    CODE_FOR_fix_truncsi_fisttp_i387_1 = 155,
    CODE_FOR_fix_truncdi_fisttp_i387_1 = 156,
    CODE_FOR_fix_trunchi_i387_fisttp = 157,
    CODE_FOR_fix_truncsi_i387_fisttp = 158,
    CODE_FOR_fix_truncdi_i387_fisttp = 159,
    CODE_FOR_fix_trunchi_i387_fisttp_with_temp = 160,
    CODE_FOR_fix_truncsi_i387_fisttp_with_temp = 161,
    CODE_FOR_fix_truncdi_i387_fisttp_with_temp = 162,
    CODE_FOR_fix_truncdi_i387 = 166,
    CODE_FOR_fix_truncdi_i387_with_temp = 167,
    CODE_FOR_fix_trunchi_i387 = 168,
    CODE_FOR_fix_truncsi_i387 = 169,
    CODE_FOR_fix_trunchi_i387_with_temp = 170,
    CODE_FOR_fix_truncsi_i387_with_temp = 171,
    CODE_FOR_x86_fnstcw_1 = 172,
    CODE_FOR_x86_fldcw_1 = 173,
    CODE_FOR_floathisf2 = 174,
    CODE_FOR_floathidf2 = 175,
    CODE_FOR_floathixf2 = 176,
    CODE_FOR_floatsixf2 = 177,
    CODE_FOR_floatdixf2 = 178,
    CODE_FOR_floatdisf2_i387_with_xmm = 185,
    CODE_FOR_floatdidf2_i387_with_xmm = 186,
    CODE_FOR_floatdixf2_i387_with_xmm = 187,
    CODE_FOR_addqi3_cc = 196,
  #define CODE_FOR_addsi_1_zext CODE_FOR_nothing
    CODE_FOR_addqi_ext_1 = 217,
    CODE_FOR_adcxsi3 = 263,
    CODE_FOR_adcxdi3 = 264,
    CODE_FOR_divmodsi4_1 = 286,
  #define CODE_FOR_divmoddi4_1 CODE_FOR_nothing
    CODE_FOR_divmodhiqi3 = 291,
    CODE_FOR_udivmodsi4_1 = 292,
  #define CODE_FOR_udivmoddi4_1 CODE_FOR_nothing
    CODE_FOR_udivmodhiqi3 = 297,
    CODE_FOR_kandnqi = 317,
    CODE_FOR_kandnhi = 318,
    CODE_FOR_andqi_ext_0 = 324,
    CODE_FOR_kxnorqi = 346,
    CODE_FOR_kxnorhi = 347,
    CODE_FOR_kortestzhi = 348,
    CODE_FOR_kortestchi = 349,
    CODE_FOR_kunpckhi = 350,
    CODE_FOR_copysignsf3_const = 402,
    CODE_FOR_copysigndf3_const = 403,
    CODE_FOR_copysigntf3_const = 404,
    CODE_FOR_copysignsf3_var = 405,
    CODE_FOR_copysigndf3_var = 406,
    CODE_FOR_copysigntf3_var = 407,
  #define CODE_FOR_x86_64_shld CODE_FOR_nothing
    CODE_FOR_x86_shld = 417,
  #define CODE_FOR_x86_64_shrd CODE_FOR_nothing
    CODE_FOR_x86_shrd = 440,
  #define CODE_FOR_ashrdi3_cvt CODE_FOR_nothing
    CODE_FOR_ashrsi3_cvt = 441,
    CODE_FOR_ix86_rotldi3_doubleword = 474,
  #define CODE_FOR_ix86_rotlti3_doubleword CODE_FOR_nothing
    CODE_FOR_ix86_rotrdi3_doubleword = 475,
  #define CODE_FOR_ix86_rotrti3_doubleword CODE_FOR_nothing
    CODE_FOR_setcc_sf_sse = 493,
    CODE_FOR_setcc_df_sse = 494,
    CODE_FOR_jump = 535,
    CODE_FOR_blockage = 552,
    CODE_FOR_prologue_use = 554,
    CODE_FOR_simple_return_internal = 555,
    CODE_FOR_simple_return_internal_long = 556,
    CODE_FOR_simple_return_pop_internal = 557,
    CODE_FOR_simple_return_indirect_internal = 558,
    CODE_FOR_nop = 559,
    CODE_FOR_nops = 560,
    CODE_FOR_pad = 561,
    CODE_FOR_set_got = 562,
    CODE_FOR_set_got_labelled = 563,
  #define CODE_FOR_set_got_rex64 CODE_FOR_nothing
  #define CODE_FOR_set_rip_rex64 CODE_FOR_nothing
    CODE_FOR_set_got_offset_rex64 = 564,
    CODE_FOR_eh_return_internal = 565,
    CODE_FOR_leave = 566,
  #define CODE_FOR_leave_rex64 CODE_FOR_nothing
    CODE_FOR_split_stack_return = 567,
    CODE_FOR_ffssi2_no_cmove = 568,
    CODE_FOR_ctzhi2 = 571,
    CODE_FOR_ctzsi2 = 572,
  #define CODE_FOR_ctzdi2 CODE_FOR_nothing
    CODE_FOR_clzhi2_lzcnt = 573,
    CODE_FOR_clzsi2_lzcnt = 574,
  #define CODE_FOR_clzdi2_lzcnt CODE_FOR_nothing
    CODE_FOR_bmi_bextr_si = 576,
  #define CODE_FOR_bmi_bextr_di CODE_FOR_nothing
    CODE_FOR_bmi2_bzhi_si3 = 580,
  #define CODE_FOR_bmi2_bzhi_di3 CODE_FOR_nothing
    CODE_FOR_bmi2_pdep_si3 = 581,
  #define CODE_FOR_bmi2_pdep_di3 CODE_FOR_nothing
    CODE_FOR_bmi2_pext_si3 = 582,
  #define CODE_FOR_bmi2_pext_di3 CODE_FOR_nothing
    CODE_FOR_tbm_bextri_si = 583,
  #define CODE_FOR_tbm_bextri_di CODE_FOR_nothing
  #define CODE_FOR_bsr_rex64 CODE_FOR_nothing
    CODE_FOR_bsr = 593,
    CODE_FOR_popcounthi2 = 595,
    CODE_FOR_popcountsi2 = 596,
  #define CODE_FOR_popcountdi2 CODE_FOR_nothing
    CODE_FOR_bswaphi_lowpart = 603,
    CODE_FOR_paritydi2_cmp = 604,
    CODE_FOR_paritysi2_cmp = 605,
  #define CODE_FOR_tls_initial_exec_64_sun CODE_FOR_nothing
    CODE_FOR_truncxfsf2_i387_noop_unspec = 657,
    CODE_FOR_truncxfdf2_i387_noop_unspec = 658,
    CODE_FOR_sqrtxf2 = 659,
    CODE_FOR_sqrt_extendsfxf2_i387 = 660,
    CODE_FOR_sqrt_extenddfxf2_i387 = 661,
    CODE_FOR_fpremxf4_i387 = 665,
    CODE_FOR_fprem1xf4_i387 = 666,
    CODE_FOR_sincosxf3 = 673,
    CODE_FOR_sincos_extendsfxf3_i387 = 674,
    CODE_FOR_sincos_extenddfxf3_i387 = 675,
    CODE_FOR_fptanxf4_i387 = 676,
    CODE_FOR_fptan_extendsfxf4_i387 = 677,
    CODE_FOR_fptan_extenddfxf4_i387 = 678,
    CODE_FOR_fpatan_extendsfxf3_i387 = 680,
    CODE_FOR_fpatan_extenddfxf3_i387 = 681,
    CODE_FOR_fyl2xxf3_i387 = 682,
    CODE_FOR_fyl2x_extendsfxf3_i387 = 683,
    CODE_FOR_fyl2x_extenddfxf3_i387 = 684,
    CODE_FOR_fyl2xp1xf3_i387 = 685,
    CODE_FOR_fyl2xp1_extendsfxf3_i387 = 686,
    CODE_FOR_fyl2xp1_extenddfxf3_i387 = 687,
    CODE_FOR_fxtractxf3_i387 = 688,
    CODE_FOR_fxtract_extendsfxf3_i387 = 689,
    CODE_FOR_fxtract_extenddfxf3_i387 = 690,
    CODE_FOR_fscalexf4_i387 = 692,
    CODE_FOR_sse4_1_roundsf2 = 693,
    CODE_FOR_sse4_1_rounddf2 = 694,
    CODE_FOR_rintxf2 = 695,
    CODE_FOR_fistdi2 = 697,
    CODE_FOR_fistdi2_with_temp = 698,
    CODE_FOR_fisthi2 = 701,
    CODE_FOR_fistsi2 = 702,
    CODE_FOR_fisthi2_with_temp = 703,
    CODE_FOR_fistsi2_with_temp = 704,
    CODE_FOR_frndintxf2_floor = 705,
    CODE_FOR_frndintxf2_ceil = 706,
    CODE_FOR_frndintxf2_trunc = 707,
    CODE_FOR_frndintxf2_floor_i387 = 708,
    CODE_FOR_frndintxf2_ceil_i387 = 709,
    CODE_FOR_frndintxf2_trunc_i387 = 710,
    CODE_FOR_frndintxf2_mask_pm = 711,
    CODE_FOR_frndintxf2_mask_pm_i387 = 712,
    CODE_FOR_fistdi2_floor = 719,
    CODE_FOR_fistdi2_ceil = 720,
    CODE_FOR_fistdi2_floor_with_temp = 721,
    CODE_FOR_fistdi2_ceil_with_temp = 722,
    CODE_FOR_fisthi2_floor = 723,
    CODE_FOR_fisthi2_ceil = 724,
    CODE_FOR_fistsi2_floor = 725,
    CODE_FOR_fistsi2_ceil = 726,
    CODE_FOR_fisthi2_floor_with_temp = 727,
    CODE_FOR_fisthi2_ceil_with_temp = 728,
    CODE_FOR_fistsi2_floor_with_temp = 729,
    CODE_FOR_fistsi2_ceil_with_temp = 730,
    CODE_FOR_fxamsf2_i387 = 731,
    CODE_FOR_fxamdf2_i387 = 732,
    CODE_FOR_fxamxf2_i387 = 733,
    CODE_FOR_fxamsf2_i387_with_temp = 734,
    CODE_FOR_fxamdf2_i387_with_temp = 735,
    CODE_FOR_movmsk_df = 736,
    CODE_FOR_cld = 737,
    CODE_FOR_smaxsf3 = 775,
    CODE_FOR_sminsf3 = 776,
    CODE_FOR_smaxdf3 = 777,
    CODE_FOR_smindf3 = 778,
    CODE_FOR_pro_epilogue_adjust_stack_si_add = 783,
    CODE_FOR_pro_epilogue_adjust_stack_di_add = 784,
    CODE_FOR_pro_epilogue_adjust_stack_si_sub = 785,
    CODE_FOR_pro_epilogue_adjust_stack_di_sub = 786,
    CODE_FOR_allocate_stack_worker_probe_si = 787,
    CODE_FOR_allocate_stack_worker_probe_di = 788,
    CODE_FOR_adjust_stack_and_probesi = 789,
    CODE_FOR_adjust_stack_and_probedi = 790,
    CODE_FOR_probe_stack_rangesi = 791,
    CODE_FOR_probe_stack_rangedi = 792,
  #define CODE_FOR_nonlocal_goto_receiver CODE_FOR_nothing
    CODE_FOR_trap = 793,
    CODE_FOR_stack_protect_set_si = 798,
    CODE_FOR_stack_protect_set_di = 799,
    CODE_FOR_stack_tls_protect_set_si = 800,
    CODE_FOR_stack_tls_protect_set_di = 801,
    CODE_FOR_stack_protect_test_si = 802,
    CODE_FOR_stack_protect_test_di = 803,
    CODE_FOR_stack_tls_protect_test_si = 804,
    CODE_FOR_stack_tls_protect_test_di = 805,
    CODE_FOR_sse4_2_crc32qi = 806,
    CODE_FOR_sse4_2_crc32hi = 807,
    CODE_FOR_sse4_2_crc32si = 808,
  #define CODE_FOR_sse4_2_crc32di CODE_FOR_nothing
    CODE_FOR_rdpmc = 809,
  #define CODE_FOR_rdpmc_rex64 CODE_FOR_nothing
    CODE_FOR_rdtsc = 810,
  #define CODE_FOR_rdtsc_rex64 CODE_FOR_nothing
    CODE_FOR_rdtscp = 811,
  #define CODE_FOR_rdtscp_rex64 CODE_FOR_nothing
    CODE_FOR_fxsave = 812,
  #define CODE_FOR_fxsave64 CODE_FOR_nothing
    CODE_FOR_fxrstor = 813,
  #define CODE_FOR_fxrstor64 CODE_FOR_nothing
    CODE_FOR_xsave = 814,
    CODE_FOR_xsaveopt = 815,
  #define CODE_FOR_xsave_rex64 CODE_FOR_nothing
  #define CODE_FOR_xsaveopt_rex64 CODE_FOR_nothing
  #define CODE_FOR_xsave64 CODE_FOR_nothing
  #define CODE_FOR_xsaveopt64 CODE_FOR_nothing
    CODE_FOR_xrstor = 816,
  #define CODE_FOR_xrstor_rex64 CODE_FOR_nothing
  #define CODE_FOR_xrstor64 CODE_FOR_nothing
    CODE_FOR_fnstenv = 817,
    CODE_FOR_fldenv = 818,
    CODE_FOR_fnstsw = 819,
    CODE_FOR_fnclex = 820,
    CODE_FOR_lwp_slwpcbsi = 823,
    CODE_FOR_lwp_slwpcbdi = 824,
  #define CODE_FOR_rdfsbasesi CODE_FOR_nothing
  #define CODE_FOR_rdgsbasesi CODE_FOR_nothing
  #define CODE_FOR_rdfsbasedi CODE_FOR_nothing
  #define CODE_FOR_rdgsbasedi CODE_FOR_nothing
  #define CODE_FOR_wrfsbasesi CODE_FOR_nothing
  #define CODE_FOR_wrgsbasesi CODE_FOR_nothing
  #define CODE_FOR_wrfsbasedi CODE_FOR_nothing
  #define CODE_FOR_wrgsbasedi CODE_FOR_nothing
    CODE_FOR_rdrandhi_1 = 827,
    CODE_FOR_rdrandsi_1 = 828,
  #define CODE_FOR_rdranddi_1 CODE_FOR_nothing
    CODE_FOR_rdseedhi_1 = 829,
    CODE_FOR_rdseedsi_1 = 830,
  #define CODE_FOR_rdseeddi_1 CODE_FOR_nothing
    CODE_FOR_xbegin_1 = 832,
    CODE_FOR_xend = 833,
    CODE_FOR_xabort = 834,
    CODE_FOR_xtest_1 = 835,
    CODE_FOR_sse_movntq = 841,
    CODE_FOR_mmx_rcpv2sf2 = 849,
    CODE_FOR_mmx_rcpit1v2sf3 = 850,
    CODE_FOR_mmx_rcpit2v2sf3 = 851,
    CODE_FOR_mmx_rsqrtv2sf2 = 852,
    CODE_FOR_mmx_rsqit1v2sf3 = 853,
    CODE_FOR_mmx_haddv2sf3 = 854,
    CODE_FOR_mmx_hsubv2sf3 = 855,
    CODE_FOR_mmx_addsubv2sf3 = 856,
    CODE_FOR_mmx_gtv2sf3 = 858,
    CODE_FOR_mmx_gev2sf3 = 859,
    CODE_FOR_mmx_pf2id = 860,
    CODE_FOR_mmx_pf2iw = 861,
    CODE_FOR_mmx_pi2fw = 862,
    CODE_FOR_mmx_floatv2si2 = 863,
    CODE_FOR_mmx_pswapdv2sf2 = 864,
    CODE_FOR_mmx_ashrv4hi3 = 895,
    CODE_FOR_mmx_ashrv2si3 = 896,
    CODE_FOR_mmx_ashlv4hi3 = 897,
    CODE_FOR_mmx_lshrv4hi3 = 898,
    CODE_FOR_mmx_ashlv2si3 = 899,
    CODE_FOR_mmx_lshrv2si3 = 900,
    CODE_FOR_mmx_ashlv1di3 = 901,
    CODE_FOR_mmx_lshrv1di3 = 902,
    CODE_FOR_mmx_gtv8qi3 = 906,
    CODE_FOR_mmx_gtv4hi3 = 907,
    CODE_FOR_mmx_gtv2si3 = 908,
    CODE_FOR_mmx_andnotv8qi3 = 909,
    CODE_FOR_mmx_andnotv4hi3 = 910,
    CODE_FOR_mmx_andnotv2si3 = 911,
    CODE_FOR_mmx_packsswb = 921,
    CODE_FOR_mmx_packssdw = 922,
    CODE_FOR_mmx_packuswb = 923,
    CODE_FOR_mmx_punpckhbw = 924,
    CODE_FOR_mmx_punpcklbw = 925,
    CODE_FOR_mmx_punpckhwd = 926,
    CODE_FOR_mmx_punpcklwd = 927,
    CODE_FOR_mmx_punpckhdq = 928,
    CODE_FOR_mmx_punpckldq = 929,
    CODE_FOR_mmx_pextrw = 931,
    CODE_FOR_mmx_pshufw_1 = 932,
    CODE_FOR_mmx_pswapdv2si2 = 933,
    CODE_FOR_mmx_psadbw = 941,
    CODE_FOR_mmx_pmovmskb = 942,
    CODE_FOR_avx512f_loadv16si_mask = 967,
    CODE_FOR_avx512f_loadv16sf_mask = 968,
    CODE_FOR_avx512f_loadv8di_mask = 969,
    CODE_FOR_avx512f_loadv8df_mask = 970,
    CODE_FOR_avx512f_blendmv16si = 971,
    CODE_FOR_avx512f_blendmv16sf = 972,
    CODE_FOR_avx512f_blendmv8di = 973,
    CODE_FOR_avx512f_blendmv8df = 974,
    CODE_FOR_avx512f_storev16si_mask = 975,
    CODE_FOR_avx512f_storev16sf_mask = 976,
    CODE_FOR_avx512f_storev8di_mask = 977,
    CODE_FOR_avx512f_storev8df_mask = 978,
    CODE_FOR_sse2_movq128 = 979,
    CODE_FOR_movdi_to_sse = 980,
    CODE_FOR_avx512f_storeups512 = 989,
    CODE_FOR_avx_storeups256 = 990,
    CODE_FOR_sse_storeups = 991,
    CODE_FOR_avx512f_storeupd512 = 992,
    CODE_FOR_avx_storeupd256 = 993,
    CODE_FOR_sse2_storeupd = 994,
    CODE_FOR_avx512f_storeups512_mask = 995,
    CODE_FOR_avx512f_storeupd512_mask = 996,
    CODE_FOR_avx_storedquv32qi = 1003,
    CODE_FOR_sse2_storedquv16qi = 1004,
    CODE_FOR_avx512f_storedquv16si = 1005,
    CODE_FOR_avx512f_storedquv8di = 1006,
    CODE_FOR_avx512f_storedquv16si_mask = 1007,
    CODE_FOR_avx512f_storedquv8di_mask = 1008,
    CODE_FOR_avx_lddqu256 = 1009,
    CODE_FOR_sse3_lddqu = 1010,
    CODE_FOR_sse2_movntisi = 1011,
  #define CODE_FOR_sse2_movntidi CODE_FOR_nothing
    CODE_FOR_avx512f_movntv16sf = 1012,
    CODE_FOR_avx_movntv8sf = 1013,
    CODE_FOR_sse_movntv4sf = 1014,
    CODE_FOR_avx512f_movntv8df = 1015,
    CODE_FOR_avx_movntv4df = 1016,
    CODE_FOR_sse2_movntv2df = 1017,
    CODE_FOR_avx512f_movntv8di = 1018,
    CODE_FOR_avx_movntv4di = 1019,
    CODE_FOR_sse2_movntv2di = 1020,
    CODE_FOR_sse_vmaddv4sf3 = 1075,
    CODE_FOR_sse_vmaddv4sf3_round = 1076,
    CODE_FOR_sse_vmsubv4sf3 = 1077,
    CODE_FOR_sse_vmsubv4sf3_round = 1078,
    CODE_FOR_sse2_vmaddv2df3 = 1079,
    CODE_FOR_sse2_vmaddv2df3_round = 1080,
    CODE_FOR_sse2_vmsubv2df3 = 1081,
    CODE_FOR_sse2_vmsubv2df3_round = 1082,
    CODE_FOR_sse_vmmulv4sf3 = 1107,
    CODE_FOR_sse_vmmulv4sf3_round = 1108,
    CODE_FOR_sse_vmdivv4sf3 = 1109,
    CODE_FOR_sse_vmdivv4sf3_round = 1110,
    CODE_FOR_sse2_vmmulv2df3 = 1111,
    CODE_FOR_sse2_vmmulv2df3_round = 1112,
    CODE_FOR_sse2_vmdivv2df3 = 1113,
    CODE_FOR_sse2_vmdivv2df3_round = 1114,
    CODE_FOR_avx512f_divv16sf3 = 1115,
    CODE_FOR_avx512f_divv16sf3_round = 1116,
    CODE_FOR_avx512f_divv16sf3_mask = 1117,
    CODE_FOR_avx512f_divv16sf3_mask_round = 1118,
    CODE_FOR_avx_divv8sf3 = 1119,
  #define CODE_FOR_avx_divv8sf3_round CODE_FOR_nothing
  #define CODE_FOR_avx_divv8sf3_mask CODE_FOR_nothing
  #define CODE_FOR_avx_divv8sf3_mask_round CODE_FOR_nothing
    CODE_FOR_sse_divv4sf3 = 1120,
  #define CODE_FOR_sse_divv4sf3_round CODE_FOR_nothing
  #define CODE_FOR_sse_divv4sf3_mask CODE_FOR_nothing
  #define CODE_FOR_sse_divv4sf3_mask_round CODE_FOR_nothing
    CODE_FOR_avx512f_divv8df3 = 1121,
    CODE_FOR_avx512f_divv8df3_round = 1122,
    CODE_FOR_avx512f_divv8df3_mask = 1123,
    CODE_FOR_avx512f_divv8df3_mask_round = 1124,
    CODE_FOR_avx_divv4df3 = 1125,
  #define CODE_FOR_avx_divv4df3_round CODE_FOR_nothing
  #define CODE_FOR_avx_divv4df3_mask CODE_FOR_nothing
  #define CODE_FOR_avx_divv4df3_mask_round CODE_FOR_nothing
    CODE_FOR_sse2_divv2df3 = 1126,
  #define CODE_FOR_sse2_divv2df3_round CODE_FOR_nothing
  #define CODE_FOR_sse2_divv2df3_mask CODE_FOR_nothing
  #define CODE_FOR_sse2_divv2df3_mask_round CODE_FOR_nothing
    CODE_FOR_avx_rcpv8sf2 = 1127,
    CODE_FOR_sse_rcpv4sf2 = 1128,
    CODE_FOR_sse_vmrcpv4sf2 = 1129,
    CODE_FOR_rcp14v16sf_mask = 1131,
    CODE_FOR_rcp14v8df_mask = 1133,
    CODE_FOR_srcp14v4sf = 1134,
    CODE_FOR_srcp14v2df = 1135,
    CODE_FOR_avx512f_sqrtv16sf2 = 1136,
    CODE_FOR_avx512f_sqrtv16sf2_round = 1137,
    CODE_FOR_avx512f_sqrtv16sf2_mask = 1138,
    CODE_FOR_avx512f_sqrtv16sf2_mask_round = 1139,
    CODE_FOR_avx_sqrtv8sf2 = 1140,
  #define CODE_FOR_avx_sqrtv8sf2_round CODE_FOR_nothing
  #define CODE_FOR_avx_sqrtv8sf2_mask CODE_FOR_nothing
  #define CODE_FOR_avx_sqrtv8sf2_mask_round CODE_FOR_nothing
    CODE_FOR_sse_sqrtv4sf2 = 1141,
  #define CODE_FOR_sse_sqrtv4sf2_round CODE_FOR_nothing
  #define CODE_FOR_sse_sqrtv4sf2_mask CODE_FOR_nothing
  #define CODE_FOR_sse_sqrtv4sf2_mask_round CODE_FOR_nothing
    CODE_FOR_avx512f_sqrtv8df2 = 1142,
    CODE_FOR_avx512f_sqrtv8df2_round = 1143,
    CODE_FOR_avx512f_sqrtv8df2_mask = 1144,
    CODE_FOR_avx512f_sqrtv8df2_mask_round = 1145,
    CODE_FOR_avx_sqrtv4df2 = 1146,
  #define CODE_FOR_avx_sqrtv4df2_round CODE_FOR_nothing
  #define CODE_FOR_avx_sqrtv4df2_mask CODE_FOR_nothing
  #define CODE_FOR_avx_sqrtv4df2_mask_round CODE_FOR_nothing
    CODE_FOR_sse2_sqrtv2df2 = 1147,
  #define CODE_FOR_sse2_sqrtv2df2_round CODE_FOR_nothing
  #define CODE_FOR_sse2_sqrtv2df2_mask CODE_FOR_nothing
  #define CODE_FOR_sse2_sqrtv2df2_mask_round CODE_FOR_nothing
    CODE_FOR_sse_vmsqrtv4sf2 = 1148,
    CODE_FOR_sse_vmsqrtv4sf2_round = 1149,
    CODE_FOR_sse2_vmsqrtv2df2 = 1150,
    CODE_FOR_sse2_vmsqrtv2df2_round = 1151,
    CODE_FOR_avx_rsqrtv8sf2 = 1152,
    CODE_FOR_sse_rsqrtv4sf2 = 1153,
    CODE_FOR_rsqrt14v16sf_mask = 1155,
    CODE_FOR_rsqrt14v8df_mask = 1157,
    CODE_FOR_rsqrt14v4sf = 1158,
    CODE_FOR_rsqrt14v2df = 1159,
    CODE_FOR_sse_vmrsqrtv4sf2 = 1160,
    CODE_FOR_sse_vmsmaxv4sf3 = 1233,
    CODE_FOR_sse_vmsmaxv4sf3_round = 1234,
    CODE_FOR_sse_vmsminv4sf3 = 1235,
    CODE_FOR_sse_vmsminv4sf3_round = 1236,
    CODE_FOR_sse2_vmsmaxv2df3 = 1237,
    CODE_FOR_sse2_vmsmaxv2df3_round = 1238,
    CODE_FOR_sse2_vmsminv2df3 = 1239,
    CODE_FOR_sse2_vmsminv2df3_round = 1240,
    CODE_FOR_avx_addsubv4df3 = 1253,
    CODE_FOR_sse3_addsubv2df3 = 1254,
    CODE_FOR_avx_addsubv8sf3 = 1255,
    CODE_FOR_sse3_addsubv4sf3 = 1256,
    CODE_FOR_avx_haddv4df3 = 1257,
    CODE_FOR_avx_hsubv4df3 = 1258,
    CODE_FOR_sse3_hsubv2df3 = 1260,
    CODE_FOR_avx_haddv8sf3 = 1263,
    CODE_FOR_avx_hsubv8sf3 = 1264,
    CODE_FOR_sse3_haddv4sf3 = 1265,
    CODE_FOR_sse3_hsubv4sf3 = 1266,
    CODE_FOR_avx_cmpv8sf3 = 1267,
    CODE_FOR_avx_cmpv4sf3 = 1268,
    CODE_FOR_avx_cmpv4df3 = 1269,
    CODE_FOR_avx_cmpv2df3 = 1270,
    CODE_FOR_avx_vmcmpv4sf3 = 1271,
    CODE_FOR_avx_vmcmpv2df3 = 1272,
    CODE_FOR_avx_maskcmpv8sf3 = 1277,
    CODE_FOR_sse_maskcmpv4sf3 = 1278,
    CODE_FOR_avx_maskcmpv4df3 = 1279,
    CODE_FOR_sse2_maskcmpv2df3 = 1280,
    CODE_FOR_sse_vmmaskcmpv4sf3 = 1281,
    CODE_FOR_sse2_vmmaskcmpv2df3 = 1282,
    CODE_FOR_avx512f_cmpv16si3 = 1283,
    CODE_FOR_avx512f_cmpv16si3_mask = 1284,
  #define CODE_FOR_avx512f_cmpv16si3_round CODE_FOR_nothing
  #define CODE_FOR_avx512f_cmpv16si3_mask_round CODE_FOR_nothing
    CODE_FOR_avx512f_cmpv16sf3 = 1285,
    CODE_FOR_avx512f_cmpv16sf3_mask = 1286,
    CODE_FOR_avx512f_cmpv16sf3_round = 1287,
    CODE_FOR_avx512f_cmpv16sf3_mask_round = 1288,
    CODE_FOR_avx512f_cmpv8di3 = 1289,
    CODE_FOR_avx512f_cmpv8di3_mask = 1290,
  #define CODE_FOR_avx512f_cmpv8di3_round CODE_FOR_nothing
  #define CODE_FOR_avx512f_cmpv8di3_mask_round CODE_FOR_nothing
    CODE_FOR_avx512f_cmpv8df3 = 1291,
    CODE_FOR_avx512f_cmpv8df3_mask = 1292,
    CODE_FOR_avx512f_cmpv8df3_round = 1293,
    CODE_FOR_avx512f_cmpv8df3_mask_round = 1294,
    CODE_FOR_avx512f_ucmpv16si3 = 1295,
    CODE_FOR_avx512f_ucmpv16si3_mask = 1296,
    CODE_FOR_avx512f_ucmpv8di3 = 1297,
    CODE_FOR_avx512f_ucmpv8di3_mask = 1298,
    CODE_FOR_avx512f_vmcmpv4sf3 = 1299,
    CODE_FOR_avx512f_vmcmpv4sf3_round = 1300,
    CODE_FOR_avx512f_vmcmpv2df3 = 1301,
    CODE_FOR_avx512f_vmcmpv2df3_round = 1302,
    CODE_FOR_avx512f_vmcmpv4sf3_mask = 1303,
    CODE_FOR_avx512f_vmcmpv4sf3_mask_round = 1304,
    CODE_FOR_avx512f_vmcmpv2df3_mask = 1305,
    CODE_FOR_avx512f_vmcmpv2df3_mask_round = 1306,
    CODE_FOR_avx512f_maskcmpv16sf3 = 1307,
    CODE_FOR_avx512f_maskcmpv8sf3 = 1308,
    CODE_FOR_avx512f_maskcmpv4sf3 = 1309,
    CODE_FOR_avx512f_maskcmpv8df3 = 1310,
    CODE_FOR_avx512f_maskcmpv4df3 = 1311,
    CODE_FOR_avx512f_maskcmpv2df3 = 1312,
    CODE_FOR_sse_comi = 1313,
    CODE_FOR_sse_comi_round = 1314,
    CODE_FOR_sse2_comi = 1315,
    CODE_FOR_sse2_comi_round = 1316,
    CODE_FOR_sse_ucomi = 1317,
    CODE_FOR_sse_ucomi_round = 1318,
    CODE_FOR_sse2_ucomi = 1319,
    CODE_FOR_sse2_ucomi_round = 1320,
    CODE_FOR_avx512f_andnotv16sf3 = 1321,
    CODE_FOR_avx_andnotv8sf3 = 1322,
    CODE_FOR_sse_andnotv4sf3 = 1323,
    CODE_FOR_avx512f_andnotv8df3 = 1324,
    CODE_FOR_avx_andnotv4df3 = 1325,
    CODE_FOR_sse2_andnotv2df3 = 1326,
    CODE_FOR_avx512f_andv16sf = 1357,
    CODE_FOR_avx512f_xorv16sf = 1358,
    CODE_FOR_avx512f_andv8df = 1359,
    CODE_FOR_avx512f_xorv8df = 1360,
  #define CODE_FOR_fma_fmadd_v4sf_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmadd_v4sf_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fmadd_v2df_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmadd_v2df_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fmadd_v8sf_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmadd_v8sf_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fmadd_v4df_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmadd_v4df_maskz_1_round CODE_FOR_nothing
    CODE_FOR_fma_fmadd_v16sf_maskz_1 = 1369,
    CODE_FOR_fma_fmadd_v16sf_maskz_1_round = 1370,
    CODE_FOR_fma_fmadd_v8df_maskz_1 = 1373,
    CODE_FOR_fma_fmadd_v8df_maskz_1_round = 1374,
    CODE_FOR_avx512f_fmadd_v16sf_mask = 1375,
    CODE_FOR_avx512f_fmadd_v16sf_mask_round = 1376,
    CODE_FOR_avx512f_fmadd_v8df_mask = 1377,
    CODE_FOR_avx512f_fmadd_v8df_mask_round = 1378,
    CODE_FOR_avx512f_fmadd_v16sf_mask3 = 1379,
    CODE_FOR_avx512f_fmadd_v16sf_mask3_round = 1380,
    CODE_FOR_avx512f_fmadd_v8df_mask3 = 1381,
    CODE_FOR_avx512f_fmadd_v8df_mask3_round = 1382,
  #define CODE_FOR_fma_fmsub_v4sf_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmsub_v4sf_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fmsub_v2df_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmsub_v2df_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fmsub_v8sf_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmsub_v8sf_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fmsub_v4df_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmsub_v4df_maskz_1_round CODE_FOR_nothing
    CODE_FOR_fma_fmsub_v16sf_maskz_1 = 1391,
    CODE_FOR_fma_fmsub_v16sf_maskz_1_round = 1392,
    CODE_FOR_fma_fmsub_v8df_maskz_1 = 1395,
    CODE_FOR_fma_fmsub_v8df_maskz_1_round = 1396,
    CODE_FOR_avx512f_fmsub_v16sf_mask = 1397,
    CODE_FOR_avx512f_fmsub_v16sf_mask_round = 1398,
    CODE_FOR_avx512f_fmsub_v8df_mask = 1399,
    CODE_FOR_avx512f_fmsub_v8df_mask_round = 1400,
    CODE_FOR_avx512f_fmsub_v16sf_mask3 = 1401,
    CODE_FOR_avx512f_fmsub_v16sf_mask3_round = 1402,
    CODE_FOR_avx512f_fmsub_v8df_mask3 = 1403,
    CODE_FOR_avx512f_fmsub_v8df_mask3_round = 1404,
  #define CODE_FOR_fma_fnmadd_v4sf_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fnmadd_v4sf_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fnmadd_v2df_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fnmadd_v2df_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fnmadd_v8sf_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fnmadd_v8sf_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fnmadd_v4df_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fnmadd_v4df_maskz_1_round CODE_FOR_nothing
    CODE_FOR_fma_fnmadd_v16sf_maskz_1 = 1413,
    CODE_FOR_fma_fnmadd_v16sf_maskz_1_round = 1414,
    CODE_FOR_fma_fnmadd_v8df_maskz_1 = 1417,
    CODE_FOR_fma_fnmadd_v8df_maskz_1_round = 1418,
    CODE_FOR_avx512f_fnmadd_v16sf_mask = 1419,
    CODE_FOR_avx512f_fnmadd_v16sf_mask_round = 1420,
    CODE_FOR_avx512f_fnmadd_v8df_mask = 1421,
    CODE_FOR_avx512f_fnmadd_v8df_mask_round = 1422,
    CODE_FOR_avx512f_fnmadd_v16sf_mask3 = 1423,
    CODE_FOR_avx512f_fnmadd_v16sf_mask3_round = 1424,
    CODE_FOR_avx512f_fnmadd_v8df_mask3 = 1425,
    CODE_FOR_avx512f_fnmadd_v8df_mask3_round = 1426,
  #define CODE_FOR_fma_fnmsub_v4sf_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fnmsub_v4sf_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fnmsub_v2df_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fnmsub_v2df_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fnmsub_v8sf_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fnmsub_v8sf_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fnmsub_v4df_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fnmsub_v4df_maskz_1_round CODE_FOR_nothing
    CODE_FOR_fma_fnmsub_v16sf_maskz_1 = 1435,
    CODE_FOR_fma_fnmsub_v16sf_maskz_1_round = 1436,
    CODE_FOR_fma_fnmsub_v8df_maskz_1 = 1439,
    CODE_FOR_fma_fnmsub_v8df_maskz_1_round = 1440,
    CODE_FOR_avx512f_fnmsub_v16sf_mask = 1441,
    CODE_FOR_avx512f_fnmsub_v16sf_mask_round = 1442,
    CODE_FOR_avx512f_fnmsub_v8df_mask = 1443,
    CODE_FOR_avx512f_fnmsub_v8df_mask_round = 1444,
    CODE_FOR_avx512f_fnmsub_v16sf_mask3 = 1445,
    CODE_FOR_avx512f_fnmsub_v16sf_mask3_round = 1446,
    CODE_FOR_avx512f_fnmsub_v8df_mask3 = 1447,
    CODE_FOR_avx512f_fnmsub_v8df_mask3_round = 1448,
  #define CODE_FOR_fma_fmaddsub_v8sf_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmaddsub_v8sf_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fmaddsub_v4sf_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmaddsub_v4sf_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fmaddsub_v4df_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmaddsub_v4df_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fmaddsub_v2df_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmaddsub_v2df_maskz_1_round CODE_FOR_nothing
    CODE_FOR_fma_fmaddsub_v16sf_maskz_1 = 1455,
    CODE_FOR_fma_fmaddsub_v16sf_maskz_1_round = 1456,
    CODE_FOR_fma_fmaddsub_v8df_maskz_1 = 1459,
    CODE_FOR_fma_fmaddsub_v8df_maskz_1_round = 1460,
    CODE_FOR_avx512f_fmaddsub_v16sf_mask = 1461,
    CODE_FOR_avx512f_fmaddsub_v16sf_mask_round = 1462,
    CODE_FOR_avx512f_fmaddsub_v8df_mask = 1463,
    CODE_FOR_avx512f_fmaddsub_v8df_mask_round = 1464,
    CODE_FOR_avx512f_fmaddsub_v16sf_mask3 = 1465,
    CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round = 1466,
    CODE_FOR_avx512f_fmaddsub_v8df_mask3 = 1467,
    CODE_FOR_avx512f_fmaddsub_v8df_mask3_round = 1468,
  #define CODE_FOR_fma_fmsubadd_v8sf_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmsubadd_v8sf_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fmsubadd_v4sf_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmsubadd_v4sf_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fmsubadd_v4df_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmsubadd_v4df_maskz_1_round CODE_FOR_nothing
  #define CODE_FOR_fma_fmsubadd_v2df_maskz_1 CODE_FOR_nothing
  #define CODE_FOR_fma_fmsubadd_v2df_maskz_1_round CODE_FOR_nothing
    CODE_FOR_fma_fmsubadd_v16sf_maskz_1 = 1475,
    CODE_FOR_fma_fmsubadd_v16sf_maskz_1_round = 1476,
    CODE_FOR_fma_fmsubadd_v8df_maskz_1 = 1479,
    CODE_FOR_fma_fmsubadd_v8df_maskz_1_round = 1480,
    CODE_FOR_avx512f_fmsubadd_v16sf_mask = 1481,
    CODE_FOR_avx512f_fmsubadd_v16sf_mask_round = 1482,
    CODE_FOR_avx512f_fmsubadd_v8df_mask = 1483,
    CODE_FOR_avx512f_fmsubadd_v8df_mask_round = 1484,
    CODE_FOR_avx512f_fmsubadd_v16sf_mask3 = 1485,
    CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round = 1486,
    CODE_FOR_avx512f_fmsubadd_v8df_mask3 = 1487,
    CODE_FOR_avx512f_fmsubadd_v8df_mask3_round = 1488,
    CODE_FOR_sse_cvtpi2ps = 1513,
    CODE_FOR_sse_cvtps2pi = 1514,
    CODE_FOR_sse_cvttps2pi = 1515,
    CODE_FOR_sse_cvtsi2ss = 1516,
    CODE_FOR_sse_cvtsi2ss_round = 1517,
  #define CODE_FOR_sse_cvtsi2ssq CODE_FOR_nothing
  #define CODE_FOR_sse_cvtsi2ssq_round CODE_FOR_nothing
    CODE_FOR_sse_cvtss2si = 1518,
    CODE_FOR_sse_cvtss2si_round = 1519,
    CODE_FOR_sse_cvtss2si_2 = 1520,
  #define CODE_FOR_sse_cvtss2siq CODE_FOR_nothing
  #define CODE_FOR_sse_cvtss2siq_round CODE_FOR_nothing
  #define CODE_FOR_sse_cvtss2siq_2 CODE_FOR_nothing
    CODE_FOR_sse_cvttss2si = 1521,
    CODE_FOR_sse_cvttss2si_round = 1522,
  #define CODE_FOR_sse_cvttss2siq CODE_FOR_nothing
  #define CODE_FOR_sse_cvttss2siq_round CODE_FOR_nothing
    CODE_FOR_cvtusi2ss32 = 1523,
    CODE_FOR_cvtusi2ss32_round = 1524,
    CODE_FOR_cvtusi2sd32 = 1525,
  #define CODE_FOR_cvtusi2sd32_round CODE_FOR_nothing
  #define CODE_FOR_cvtusi2ss64 CODE_FOR_nothing
  #define CODE_FOR_cvtusi2ss64_round CODE_FOR_nothing
  #define CODE_FOR_cvtusi2sd64 CODE_FOR_nothing
  #define CODE_FOR_cvtusi2sd64_round CODE_FOR_nothing
    CODE_FOR_floatv16siv16sf2 = 1526,
    CODE_FOR_floatv16siv16sf2_round = 1527,
    CODE_FOR_floatv16siv16sf2_mask = 1528,
    CODE_FOR_floatv16siv16sf2_mask_round = 1529,
    CODE_FOR_floatv8siv8sf2 = 1530,
  #define CODE_FOR_floatv8siv8sf2_round CODE_FOR_nothing
  #define CODE_FOR_floatv8siv8sf2_mask CODE_FOR_nothing
  #define CODE_FOR_floatv8siv8sf2_mask_round CODE_FOR_nothing
    CODE_FOR_floatv4siv4sf2 = 1531,
  #define CODE_FOR_floatv4siv4sf2_round CODE_FOR_nothing
  #define CODE_FOR_floatv4siv4sf2_mask CODE_FOR_nothing
  #define CODE_FOR_floatv4siv4sf2_mask_round CODE_FOR_nothing
    CODE_FOR_ufloatv16siv16sf2 = 1532,
    CODE_FOR_ufloatv16siv16sf2_round = 1533,
    CODE_FOR_ufloatv16siv16sf2_mask = 1534,
    CODE_FOR_ufloatv16siv16sf2_mask_round = 1535,
    CODE_FOR_avx_fix_notruncv8sfv8si = 1536,
    CODE_FOR_sse2_fix_notruncv4sfv4si = 1537,
    CODE_FOR_avx512f_fix_notruncv16sfv16si_mask = 1540,
    CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round = 1541,
    CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask = 1544,
    CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round = 1545,
    CODE_FOR_fix_truncv16sfv16si2 = 1546,
    CODE_FOR_fix_truncv16sfv16si2_round = 1547,
    CODE_FOR_fix_truncv16sfv16si2_mask = 1548,
    CODE_FOR_fix_truncv16sfv16si2_mask_round = 1549,
    CODE_FOR_ufix_truncv16sfv16si2 = 1550,
    CODE_FOR_ufix_truncv16sfv16si2_round = 1551,
    CODE_FOR_ufix_truncv16sfv16si2_mask = 1552,
    CODE_FOR_ufix_truncv16sfv16si2_mask_round = 1553,
    CODE_FOR_fix_truncv8sfv8si2 = 1554,
    CODE_FOR_fix_truncv4sfv4si2 = 1555,
    CODE_FOR_sse2_cvtpi2pd = 1556,
    CODE_FOR_sse2_cvtpd2pi = 1557,
    CODE_FOR_sse2_cvttpd2pi = 1558,
    CODE_FOR_sse2_cvtsi2sd = 1559,
  #define CODE_FOR_sse2_cvtsi2sdq CODE_FOR_nothing
  #define CODE_FOR_sse2_cvtsi2sdq_round CODE_FOR_nothing
    CODE_FOR_avx512f_vcvtss2usi = 1560,
    CODE_FOR_avx512f_vcvtss2usi_round = 1561,
  #define CODE_FOR_avx512f_vcvtss2usiq CODE_FOR_nothing
  #define CODE_FOR_avx512f_vcvtss2usiq_round CODE_FOR_nothing
    CODE_FOR_avx512f_vcvttss2usi = 1562,
    CODE_FOR_avx512f_vcvttss2usi_round = 1563,
  #define CODE_FOR_avx512f_vcvttss2usiq CODE_FOR_nothing
  #define CODE_FOR_avx512f_vcvttss2usiq_round CODE_FOR_nothing
    CODE_FOR_avx512f_vcvtsd2usi = 1564,
    CODE_FOR_avx512f_vcvtsd2usi_round = 1565,
  #define CODE_FOR_avx512f_vcvtsd2usiq CODE_FOR_nothing
  #define CODE_FOR_avx512f_vcvtsd2usiq_round CODE_FOR_nothing
    CODE_FOR_avx512f_vcvttsd2usi = 1566,
    CODE_FOR_avx512f_vcvttsd2usi_round = 1567,
  #define CODE_FOR_avx512f_vcvttsd2usiq CODE_FOR_nothing
  #define CODE_FOR_avx512f_vcvttsd2usiq_round CODE_FOR_nothing
    CODE_FOR_sse2_cvtsd2si = 1568,
    CODE_FOR_sse2_cvtsd2si_round = 1569,
    CODE_FOR_sse2_cvtsd2si_2 = 1570,
  #define CODE_FOR_sse2_cvtsd2siq CODE_FOR_nothing
  #define CODE_FOR_sse2_cvtsd2siq_round CODE_FOR_nothing
  #define CODE_FOR_sse2_cvtsd2siq_2 CODE_FOR_nothing
    CODE_FOR_sse2_cvttsd2si = 1571,
    CODE_FOR_sse2_cvttsd2si_round = 1572,
  #define CODE_FOR_sse2_cvttsd2siq CODE_FOR_nothing
  #define CODE_FOR_sse2_cvttsd2siq_round CODE_FOR_nothing
    CODE_FOR_floatv8siv8df2 = 1573,
    CODE_FOR_floatv8siv8df2_mask = 1574,
    CODE_FOR_floatv4siv4df2 = 1575,
  #define CODE_FOR_floatv4siv4df2_mask CODE_FOR_nothing
    CODE_FOR_ufloatv8siv8df = 1576,
    CODE_FOR_ufloatv8siv8df_mask = 1577,
    CODE_FOR_avx512f_cvtdq2pd512_2 = 1578,
    CODE_FOR_avx_cvtdq2pd256_2 = 1579,
    CODE_FOR_sse2_cvtdq2pd = 1580,
    CODE_FOR_avx512f_cvtpd2dq512_mask = 1583,
    CODE_FOR_avx512f_cvtpd2dq512_mask_round = 1584,
    CODE_FOR_avx_cvtpd2dq256 = 1585,
    CODE_FOR_avx512f_ufix_notruncv8dfv8si = 1588,
    CODE_FOR_avx512f_ufix_notruncv8dfv8si_round = 1589,
    CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask = 1590,
    CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round = 1591,
    CODE_FOR_fix_truncv8dfv8si2 = 1592,
    CODE_FOR_fix_truncv8dfv8si2_round = 1593,
    CODE_FOR_fix_truncv8dfv8si2_mask = 1594,
    CODE_FOR_fix_truncv8dfv8si2_mask_round = 1595,
    CODE_FOR_ufix_truncv8dfv8si2 = 1596,
    CODE_FOR_ufix_truncv8dfv8si2_round = 1597,
    CODE_FOR_ufix_truncv8dfv8si2_mask = 1598,
    CODE_FOR_ufix_truncv8dfv8si2_mask_round = 1599,
    CODE_FOR_fix_truncv4dfv4si2 = 1600,
    CODE_FOR_sse2_cvtsd2ss = 1603,
    CODE_FOR_sse2_cvtsd2ss_round = 1604,
    CODE_FOR_sse2_cvtss2sd = 1605,
    CODE_FOR_sse2_cvtss2sd_round = 1606,
    CODE_FOR_avx512f_cvtpd2ps512_mask = 1609,
    CODE_FOR_avx512f_cvtpd2ps512_mask_round = 1610,
    CODE_FOR_avx_cvtpd2ps256 = 1611,
    CODE_FOR_avx512f_cvtps2pd512 = 1613,
    CODE_FOR_avx512f_cvtps2pd512_round = 1614,
    CODE_FOR_avx512f_cvtps2pd512_mask = 1615,
    CODE_FOR_avx512f_cvtps2pd512_mask_round = 1616,
    CODE_FOR_avx_cvtps2pd256 = 1617,
  #define CODE_FOR_avx_cvtps2pd256_round CODE_FOR_nothing
  #define CODE_FOR_avx_cvtps2pd256_mask CODE_FOR_nothing
  #define CODE_FOR_avx_cvtps2pd256_mask_round CODE_FOR_nothing
    CODE_FOR_vec_unpacks_lo_v16sf = 1619,
    CODE_FOR_sse2_cvtps2pd = 1620,
    CODE_FOR_sse_movhlps = 1621,
    CODE_FOR_sse_movlhps = 1622,
    CODE_FOR_avx512f_unpckhps512_mask = 1624,
    CODE_FOR_avx_unpckhps256 = 1625,
    CODE_FOR_vec_interleave_highv4sf = 1626,
    CODE_FOR_avx512f_unpcklps512_mask = 1628,
    CODE_FOR_avx_unpcklps256 = 1629,
    CODE_FOR_vec_interleave_lowv4sf = 1630,
    CODE_FOR_avx_movshdup256 = 1631,
    CODE_FOR_sse3_movshdup = 1632,
    CODE_FOR_avx512f_movshdup512_mask = 1634,
    CODE_FOR_avx_movsldup256 = 1635,
    CODE_FOR_sse3_movsldup = 1636,
    CODE_FOR_avx512f_movsldup512_mask = 1638,
    CODE_FOR_avx_shufps256_1 = 1639,
    CODE_FOR_sse_shufps_v4si = 1640,
    CODE_FOR_sse_shufps_v4sf = 1641,
    CODE_FOR_sse_storehps = 1642,
    CODE_FOR_sse_loadhps = 1643,
    CODE_FOR_sse_storelps = 1644,
    CODE_FOR_sse_loadlps = 1645,
    CODE_FOR_sse_movss = 1646,
    CODE_FOR_avx2_vec_dupv8sf = 1647,
    CODE_FOR_avx2_vec_dupv4sf = 1648,
    CODE_FOR_avx2_vec_dupv8sf_1 = 1649,
    CODE_FOR_vec_dupv4sf = 1650,
    CODE_FOR_vec_setv4si_0 = 1654,
    CODE_FOR_vec_setv4sf_0 = 1655,
    CODE_FOR_sse4_1_insertps = 1657,
    CODE_FOR_avx512f_vextractf32x4_1_maskm = 1661,
    CODE_FOR_avx512f_vextracti32x4_1_maskm = 1662,
    CODE_FOR_avx512f_vextractf32x4_1_mask = 1664,
    CODE_FOR_avx512f_vextracti32x4_1_mask = 1666,
    CODE_FOR_vec_extract_lo_v8df_maskm = 1667,
    CODE_FOR_vec_extract_lo_v8di_maskm = 1668,
    CODE_FOR_vec_extract_lo_v8df = 1669,
    CODE_FOR_vec_extract_lo_v8df_mask = 1670,
    CODE_FOR_vec_extract_lo_v8di = 1671,
    CODE_FOR_vec_extract_lo_v8di_mask = 1672,
    CODE_FOR_vec_extract_hi_v8df_maskm = 1673,
    CODE_FOR_vec_extract_hi_v8di_maskm = 1674,
    CODE_FOR_vec_extract_hi_v8df = 1675,
    CODE_FOR_vec_extract_hi_v8df_mask = 1676,
    CODE_FOR_vec_extract_hi_v8di = 1677,
    CODE_FOR_vec_extract_hi_v8di_mask = 1678,
    CODE_FOR_vec_extract_lo_v16sf = 1679,
    CODE_FOR_vec_extract_lo_v16si = 1680,
    CODE_FOR_vec_extract_hi_v16sf = 1681,
    CODE_FOR_vec_extract_hi_v16si = 1682,
    CODE_FOR_vec_extract_lo_v4di = 1683,
    CODE_FOR_vec_extract_lo_v4df = 1684,
    CODE_FOR_vec_extract_hi_v4di = 1685,
    CODE_FOR_vec_extract_hi_v4df = 1686,
    CODE_FOR_vec_extract_lo_v8si = 1687,
    CODE_FOR_vec_extract_lo_v8sf = 1688,
    CODE_FOR_vec_extract_hi_v8si = 1689,
    CODE_FOR_vec_extract_hi_v8sf = 1690,
    CODE_FOR_vec_extract_lo_v32hi = 1691,
    CODE_FOR_vec_extract_hi_v32hi = 1692,
    CODE_FOR_vec_extract_lo_v16hi = 1693,
    CODE_FOR_vec_extract_hi_v16hi = 1694,
    CODE_FOR_vec_extract_lo_v64qi = 1695,
    CODE_FOR_vec_extract_hi_v64qi = 1696,
    CODE_FOR_vec_extract_lo_v32qi = 1697,
    CODE_FOR_vec_extract_hi_v32qi = 1698,
    CODE_FOR_avx512f_unpckhpd512_mask = 1700,
    CODE_FOR_avx_unpckhpd256 = 1701,
    CODE_FOR_avx512f_vmscalefv4sf = 1707,
    CODE_FOR_avx512f_vmscalefv4sf_round = 1708,
    CODE_FOR_avx512f_vmscalefv2df = 1709,
    CODE_FOR_avx512f_vmscalefv2df_round = 1710,
    CODE_FOR_avx512f_scalefv16sf = 1711,
    CODE_FOR_avx512f_scalefv16sf_round = 1712,
    CODE_FOR_avx512f_scalefv16sf_mask = 1713,
    CODE_FOR_avx512f_scalefv16sf_mask_round = 1714,
    CODE_FOR_avx512f_scalefv8df = 1715,
    CODE_FOR_avx512f_scalefv8df_round = 1716,
    CODE_FOR_avx512f_scalefv8df_mask = 1717,
    CODE_FOR_avx512f_scalefv8df_mask_round = 1718,
    CODE_FOR_avx512f_vternlogv16si = 1719,
    CODE_FOR_avx512f_vternlogv16si_maskz_1 = 1720,
    CODE_FOR_avx512f_vternlogv8di = 1721,
    CODE_FOR_avx512f_vternlogv8di_maskz_1 = 1722,
    CODE_FOR_avx512f_vternlogv16si_mask = 1723,
    CODE_FOR_avx512f_vternlogv8di_mask = 1724,
    CODE_FOR_avx512f_getexpv16sf = 1725,
    CODE_FOR_avx512f_getexpv16sf_round = 1726,
    CODE_FOR_avx512f_getexpv16sf_mask = 1727,
    CODE_FOR_avx512f_getexpv16sf_mask_round = 1728,
    CODE_FOR_avx512f_getexpv8df = 1729,
    CODE_FOR_avx512f_getexpv8df_round = 1730,
    CODE_FOR_avx512f_getexpv8df_mask = 1731,
    CODE_FOR_avx512f_getexpv8df_mask_round = 1732,
    CODE_FOR_avx512f_sgetexpv4sf = 1733,
    CODE_FOR_avx512f_sgetexpv4sf_round = 1734,
    CODE_FOR_avx512f_sgetexpv2df = 1735,
    CODE_FOR_avx512f_sgetexpv2df_round = 1736,
    CODE_FOR_avx512f_alignv16si_mask = 1738,
    CODE_FOR_avx512f_alignv8di_mask = 1740,
    CODE_FOR_avx512f_fixupimmv16sf = 1741,
    CODE_FOR_avx512f_fixupimmv16sf_round = 1742,
    CODE_FOR_avx512f_fixupimmv16sf_maskz_1 = 1743,
    CODE_FOR_avx512f_fixupimmv16sf_maskz_1_round = 1744,
    CODE_FOR_avx512f_fixupimmv8df = 1745,
    CODE_FOR_avx512f_fixupimmv8df_round = 1746,
    CODE_FOR_avx512f_fixupimmv8df_maskz_1 = 1747,
    CODE_FOR_avx512f_fixupimmv8df_maskz_1_round = 1748,
    CODE_FOR_avx512f_fixupimmv16sf_mask = 1749,
    CODE_FOR_avx512f_fixupimmv16sf_mask_round = 1750,
    CODE_FOR_avx512f_fixupimmv8df_mask = 1751,
    CODE_FOR_avx512f_fixupimmv8df_mask_round = 1752,
    CODE_FOR_avx512f_sfixupimmv4sf = 1753,
    CODE_FOR_avx512f_sfixupimmv4sf_round = 1754,
    CODE_FOR_avx512f_sfixupimmv4sf_maskz_1 = 1755,
    CODE_FOR_avx512f_sfixupimmv4sf_maskz_1_round = 1756,
    CODE_FOR_avx512f_sfixupimmv2df = 1757,
    CODE_FOR_avx512f_sfixupimmv2df_round = 1758,
    CODE_FOR_avx512f_sfixupimmv2df_maskz_1 = 1759,
    CODE_FOR_avx512f_sfixupimmv2df_maskz_1_round = 1760,
    CODE_FOR_avx512f_sfixupimmv4sf_mask = 1761,
    CODE_FOR_avx512f_sfixupimmv4sf_mask_round = 1762,
    CODE_FOR_avx512f_sfixupimmv2df_mask = 1763,
    CODE_FOR_avx512f_sfixupimmv2df_mask_round = 1764,
    CODE_FOR_avx512f_rndscalev16sf = 1765,
    CODE_FOR_avx512f_rndscalev16sf_round = 1766,
    CODE_FOR_avx512f_rndscalev16sf_mask = 1767,
    CODE_FOR_avx512f_rndscalev16sf_mask_round = 1768,
    CODE_FOR_avx512f_rndscalev8df = 1769,
    CODE_FOR_avx512f_rndscalev8df_round = 1770,
    CODE_FOR_avx512f_rndscalev8df_mask = 1771,
    CODE_FOR_avx512f_rndscalev8df_mask_round = 1772,
    CODE_FOR_avx512f_rndscalev4sf = 1773,
    CODE_FOR_avx512f_rndscalev4sf_round = 1774,
    CODE_FOR_avx512f_rndscalev2df = 1775,
    CODE_FOR_avx512f_rndscalev2df_round = 1776,
    CODE_FOR_avx512f_shufps512_1 = 1777,
    CODE_FOR_avx512f_shufps512_1_mask = 1778,
    CODE_FOR_avx512f_shufpd512_1 = 1779,
    CODE_FOR_avx512f_shufpd512_1_mask = 1780,
    CODE_FOR_avx_shufpd256_1 = 1781,
    CODE_FOR_avx2_interleave_highv4di = 1782,
    CODE_FOR_avx512f_interleave_highv8di_mask = 1784,
    CODE_FOR_vec_interleave_highv2di = 1785,
    CODE_FOR_avx2_interleave_lowv4di = 1786,
    CODE_FOR_avx512f_interleave_lowv8di_mask = 1788,
    CODE_FOR_vec_interleave_lowv2di = 1789,
    CODE_FOR_sse2_shufpd_v2di = 1790,
    CODE_FOR_sse2_shufpd_v2df = 1791,
    CODE_FOR_sse2_storehpd = 1792,
    CODE_FOR_sse2_storelpd = 1794,
    CODE_FOR_sse2_loadhpd = 1796,
    CODE_FOR_sse2_loadlpd = 1797,
    CODE_FOR_sse2_movsd = 1798,
    CODE_FOR_vec_dupv2df = 1799,
    CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask = 1813,
    CODE_FOR_avx512f_truncatev16siv16qi2_mask = 1814,
    CODE_FOR_avx512f_us_truncatev16siv16qi2_mask = 1815,
    CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask = 1816,
    CODE_FOR_avx512f_truncatev16siv16hi2_mask = 1817,
    CODE_FOR_avx512f_us_truncatev16siv16hi2_mask = 1818,
    CODE_FOR_avx512f_ss_truncatev8div8si2_mask = 1819,
    CODE_FOR_avx512f_truncatev8div8si2_mask = 1820,
    CODE_FOR_avx512f_us_truncatev8div8si2_mask = 1821,
    CODE_FOR_avx512f_ss_truncatev8div8hi2_mask = 1822,
    CODE_FOR_avx512f_truncatev8div8hi2_mask = 1823,
    CODE_FOR_avx512f_us_truncatev8div8hi2_mask = 1824,
    CODE_FOR_avx512f_ss_truncatev8div16qi2_mask = 1831,
    CODE_FOR_avx512f_truncatev8div16qi2_mask = 1832,
    CODE_FOR_avx512f_us_truncatev8div16qi2_mask = 1833,
    CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store = 1834,
    CODE_FOR_avx512f_truncatev8div16qi2_mask_store = 1835,
    CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store = 1836,
    CODE_FOR_ashrv16hi3 = 1913,
    CODE_FOR_ashrv8hi3 = 1914,
    CODE_FOR_ashrv8si3 = 1915,
    CODE_FOR_ashrv4si3 = 1916,
    CODE_FOR_ashrv16si3 = 1917,
    CODE_FOR_ashrv16si3_mask = 1918,
    CODE_FOR_ashrv8di3 = 1919,
    CODE_FOR_ashrv8di3_mask = 1920,
    CODE_FOR_ashlv16hi3 = 1921,
    CODE_FOR_lshrv16hi3 = 1922,
    CODE_FOR_ashlv8hi3 = 1923,
    CODE_FOR_lshrv8hi3 = 1924,
    CODE_FOR_ashlv8si3 = 1925,
    CODE_FOR_lshrv8si3 = 1926,
    CODE_FOR_ashlv4si3 = 1927,
    CODE_FOR_lshrv4si3 = 1928,
    CODE_FOR_ashlv4di3 = 1929,
    CODE_FOR_lshrv4di3 = 1930,
    CODE_FOR_ashlv2di3 = 1931,
    CODE_FOR_lshrv2di3 = 1932,
    CODE_FOR_ashlv16si3 = 1933,
    CODE_FOR_ashlv16si3_mask = 1934,
    CODE_FOR_lshrv16si3 = 1935,
    CODE_FOR_lshrv16si3_mask = 1936,
    CODE_FOR_ashlv8di3 = 1937,
    CODE_FOR_ashlv8di3_mask = 1938,
    CODE_FOR_lshrv8di3 = 1939,
    CODE_FOR_lshrv8di3_mask = 1940,
    CODE_FOR_avx2_ashlv2ti3 = 1941,
    CODE_FOR_sse2_ashlv1ti3 = 1942,
    CODE_FOR_avx2_lshrv2ti3 = 1943,
    CODE_FOR_sse2_lshrv1ti3 = 1944,
    CODE_FOR_avx512f_rolvv16si = 1945,
    CODE_FOR_avx512f_rolvv16si_mask = 1946,
    CODE_FOR_avx512f_rorvv16si = 1947,
    CODE_FOR_avx512f_rorvv16si_mask = 1948,
    CODE_FOR_avx512f_rolvv8di = 1949,
    CODE_FOR_avx512f_rolvv8di_mask = 1950,
    CODE_FOR_avx512f_rorvv8di = 1951,
    CODE_FOR_avx512f_rorvv8di_mask = 1952,
    CODE_FOR_avx512f_rolv16si = 1953,
    CODE_FOR_avx512f_rolv16si_mask = 1954,
    CODE_FOR_avx512f_rorv16si = 1955,
    CODE_FOR_avx512f_rorv16si_mask = 1956,
    CODE_FOR_avx512f_rolv8di = 1957,
    CODE_FOR_avx512f_rolv8di_mask = 1958,
    CODE_FOR_avx512f_rorv8di = 1959,
    CODE_FOR_avx512f_rorv8di_mask = 1960,
    CODE_FOR_avx512f_eqv16si3_1 = 2045,
    CODE_FOR_avx512f_eqv16si3_mask_1 = 2046,
    CODE_FOR_avx512f_eqv8di3_1 = 2047,
    CODE_FOR_avx512f_eqv8di3_mask_1 = 2048,
    CODE_FOR_sse4_2_gtv2di3 = 2053,
    CODE_FOR_avx2_gtv32qi3 = 2054,
    CODE_FOR_avx2_gtv16hi3 = 2055,
    CODE_FOR_avx2_gtv8si3 = 2056,
    CODE_FOR_avx2_gtv4di3 = 2057,
    CODE_FOR_avx512f_gtv16si3 = 2058,
    CODE_FOR_avx512f_gtv16si3_mask = 2059,
    CODE_FOR_avx512f_gtv8di3 = 2060,
    CODE_FOR_avx512f_gtv8di3_mask = 2061,
    CODE_FOR_sse2_gtv16qi3 = 2062,
    CODE_FOR_sse2_gtv8hi3 = 2063,
    CODE_FOR_sse2_gtv4si3 = 2064,
    CODE_FOR_andv16si3_mask = 2078,
    CODE_FOR_iorv16si3_mask = 2080,
    CODE_FOR_xorv16si3_mask = 2082,
    CODE_FOR_andv8di3_mask = 2084,
    CODE_FOR_iorv8di3_mask = 2086,
    CODE_FOR_xorv8di3_mask = 2088,
  #define CODE_FOR_andv16qi3_mask CODE_FOR_nothing
  #define CODE_FOR_iorv16qi3_mask CODE_FOR_nothing
  #define CODE_FOR_xorv16qi3_mask CODE_FOR_nothing
  #define CODE_FOR_andv16hi3_mask CODE_FOR_nothing
  #define CODE_FOR_iorv16hi3_mask CODE_FOR_nothing
  #define CODE_FOR_xorv16hi3_mask CODE_FOR_nothing
  #define CODE_FOR_andv8hi3_mask CODE_FOR_nothing
  #define CODE_FOR_iorv8hi3_mask CODE_FOR_nothing
  #define CODE_FOR_xorv8hi3_mask CODE_FOR_nothing
  #define CODE_FOR_andv8si3_mask CODE_FOR_nothing
  #define CODE_FOR_iorv8si3_mask CODE_FOR_nothing
  #define CODE_FOR_xorv8si3_mask CODE_FOR_nothing
  #define CODE_FOR_andv4si3_mask CODE_FOR_nothing
  #define CODE_FOR_iorv4si3_mask CODE_FOR_nothing
  #define CODE_FOR_xorv4si3_mask CODE_FOR_nothing
  #define CODE_FOR_andv4di3_mask CODE_FOR_nothing
  #define CODE_FOR_iorv4di3_mask CODE_FOR_nothing
  #define CODE_FOR_xorv4di3_mask CODE_FOR_nothing
  #define CODE_FOR_andv2di3_mask CODE_FOR_nothing
  #define CODE_FOR_iorv2di3_mask CODE_FOR_nothing
  #define CODE_FOR_xorv2di3_mask CODE_FOR_nothing
    CODE_FOR_avx512f_testmv16si3 = 2113,
    CODE_FOR_avx512f_testmv16si3_mask = 2114,
    CODE_FOR_avx512f_testmv8di3 = 2115,
    CODE_FOR_avx512f_testmv8di3_mask = 2116,
    CODE_FOR_avx512f_testnmv16si3 = 2117,
    CODE_FOR_avx512f_testnmv16si3_mask = 2118,
    CODE_FOR_avx512f_testnmv8di3 = 2119,
    CODE_FOR_avx512f_testnmv8di3_mask = 2120,
    CODE_FOR_avx2_packsswb = 2121,
    CODE_FOR_sse2_packsswb = 2122,
    CODE_FOR_avx2_packssdw = 2123,
    CODE_FOR_sse2_packssdw = 2124,
    CODE_FOR_avx2_packuswb = 2125,
    CODE_FOR_sse2_packuswb = 2126,
    CODE_FOR_avx2_interleave_highv32qi = 2127,
    CODE_FOR_vec_interleave_highv16qi = 2128,
    CODE_FOR_avx2_interleave_lowv32qi = 2129,
    CODE_FOR_vec_interleave_lowv16qi = 2130,
    CODE_FOR_avx2_interleave_highv16hi = 2131,
    CODE_FOR_vec_interleave_highv8hi = 2132,
    CODE_FOR_avx2_interleave_lowv16hi = 2133,
    CODE_FOR_vec_interleave_lowv8hi = 2134,
    CODE_FOR_avx2_interleave_highv8si = 2135,
    CODE_FOR_avx512f_interleave_highv16si_mask = 2137,
    CODE_FOR_vec_interleave_highv4si = 2138,
    CODE_FOR_avx2_interleave_lowv8si = 2139,
    CODE_FOR_avx512f_interleave_lowv16si_mask = 2141,
    CODE_FOR_vec_interleave_lowv4si = 2142,
    CODE_FOR_sse4_1_pinsrb = 2143,
    CODE_FOR_sse2_pinsrw = 2144,
    CODE_FOR_sse4_1_pinsrd = 2145,
    CODE_FOR_sse4_1_pinsrq = 2146,
    CODE_FOR_avx512f_vinsertf32x4_1_mask = 2148,
    CODE_FOR_avx512f_vinserti32x4_1_mask = 2150,
    CODE_FOR_vec_set_lo_v8df = 2151,
    CODE_FOR_vec_set_lo_v8df_mask = 2152,
    CODE_FOR_vec_set_lo_v8di = 2153,
    CODE_FOR_vec_set_lo_v8di_mask = 2154,
    CODE_FOR_vec_set_hi_v8df = 2155,
    CODE_FOR_vec_set_hi_v8df_mask = 2156,
    CODE_FOR_vec_set_hi_v8di = 2157,
    CODE_FOR_vec_set_hi_v8di_mask = 2158,
    CODE_FOR_avx512f_shuf_f64x2_1 = 2159,
    CODE_FOR_avx512f_shuf_f64x2_1_mask = 2160,
    CODE_FOR_avx512f_shuf_i64x2_1 = 2161,
    CODE_FOR_avx512f_shuf_i64x2_1_mask = 2162,
    CODE_FOR_avx512f_shuf_f32x4_1 = 2163,
    CODE_FOR_avx512f_shuf_f32x4_1_mask = 2164,
    CODE_FOR_avx512f_shuf_i32x4_1 = 2165,
    CODE_FOR_avx512f_shuf_i32x4_1_mask = 2166,
    CODE_FOR_avx512f_pshufd_1 = 2167,
    CODE_FOR_avx512f_pshufd_1_mask = 2168,
    CODE_FOR_avx2_pshufd_1 = 2169,
    CODE_FOR_sse2_pshufd_1 = 2170,
    CODE_FOR_avx2_pshuflw_1 = 2171,
    CODE_FOR_sse2_pshuflw_1 = 2172,
    CODE_FOR_avx2_pshufhw_1 = 2173,
    CODE_FOR_sse2_pshufhw_1 = 2174,
    CODE_FOR_sse2_loadld = 2175,
    CODE_FOR_vec_concatv2di = 2193,
    CODE_FOR_avx2_psadbw = 2198,
    CODE_FOR_sse2_psadbw = 2199,
    CODE_FOR_avx_movmskps256 = 2200,
    CODE_FOR_sse_movmskps = 2201,
    CODE_FOR_avx_movmskpd256 = 2202,
    CODE_FOR_sse2_movmskpd = 2203,
    CODE_FOR_avx2_pmovmskb = 2204,
    CODE_FOR_sse2_pmovmskb = 2205,
    CODE_FOR_sse_ldmxcsr = 2208,
    CODE_FOR_sse_stmxcsr = 2209,
    CODE_FOR_sse2_clflush = 2210,
    CODE_FOR_sse3_mwait = 2211,
    CODE_FOR_sse3_monitor_si = 2212,
    CODE_FOR_sse3_monitor_di = 2213,
    CODE_FOR_avx2_phaddwv16hi3 = 2214,
    CODE_FOR_avx2_phaddswv16hi3 = 2215,
    CODE_FOR_avx2_phsubwv16hi3 = 2216,
    CODE_FOR_avx2_phsubswv16hi3 = 2217,
    CODE_FOR_ssse3_phaddwv8hi3 = 2218,
    CODE_FOR_ssse3_phaddswv8hi3 = 2219,
    CODE_FOR_ssse3_phsubwv8hi3 = 2220,
    CODE_FOR_ssse3_phsubswv8hi3 = 2221,
    CODE_FOR_ssse3_phaddwv4hi3 = 2222,
    CODE_FOR_ssse3_phaddswv4hi3 = 2223,
    CODE_FOR_ssse3_phsubwv4hi3 = 2224,
    CODE_FOR_ssse3_phsubswv4hi3 = 2225,
    CODE_FOR_avx2_phadddv8si3 = 2226,
    CODE_FOR_avx2_phsubdv8si3 = 2227,
    CODE_FOR_ssse3_phadddv4si3 = 2228,
    CODE_FOR_ssse3_phsubdv4si3 = 2229,
    CODE_FOR_ssse3_phadddv2si3 = 2230,
    CODE_FOR_ssse3_phsubdv2si3 = 2231,
    CODE_FOR_avx2_pmaddubsw256 = 2232,
    CODE_FOR_ssse3_pmaddubsw128 = 2233,
    CODE_FOR_ssse3_pmaddubsw = 2234,
    CODE_FOR_avx2_pshufbv32qi3 = 2238,
    CODE_FOR_ssse3_pshufbv16qi3 = 2239,
    CODE_FOR_ssse3_pshufbv8qi3 = 2240,
    CODE_FOR_avx2_psignv32qi3 = 2241,
    CODE_FOR_ssse3_psignv16qi3 = 2242,
    CODE_FOR_avx2_psignv16hi3 = 2243,
    CODE_FOR_ssse3_psignv8hi3 = 2244,
    CODE_FOR_avx2_psignv8si3 = 2245,
    CODE_FOR_ssse3_psignv4si3 = 2246,
    CODE_FOR_ssse3_psignv8qi3 = 2247,
    CODE_FOR_ssse3_psignv4hi3 = 2248,
    CODE_FOR_ssse3_psignv2si3 = 2249,
    CODE_FOR_avx2_palignrv2ti = 2250,
    CODE_FOR_ssse3_palignrti = 2251,
    CODE_FOR_ssse3_palignrdi = 2252,
  #define CODE_FOR_absv16qi2_mask CODE_FOR_nothing
  #define CODE_FOR_absv16hi2_mask CODE_FOR_nothing
  #define CODE_FOR_absv8hi2_mask CODE_FOR_nothing
    CODE_FOR_absv16si2_mask = 2258,
  #define CODE_FOR_absv8si2_mask CODE_FOR_nothing
  #define CODE_FOR_absv4si2_mask CODE_FOR_nothing
    CODE_FOR_absv8di2_mask = 2262,
    CODE_FOR_absv8qi2 = 2263,
    CODE_FOR_absv4hi2 = 2264,
    CODE_FOR_absv2si2 = 2265,
    CODE_FOR_sse4a_movntsf = 2266,
    CODE_FOR_sse4a_movntdf = 2267,
    CODE_FOR_sse4a_vmmovntv4sf = 2268,
    CODE_FOR_sse4a_vmmovntv2df = 2269,
    CODE_FOR_sse4a_extrqi = 2270,
    CODE_FOR_sse4a_extrq = 2271,
    CODE_FOR_sse4a_insertqi = 2272,
    CODE_FOR_sse4a_insertq = 2273,
    CODE_FOR_avx_blendps256 = 2274,
    CODE_FOR_sse4_1_blendps = 2275,
    CODE_FOR_avx_blendpd256 = 2276,
    CODE_FOR_sse4_1_blendpd = 2277,
    CODE_FOR_avx_blendvps256 = 2278,
    CODE_FOR_sse4_1_blendvps = 2279,
    CODE_FOR_avx_blendvpd256 = 2280,
    CODE_FOR_sse4_1_blendvpd = 2281,
    CODE_FOR_avx_dpps256 = 2282,
    CODE_FOR_sse4_1_dpps = 2283,
    CODE_FOR_avx_dppd256 = 2284,
    CODE_FOR_sse4_1_dppd = 2285,
    CODE_FOR_avx512f_movntdqa = 2286,
    CODE_FOR_avx2_movntdqa = 2287,
    CODE_FOR_sse4_1_movntdqa = 2288,
    CODE_FOR_avx2_mpsadbw = 2289,
    CODE_FOR_sse4_1_mpsadbw = 2290,
    CODE_FOR_avx2_packusdw = 2291,
    CODE_FOR_sse4_1_packusdw = 2292,
    CODE_FOR_avx2_pblendvb = 2293,
    CODE_FOR_sse4_1_pblendvb = 2294,
    CODE_FOR_sse4_1_pblendw = 2295,
    CODE_FOR_avx2_pblenddv8si = 2297,
    CODE_FOR_avx2_pblenddv4si = 2298,
    CODE_FOR_sse4_1_phminposuw = 2299,
    CODE_FOR_avx2_sign_extendv16qiv16hi2 = 2300,
    CODE_FOR_avx2_zero_extendv16qiv16hi2 = 2301,
    CODE_FOR_sse4_1_sign_extendv8qiv8hi2 = 2302,
    CODE_FOR_sse4_1_zero_extendv8qiv8hi2 = 2303,
    CODE_FOR_avx512f_sign_extendv16qiv16si2_mask = 2305,
    CODE_FOR_avx512f_zero_extendv16qiv16si2_mask = 2307,
    CODE_FOR_avx2_sign_extendv8qiv8si2 = 2308,
    CODE_FOR_avx2_zero_extendv8qiv8si2 = 2309,
    CODE_FOR_sse4_1_sign_extendv4qiv4si2 = 2310,
    CODE_FOR_sse4_1_zero_extendv4qiv4si2 = 2311,
    CODE_FOR_avx512f_sign_extendv16hiv16si2 = 2312,
    CODE_FOR_avx512f_sign_extendv16hiv16si2_mask = 2313,
    CODE_FOR_avx512f_zero_extendv16hiv16si2 = 2314,
    CODE_FOR_avx512f_zero_extendv16hiv16si2_mask = 2315,
    CODE_FOR_avx2_sign_extendv8hiv8si2 = 2316,
    CODE_FOR_avx2_zero_extendv8hiv8si2 = 2317,
    CODE_FOR_sse4_1_sign_extendv4hiv4si2 = 2318,
    CODE_FOR_sse4_1_zero_extendv4hiv4si2 = 2319,
    CODE_FOR_avx512f_sign_extendv8qiv8di2 = 2320,
    CODE_FOR_avx512f_sign_extendv8qiv8di2_mask = 2321,
    CODE_FOR_avx512f_zero_extendv8qiv8di2 = 2322,
    CODE_FOR_avx512f_zero_extendv8qiv8di2_mask = 2323,
    CODE_FOR_avx2_sign_extendv4qiv4di2 = 2324,
    CODE_FOR_avx2_zero_extendv4qiv4di2 = 2325,
    CODE_FOR_sse4_1_sign_extendv2qiv2di2 = 2326,
    CODE_FOR_sse4_1_zero_extendv2qiv2di2 = 2327,
    CODE_FOR_avx512f_sign_extendv8hiv8di2 = 2328,
    CODE_FOR_avx512f_sign_extendv8hiv8di2_mask = 2329,
    CODE_FOR_avx512f_zero_extendv8hiv8di2 = 2330,
    CODE_FOR_avx512f_zero_extendv8hiv8di2_mask = 2331,
    CODE_FOR_avx2_sign_extendv4hiv4di2 = 2332,
    CODE_FOR_avx2_zero_extendv4hiv4di2 = 2333,
    CODE_FOR_sse4_1_sign_extendv2hiv2di2 = 2334,
    CODE_FOR_sse4_1_zero_extendv2hiv2di2 = 2335,
    CODE_FOR_avx512f_sign_extendv8siv8di2 = 2336,
    CODE_FOR_avx512f_sign_extendv8siv8di2_mask = 2337,
    CODE_FOR_avx512f_zero_extendv8siv8di2 = 2338,
    CODE_FOR_avx512f_zero_extendv8siv8di2_mask = 2339,
    CODE_FOR_avx2_sign_extendv4siv4di2 = 2340,
    CODE_FOR_avx2_zero_extendv4siv4di2 = 2341,
    CODE_FOR_sse4_1_sign_extendv2siv2di2 = 2342,
    CODE_FOR_sse4_1_zero_extendv2siv2di2 = 2343,
    CODE_FOR_avx_vtestps256 = 2344,
    CODE_FOR_avx_vtestps = 2345,
    CODE_FOR_avx_vtestpd256 = 2346,
    CODE_FOR_avx_vtestpd = 2347,
    CODE_FOR_avx_ptest256 = 2348,
    CODE_FOR_sse4_1_ptest = 2349,
    CODE_FOR_avx_roundps256 = 2350,
    CODE_FOR_sse4_1_roundps = 2351,
    CODE_FOR_avx_roundpd256 = 2352,
    CODE_FOR_sse4_1_roundpd = 2353,
    CODE_FOR_sse4_1_roundss = 2354,
    CODE_FOR_sse4_1_roundsd = 2355,
    CODE_FOR_sse4_2_pcmpestr = 2356,
    CODE_FOR_sse4_2_pcmpestri = 2358,
    CODE_FOR_sse4_2_pcmpestrm = 2359,
    CODE_FOR_sse4_2_pcmpestr_cconly = 2360,
    CODE_FOR_sse4_2_pcmpistr = 2361,
    CODE_FOR_sse4_2_pcmpistri = 2363,
    CODE_FOR_sse4_2_pcmpistrm = 2364,
    CODE_FOR_sse4_2_pcmpistr_cconly = 2365,
    CODE_FOR_avx512er_exp2v16sf = 2398,
    CODE_FOR_avx512er_exp2v16sf_round = 2399,
    CODE_FOR_avx512er_exp2v16sf_mask = 2400,
    CODE_FOR_avx512er_exp2v16sf_mask_round = 2401,
    CODE_FOR_avx512er_exp2v8df = 2402,
    CODE_FOR_avx512er_exp2v8df_round = 2403,
    CODE_FOR_avx512er_exp2v8df_mask = 2404,
    CODE_FOR_avx512er_exp2v8df_mask_round = 2405,
    CODE_FOR_avx512er_rcp28v16sf_mask = 2408,
    CODE_FOR_avx512er_rcp28v16sf_mask_round = 2409,
    CODE_FOR_avx512er_rcp28v8df_mask = 2412,
    CODE_FOR_avx512er_rcp28v8df_mask_round = 2413,
    CODE_FOR_avx512er_vmrcp28v4sf = 2414,
    CODE_FOR_avx512er_vmrcp28v4sf_round = 2415,
    CODE_FOR_avx512er_vmrcp28v2df = 2416,
    CODE_FOR_avx512er_vmrcp28v2df_round = 2417,
    CODE_FOR_avx512er_rsqrt28v16sf_mask = 2420,
    CODE_FOR_avx512er_rsqrt28v16sf_mask_round = 2421,
    CODE_FOR_avx512er_rsqrt28v8df_mask = 2424,
    CODE_FOR_avx512er_rsqrt28v8df_mask_round = 2425,
    CODE_FOR_avx512er_vmrsqrt28v4sf = 2426,
    CODE_FOR_avx512er_vmrsqrt28v4sf_round = 2427,
    CODE_FOR_avx512er_vmrsqrt28v2df = 2428,
    CODE_FOR_avx512er_vmrsqrt28v2df_round = 2429,
    CODE_FOR_xop_pmacsww = 2430,
    CODE_FOR_xop_pmacssww = 2431,
    CODE_FOR_xop_pmacsdd = 2432,
    CODE_FOR_xop_pmacssdd = 2433,
    CODE_FOR_xop_pmacsdql = 2434,
    CODE_FOR_xop_pmacssdql = 2435,
    CODE_FOR_xop_pmacsdqh = 2436,
    CODE_FOR_xop_pmacssdqh = 2437,
    CODE_FOR_xop_pmacswd = 2438,
    CODE_FOR_xop_pmacsswd = 2439,
    CODE_FOR_xop_pmadcswd = 2440,
    CODE_FOR_xop_pmadcsswd = 2441,
    CODE_FOR_xop_pcmov_v32qi256 = 2442,
    CODE_FOR_xop_pcmov_v16qi = 2443,
    CODE_FOR_xop_pcmov_v16hi256 = 2444,
    CODE_FOR_xop_pcmov_v8hi = 2445,
    CODE_FOR_xop_pcmov_v16si512 = 2446,
    CODE_FOR_xop_pcmov_v8si256 = 2447,
    CODE_FOR_xop_pcmov_v4si = 2448,
    CODE_FOR_xop_pcmov_v8di512 = 2449,
    CODE_FOR_xop_pcmov_v4di256 = 2450,
    CODE_FOR_xop_pcmov_v2di = 2451,
    CODE_FOR_xop_pcmov_v16sf512 = 2452,
    CODE_FOR_xop_pcmov_v8sf256 = 2453,
    CODE_FOR_xop_pcmov_v4sf = 2454,
    CODE_FOR_xop_pcmov_v8df512 = 2455,
    CODE_FOR_xop_pcmov_v4df256 = 2456,
    CODE_FOR_xop_pcmov_v2df = 2457,
    CODE_FOR_xop_phaddbw = 2458,
    CODE_FOR_xop_phaddubw = 2459,
    CODE_FOR_xop_phaddbd = 2460,
    CODE_FOR_xop_phaddubd = 2461,
    CODE_FOR_xop_phaddbq = 2462,
    CODE_FOR_xop_phaddubq = 2463,
    CODE_FOR_xop_phaddwd = 2464,
    CODE_FOR_xop_phadduwd = 2465,
    CODE_FOR_xop_phaddwq = 2466,
    CODE_FOR_xop_phadduwq = 2467,
    CODE_FOR_xop_phadddq = 2468,
    CODE_FOR_xop_phaddudq = 2469,
    CODE_FOR_xop_phsubbw = 2470,
    CODE_FOR_xop_phsubwd = 2471,
    CODE_FOR_xop_phsubdq = 2472,
    CODE_FOR_xop_pperm = 2473,
    CODE_FOR_xop_pperm_pack_v2di_v4si = 2474,
    CODE_FOR_xop_pperm_pack_v4si_v8hi = 2475,
    CODE_FOR_xop_pperm_pack_v8hi_v16qi = 2476,
    CODE_FOR_xop_rotlv16qi3 = 2477,
    CODE_FOR_xop_rotlv8hi3 = 2478,
    CODE_FOR_xop_rotlv4si3 = 2479,
    CODE_FOR_xop_rotlv2di3 = 2480,
    CODE_FOR_xop_rotrv16qi3 = 2481,
    CODE_FOR_xop_rotrv8hi3 = 2482,
    CODE_FOR_xop_rotrv4si3 = 2483,
    CODE_FOR_xop_rotrv2di3 = 2484,
    CODE_FOR_xop_vrotlv16qi3 = 2485,
    CODE_FOR_xop_vrotlv8hi3 = 2486,
    CODE_FOR_xop_vrotlv4si3 = 2487,
    CODE_FOR_xop_vrotlv2di3 = 2488,
    CODE_FOR_xop_shav16qi3 = 2489,
    CODE_FOR_xop_shav8hi3 = 2490,
    CODE_FOR_xop_shav4si3 = 2491,
    CODE_FOR_xop_shav2di3 = 2492,
    CODE_FOR_xop_shlv16qi3 = 2493,
    CODE_FOR_xop_shlv8hi3 = 2494,
    CODE_FOR_xop_shlv4si3 = 2495,
    CODE_FOR_xop_shlv2di3 = 2496,
    CODE_FOR_xop_frczsf2 = 2497,
    CODE_FOR_xop_frczdf2 = 2498,
    CODE_FOR_xop_frczv4sf2 = 2499,
    CODE_FOR_xop_frczv2df2 = 2500,
    CODE_FOR_xop_frczv8sf2 = 2501,
    CODE_FOR_xop_frczv4df2 = 2502,
    CODE_FOR_xop_frczv16sf2 = 2503,
    CODE_FOR_xop_frczv8df2 = 2504,
    CODE_FOR_xop_maskcmpv16qi3 = 2507,
    CODE_FOR_xop_maskcmpv8hi3 = 2508,
    CODE_FOR_xop_maskcmpv4si3 = 2509,
    CODE_FOR_xop_maskcmpv2di3 = 2510,
    CODE_FOR_xop_maskcmp_unsv16qi3 = 2511,
    CODE_FOR_xop_maskcmp_unsv8hi3 = 2512,
    CODE_FOR_xop_maskcmp_unsv4si3 = 2513,
    CODE_FOR_xop_maskcmp_unsv2di3 = 2514,
    CODE_FOR_xop_maskcmp_uns2v16qi3 = 2515,
    CODE_FOR_xop_maskcmp_uns2v8hi3 = 2516,
    CODE_FOR_xop_maskcmp_uns2v4si3 = 2517,
    CODE_FOR_xop_maskcmp_uns2v2di3 = 2518,
    CODE_FOR_xop_pcom_tfv16qi3 = 2519,
    CODE_FOR_xop_pcom_tfv8hi3 = 2520,
    CODE_FOR_xop_pcom_tfv4si3 = 2521,
    CODE_FOR_xop_pcom_tfv2di3 = 2522,
    CODE_FOR_xop_vpermil2v8sf3 = 2523,
    CODE_FOR_xop_vpermil2v4sf3 = 2524,
    CODE_FOR_xop_vpermil2v4df3 = 2525,
    CODE_FOR_xop_vpermil2v2df3 = 2526,
    CODE_FOR_aesenc = 2527,
    CODE_FOR_aesenclast = 2528,
    CODE_FOR_aesdec = 2529,
    CODE_FOR_aesdeclast = 2530,
    CODE_FOR_aesimc = 2531,
    CODE_FOR_aeskeygenassist = 2532,
    CODE_FOR_pclmulqdq = 2533,
    CODE_FOR_avx_vzeroupper = 2535,
    CODE_FOR_avx2_pbroadcastv16si = 2536,
    CODE_FOR_avx2_pbroadcastv8di = 2537,
    CODE_FOR_avx2_pbroadcastv32qi = 2538,
    CODE_FOR_avx2_pbroadcastv16qi = 2539,
    CODE_FOR_avx2_pbroadcastv16hi = 2540,
    CODE_FOR_avx2_pbroadcastv8hi = 2541,
    CODE_FOR_avx2_pbroadcastv8si = 2542,
    CODE_FOR_avx2_pbroadcastv4si = 2543,
    CODE_FOR_avx2_pbroadcastv4di = 2544,
    CODE_FOR_avx2_pbroadcastv2di = 2545,
    CODE_FOR_avx2_pbroadcastv32qi_1 = 2546,
    CODE_FOR_avx2_pbroadcastv16hi_1 = 2547,
    CODE_FOR_avx2_pbroadcastv8si_1 = 2548,
    CODE_FOR_avx2_pbroadcastv4di_1 = 2549,
    CODE_FOR_avx2_permvarv8si = 2550,
  #define CODE_FOR_avx2_permvarv8si_mask CODE_FOR_nothing
    CODE_FOR_avx2_permvarv8sf = 2551,
  #define CODE_FOR_avx2_permvarv8sf_mask CODE_FOR_nothing
    CODE_FOR_avx512f_permvarv16si = 2552,
    CODE_FOR_avx512f_permvarv16si_mask = 2553,
    CODE_FOR_avx512f_permvarv16sf = 2554,
    CODE_FOR_avx512f_permvarv16sf_mask = 2555,
    CODE_FOR_avx512f_permvarv8di = 2556,
    CODE_FOR_avx512f_permvarv8di_mask = 2557,
    CODE_FOR_avx512f_permvarv8df = 2558,
    CODE_FOR_avx512f_permvarv8df_mask = 2559,
    CODE_FOR_avx2_permv4di_1 = 2560,
  #define CODE_FOR_avx2_permv4di_1_mask CODE_FOR_nothing
    CODE_FOR_avx2_permv4df_1 = 2561,
  #define CODE_FOR_avx2_permv4df_1_mask CODE_FOR_nothing
    CODE_FOR_avx512f_permv8di_1 = 2562,
    CODE_FOR_avx512f_permv8di_1_mask = 2563,
    CODE_FOR_avx512f_permv8df_1 = 2564,
    CODE_FOR_avx512f_permv8df_1_mask = 2565,
    CODE_FOR_avx2_permv2ti = 2566,
    CODE_FOR_avx2_vec_dupv4df = 2567,
    CODE_FOR_vec_dupv8si = 2568,
    CODE_FOR_vec_dupv8sf = 2569,
    CODE_FOR_vec_dupv4di = 2570,
    CODE_FOR_vec_dupv4df = 2571,
    CODE_FOR_avx512f_vec_dupv16si_mask = 2573,
    CODE_FOR_avx512f_vec_dupv16sf_mask = 2575,
    CODE_FOR_avx512f_vec_dupv8di_mask = 2577,
    CODE_FOR_avx512f_vec_dupv8df_mask = 2579,
    CODE_FOR_avx512f_broadcastv16sf_mask = 2581,
    CODE_FOR_avx512f_broadcastv16si_mask = 2583,
    CODE_FOR_avx512f_broadcastv8df_mask = 2585,
    CODE_FOR_avx512f_broadcastv8di_mask = 2587,
    CODE_FOR_avx512f_vec_dup_gprv16si_mask = 2589,
  #define CODE_FOR_avx512f_vec_dup_gprv8di_mask CODE_FOR_nothing
    CODE_FOR_avx512f_vec_dup_memv16si_mask = 2591,
    CODE_FOR_avx512f_vec_dup_memv16sf_mask = 2593,
    CODE_FOR_avx512f_vec_dup_memv8di_mask = 2595,
    CODE_FOR_avx512f_vec_dup_memv8df_mask = 2597,
    CODE_FOR_avx2_vbroadcasti128_v32qi = 2598,
    CODE_FOR_avx2_vbroadcasti128_v16hi = 2599,
    CODE_FOR_avx2_vbroadcasti128_v8si = 2600,
    CODE_FOR_avx2_vbroadcasti128_v4di = 2601,
    CODE_FOR_avx_vbroadcastf128_v32qi = 2602,
    CODE_FOR_avx_vbroadcastf128_v16hi = 2603,
    CODE_FOR_avx_vbroadcastf128_v8si = 2604,
    CODE_FOR_avx_vbroadcastf128_v4di = 2605,
    CODE_FOR_avx_vbroadcastf128_v8sf = 2606,
    CODE_FOR_avx_vbroadcastf128_v4df = 2607,
    CODE_FOR_avx512cd_maskb_vec_dupv8di = 2608,
    CODE_FOR_avx512cd_maskw_vec_dupv16si = 2609,
    CODE_FOR_avx512f_vpermilvarv16sf3 = 2621,
    CODE_FOR_avx512f_vpermilvarv16sf3_mask = 2622,
    CODE_FOR_avx_vpermilvarv8sf3 = 2623,
  #define CODE_FOR_avx_vpermilvarv8sf3_mask CODE_FOR_nothing
    CODE_FOR_avx_vpermilvarv4sf3 = 2624,
  #define CODE_FOR_avx_vpermilvarv4sf3_mask CODE_FOR_nothing
    CODE_FOR_avx512f_vpermilvarv8df3 = 2625,
    CODE_FOR_avx512f_vpermilvarv8df3_mask = 2626,
    CODE_FOR_avx_vpermilvarv4df3 = 2627,
  #define CODE_FOR_avx_vpermilvarv4df3_mask CODE_FOR_nothing
    CODE_FOR_avx_vpermilvarv2df3 = 2628,
  #define CODE_FOR_avx_vpermilvarv2df3_mask CODE_FOR_nothing
    CODE_FOR_avx512f_vpermi2varv16si3 = 2629,
    CODE_FOR_avx512f_vpermi2varv16si3_maskz_1 = 2630,
    CODE_FOR_avx512f_vpermi2varv16sf3 = 2631,
    CODE_FOR_avx512f_vpermi2varv16sf3_maskz_1 = 2632,
    CODE_FOR_avx512f_vpermi2varv8di3 = 2633,
    CODE_FOR_avx512f_vpermi2varv8di3_maskz_1 = 2634,
    CODE_FOR_avx512f_vpermi2varv8df3 = 2635,
    CODE_FOR_avx512f_vpermi2varv8df3_maskz_1 = 2636,
    CODE_FOR_avx512f_vpermi2varv16si3_mask = 2637,
    CODE_FOR_avx512f_vpermi2varv16sf3_mask = 2638,
    CODE_FOR_avx512f_vpermi2varv8di3_mask = 2639,
    CODE_FOR_avx512f_vpermi2varv8df3_mask = 2640,
    CODE_FOR_avx512f_vpermt2varv16si3 = 2641,
    CODE_FOR_avx512f_vpermt2varv16si3_maskz_1 = 2642,
    CODE_FOR_avx512f_vpermt2varv16sf3 = 2643,
    CODE_FOR_avx512f_vpermt2varv16sf3_maskz_1 = 2644,
    CODE_FOR_avx512f_vpermt2varv8di3 = 2645,
    CODE_FOR_avx512f_vpermt2varv8di3_maskz_1 = 2646,
    CODE_FOR_avx512f_vpermt2varv8df3 = 2647,
    CODE_FOR_avx512f_vpermt2varv8df3_maskz_1 = 2648,
    CODE_FOR_avx512f_vpermt2varv16si3_mask = 2649,
    CODE_FOR_avx512f_vpermt2varv16sf3_mask = 2650,
    CODE_FOR_avx512f_vpermt2varv8di3_mask = 2651,
    CODE_FOR_avx512f_vpermt2varv8df3_mask = 2652,
    CODE_FOR_avx2_vec_set_lo_v4di = 2659,
    CODE_FOR_avx2_vec_set_hi_v4di = 2660,
    CODE_FOR_vec_set_lo_v4di = 2661,
    CODE_FOR_vec_set_lo_v4df = 2662,
    CODE_FOR_vec_set_hi_v4di = 2663,
    CODE_FOR_vec_set_hi_v4df = 2664,
    CODE_FOR_vec_set_lo_v8si = 2665,
    CODE_FOR_vec_set_lo_v8sf = 2666,
    CODE_FOR_vec_set_hi_v8si = 2667,
    CODE_FOR_vec_set_hi_v8sf = 2668,
    CODE_FOR_vec_set_lo_v16hi = 2669,
    CODE_FOR_vec_set_hi_v16hi = 2670,
    CODE_FOR_vec_set_lo_v32qi = 2671,
    CODE_FOR_vec_set_hi_v32qi = 2672,
    CODE_FOR_avx_maskloadps = 2673,
    CODE_FOR_avx_maskloadpd = 2674,
    CODE_FOR_avx_maskloadps256 = 2675,
    CODE_FOR_avx_maskloadpd256 = 2676,
    CODE_FOR_avx2_maskloadd = 2677,
    CODE_FOR_avx2_maskloadq = 2678,
    CODE_FOR_avx2_maskloadd256 = 2679,
    CODE_FOR_avx2_maskloadq256 = 2680,
    CODE_FOR_avx_maskstoreps = 2681,
    CODE_FOR_avx_maskstorepd = 2682,
    CODE_FOR_avx_maskstoreps256 = 2683,
    CODE_FOR_avx_maskstorepd256 = 2684,
    CODE_FOR_avx2_maskstored = 2685,
    CODE_FOR_avx2_maskstoreq = 2686,
    CODE_FOR_avx2_maskstored256 = 2687,
    CODE_FOR_avx2_maskstoreq256 = 2688,
    CODE_FOR_avx_si256_si = 2689,
    CODE_FOR_avx_ps256_ps = 2690,
    CODE_FOR_avx_pd256_pd = 2691,
    CODE_FOR_avx512f_ashrvv16si = 2692,
    CODE_FOR_avx512f_ashrvv16si_mask = 2693,
    CODE_FOR_avx2_ashrvv8si = 2694,
  #define CODE_FOR_avx2_ashrvv8si_mask CODE_FOR_nothing
    CODE_FOR_avx2_ashrvv4si = 2695,
  #define CODE_FOR_avx2_ashrvv4si_mask CODE_FOR_nothing
    CODE_FOR_avx512f_ashrvv8di = 2696,
    CODE_FOR_avx512f_ashrvv8di_mask = 2697,
    CODE_FOR_avx512f_ashlvv16si = 2698,
    CODE_FOR_avx512f_ashlvv16si_mask = 2699,
    CODE_FOR_avx512f_lshrvv16si = 2700,
    CODE_FOR_avx512f_lshrvv16si_mask = 2701,
    CODE_FOR_avx2_ashlvv8si = 2702,
  #define CODE_FOR_avx2_ashlvv8si_mask CODE_FOR_nothing
    CODE_FOR_avx2_lshrvv8si = 2703,
  #define CODE_FOR_avx2_lshrvv8si_mask CODE_FOR_nothing
    CODE_FOR_avx2_ashlvv4si = 2704,
  #define CODE_FOR_avx2_ashlvv4si_mask CODE_FOR_nothing
    CODE_FOR_avx2_lshrvv4si = 2705,
  #define CODE_FOR_avx2_lshrvv4si_mask CODE_FOR_nothing
    CODE_FOR_avx512f_ashlvv8di = 2706,
    CODE_FOR_avx512f_ashlvv8di_mask = 2707,
    CODE_FOR_avx512f_lshrvv8di = 2708,
    CODE_FOR_avx512f_lshrvv8di_mask = 2709,
    CODE_FOR_avx2_ashlvv4di = 2710,
  #define CODE_FOR_avx2_ashlvv4di_mask CODE_FOR_nothing
    CODE_FOR_avx2_lshrvv4di = 2711,
  #define CODE_FOR_avx2_lshrvv4di_mask CODE_FOR_nothing
    CODE_FOR_avx2_ashlvv2di = 2712,
  #define CODE_FOR_avx2_ashlvv2di_mask CODE_FOR_nothing
    CODE_FOR_avx2_lshrvv2di = 2713,
  #define CODE_FOR_avx2_lshrvv2di_mask CODE_FOR_nothing
    CODE_FOR_avx_vec_concatv32qi = 2714,
    CODE_FOR_avx_vec_concatv16hi = 2715,
    CODE_FOR_avx_vec_concatv8si = 2716,
    CODE_FOR_avx_vec_concatv4di = 2717,
    CODE_FOR_avx_vec_concatv8sf = 2718,
    CODE_FOR_avx_vec_concatv4df = 2719,
    CODE_FOR_avx_vec_concatv64qi = 2720,
    CODE_FOR_avx_vec_concatv32hi = 2721,
    CODE_FOR_avx_vec_concatv16si = 2722,
    CODE_FOR_avx_vec_concatv8di = 2723,
    CODE_FOR_avx_vec_concatv16sf = 2724,
    CODE_FOR_avx_vec_concatv8df = 2725,
    CODE_FOR_vcvtph2ps = 2726,
    CODE_FOR_vcvtph2ps256 = 2728,
    CODE_FOR_avx512f_vcvtph2ps512_mask = 2731,
    CODE_FOR_avx512f_vcvtph2ps512_mask_round = 2732,
    CODE_FOR_vcvtps2ph256 = 2735,
    CODE_FOR_avx512f_vcvtps2ph512_mask = 2737,
    CODE_FOR_avx512f_compressv16si_mask = 2858,
    CODE_FOR_avx512f_compressv16sf_mask = 2859,
    CODE_FOR_avx512f_compressv8di_mask = 2860,
    CODE_FOR_avx512f_compressv8df_mask = 2861,
    CODE_FOR_avx512f_compressstorev16si_mask = 2862,
    CODE_FOR_avx512f_compressstorev16sf_mask = 2863,
    CODE_FOR_avx512f_compressstorev8di_mask = 2864,
    CODE_FOR_avx512f_compressstorev8df_mask = 2865,
    CODE_FOR_avx512f_expandv16si_mask = 2866,
    CODE_FOR_avx512f_expandv16sf_mask = 2867,
    CODE_FOR_avx512f_expandv8di_mask = 2868,
    CODE_FOR_avx512f_expandv8df_mask = 2869,
    CODE_FOR_avx512f_getmantv16sf = 2870,
    CODE_FOR_avx512f_getmantv16sf_round = 2871,
    CODE_FOR_avx512f_getmantv16sf_mask = 2872,
    CODE_FOR_avx512f_getmantv16sf_mask_round = 2873,
    CODE_FOR_avx512f_getmantv8df = 2874,
    CODE_FOR_avx512f_getmantv8df_round = 2875,
    CODE_FOR_avx512f_getmantv8df_mask = 2876,
    CODE_FOR_avx512f_getmantv8df_mask_round = 2877,
    CODE_FOR_avx512f_getmantv4sf = 2878,
    CODE_FOR_avx512f_getmantv4sf_round = 2879,
    CODE_FOR_avx512f_getmantv2df = 2880,
    CODE_FOR_avx512f_getmantv2df_round = 2881,
    CODE_FOR_clzv16si2 = 2882,
    CODE_FOR_clzv16si2_mask = 2883,
    CODE_FOR_clzv8di2 = 2884,
    CODE_FOR_clzv8di2_mask = 2885,
    CODE_FOR_conflictv16si_mask = 2887,
    CODE_FOR_conflictv8di_mask = 2889,
    CODE_FOR_sha1msg1 = 2890,
    CODE_FOR_sha1msg2 = 2891,
    CODE_FOR_sha1nexte = 2892,
    CODE_FOR_sha1rnds4 = 2893,
    CODE_FOR_sha256msg1 = 2894,
    CODE_FOR_sha256msg2 = 2895,
    CODE_FOR_sha256rnds2 = 2896,
    CODE_FOR_mfence_sse2 = 2899,
    CODE_FOR_mfence_nosse = 2900,
    CODE_FOR_atomic_loaddi_fpu = 2901,
    CODE_FOR_atomic_storeqi_1 = 2902,
    CODE_FOR_atomic_storehi_1 = 2903,
    CODE_FOR_atomic_storesi_1 = 2904,
  #define CODE_FOR_atomic_storedi_1 CODE_FOR_nothing
    CODE_FOR_atomic_storedi_fpu = 2905,
    CODE_FOR_loaddi_via_fpu = 2906,
    CODE_FOR_storedi_via_fpu = 2907,
    CODE_FOR_atomic_compare_and_swapqi_1 = 2908,
    CODE_FOR_atomic_compare_and_swaphi_1 = 2909,
    CODE_FOR_atomic_compare_and_swapsi_1 = 2910,
  #define CODE_FOR_atomic_compare_and_swapdi_1 CODE_FOR_nothing
    CODE_FOR_atomic_compare_and_swapdi_doubleword = 2911,
  #define CODE_FOR_atomic_compare_and_swapti_doubleword CODE_FOR_nothing
    CODE_FOR_atomic_fetch_addqi = 2912,
    CODE_FOR_atomic_fetch_addhi = 2913,
    CODE_FOR_atomic_fetch_addsi = 2914,
  #define CODE_FOR_atomic_fetch_adddi CODE_FOR_nothing
    CODE_FOR_atomic_exchangeqi = 2918,
    CODE_FOR_atomic_exchangehi = 2919,
    CODE_FOR_atomic_exchangesi = 2920,
  #define CODE_FOR_atomic_exchangedi CODE_FOR_nothing
    CODE_FOR_atomic_addqi = 2921,
    CODE_FOR_atomic_addhi = 2922,
    CODE_FOR_atomic_addsi = 2923,
  #define CODE_FOR_atomic_adddi CODE_FOR_nothing
    CODE_FOR_atomic_subqi = 2924,
    CODE_FOR_atomic_subhi = 2925,
    CODE_FOR_atomic_subsi = 2926,
  #define CODE_FOR_atomic_subdi CODE_FOR_nothing
    CODE_FOR_atomic_andqi = 2927,
    CODE_FOR_atomic_orqi = 2928,
    CODE_FOR_atomic_xorqi = 2929,
    CODE_FOR_atomic_andhi = 2930,
    CODE_FOR_atomic_orhi = 2931,
    CODE_FOR_atomic_xorhi = 2932,
    CODE_FOR_atomic_andsi = 2933,
    CODE_FOR_atomic_orsi = 2934,
    CODE_FOR_atomic_xorsi = 2935,
  #define CODE_FOR_atomic_anddi CODE_FOR_nothing
  #define CODE_FOR_atomic_ordi CODE_FOR_nothing
  #define CODE_FOR_atomic_xordi CODE_FOR_nothing
    CODE_FOR_cbranchqi4 = 2936,
    CODE_FOR_cbranchhi4 = 2937,
    CODE_FOR_cbranchsi4 = 2938,
    CODE_FOR_cbranchdi4 = 2939,
  #define CODE_FOR_cbranchti4 CODE_FOR_nothing
    CODE_FOR_cstoreqi4 = 2940,
    CODE_FOR_cstorehi4 = 2941,
    CODE_FOR_cstoresi4 = 2942,
  #define CODE_FOR_cstoredi4 CODE_FOR_nothing
    CODE_FOR_cmpsi_1 = 2943,
  #define CODE_FOR_cmpdi_1 CODE_FOR_nothing
    CODE_FOR_cmpqi_ext_3 = 2944,
    CODE_FOR_cbranchxf4 = 2945,
    CODE_FOR_cstorexf4 = 2946,
    CODE_FOR_cbranchsf4 = 2947,
    CODE_FOR_cbranchdf4 = 2948,
    CODE_FOR_cstoresf4 = 2949,
    CODE_FOR_cstoredf4 = 2950,
    CODE_FOR_cbranchcc4 = 2951,
    CODE_FOR_cstorecc4 = 2952,
    CODE_FOR_movxi = 2969,
  #define CODE_FOR_reload_noff_store CODE_FOR_nothing
  #define CODE_FOR_reload_noff_load CODE_FOR_nothing
    CODE_FOR_movoi = 2970,
    CODE_FOR_movti = 2971,
    CODE_FOR_movcdi = 2972,
    CODE_FOR_movqi = 2973,
    CODE_FOR_movhi = 2974,
    CODE_FOR_movsi = 2975,
    CODE_FOR_movdi = 2976,
    CODE_FOR_movstrictqi = 2979,
    CODE_FOR_movstricthi = 2980,
    CODE_FOR_movtf = 2991,
    CODE_FOR_movsf = 2992,
    CODE_FOR_movdf = 2993,
    CODE_FOR_movxf = 2994,
    CODE_FOR_zero_extendsidi2 = 3001,
    CODE_FOR_zero_extendqisi2 = 3005,
    CODE_FOR_zero_extendhisi2 = 3006,
    CODE_FOR_zero_extendqihi2 = 3009,
    CODE_FOR_extendsidi2 = 3011,
    CODE_FOR_extendsfdf2 = 3022,
    CODE_FOR_extendsfxf2 = 3025,
    CODE_FOR_extenddfxf2 = 3026,
    CODE_FOR_truncdfsf2 = 3027,
    CODE_FOR_truncdfsf2_with_temp = 3030,
    CODE_FOR_truncxfsf2 = 3032,
    CODE_FOR_truncxfdf2 = 3033,
    CODE_FOR_fix_truncxfdi2 = 3038,
    CODE_FOR_fix_truncsfdi2 = 3039,
    CODE_FOR_fix_truncdfdi2 = 3040,
    CODE_FOR_fix_truncxfsi2 = 3041,
    CODE_FOR_fix_truncsfsi2 = 3042,
    CODE_FOR_fix_truncdfsi2 = 3043,
    CODE_FOR_fix_truncsfhi2 = 3044,
    CODE_FOR_fix_truncdfhi2 = 3045,
    CODE_FOR_fix_truncxfhi2 = 3046,
    CODE_FOR_fixuns_truncsfsi2 = 3047,
    CODE_FOR_fixuns_truncdfsi2 = 3048,
    CODE_FOR_fixuns_truncsfhi2 = 3051,
    CODE_FOR_fixuns_truncdfhi2 = 3052,
    CODE_FOR_floatsisf2 = 3075,
  #define CODE_FOR_floatdisf2 CODE_FOR_nothing
    CODE_FOR_floatsidf2 = 3076,
  #define CODE_FOR_floatdidf2 CODE_FOR_nothing
    CODE_FOR_floatunsqisf2 = 3091,
    CODE_FOR_floatunshisf2 = 3092,
    CODE_FOR_floatunsqidf2 = 3093,
    CODE_FOR_floatunshidf2 = 3094,
    CODE_FOR_floatunssisf2 = 3098,
    CODE_FOR_floatunssidf2 = 3099,
    CODE_FOR_floatunssixf2 = 3100,
  #define CODE_FOR_floatunsdisf2 CODE_FOR_nothing
  #define CODE_FOR_floatunsdidf2 CODE_FOR_nothing
    CODE_FOR_addqi3 = 3103,
    CODE_FOR_addhi3 = 3104,
    CODE_FOR_addsi3 = 3105,
    CODE_FOR_adddi3 = 3106,
  #define CODE_FOR_addti3 CODE_FOR_nothing
    CODE_FOR_addvqi4 = 3114,
    CODE_FOR_addvhi4 = 3115,
    CODE_FOR_addvsi4 = 3116,
  #define CODE_FOR_addvdi4 CODE_FOR_nothing
    CODE_FOR_subqi3 = 3122,
    CODE_FOR_subhi3 = 3123,
    CODE_FOR_subsi3 = 3124,
    CODE_FOR_subdi3 = 3125,
  #define CODE_FOR_subti3 CODE_FOR_nothing
    CODE_FOR_subvqi4 = 3127,
    CODE_FOR_subvhi4 = 3128,
    CODE_FOR_subvsi4 = 3129,
  #define CODE_FOR_subvdi4 CODE_FOR_nothing
    CODE_FOR_addqi3_carry = 3130,
    CODE_FOR_subqi3_carry = 3131,
    CODE_FOR_addhi3_carry = 3132,
    CODE_FOR_subhi3_carry = 3133,
    CODE_FOR_addsi3_carry = 3134,
    CODE_FOR_subsi3_carry = 3135,
    CODE_FOR_adddi3_carry = 3136,
    CODE_FOR_subdi3_carry = 3137,
    CODE_FOR_addxf3 = 3138,
    CODE_FOR_subxf3 = 3139,
    CODE_FOR_addsf3 = 3140,
    CODE_FOR_subsf3 = 3141,
    CODE_FOR_adddf3 = 3142,
    CODE_FOR_subdf3 = 3143,
    CODE_FOR_mulhi3 = 3144,
    CODE_FOR_mulsi3 = 3145,
  #define CODE_FOR_muldi3 CODE_FOR_nothing
    CODE_FOR_mulqi3 = 3146,
    CODE_FOR_mulvsi4 = 3147,
  #define CODE_FOR_mulvdi4 CODE_FOR_nothing
    CODE_FOR_mulsidi3 = 3148,
    CODE_FOR_umulsidi3 = 3149,
  #define CODE_FOR_mulditi3 CODE_FOR_nothing
  #define CODE_FOR_umulditi3 CODE_FOR_nothing
    CODE_FOR_mulqihi3 = 3150,
    CODE_FOR_umulqihi3 = 3151,
    CODE_FOR_smulsi3_highpart = 3154,
    CODE_FOR_umulsi3_highpart = 3155,
  #define CODE_FOR_smuldi3_highpart CODE_FOR_nothing
  #define CODE_FOR_umuldi3_highpart CODE_FOR_nothing
    CODE_FOR_mulxf3 = 3156,
    CODE_FOR_mulsf3 = 3157,
    CODE_FOR_muldf3 = 3158,
    CODE_FOR_divxf3 = 3159,
    CODE_FOR_divdf3 = 3160,
    CODE_FOR_divsf3 = 3161,
    CODE_FOR_divmodhi4 = 3162,
    CODE_FOR_divmodsi4 = 3163,
  #define CODE_FOR_divmoddi4 CODE_FOR_nothing
    CODE_FOR_divmodqi4 = 3169,
    CODE_FOR_udivmodhi4 = 3170,
    CODE_FOR_udivmodsi4 = 3171,
  #define CODE_FOR_udivmoddi4 CODE_FOR_nothing
    CODE_FOR_udivmodqi4 = 3177,
    CODE_FOR_testsi_ccno_1 = 3178,
    CODE_FOR_testqi_ccz_1 = 3179,
  #define CODE_FOR_testdi_ccno_1 CODE_FOR_nothing
    CODE_FOR_testqi_ext_ccno_0 = 3180,
    CODE_FOR_andqi3 = 3190,
    CODE_FOR_andhi3 = 3191,
    CODE_FOR_andsi3 = 3192,
  #define CODE_FOR_anddi3 CODE_FOR_nothing
    CODE_FOR_iorqi3 = 3203,
    CODE_FOR_xorqi3 = 3204,
    CODE_FOR_iorhi3 = 3205,
    CODE_FOR_xorhi3 = 3206,
    CODE_FOR_iorsi3 = 3207,
    CODE_FOR_xorsi3 = 3208,
  #define CODE_FOR_iordi3 CODE_FOR_nothing
  #define CODE_FOR_xordi3 CODE_FOR_nothing
    CODE_FOR_xorqi_cc_ext_1 = 3215,
    CODE_FOR_negqi2 = 3216,
    CODE_FOR_neghi2 = 3217,
    CODE_FOR_negsi2 = 3218,
    CODE_FOR_negdi2 = 3219,
  #define CODE_FOR_negti2 CODE_FOR_nothing
    CODE_FOR_negvqi3 = 3221,
    CODE_FOR_negvhi3 = 3222,
    CODE_FOR_negvsi3 = 3223,
  #define CODE_FOR_negvdi3 CODE_FOR_nothing
    CODE_FOR_abssf2 = 3224,
    CODE_FOR_negsf2 = 3225,
    CODE_FOR_absdf2 = 3226,
    CODE_FOR_negdf2 = 3227,
    CODE_FOR_absxf2 = 3228,
    CODE_FOR_negxf2 = 3229,
    CODE_FOR_abstf2 = 3230,
    CODE_FOR_negtf2 = 3231,
    CODE_FOR_copysignsf3 = 3237,
    CODE_FOR_copysigndf3 = 3238,
    CODE_FOR_copysigntf3 = 3239,
    CODE_FOR_one_cmplqi2 = 3246,
    CODE_FOR_one_cmplhi2 = 3247,
    CODE_FOR_one_cmplsi2 = 3248,
  #define CODE_FOR_one_cmpldi2 CODE_FOR_nothing
    CODE_FOR_ashlqi3 = 3254,
    CODE_FOR_ashlhi3 = 3255,
    CODE_FOR_ashlsi3 = 3256,
    CODE_FOR_ashldi3 = 3257,
  #define CODE_FOR_ashlti3 CODE_FOR_nothing
    CODE_FOR_x86_shiftsi_adj_1 = 3260,
  #define CODE_FOR_x86_shiftdi_adj_1 CODE_FOR_nothing
    CODE_FOR_x86_shiftsi_adj_2 = 3261,
  #define CODE_FOR_x86_shiftdi_adj_2 CODE_FOR_nothing
    CODE_FOR_lshrqi3 = 3264,
    CODE_FOR_ashrqi3 = 3265,
    CODE_FOR_lshrhi3 = 3266,
    CODE_FOR_ashrhi3 = 3267,
    CODE_FOR_lshrsi3 = 3268,
    CODE_FOR_ashrsi3 = 3269,
    CODE_FOR_lshrdi3 = 3270,
    CODE_FOR_ashrdi3 = 3271,
  #define CODE_FOR_lshrti3 CODE_FOR_nothing
  #define CODE_FOR_ashrti3 CODE_FOR_nothing
    CODE_FOR_x86_shiftsi_adj_3 = 3276,
  #define CODE_FOR_x86_shiftdi_adj_3 CODE_FOR_nothing
  #define CODE_FOR_rotlti3 CODE_FOR_nothing
  #define CODE_FOR_rotrti3 CODE_FOR_nothing
    CODE_FOR_rotldi3 = 3279,
    CODE_FOR_rotrdi3 = 3280,
    CODE_FOR_rotlqi3 = 3281,
    CODE_FOR_rotrqi3 = 3282,
    CODE_FOR_rotlhi3 = 3283,
    CODE_FOR_rotrhi3 = 3284,
    CODE_FOR_rotlsi3 = 3285,
    CODE_FOR_rotrsi3 = 3286,
    CODE_FOR_extv = 3293,
    CODE_FOR_extzv = 3294,
    CODE_FOR_insv = 3295,
    CODE_FOR_indirect_jump = 3324,
    CODE_FOR_tablejump = 3325,
    CODE_FOR_call = 3330,
    CODE_FOR_sibcall = 3331,
    CODE_FOR_call_pop = 3332,
    CODE_FOR_call_value = 3333,
    CODE_FOR_sibcall_value = 3334,
    CODE_FOR_call_value_pop = 3335,
    CODE_FOR_untyped_call = 3336,
    CODE_FOR_memory_blockage = 3337,
    CODE_FOR_return = 3338,
    CODE_FOR_simple_return = 3339,
    CODE_FOR_prologue = 3340,
    CODE_FOR_epilogue = 3341,
    CODE_FOR_sibcall_epilogue = 3342,
    CODE_FOR_eh_return = 3343,
    CODE_FOR_split_stack_prologue = 3345,
    CODE_FOR_split_stack_space_check = 3346,
    CODE_FOR_ffssi2 = 3347,
  #define CODE_FOR_ffsdi2 CODE_FOR_nothing
    CODE_FOR_clzhi2 = 3349,
    CODE_FOR_clzsi2 = 3350,
  #define CODE_FOR_clzdi2 CODE_FOR_nothing
  #define CODE_FOR_bswapdi2 CODE_FOR_nothing
    CODE_FOR_bswapsi2 = 3351,
    CODE_FOR_paritydi2 = 3352,
    CODE_FOR_paritysi2 = 3353,
    CODE_FOR_tls_global_dynamic_32 = 3356,
  #define CODE_FOR_tls_global_dynamic_64_si CODE_FOR_nothing
  #define CODE_FOR_tls_global_dynamic_64_di CODE_FOR_nothing
    CODE_FOR_tls_local_dynamic_base_32 = 3357,
  #define CODE_FOR_tls_local_dynamic_base_64_si CODE_FOR_nothing
  #define CODE_FOR_tls_local_dynamic_base_64_di CODE_FOR_nothing
    CODE_FOR_tls_dynamic_gnu2_32 = 3359,
  #define CODE_FOR_tls_dynamic_gnu2_64 CODE_FOR_nothing
    CODE_FOR_rsqrtsf2 = 3362,
    CODE_FOR_sqrtsf2 = 3363,
    CODE_FOR_sqrtdf2 = 3364,
    CODE_FOR_fmodxf3 = 3365,
    CODE_FOR_fmodsf3 = 3366,
    CODE_FOR_fmoddf3 = 3367,
    CODE_FOR_remainderxf3 = 3368,
    CODE_FOR_remaindersf3 = 3369,
    CODE_FOR_remainderdf3 = 3370,
    CODE_FOR_sincossf3 = 3377,
    CODE_FOR_sincosdf3 = 3378,
    CODE_FOR_tanxf2 = 3379,
    CODE_FOR_tansf2 = 3380,
    CODE_FOR_tandf2 = 3381,
    CODE_FOR_atan2xf3 = 3382,
    CODE_FOR_atan2sf3 = 3383,
    CODE_FOR_atan2df3 = 3384,
    CODE_FOR_atanxf2 = 3385,
    CODE_FOR_atansf2 = 3386,
    CODE_FOR_atandf2 = 3387,
    CODE_FOR_asinxf2 = 3388,
    CODE_FOR_asinsf2 = 3389,
    CODE_FOR_asindf2 = 3390,
    CODE_FOR_acosxf2 = 3391,
    CODE_FOR_acossf2 = 3392,
    CODE_FOR_acosdf2 = 3393,
    CODE_FOR_logxf2 = 3394,
    CODE_FOR_logsf2 = 3395,
    CODE_FOR_logdf2 = 3396,
    CODE_FOR_log10xf2 = 3397,
    CODE_FOR_log10sf2 = 3398,
    CODE_FOR_log10df2 = 3399,
    CODE_FOR_log2xf2 = 3400,
    CODE_FOR_log2sf2 = 3401,
    CODE_FOR_log2df2 = 3402,
    CODE_FOR_log1pxf2 = 3403,
    CODE_FOR_log1psf2 = 3404,
    CODE_FOR_log1pdf2 = 3405,
    CODE_FOR_logbxf2 = 3406,
    CODE_FOR_logbsf2 = 3407,
    CODE_FOR_logbdf2 = 3408,
    CODE_FOR_ilogbxf2 = 3409,
    CODE_FOR_ilogbsf2 = 3410,
    CODE_FOR_ilogbdf2 = 3411,
    CODE_FOR_expNcorexf3 = 3412,
    CODE_FOR_expxf2 = 3413,
    CODE_FOR_expsf2 = 3414,
    CODE_FOR_expdf2 = 3415,
    CODE_FOR_exp10xf2 = 3416,
    CODE_FOR_exp10sf2 = 3417,
    CODE_FOR_exp10df2 = 3418,
    CODE_FOR_exp2xf2 = 3419,
    CODE_FOR_exp2sf2 = 3420,
    CODE_FOR_exp2df2 = 3421,
    CODE_FOR_expm1xf2 = 3422,
    CODE_FOR_expm1sf2 = 3423,
    CODE_FOR_expm1df2 = 3424,
    CODE_FOR_ldexpxf3 = 3425,
    CODE_FOR_ldexpsf3 = 3426,
    CODE_FOR_ldexpdf3 = 3427,
    CODE_FOR_scalbxf3 = 3428,
    CODE_FOR_scalbsf3 = 3429,
    CODE_FOR_scalbdf3 = 3430,
    CODE_FOR_significandxf2 = 3431,
    CODE_FOR_significandsf2 = 3432,
    CODE_FOR_significanddf2 = 3433,
    CODE_FOR_rintsf2 = 3434,
    CODE_FOR_rintdf2 = 3435,
    CODE_FOR_roundsf2 = 3436,
    CODE_FOR_rounddf2 = 3437,
    CODE_FOR_roundxf2 = 3438,
    CODE_FOR_lrintxfhi2 = 3448,
    CODE_FOR_lrintxfsi2 = 3449,
    CODE_FOR_lrintxfdi2 = 3450,
    CODE_FOR_lrintsfsi2 = 3451,
  #define CODE_FOR_lrintsfdi2 CODE_FOR_nothing
    CODE_FOR_lrintdfsi2 = 3452,
  #define CODE_FOR_lrintdfdi2 CODE_FOR_nothing
    CODE_FOR_lroundsfhi2 = 3453,
    CODE_FOR_lrounddfhi2 = 3454,
    CODE_FOR_lroundxfhi2 = 3455,
    CODE_FOR_lroundsfsi2 = 3456,
    CODE_FOR_lrounddfsi2 = 3457,
    CODE_FOR_lroundxfsi2 = 3458,
    CODE_FOR_lroundsfdi2 = 3459,
    CODE_FOR_lrounddfdi2 = 3460,
    CODE_FOR_lroundxfdi2 = 3461,
    CODE_FOR_floorxf2 = 3465,
    CODE_FOR_ceilxf2 = 3466,
    CODE_FOR_btruncxf2 = 3467,
    CODE_FOR_floorsf2 = 3468,
    CODE_FOR_ceilsf2 = 3469,
    CODE_FOR_btruncsf2 = 3470,
    CODE_FOR_floordf2 = 3471,
    CODE_FOR_ceildf2 = 3472,
    CODE_FOR_btruncdf2 = 3473,
    CODE_FOR_nearbyintxf2 = 3475,
    CODE_FOR_nearbyintsf2 = 3476,
    CODE_FOR_nearbyintdf2 = 3477,
    CODE_FOR_lfloorxfhi2 = 3496,
    CODE_FOR_lceilxfhi2 = 3497,
    CODE_FOR_lfloorxfsi2 = 3498,
    CODE_FOR_lceilxfsi2 = 3499,
    CODE_FOR_lfloorxfdi2 = 3500,
    CODE_FOR_lceilxfdi2 = 3501,
    CODE_FOR_lfloorsfsi2 = 3502,
    CODE_FOR_lceilsfsi2 = 3503,
  #define CODE_FOR_lfloorsfdi2 CODE_FOR_nothing
  #define CODE_FOR_lceilsfdi2 CODE_FOR_nothing
    CODE_FOR_lfloordfsi2 = 3504,
    CODE_FOR_lceildfsi2 = 3505,
  #define CODE_FOR_lfloordfdi2 CODE_FOR_nothing
  #define CODE_FOR_lceildfdi2 CODE_FOR_nothing
    CODE_FOR_isinfxf2 = 3508,
    CODE_FOR_isinfsf2 = 3509,
    CODE_FOR_isinfdf2 = 3510,
    CODE_FOR_signbitxf2 = 3511,
    CODE_FOR_signbitdf2 = 3512,
    CODE_FOR_signbitsf2 = 3513,
    CODE_FOR_movmemsi = 3514,
  #define CODE_FOR_movmemdi CODE_FOR_nothing
    CODE_FOR_strmov = 3515,
    CODE_FOR_strmov_singleop = 3516,
    CODE_FOR_rep_mov = 3517,
    CODE_FOR_setmemsi = 3518,
  #define CODE_FOR_setmemdi CODE_FOR_nothing
    CODE_FOR_strset = 3519,
    CODE_FOR_strset_singleop = 3520,
    CODE_FOR_rep_stos = 3521,
    CODE_FOR_cmpstrnsi = 3522,
    CODE_FOR_cmpintqi = 3523,
    CODE_FOR_cmpstrnqi_nz_1 = 3524,
    CODE_FOR_cmpstrnqi_1 = 3525,
    CODE_FOR_strlensi = 3526,
    CODE_FOR_strlendi = 3527,
    CODE_FOR_strlenqi_1 = 3528,
    CODE_FOR_movqicc = 3531,
    CODE_FOR_movhicc = 3532,
    CODE_FOR_movsicc = 3533,
  #define CODE_FOR_movdicc CODE_FOR_nothing
    CODE_FOR_x86_movsicc_0_m1 = 3534,
  #define CODE_FOR_x86_movdicc_0_m1 CODE_FOR_nothing
    CODE_FOR_movsfcc = 3546,
    CODE_FOR_movdfcc = 3547,
    CODE_FOR_movxfcc = 3548,
    CODE_FOR_addqicc = 3555,
    CODE_FOR_addhicc = 3556,
    CODE_FOR_addsicc = 3557,
  #define CODE_FOR_adddicc CODE_FOR_nothing
    CODE_FOR_allocate_stack = 3558,
    CODE_FOR_probe_stack = 3559,
    CODE_FOR_builtin_setjmp_receiver = 3560,
    CODE_FOR_prefetch = 3663,
    CODE_FOR_stack_protect_set = 3664,
    CODE_FOR_stack_protect_test = 3665,
    CODE_FOR_lwp_llwpcb = 3666,
    CODE_FOR_lwp_slwpcb = 3667,
    CODE_FOR_lwp_lwpvalsi3 = 3668,
  #define CODE_FOR_lwp_lwpvaldi3 CODE_FOR_nothing
    CODE_FOR_lwp_lwpinssi3 = 3669,
  #define CODE_FOR_lwp_lwpinsdi3 CODE_FOR_nothing
    CODE_FOR_pause = 3670,
    CODE_FOR_xbegin = 3671,
    CODE_FOR_xtest = 3672,
    CODE_FOR_movv8qi = 3673,
    CODE_FOR_movv4hi = 3674,
    CODE_FOR_movv2si = 3675,
    CODE_FOR_movv1di = 3676,
    CODE_FOR_movv2sf = 3677,
    CODE_FOR_movmisalignv8qi = 3683,
    CODE_FOR_movmisalignv4hi = 3684,
    CODE_FOR_movmisalignv2si = 3685,
    CODE_FOR_movmisalignv1di = 3686,
    CODE_FOR_movmisalignv2sf = 3687,
    CODE_FOR_mmx_addv2sf3 = 3688,
    CODE_FOR_mmx_subv2sf3 = 3689,
    CODE_FOR_mmx_subrv2sf3 = 3690,
    CODE_FOR_mmx_mulv2sf3 = 3691,
    CODE_FOR_mmx_smaxv2sf3 = 3692,
    CODE_FOR_mmx_sminv2sf3 = 3693,
    CODE_FOR_mmx_eqv2sf3 = 3694,
    CODE_FOR_vec_setv2sf = 3695,
    CODE_FOR_vec_extractv2sf = 3698,
    CODE_FOR_vec_initv2sf = 3699,
    CODE_FOR_mmx_addv8qi3 = 3700,
    CODE_FOR_mmx_subv8qi3 = 3701,
    CODE_FOR_mmx_addv4hi3 = 3702,
    CODE_FOR_mmx_subv4hi3 = 3703,
    CODE_FOR_mmx_addv2si3 = 3704,
    CODE_FOR_mmx_subv2si3 = 3705,
    CODE_FOR_mmx_addv1di3 = 3706,
    CODE_FOR_mmx_subv1di3 = 3707,
    CODE_FOR_mmx_ssaddv8qi3 = 3708,
    CODE_FOR_mmx_usaddv8qi3 = 3709,
    CODE_FOR_mmx_sssubv8qi3 = 3710,
    CODE_FOR_mmx_ussubv8qi3 = 3711,
    CODE_FOR_mmx_ssaddv4hi3 = 3712,
    CODE_FOR_mmx_usaddv4hi3 = 3713,
    CODE_FOR_mmx_sssubv4hi3 = 3714,
    CODE_FOR_mmx_ussubv4hi3 = 3715,
    CODE_FOR_mmx_mulv4hi3 = 3716,
    CODE_FOR_mmx_smulv4hi3_highpart = 3717,
    CODE_FOR_mmx_umulv4hi3_highpart = 3718,
    CODE_FOR_mmx_pmaddwd = 3719,
    CODE_FOR_mmx_pmulhrwv4hi3 = 3720,
    CODE_FOR_sse2_umulv1siv1di3 = 3721,
    CODE_FOR_mmx_smaxv4hi3 = 3722,
    CODE_FOR_mmx_sminv4hi3 = 3723,
    CODE_FOR_mmx_umaxv8qi3 = 3724,
    CODE_FOR_mmx_uminv8qi3 = 3725,
    CODE_FOR_mmx_eqv8qi3 = 3726,
    CODE_FOR_mmx_eqv4hi3 = 3727,
    CODE_FOR_mmx_eqv2si3 = 3728,
    CODE_FOR_mmx_andv8qi3 = 3729,
    CODE_FOR_mmx_iorv8qi3 = 3730,
    CODE_FOR_mmx_xorv8qi3 = 3731,
    CODE_FOR_mmx_andv4hi3 = 3732,
    CODE_FOR_mmx_iorv4hi3 = 3733,
    CODE_FOR_mmx_xorv4hi3 = 3734,
    CODE_FOR_mmx_andv2si3 = 3735,
    CODE_FOR_mmx_iorv2si3 = 3736,
    CODE_FOR_mmx_xorv2si3 = 3737,
    CODE_FOR_mmx_pinsrw = 3738,
    CODE_FOR_mmx_pshufw = 3739,
    CODE_FOR_vec_setv2si = 3740,
    CODE_FOR_vec_extractv2si = 3743,
    CODE_FOR_vec_initv2si = 3744,
    CODE_FOR_vec_setv4hi = 3745,
    CODE_FOR_vec_extractv4hi = 3746,
    CODE_FOR_vec_initv4hi = 3747,
    CODE_FOR_vec_setv8qi = 3748,
    CODE_FOR_vec_extractv8qi = 3749,
    CODE_FOR_vec_initv8qi = 3750,
    CODE_FOR_mmx_uavgv8qi3 = 3751,
    CODE_FOR_mmx_uavgv4hi3 = 3752,
    CODE_FOR_mmx_maskmovq = 3753,
    CODE_FOR_mmx_emms = 3754,
    CODE_FOR_mmx_femms = 3755,
    CODE_FOR_movv64qi = 3756,
    CODE_FOR_movv32qi = 3757,
    CODE_FOR_movv16qi = 3758,
    CODE_FOR_movv32hi = 3759,
    CODE_FOR_movv16hi = 3760,
    CODE_FOR_movv8hi = 3761,
    CODE_FOR_movv16si = 3762,
    CODE_FOR_movv8si = 3763,
    CODE_FOR_movv4si = 3764,
    CODE_FOR_movv8di = 3765,
    CODE_FOR_movv4di = 3766,
    CODE_FOR_movv2di = 3767,
    CODE_FOR_movv2ti = 3768,
    CODE_FOR_movv1ti = 3769,
    CODE_FOR_movv16sf = 3770,
    CODE_FOR_movv8sf = 3771,
    CODE_FOR_movv4sf = 3772,
    CODE_FOR_movv8df = 3773,
    CODE_FOR_movv4df = 3774,
    CODE_FOR_movv2df = 3775,
    CODE_FOR_movmisalignv64qi = 3779,
    CODE_FOR_movmisalignv32qi = 3780,
    CODE_FOR_movmisalignv16qi = 3781,
    CODE_FOR_movmisalignv32hi = 3782,
    CODE_FOR_movmisalignv16hi = 3783,
    CODE_FOR_movmisalignv8hi = 3784,
    CODE_FOR_movmisalignv16si = 3785,
    CODE_FOR_movmisalignv8si = 3786,
    CODE_FOR_movmisalignv4si = 3787,
    CODE_FOR_movmisalignv8di = 3788,
    CODE_FOR_movmisalignv4di = 3789,
    CODE_FOR_movmisalignv2di = 3790,
    CODE_FOR_movmisalignv2ti = 3791,
    CODE_FOR_movmisalignv1ti = 3792,
    CODE_FOR_movmisalignv16sf = 3793,
    CODE_FOR_movmisalignv8sf = 3794,
    CODE_FOR_movmisalignv4sf = 3795,
    CODE_FOR_movmisalignv8df = 3796,
    CODE_FOR_movmisalignv4df = 3797,
    CODE_FOR_movmisalignv2df = 3798,
    CODE_FOR_avx512f_loadups512 = 3799,
    CODE_FOR_avx512f_loadups512_mask = 3800,
    CODE_FOR_avx_loadups256 = 3801,
  #define CODE_FOR_avx_loadups256_mask CODE_FOR_nothing
    CODE_FOR_sse_loadups = 3802,
  #define CODE_FOR_sse_loadups_mask CODE_FOR_nothing
    CODE_FOR_avx512f_loadupd512 = 3803,
    CODE_FOR_avx512f_loadupd512_mask = 3804,
    CODE_FOR_avx_loadupd256 = 3805,
  #define CODE_FOR_avx_loadupd256_mask CODE_FOR_nothing
    CODE_FOR_sse2_loadupd = 3806,
  #define CODE_FOR_sse2_loadupd_mask CODE_FOR_nothing
    CODE_FOR_avx_loaddquv32qi = 3807,
    CODE_FOR_sse2_loaddquv16qi = 3808,
  #define CODE_FOR_sse2_loaddquv16qi_mask CODE_FOR_nothing
    CODE_FOR_avx512f_loaddquv16si = 3809,
    CODE_FOR_avx512f_loaddquv16si_mask = 3810,
    CODE_FOR_avx512f_loaddquv8di = 3811,
    CODE_FOR_avx512f_loaddquv8di_mask = 3812,
  #define CODE_FOR_storentdi CODE_FOR_nothing
    CODE_FOR_storentsi = 3813,
    CODE_FOR_storentsf = 3814,
    CODE_FOR_storentdf = 3815,
    CODE_FOR_storentv8di = 3816,
    CODE_FOR_storentv4di = 3817,
    CODE_FOR_storentv2di = 3818,
    CODE_FOR_storentv16sf = 3819,
    CODE_FOR_storentv8sf = 3820,
    CODE_FOR_storentv4sf = 3821,
    CODE_FOR_storentv8df = 3822,
    CODE_FOR_storentv4df = 3823,
    CODE_FOR_storentv2df = 3824,
    CODE_FOR_absv16sf2 = 3825,
    CODE_FOR_negv16sf2 = 3826,
    CODE_FOR_absv8sf2 = 3827,
    CODE_FOR_negv8sf2 = 3828,
    CODE_FOR_absv4sf2 = 3829,
    CODE_FOR_negv4sf2 = 3830,
    CODE_FOR_absv8df2 = 3831,
    CODE_FOR_negv8df2 = 3832,
    CODE_FOR_absv4df2 = 3833,
    CODE_FOR_negv4df2 = 3834,
    CODE_FOR_absv2df2 = 3835,
    CODE_FOR_negv2df2 = 3836,
    CODE_FOR_addv16sf3 = 3843,
    CODE_FOR_addv16sf3_round = 3844,
    CODE_FOR_addv16sf3_mask = 3845,
    CODE_FOR_addv16sf3_mask_round = 3846,
    CODE_FOR_subv16sf3 = 3847,
    CODE_FOR_subv16sf3_round = 3848,
    CODE_FOR_subv16sf3_mask = 3849,
    CODE_FOR_subv16sf3_mask_round = 3850,
    CODE_FOR_addv8sf3 = 3851,
  #define CODE_FOR_addv8sf3_round CODE_FOR_nothing
  #define CODE_FOR_addv8sf3_mask CODE_FOR_nothing
  #define CODE_FOR_addv8sf3_mask_round CODE_FOR_nothing
    CODE_FOR_subv8sf3 = 3852,
  #define CODE_FOR_subv8sf3_round CODE_FOR_nothing
  #define CODE_FOR_subv8sf3_mask CODE_FOR_nothing
  #define CODE_FOR_subv8sf3_mask_round CODE_FOR_nothing
    CODE_FOR_addv4sf3 = 3853,
  #define CODE_FOR_addv4sf3_round CODE_FOR_nothing
  #define CODE_FOR_addv4sf3_mask CODE_FOR_nothing
  #define CODE_FOR_addv4sf3_mask_round CODE_FOR_nothing
    CODE_FOR_subv4sf3 = 3854,
  #define CODE_FOR_subv4sf3_round CODE_FOR_nothing
  #define CODE_FOR_subv4sf3_mask CODE_FOR_nothing
  #define CODE_FOR_subv4sf3_mask_round CODE_FOR_nothing
    CODE_FOR_addv8df3 = 3855,
    CODE_FOR_addv8df3_round = 3856,
    CODE_FOR_addv8df3_mask = 3857,
    CODE_FOR_addv8df3_mask_round = 3858,
    CODE_FOR_subv8df3 = 3859,
    CODE_FOR_subv8df3_round = 3860,
    CODE_FOR_subv8df3_mask = 3861,
    CODE_FOR_subv8df3_mask_round = 3862,
    CODE_FOR_addv4df3 = 3863,
  #define CODE_FOR_addv4df3_round CODE_FOR_nothing
  #define CODE_FOR_addv4df3_mask CODE_FOR_nothing
  #define CODE_FOR_addv4df3_mask_round CODE_FOR_nothing
    CODE_FOR_subv4df3 = 3864,
  #define CODE_FOR_subv4df3_round CODE_FOR_nothing
  #define CODE_FOR_subv4df3_mask CODE_FOR_nothing
  #define CODE_FOR_subv4df3_mask_round CODE_FOR_nothing
    CODE_FOR_addv2df3 = 3865,
  #define CODE_FOR_addv2df3_round CODE_FOR_nothing
  #define CODE_FOR_addv2df3_mask CODE_FOR_nothing
  #define CODE_FOR_addv2df3_mask_round CODE_FOR_nothing
    CODE_FOR_subv2df3 = 3866,
  #define CODE_FOR_subv2df3_round CODE_FOR_nothing
  #define CODE_FOR_subv2df3_mask CODE_FOR_nothing
  #define CODE_FOR_subv2df3_mask_round CODE_FOR_nothing
    CODE_FOR_mulv16sf3 = 3867,
    CODE_FOR_mulv16sf3_round = 3868,
    CODE_FOR_mulv16sf3_mask = 3869,
    CODE_FOR_mulv16sf3_mask_round = 3870,
    CODE_FOR_mulv8sf3 = 3871,
  #define CODE_FOR_mulv8sf3_round CODE_FOR_nothing
  #define CODE_FOR_mulv8sf3_mask CODE_FOR_nothing
  #define CODE_FOR_mulv8sf3_mask_round CODE_FOR_nothing
    CODE_FOR_mulv4sf3 = 3872,
  #define CODE_FOR_mulv4sf3_round CODE_FOR_nothing
  #define CODE_FOR_mulv4sf3_mask CODE_FOR_nothing
  #define CODE_FOR_mulv4sf3_mask_round CODE_FOR_nothing
    CODE_FOR_mulv8df3 = 3873,
    CODE_FOR_mulv8df3_round = 3874,
    CODE_FOR_mulv8df3_mask = 3875,
    CODE_FOR_mulv8df3_mask_round = 3876,
    CODE_FOR_mulv4df3 = 3877,
  #define CODE_FOR_mulv4df3_round CODE_FOR_nothing
  #define CODE_FOR_mulv4df3_mask CODE_FOR_nothing
  #define CODE_FOR_mulv4df3_mask_round CODE_FOR_nothing
    CODE_FOR_mulv2df3 = 3878,
  #define CODE_FOR_mulv2df3_round CODE_FOR_nothing
  #define CODE_FOR_mulv2df3_mask CODE_FOR_nothing
  #define CODE_FOR_mulv2df3_mask_round CODE_FOR_nothing
    CODE_FOR_divv8df3 = 3879,
    CODE_FOR_divv4df3 = 3880,
    CODE_FOR_divv2df3 = 3881,
    CODE_FOR_divv16sf3 = 3882,
    CODE_FOR_divv8sf3 = 3883,
    CODE_FOR_divv4sf3 = 3884,
    CODE_FOR_sqrtv8df2 = 3885,
    CODE_FOR_sqrtv4df2 = 3886,
    CODE_FOR_sqrtv2df2 = 3887,
    CODE_FOR_sqrtv16sf2 = 3888,
    CODE_FOR_sqrtv8sf2 = 3889,
    CODE_FOR_sqrtv4sf2 = 3890,
    CODE_FOR_rsqrtv8sf2 = 3891,
    CODE_FOR_rsqrtv4sf2 = 3892,
    CODE_FOR_smaxv16sf3 = 3893,
    CODE_FOR_smaxv16sf3_round = 3894,
    CODE_FOR_smaxv16sf3_mask = 3895,
    CODE_FOR_smaxv16sf3_mask_round = 3896,
    CODE_FOR_sminv16sf3 = 3897,
    CODE_FOR_sminv16sf3_round = 3898,
    CODE_FOR_sminv16sf3_mask = 3899,
    CODE_FOR_sminv16sf3_mask_round = 3900,
    CODE_FOR_smaxv8sf3 = 3901,
  #define CODE_FOR_smaxv8sf3_round CODE_FOR_nothing
  #define CODE_FOR_smaxv8sf3_mask CODE_FOR_nothing
  #define CODE_FOR_smaxv8sf3_mask_round CODE_FOR_nothing
    CODE_FOR_sminv8sf3 = 3902,
  #define CODE_FOR_sminv8sf3_round CODE_FOR_nothing
  #define CODE_FOR_sminv8sf3_mask CODE_FOR_nothing
  #define CODE_FOR_sminv8sf3_mask_round CODE_FOR_nothing
    CODE_FOR_smaxv4sf3 = 3903,
  #define CODE_FOR_smaxv4sf3_round CODE_FOR_nothing
  #define CODE_FOR_smaxv4sf3_mask CODE_FOR_nothing
  #define CODE_FOR_smaxv4sf3_mask_round CODE_FOR_nothing
    CODE_FOR_sminv4sf3 = 3904,
  #define CODE_FOR_sminv4sf3_round CODE_FOR_nothing
  #define CODE_FOR_sminv4sf3_mask CODE_FOR_nothing
  #define CODE_FOR_sminv4sf3_mask_round CODE_FOR_nothing
    CODE_FOR_smaxv8df3 = 3905,
    CODE_FOR_smaxv8df3_round = 3906,
    CODE_FOR_smaxv8df3_mask = 3907,
    CODE_FOR_smaxv8df3_mask_round = 3908,
    CODE_FOR_sminv8df3 = 3909,
    CODE_FOR_sminv8df3_round = 3910,
    CODE_FOR_sminv8df3_mask = 3911,
    CODE_FOR_sminv8df3_mask_round = 3912,
    CODE_FOR_smaxv4df3 = 3913,
  #define CODE_FOR_smaxv4df3_round CODE_FOR_nothing
  #define CODE_FOR_smaxv4df3_mask CODE_FOR_nothing
  #define CODE_FOR_smaxv4df3_mask_round CODE_FOR_nothing
    CODE_FOR_sminv4df3 = 3914,
  #define CODE_FOR_sminv4df3_round CODE_FOR_nothing
  #define CODE_FOR_sminv4df3_mask CODE_FOR_nothing
  #define CODE_FOR_sminv4df3_mask_round CODE_FOR_nothing
    CODE_FOR_smaxv2df3 = 3915,
  #define CODE_FOR_smaxv2df3_round CODE_FOR_nothing
  #define CODE_FOR_smaxv2df3_mask CODE_FOR_nothing
  #define CODE_FOR_smaxv2df3_mask_round CODE_FOR_nothing
    CODE_FOR_sminv2df3 = 3916,
  #define CODE_FOR_sminv2df3_round CODE_FOR_nothing
  #define CODE_FOR_sminv2df3_mask CODE_FOR_nothing
  #define CODE_FOR_sminv2df3_mask_round CODE_FOR_nothing
    CODE_FOR_sse3_haddv2df3 = 3917,
    CODE_FOR_reduc_splus_v8df = 3918,
    CODE_FOR_reduc_splus_v4df = 3919,
    CODE_FOR_reduc_splus_v2df = 3920,
    CODE_FOR_reduc_splus_v16sf = 3921,
    CODE_FOR_reduc_splus_v8sf = 3922,
    CODE_FOR_reduc_splus_v4sf = 3923,
    CODE_FOR_reduc_smax_v32qi = 3924,
    CODE_FOR_reduc_smin_v32qi = 3925,
    CODE_FOR_reduc_smax_v16hi = 3926,
    CODE_FOR_reduc_smin_v16hi = 3927,
    CODE_FOR_reduc_smax_v8si = 3928,
    CODE_FOR_reduc_smin_v8si = 3929,
    CODE_FOR_reduc_smax_v4di = 3930,
    CODE_FOR_reduc_smin_v4di = 3931,
    CODE_FOR_reduc_smax_v8sf = 3932,
    CODE_FOR_reduc_smin_v8sf = 3933,
    CODE_FOR_reduc_smax_v4df = 3934,
    CODE_FOR_reduc_smin_v4df = 3935,
    CODE_FOR_reduc_smax_v4sf = 3936,
    CODE_FOR_reduc_smin_v4sf = 3937,
    CODE_FOR_reduc_smax_v16si = 3938,
    CODE_FOR_reduc_smin_v16si = 3939,
    CODE_FOR_reduc_smax_v8di = 3940,
    CODE_FOR_reduc_smin_v8di = 3941,
    CODE_FOR_reduc_smax_v16sf = 3942,
    CODE_FOR_reduc_smin_v16sf = 3943,
    CODE_FOR_reduc_smax_v8df = 3944,
    CODE_FOR_reduc_smin_v8df = 3945,
    CODE_FOR_reduc_umax_v16si = 3946,
    CODE_FOR_reduc_umin_v16si = 3947,
    CODE_FOR_reduc_umax_v8di = 3948,
    CODE_FOR_reduc_umin_v8di = 3949,
    CODE_FOR_reduc_umax_v32qi = 3950,
    CODE_FOR_reduc_umin_v32qi = 3951,
    CODE_FOR_reduc_umax_v16hi = 3952,
    CODE_FOR_reduc_umin_v16hi = 3953,
    CODE_FOR_reduc_umax_v8si = 3954,
    CODE_FOR_reduc_umin_v8si = 3955,
    CODE_FOR_reduc_umax_v4di = 3956,
    CODE_FOR_reduc_umin_v4di = 3957,
    CODE_FOR_reduc_umin_v8hi = 3958,
    CODE_FOR_vcondv64qiv16sf = 3959,
    CODE_FOR_vcondv32hiv16sf = 3960,
    CODE_FOR_vcondv16siv16sf = 3961,
    CODE_FOR_vcondv8div16sf = 3962,
    CODE_FOR_vcondv16sfv16sf = 3963,
    CODE_FOR_vcondv8dfv16sf = 3964,
    CODE_FOR_vcondv64qiv8df = 3965,
    CODE_FOR_vcondv32hiv8df = 3966,
    CODE_FOR_vcondv16siv8df = 3967,
    CODE_FOR_vcondv8div8df = 3968,
    CODE_FOR_vcondv16sfv8df = 3969,
    CODE_FOR_vcondv8dfv8df = 3970,
    CODE_FOR_vcondv32qiv8sf = 3971,
    CODE_FOR_vcondv32qiv4df = 3972,
    CODE_FOR_vcondv16hiv8sf = 3973,
    CODE_FOR_vcondv16hiv4df = 3974,
    CODE_FOR_vcondv8siv8sf = 3975,
    CODE_FOR_vcondv8siv4df = 3976,
    CODE_FOR_vcondv4div8sf = 3977,
    CODE_FOR_vcondv4div4df = 3978,
    CODE_FOR_vcondv8sfv8sf = 3979,
    CODE_FOR_vcondv8sfv4df = 3980,
    CODE_FOR_vcondv4dfv8sf = 3981,
    CODE_FOR_vcondv4dfv4df = 3982,
    CODE_FOR_vcondv16qiv4sf = 3983,
    CODE_FOR_vcondv16qiv2df = 3984,
    CODE_FOR_vcondv8hiv4sf = 3985,
    CODE_FOR_vcondv8hiv2df = 3986,
    CODE_FOR_vcondv4siv4sf = 3987,
    CODE_FOR_vcondv4siv2df = 3988,
    CODE_FOR_vcondv2div4sf = 3989,
    CODE_FOR_vcondv2div2df = 3990,
    CODE_FOR_vcondv4sfv4sf = 3991,
    CODE_FOR_vcondv4sfv2df = 3992,
    CODE_FOR_vcondv2dfv4sf = 3993,
    CODE_FOR_vcondv2dfv2df = 3994,
    CODE_FOR_andv8sf3 = 3995,
    CODE_FOR_iorv8sf3 = 3996,
    CODE_FOR_xorv8sf3 = 3997,
    CODE_FOR_andv4sf3 = 3998,
    CODE_FOR_iorv4sf3 = 3999,
    CODE_FOR_xorv4sf3 = 4000,
    CODE_FOR_andv4df3 = 4001,
    CODE_FOR_iorv4df3 = 4002,
    CODE_FOR_xorv4df3 = 4003,
    CODE_FOR_andv2df3 = 4004,
    CODE_FOR_iorv2df3 = 4005,
    CODE_FOR_xorv2df3 = 4006,
    CODE_FOR_andv16sf3 = 4007,
    CODE_FOR_xorv16sf3 = 4008,
    CODE_FOR_andv8df3 = 4009,
    CODE_FOR_xorv8df3 = 4010,
    CODE_FOR_copysignv16sf3 = 4011,
    CODE_FOR_copysignv8sf3 = 4012,
    CODE_FOR_copysignv4sf3 = 4013,
    CODE_FOR_copysignv8df3 = 4014,
    CODE_FOR_copysignv4df3 = 4015,
    CODE_FOR_copysignv2df3 = 4016,
    CODE_FOR_andtf3 = 4017,
    CODE_FOR_iortf3 = 4018,
    CODE_FOR_xortf3 = 4019,
    CODE_FOR_fmasf4 = 4020,
    CODE_FOR_fmadf4 = 4021,
    CODE_FOR_fmav4sf4 = 4022,
    CODE_FOR_fmav2df4 = 4023,
    CODE_FOR_fmav8sf4 = 4024,
    CODE_FOR_fmav4df4 = 4025,
    CODE_FOR_fmav16sf4 = 4026,
    CODE_FOR_fmav8df4 = 4027,
    CODE_FOR_fmssf4 = 4028,
    CODE_FOR_fmsdf4 = 4029,
    CODE_FOR_fmsv4sf4 = 4030,
    CODE_FOR_fmsv2df4 = 4031,
    CODE_FOR_fmsv8sf4 = 4032,
    CODE_FOR_fmsv4df4 = 4033,
    CODE_FOR_fmsv16sf4 = 4034,
    CODE_FOR_fmsv8df4 = 4035,
    CODE_FOR_fnmasf4 = 4036,
    CODE_FOR_fnmadf4 = 4037,
    CODE_FOR_fnmav4sf4 = 4038,
    CODE_FOR_fnmav2df4 = 4039,
    CODE_FOR_fnmav8sf4 = 4040,
    CODE_FOR_fnmav4df4 = 4041,
    CODE_FOR_fnmav16sf4 = 4042,
    CODE_FOR_fnmav8df4 = 4043,
    CODE_FOR_fnmssf4 = 4044,
    CODE_FOR_fnmsdf4 = 4045,
    CODE_FOR_fnmsv4sf4 = 4046,
    CODE_FOR_fnmsv2df4 = 4047,
    CODE_FOR_fnmsv8sf4 = 4048,
    CODE_FOR_fnmsv4df4 = 4049,
    CODE_FOR_fnmsv16sf4 = 4050,
    CODE_FOR_fnmsv8df4 = 4051,
    CODE_FOR_fma4i_fmadd_sf = 4052,
    CODE_FOR_fma4i_fmadd_df = 4053,
    CODE_FOR_fma4i_fmadd_v4sf = 4054,
    CODE_FOR_fma4i_fmadd_v2df = 4055,
    CODE_FOR_fma4i_fmadd_v8sf = 4056,
    CODE_FOR_fma4i_fmadd_v4df = 4057,
    CODE_FOR_fma4i_fmadd_v16sf = 4058,
    CODE_FOR_fma4i_fmadd_v8df = 4059,
    CODE_FOR_avx512f_fmadd_v16sf_maskz = 4060,
    CODE_FOR_avx512f_fmadd_v16sf_maskz_round = 4061,
    CODE_FOR_avx512f_fmadd_v8df_maskz = 4062,
    CODE_FOR_avx512f_fmadd_v8df_maskz_round = 4063,
    CODE_FOR_fmaddsub_v16sf = 4064,
    CODE_FOR_fmaddsub_v8sf = 4065,
    CODE_FOR_fmaddsub_v4sf = 4066,
    CODE_FOR_fmaddsub_v8df = 4067,
    CODE_FOR_fmaddsub_v4df = 4068,
    CODE_FOR_fmaddsub_v2df = 4069,
    CODE_FOR_avx512f_fmaddsub_v16sf_maskz = 4070,
    CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round = 4071,
    CODE_FOR_avx512f_fmaddsub_v8df_maskz = 4072,
    CODE_FOR_avx512f_fmaddsub_v8df_maskz_round = 4073,
    CODE_FOR_fmai_vmfmadd_v4sf = 4074,
    CODE_FOR_fmai_vmfmadd_v4sf_round = 4075,
    CODE_FOR_fmai_vmfmadd_v2df = 4076,
    CODE_FOR_fmai_vmfmadd_v2df_round = 4077,
    CODE_FOR_fma4i_vmfmadd_v4sf = 4078,
    CODE_FOR_fma4i_vmfmadd_v2df = 4079,
    CODE_FOR_floatunsv16siv16sf2 = 4080,
    CODE_FOR_floatunsv8siv8sf2 = 4081,
    CODE_FOR_floatunsv4siv4sf2 = 4082,
    CODE_FOR_fixuns_truncv16sfv16si2 = 4083,
    CODE_FOR_fixuns_truncv8sfv8si2 = 4084,
    CODE_FOR_fixuns_truncv4sfv4si2 = 4085,
    CODE_FOR_avx_cvtpd2dq256_2 = 4086,
    CODE_FOR_sse2_cvtpd2dq = 4087,
    CODE_FOR_avx_cvttpd2dq256_2 = 4088,
    CODE_FOR_sse2_cvttpd2dq = 4089,
    CODE_FOR_sse2_cvtpd2ps = 4090,
    CODE_FOR_vec_unpacks_hi_v4sf = 4091,
    CODE_FOR_vec_unpacks_hi_v8sf = 4092,
    CODE_FOR_vec_unpacks_hi_v16sf = 4093,
    CODE_FOR_vec_unpacks_lo_v4sf = 4094,
    CODE_FOR_vec_unpacks_lo_v8sf = 4095,
    CODE_FOR_vec_unpacks_float_hi_v32hi = 4096,
    CODE_FOR_vec_unpacks_float_hi_v16hi = 4097,
    CODE_FOR_vec_unpacks_float_hi_v8hi = 4098,
    CODE_FOR_vec_unpacks_float_lo_v32hi = 4099,
    CODE_FOR_vec_unpacks_float_lo_v16hi = 4100,
    CODE_FOR_vec_unpacks_float_lo_v8hi = 4101,
    CODE_FOR_vec_unpacku_float_hi_v32hi = 4102,
    CODE_FOR_vec_unpacku_float_hi_v16hi = 4103,
    CODE_FOR_vec_unpacku_float_hi_v8hi = 4104,
    CODE_FOR_vec_unpacku_float_lo_v32hi = 4105,
    CODE_FOR_vec_unpacku_float_lo_v16hi = 4106,
    CODE_FOR_vec_unpacku_float_lo_v8hi = 4107,
    CODE_FOR_vec_unpacks_float_hi_v4si = 4108,
    CODE_FOR_vec_unpacks_float_lo_v4si = 4109,
    CODE_FOR_vec_unpacks_float_hi_v8si = 4110,
    CODE_FOR_vec_unpacks_float_lo_v8si = 4111,
    CODE_FOR_vec_unpacks_float_hi_v16si = 4112,
    CODE_FOR_vec_unpacks_float_lo_v16si = 4113,
    CODE_FOR_vec_unpacku_float_hi_v4si = 4114,
    CODE_FOR_vec_unpacku_float_lo_v4si = 4115,
    CODE_FOR_vec_unpacku_float_hi_v8si = 4116,
    CODE_FOR_vec_unpacku_float_hi_v16si = 4117,
    CODE_FOR_vec_unpacku_float_lo_v8si = 4118,
    CODE_FOR_vec_unpacku_float_lo_v16si = 4119,
    CODE_FOR_vec_pack_trunc_v8df = 4120,
    CODE_FOR_vec_pack_trunc_v4df = 4121,
    CODE_FOR_vec_pack_trunc_v2df = 4122,
    CODE_FOR_vec_pack_sfix_trunc_v8df = 4123,
    CODE_FOR_vec_pack_sfix_trunc_v4df = 4124,
    CODE_FOR_vec_pack_sfix_trunc_v2df = 4125,
    CODE_FOR_vec_pack_ufix_trunc_v8df = 4126,
    CODE_FOR_vec_pack_ufix_trunc_v4df = 4127,
    CODE_FOR_vec_pack_ufix_trunc_v2df = 4128,
    CODE_FOR_vec_pack_sfix_v4df = 4129,
    CODE_FOR_vec_pack_sfix_v2df = 4130,
    CODE_FOR_sse_movhlps_exp = 4131,
    CODE_FOR_sse_movlhps_exp = 4132,
    CODE_FOR_vec_interleave_highv8sf = 4133,
    CODE_FOR_vec_interleave_lowv8sf = 4134,
    CODE_FOR_avx_shufps256 = 4135,
    CODE_FOR_sse_shufps = 4136,
    CODE_FOR_sse_loadhps_exp = 4137,
    CODE_FOR_sse_loadlps_exp = 4138,
    CODE_FOR_vec_initv16qi = 4139,
    CODE_FOR_vec_initv8hi = 4140,
    CODE_FOR_vec_initv4si = 4141,
    CODE_FOR_vec_initv2di = 4142,
    CODE_FOR_vec_initv4sf = 4143,
    CODE_FOR_vec_initv2df = 4144,
    CODE_FOR_vec_setv32qi = 4147,
    CODE_FOR_vec_setv16qi = 4148,
    CODE_FOR_vec_setv16hi = 4149,
    CODE_FOR_vec_setv8hi = 4150,
    CODE_FOR_vec_setv16si = 4151,
    CODE_FOR_vec_setv8si = 4152,
    CODE_FOR_vec_setv4si = 4153,
    CODE_FOR_vec_setv8di = 4154,
    CODE_FOR_vec_setv4di = 4155,
    CODE_FOR_vec_setv2di = 4156,
    CODE_FOR_vec_setv16sf = 4157,
    CODE_FOR_vec_setv8sf = 4158,
    CODE_FOR_vec_setv4sf = 4159,
    CODE_FOR_vec_setv8df = 4160,
    CODE_FOR_vec_setv4df = 4161,
    CODE_FOR_vec_setv2df = 4162,
    CODE_FOR_avx512f_vextractf32x4_mask = 4166,
    CODE_FOR_avx512f_vextracti32x4_mask = 4167,
    CODE_FOR_avx512f_vextractf64x4_mask = 4168,
    CODE_FOR_avx512f_vextracti64x4_mask = 4169,
    CODE_FOR_avx_vextractf128v32qi = 4172,
    CODE_FOR_avx_vextractf128v16hi = 4173,
    CODE_FOR_avx_vextractf128v8si = 4174,
    CODE_FOR_avx_vextractf128v4di = 4175,
    CODE_FOR_avx_vextractf128v8sf = 4176,
    CODE_FOR_avx_vextractf128v4df = 4177,
    CODE_FOR_vec_extractv32qi = 4188,
    CODE_FOR_vec_extractv16qi = 4189,
    CODE_FOR_vec_extractv16hi = 4190,
    CODE_FOR_vec_extractv8hi = 4191,
    CODE_FOR_vec_extractv16si = 4192,
    CODE_FOR_vec_extractv8si = 4193,
    CODE_FOR_vec_extractv4si = 4194,
    CODE_FOR_vec_extractv8di = 4195,
    CODE_FOR_vec_extractv4di = 4196,
    CODE_FOR_vec_extractv2di = 4197,
    CODE_FOR_vec_extractv16sf = 4198,
    CODE_FOR_vec_extractv8sf = 4199,
    CODE_FOR_vec_extractv4sf = 4200,
    CODE_FOR_vec_extractv8df = 4201,
    CODE_FOR_vec_extractv4df = 4202,
    CODE_FOR_vec_extractv2df = 4203,
    CODE_FOR_vec_interleave_highv4df = 4204,
    CODE_FOR_vec_interleave_highv2df = 4205,
    CODE_FOR_avx512f_movddup512 = 4206,
    CODE_FOR_avx512f_movddup512_mask = 4207,
    CODE_FOR_avx512f_unpcklpd512 = 4208,
    CODE_FOR_avx512f_unpcklpd512_mask = 4209,
    CODE_FOR_avx_movddup256 = 4210,
    CODE_FOR_avx_unpcklpd256 = 4211,
    CODE_FOR_vec_interleave_lowv4df = 4212,
    CODE_FOR_vec_interleave_lowv2df = 4213,
    CODE_FOR_avx512f_vternlogv16si_maskz = 4216,
    CODE_FOR_avx512f_vternlogv8di_maskz = 4217,
    CODE_FOR_avx512f_shufps512_mask = 4218,
    CODE_FOR_avx512f_fixupimmv16sf_maskz = 4219,
    CODE_FOR_avx512f_fixupimmv16sf_maskz_round = 4220,
    CODE_FOR_avx512f_fixupimmv8df_maskz = 4221,
    CODE_FOR_avx512f_fixupimmv8df_maskz_round = 4222,
    CODE_FOR_avx512f_sfixupimmv4sf_maskz = 4223,
    CODE_FOR_avx512f_sfixupimmv4sf_maskz_round = 4224,
    CODE_FOR_avx512f_sfixupimmv2df_maskz = 4225,
    CODE_FOR_avx512f_sfixupimmv2df_maskz_round = 4226,
    CODE_FOR_avx512f_shufpd512_mask = 4227,
    CODE_FOR_avx_shufpd256 = 4228,
    CODE_FOR_sse2_shufpd = 4229,
    CODE_FOR_sse2_loadhpd_exp = 4232,
    CODE_FOR_sse2_loadlpd_exp = 4234,
    CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store = 4236,
    CODE_FOR_avx512f_truncatev16siv16qi2_mask_store = 4237,
    CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store = 4238,
    CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store = 4239,
    CODE_FOR_avx512f_truncatev16siv16hi2_mask_store = 4240,
    CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store = 4241,
    CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store = 4242,
    CODE_FOR_avx512f_truncatev8div8si2_mask_store = 4243,
    CODE_FOR_avx512f_us_truncatev8div8si2_mask_store = 4244,
    CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store = 4245,
    CODE_FOR_avx512f_truncatev8div8hi2_mask_store = 4246,
    CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store = 4247,
    CODE_FOR_negv32qi2 = 4248,
    CODE_FOR_negv16qi2 = 4249,
    CODE_FOR_negv16hi2 = 4250,
    CODE_FOR_negv8hi2 = 4251,
    CODE_FOR_negv16si2 = 4252,
    CODE_FOR_negv8si2 = 4253,
    CODE_FOR_negv4si2 = 4254,
    CODE_FOR_negv8di2 = 4255,
    CODE_FOR_negv4di2 = 4256,
    CODE_FOR_negv2di2 = 4257,
    CODE_FOR_addv32qi3 = 4258,
    CODE_FOR_subv32qi3 = 4259,
    CODE_FOR_addv16qi3 = 4260,
  #define CODE_FOR_addv16qi3_mask CODE_FOR_nothing
    CODE_FOR_subv16qi3 = 4261,
  #define CODE_FOR_subv16qi3_mask CODE_FOR_nothing
    CODE_FOR_addv16hi3 = 4262,
  #define CODE_FOR_addv16hi3_mask CODE_FOR_nothing
    CODE_FOR_subv16hi3 = 4263,
  #define CODE_FOR_subv16hi3_mask CODE_FOR_nothing
    CODE_FOR_addv8hi3 = 4264,
  #define CODE_FOR_addv8hi3_mask CODE_FOR_nothing
    CODE_FOR_subv8hi3 = 4265,
  #define CODE_FOR_subv8hi3_mask CODE_FOR_nothing
    CODE_FOR_addv16si3 = 4266,
    CODE_FOR_addv16si3_mask = 4267,
    CODE_FOR_subv16si3 = 4268,
    CODE_FOR_subv16si3_mask = 4269,
    CODE_FOR_addv8si3 = 4270,
  #define CODE_FOR_addv8si3_mask CODE_FOR_nothing
    CODE_FOR_subv8si3 = 4271,
  #define CODE_FOR_subv8si3_mask CODE_FOR_nothing
    CODE_FOR_addv4si3 = 4272,
  #define CODE_FOR_addv4si3_mask CODE_FOR_nothing
    CODE_FOR_subv4si3 = 4273,
  #define CODE_FOR_subv4si3_mask CODE_FOR_nothing
    CODE_FOR_addv8di3 = 4274,
    CODE_FOR_addv8di3_mask = 4275,
    CODE_FOR_subv8di3 = 4276,
    CODE_FOR_subv8di3_mask = 4277,
    CODE_FOR_addv4di3 = 4278,
  #define CODE_FOR_addv4di3_mask CODE_FOR_nothing
    CODE_FOR_subv4di3 = 4279,
  #define CODE_FOR_subv4di3_mask CODE_FOR_nothing
    CODE_FOR_addv2di3 = 4280,
  #define CODE_FOR_addv2di3_mask CODE_FOR_nothing
    CODE_FOR_subv2di3 = 4281,
  #define CODE_FOR_subv2di3_mask CODE_FOR_nothing
    CODE_FOR_avx2_ssaddv32qi3 = 4282,
    CODE_FOR_avx2_usaddv32qi3 = 4283,
    CODE_FOR_avx2_sssubv32qi3 = 4284,
    CODE_FOR_avx2_ussubv32qi3 = 4285,
    CODE_FOR_sse2_ssaddv16qi3 = 4286,
    CODE_FOR_sse2_usaddv16qi3 = 4287,
    CODE_FOR_sse2_sssubv16qi3 = 4288,
    CODE_FOR_sse2_ussubv16qi3 = 4289,
    CODE_FOR_avx2_ssaddv16hi3 = 4290,
    CODE_FOR_avx2_usaddv16hi3 = 4291,
    CODE_FOR_avx2_sssubv16hi3 = 4292,
    CODE_FOR_avx2_ussubv16hi3 = 4293,
    CODE_FOR_sse2_ssaddv8hi3 = 4294,
    CODE_FOR_sse2_usaddv8hi3 = 4295,
    CODE_FOR_sse2_sssubv8hi3 = 4296,
    CODE_FOR_sse2_ussubv8hi3 = 4297,
    CODE_FOR_mulv32qi3 = 4298,
    CODE_FOR_mulv16qi3 = 4299,
    CODE_FOR_mulv16hi3 = 4300,
    CODE_FOR_mulv8hi3 = 4301,
    CODE_FOR_smulv16hi3_highpart = 4302,
    CODE_FOR_umulv16hi3_highpart = 4303,
    CODE_FOR_smulv8hi3_highpart = 4304,
    CODE_FOR_umulv8hi3_highpart = 4305,
    CODE_FOR_vec_widen_umult_even_v16si = 4306,
    CODE_FOR_vec_widen_umult_even_v16si_mask = 4307,
    CODE_FOR_vec_widen_umult_even_v8si = 4308,
    CODE_FOR_vec_widen_umult_even_v4si = 4309,
    CODE_FOR_vec_widen_smult_even_v16si = 4310,
    CODE_FOR_vec_widen_smult_even_v16si_mask = 4311,
    CODE_FOR_vec_widen_smult_even_v8si = 4312,
    CODE_FOR_sse4_1_mulv2siv2di3 = 4313,
    CODE_FOR_avx2_pmaddwd = 4314,
    CODE_FOR_sse2_pmaddwd = 4315,
    CODE_FOR_mulv16si3 = 4316,
    CODE_FOR_mulv16si3_mask = 4317,
    CODE_FOR_mulv8si3 = 4318,
  #define CODE_FOR_mulv8si3_mask CODE_FOR_nothing
    CODE_FOR_mulv4si3 = 4319,
  #define CODE_FOR_mulv4si3_mask CODE_FOR_nothing
    CODE_FOR_mulv8di3 = 4320,
    CODE_FOR_mulv4di3 = 4321,
    CODE_FOR_mulv2di3 = 4322,
    CODE_FOR_vec_widen_smult_hi_v32qi = 4323,
    CODE_FOR_vec_widen_umult_hi_v32qi = 4324,
    CODE_FOR_vec_widen_smult_hi_v16qi = 4325,
    CODE_FOR_vec_widen_umult_hi_v16qi = 4326,
    CODE_FOR_vec_widen_smult_hi_v16hi = 4327,
    CODE_FOR_vec_widen_umult_hi_v16hi = 4328,
    CODE_FOR_vec_widen_smult_hi_v8hi = 4329,
    CODE_FOR_vec_widen_umult_hi_v8hi = 4330,
    CODE_FOR_vec_widen_smult_hi_v8si = 4331,
    CODE_FOR_vec_widen_umult_hi_v8si = 4332,
    CODE_FOR_vec_widen_smult_hi_v4si = 4333,
    CODE_FOR_vec_widen_umult_hi_v4si = 4334,
    CODE_FOR_vec_widen_smult_lo_v32qi = 4335,
    CODE_FOR_vec_widen_umult_lo_v32qi = 4336,
    CODE_FOR_vec_widen_smult_lo_v16qi = 4337,
    CODE_FOR_vec_widen_umult_lo_v16qi = 4338,
    CODE_FOR_vec_widen_smult_lo_v16hi = 4339,
    CODE_FOR_vec_widen_umult_lo_v16hi = 4340,
    CODE_FOR_vec_widen_smult_lo_v8hi = 4341,
    CODE_FOR_vec_widen_umult_lo_v8hi = 4342,
    CODE_FOR_vec_widen_smult_lo_v8si = 4343,
    CODE_FOR_vec_widen_umult_lo_v8si = 4344,
    CODE_FOR_vec_widen_smult_lo_v4si = 4345,
    CODE_FOR_vec_widen_umult_lo_v4si = 4346,
    CODE_FOR_vec_widen_smult_even_v4si = 4347,
    CODE_FOR_vec_widen_smult_odd_v16si = 4348,
    CODE_FOR_vec_widen_umult_odd_v16si = 4349,
    CODE_FOR_vec_widen_smult_odd_v8si = 4350,
    CODE_FOR_vec_widen_umult_odd_v8si = 4351,
    CODE_FOR_vec_widen_smult_odd_v4si = 4352,
    CODE_FOR_vec_widen_umult_odd_v4si = 4353,
    CODE_FOR_sdot_prodv16hi = 4354,
    CODE_FOR_sdot_prodv8hi = 4355,
    CODE_FOR_sdot_prodv4si = 4356,
    CODE_FOR_vec_shl_v16qi = 4357,
    CODE_FOR_vec_shl_v8hi = 4358,
    CODE_FOR_vec_shl_v4si = 4359,
    CODE_FOR_vec_shl_v2di = 4360,
    CODE_FOR_vec_shr_v16qi = 4361,
    CODE_FOR_vec_shr_v8hi = 4362,
    CODE_FOR_vec_shr_v4si = 4363,
    CODE_FOR_vec_shr_v2di = 4364,
    CODE_FOR_smaxv32qi3 = 4365,
    CODE_FOR_sminv32qi3 = 4366,
    CODE_FOR_umaxv32qi3 = 4367,
    CODE_FOR_uminv32qi3 = 4368,
    CODE_FOR_smaxv16hi3 = 4369,
  #define CODE_FOR_smaxv16hi3_round CODE_FOR_nothing
  #define CODE_FOR_smaxv16hi3_mask CODE_FOR_nothing
  #define CODE_FOR_smaxv16hi3_mask_round CODE_FOR_nothing
    CODE_FOR_sminv16hi3 = 4370,
  #define CODE_FOR_sminv16hi3_round CODE_FOR_nothing
  #define CODE_FOR_sminv16hi3_mask CODE_FOR_nothing
  #define CODE_FOR_sminv16hi3_mask_round CODE_FOR_nothing
    CODE_FOR_umaxv16hi3 = 4371,
  #define CODE_FOR_umaxv16hi3_round CODE_FOR_nothing
  #define CODE_FOR_umaxv16hi3_mask CODE_FOR_nothing
  #define CODE_FOR_umaxv16hi3_mask_round CODE_FOR_nothing
    CODE_FOR_uminv16hi3 = 4372,
  #define CODE_FOR_uminv16hi3_round CODE_FOR_nothing
  #define CODE_FOR_uminv16hi3_mask CODE_FOR_nothing
  #define CODE_FOR_uminv16hi3_mask_round CODE_FOR_nothing
    CODE_FOR_smaxv8si3 = 4373,
  #define CODE_FOR_smaxv8si3_round CODE_FOR_nothing
  #define CODE_FOR_smaxv8si3_mask CODE_FOR_nothing
  #define CODE_FOR_smaxv8si3_mask_round CODE_FOR_nothing
    CODE_FOR_sminv8si3 = 4374,
  #define CODE_FOR_sminv8si3_round CODE_FOR_nothing
  #define CODE_FOR_sminv8si3_mask CODE_FOR_nothing
  #define CODE_FOR_sminv8si3_mask_round CODE_FOR_nothing
    CODE_FOR_umaxv8si3 = 4375,
  #define CODE_FOR_umaxv8si3_round CODE_FOR_nothing
  #define CODE_FOR_umaxv8si3_mask CODE_FOR_nothing
  #define CODE_FOR_umaxv8si3_mask_round CODE_FOR_nothing
    CODE_FOR_uminv8si3 = 4376,
  #define CODE_FOR_uminv8si3_round CODE_FOR_nothing
  #define CODE_FOR_uminv8si3_mask CODE_FOR_nothing
  #define CODE_FOR_uminv8si3_mask_round CODE_FOR_nothing
    CODE_FOR_smaxv8di3 = 4377,
  #define CODE_FOR_smaxv8di3_round CODE_FOR_nothing
    CODE_FOR_smaxv8di3_mask = 4378,
  #define CODE_FOR_smaxv8di3_mask_round CODE_FOR_nothing
    CODE_FOR_sminv8di3 = 4379,
  #define CODE_FOR_sminv8di3_round CODE_FOR_nothing
    CODE_FOR_sminv8di3_mask = 4380,
  #define CODE_FOR_sminv8di3_mask_round CODE_FOR_nothing
    CODE_FOR_umaxv8di3 = 4381,
  #define CODE_FOR_umaxv8di3_round CODE_FOR_nothing
    CODE_FOR_umaxv8di3_mask = 4382,
  #define CODE_FOR_umaxv8di3_mask_round CODE_FOR_nothing
    CODE_FOR_uminv8di3 = 4383,
  #define CODE_FOR_uminv8di3_round CODE_FOR_nothing
    CODE_FOR_uminv8di3_mask = 4384,
  #define CODE_FOR_uminv8di3_mask_round CODE_FOR_nothing
    CODE_FOR_smaxv16si3 = 4385,
  #define CODE_FOR_smaxv16si3_round CODE_FOR_nothing
    CODE_FOR_smaxv16si3_mask = 4386,
  #define CODE_FOR_smaxv16si3_mask_round CODE_FOR_nothing
    CODE_FOR_sminv16si3 = 4387,
  #define CODE_FOR_sminv16si3_round CODE_FOR_nothing
    CODE_FOR_sminv16si3_mask = 4388,
  #define CODE_FOR_sminv16si3_mask_round CODE_FOR_nothing
    CODE_FOR_umaxv16si3 = 4389,
  #define CODE_FOR_umaxv16si3_round CODE_FOR_nothing
    CODE_FOR_umaxv16si3_mask = 4390,
  #define CODE_FOR_umaxv16si3_mask_round CODE_FOR_nothing
    CODE_FOR_uminv16si3 = 4391,
  #define CODE_FOR_uminv16si3_round CODE_FOR_nothing
    CODE_FOR_uminv16si3_mask = 4392,
  #define CODE_FOR_uminv16si3_mask_round CODE_FOR_nothing
    CODE_FOR_smaxv4di3 = 4393,
    CODE_FOR_sminv4di3 = 4394,
    CODE_FOR_umaxv4di3 = 4395,
    CODE_FOR_uminv4di3 = 4396,
    CODE_FOR_smaxv2di3 = 4397,
    CODE_FOR_sminv2di3 = 4398,
    CODE_FOR_umaxv2di3 = 4399,
    CODE_FOR_uminv2di3 = 4400,
    CODE_FOR_smaxv16qi3 = 4401,
    CODE_FOR_sminv16qi3 = 4402,
    CODE_FOR_smaxv8hi3 = 4403,
    CODE_FOR_sminv8hi3 = 4404,
    CODE_FOR_smaxv4si3 = 4405,
    CODE_FOR_sminv4si3 = 4406,
    CODE_FOR_umaxv16qi3 = 4407,
    CODE_FOR_uminv16qi3 = 4408,
    CODE_FOR_umaxv8hi3 = 4409,
    CODE_FOR_uminv8hi3 = 4410,
    CODE_FOR_umaxv4si3 = 4411,
    CODE_FOR_uminv4si3 = 4412,
    CODE_FOR_avx2_eqv32qi3 = 4413,
    CODE_FOR_avx2_eqv16hi3 = 4414,
    CODE_FOR_avx2_eqv8si3 = 4415,
    CODE_FOR_avx2_eqv4di3 = 4416,
    CODE_FOR_avx512f_eqv16si3 = 4417,
    CODE_FOR_avx512f_eqv16si3_mask = 4418,
    CODE_FOR_avx512f_eqv8di3 = 4419,
    CODE_FOR_avx512f_eqv8di3_mask = 4420,
    CODE_FOR_sse2_eqv16qi3 = 4421,
    CODE_FOR_sse2_eqv8hi3 = 4422,
    CODE_FOR_sse2_eqv4si3 = 4423,
    CODE_FOR_sse4_1_eqv2di3 = 4424,
    CODE_FOR_vcondv64qiv64qi = 4425,
    CODE_FOR_vcondv32hiv64qi = 4426,
    CODE_FOR_vcondv16siv64qi = 4427,
    CODE_FOR_vcondv8div64qi = 4428,
    CODE_FOR_vcondv16sfv64qi = 4429,
    CODE_FOR_vcondv8dfv64qi = 4430,
    CODE_FOR_vcondv64qiv32hi = 4431,
    CODE_FOR_vcondv32hiv32hi = 4432,
    CODE_FOR_vcondv16siv32hi = 4433,
    CODE_FOR_vcondv8div32hi = 4434,
    CODE_FOR_vcondv16sfv32hi = 4435,
    CODE_FOR_vcondv8dfv32hi = 4436,
    CODE_FOR_vcondv64qiv16si = 4437,
    CODE_FOR_vcondv32hiv16si = 4438,
    CODE_FOR_vcondv16siv16si = 4439,
    CODE_FOR_vcondv8div16si = 4440,
    CODE_FOR_vcondv16sfv16si = 4441,
    CODE_FOR_vcondv8dfv16si = 4442,
    CODE_FOR_vcondv64qiv8di = 4443,
    CODE_FOR_vcondv32hiv8di = 4444,
    CODE_FOR_vcondv16siv8di = 4445,
    CODE_FOR_vcondv8div8di = 4446,
    CODE_FOR_vcondv16sfv8di = 4447,
    CODE_FOR_vcondv8dfv8di = 4448,
    CODE_FOR_vcondv32qiv32qi = 4449,
    CODE_FOR_vcondv16hiv32qi = 4450,
    CODE_FOR_vcondv8siv32qi = 4451,
    CODE_FOR_vcondv4div32qi = 4452,
    CODE_FOR_vcondv8sfv32qi = 4453,
    CODE_FOR_vcondv4dfv32qi = 4454,
    CODE_FOR_vcondv32qiv16hi = 4455,
    CODE_FOR_vcondv16hiv16hi = 4456,
    CODE_FOR_vcondv8siv16hi = 4457,
    CODE_FOR_vcondv4div16hi = 4458,
    CODE_FOR_vcondv8sfv16hi = 4459,
    CODE_FOR_vcondv4dfv16hi = 4460,
    CODE_FOR_vcondv32qiv8si = 4461,
    CODE_FOR_vcondv16hiv8si = 4462,
    CODE_FOR_vcondv8siv8si = 4463,
    CODE_FOR_vcondv4div8si = 4464,
    CODE_FOR_vcondv8sfv8si = 4465,
    CODE_FOR_vcondv4dfv8si = 4466,
    CODE_FOR_vcondv32qiv4di = 4467,
    CODE_FOR_vcondv16hiv4di = 4468,
    CODE_FOR_vcondv8siv4di = 4469,
    CODE_FOR_vcondv4div4di = 4470,
    CODE_FOR_vcondv8sfv4di = 4471,
    CODE_FOR_vcondv4dfv4di = 4472,
    CODE_FOR_vcondv16qiv16qi = 4473,
    CODE_FOR_vcondv16qiv8hi = 4474,
    CODE_FOR_vcondv16qiv4si = 4475,
    CODE_FOR_vcondv8hiv16qi = 4476,
    CODE_FOR_vcondv8hiv8hi = 4477,
    CODE_FOR_vcondv8hiv4si = 4478,
    CODE_FOR_vcondv4siv16qi = 4479,
    CODE_FOR_vcondv4siv8hi = 4480,
    CODE_FOR_vcondv4siv4si = 4481,
    CODE_FOR_vcondv2div16qi = 4482,
    CODE_FOR_vcondv2div8hi = 4483,
    CODE_FOR_vcondv2div4si = 4484,
    CODE_FOR_vcondv4sfv16qi = 4485,
    CODE_FOR_vcondv4sfv8hi = 4486,
    CODE_FOR_vcondv4sfv4si = 4487,
    CODE_FOR_vcondv2dfv16qi = 4488,
    CODE_FOR_vcondv2dfv8hi = 4489,
    CODE_FOR_vcondv2dfv4si = 4490,
    CODE_FOR_vcondv2div2di = 4491,
    CODE_FOR_vcondv2dfv2di = 4492,
    CODE_FOR_vconduv64qiv64qi = 4493,
    CODE_FOR_vconduv32hiv64qi = 4494,
    CODE_FOR_vconduv16siv64qi = 4495,
    CODE_FOR_vconduv8div64qi = 4496,
    CODE_FOR_vconduv16sfv64qi = 4497,
    CODE_FOR_vconduv8dfv64qi = 4498,
    CODE_FOR_vconduv64qiv32hi = 4499,
    CODE_FOR_vconduv32hiv32hi = 4500,
    CODE_FOR_vconduv16siv32hi = 4501,
    CODE_FOR_vconduv8div32hi = 4502,
    CODE_FOR_vconduv16sfv32hi = 4503,
    CODE_FOR_vconduv8dfv32hi = 4504,
    CODE_FOR_vconduv64qiv16si = 4505,
    CODE_FOR_vconduv32hiv16si = 4506,
    CODE_FOR_vconduv16siv16si = 4507,
    CODE_FOR_vconduv8div16si = 4508,
    CODE_FOR_vconduv16sfv16si = 4509,
    CODE_FOR_vconduv8dfv16si = 4510,
    CODE_FOR_vconduv64qiv8di = 4511,
    CODE_FOR_vconduv32hiv8di = 4512,
    CODE_FOR_vconduv16siv8di = 4513,
    CODE_FOR_vconduv8div8di = 4514,
    CODE_FOR_vconduv16sfv8di = 4515,
    CODE_FOR_vconduv8dfv8di = 4516,
    CODE_FOR_vconduv32qiv32qi = 4517,
    CODE_FOR_vconduv16hiv32qi = 4518,
    CODE_FOR_vconduv8siv32qi = 4519,
    CODE_FOR_vconduv4div32qi = 4520,
    CODE_FOR_vconduv8sfv32qi = 4521,
    CODE_FOR_vconduv4dfv32qi = 4522,
    CODE_FOR_vconduv32qiv16hi = 4523,
    CODE_FOR_vconduv16hiv16hi = 4524,
    CODE_FOR_vconduv8siv16hi = 4525,
    CODE_FOR_vconduv4div16hi = 4526,
    CODE_FOR_vconduv8sfv16hi = 4527,
    CODE_FOR_vconduv4dfv16hi = 4528,
    CODE_FOR_vconduv32qiv8si = 4529,
    CODE_FOR_vconduv16hiv8si = 4530,
    CODE_FOR_vconduv8siv8si = 4531,
    CODE_FOR_vconduv4div8si = 4532,
    CODE_FOR_vconduv8sfv8si = 4533,
    CODE_FOR_vconduv4dfv8si = 4534,
    CODE_FOR_vconduv32qiv4di = 4535,
    CODE_FOR_vconduv16hiv4di = 4536,
    CODE_FOR_vconduv8siv4di = 4537,
    CODE_FOR_vconduv4div4di = 4538,
    CODE_FOR_vconduv8sfv4di = 4539,
    CODE_FOR_vconduv4dfv4di = 4540,
    CODE_FOR_vconduv16qiv16qi = 4541,
    CODE_FOR_vconduv16qiv8hi = 4542,
    CODE_FOR_vconduv16qiv4si = 4543,
    CODE_FOR_vconduv8hiv16qi = 4544,
    CODE_FOR_vconduv8hiv8hi = 4545,
    CODE_FOR_vconduv8hiv4si = 4546,
    CODE_FOR_vconduv4siv16qi = 4547,
    CODE_FOR_vconduv4siv8hi = 4548,
    CODE_FOR_vconduv4siv4si = 4549,
    CODE_FOR_vconduv2div16qi = 4550,
    CODE_FOR_vconduv2div8hi = 4551,
    CODE_FOR_vconduv2div4si = 4552,
    CODE_FOR_vconduv4sfv16qi = 4553,
    CODE_FOR_vconduv4sfv8hi = 4554,
    CODE_FOR_vconduv4sfv4si = 4555,
    CODE_FOR_vconduv2dfv16qi = 4556,
    CODE_FOR_vconduv2dfv8hi = 4557,
    CODE_FOR_vconduv2dfv4si = 4558,
    CODE_FOR_vconduv2div2di = 4559,
    CODE_FOR_vconduv2dfv2di = 4560,
    CODE_FOR_vec_permv16qi = 4561,
    CODE_FOR_vec_permv8hi = 4562,
    CODE_FOR_vec_permv4si = 4563,
    CODE_FOR_vec_permv2di = 4564,
    CODE_FOR_vec_permv4sf = 4565,
    CODE_FOR_vec_permv2df = 4566,
    CODE_FOR_vec_permv32qi = 4567,
    CODE_FOR_vec_permv16hi = 4568,
    CODE_FOR_vec_permv8si = 4569,
    CODE_FOR_vec_permv4di = 4570,
    CODE_FOR_vec_permv8sf = 4571,
    CODE_FOR_vec_permv4df = 4572,
    CODE_FOR_vec_permv16sf = 4573,
    CODE_FOR_vec_permv8df = 4574,
    CODE_FOR_vec_permv16si = 4575,
    CODE_FOR_vec_permv8di = 4576,
    CODE_FOR_vec_perm_constv4sf = 4577,
    CODE_FOR_vec_perm_constv4si = 4578,
    CODE_FOR_vec_perm_constv2df = 4579,
    CODE_FOR_vec_perm_constv2di = 4580,
    CODE_FOR_vec_perm_constv16qi = 4581,
    CODE_FOR_vec_perm_constv8hi = 4582,
    CODE_FOR_vec_perm_constv8sf = 4583,
    CODE_FOR_vec_perm_constv4df = 4584,
    CODE_FOR_vec_perm_constv8si = 4585,
    CODE_FOR_vec_perm_constv4di = 4586,
    CODE_FOR_vec_perm_constv32qi = 4587,
    CODE_FOR_vec_perm_constv16hi = 4588,
    CODE_FOR_vec_perm_constv16si = 4589,
    CODE_FOR_vec_perm_constv8di = 4590,
    CODE_FOR_vec_perm_constv16sf = 4591,
    CODE_FOR_vec_perm_constv8df = 4592,
    CODE_FOR_one_cmplv16si2 = 4593,
    CODE_FOR_one_cmplv8di2 = 4594,
    CODE_FOR_one_cmplv32qi2 = 4595,
    CODE_FOR_one_cmplv16qi2 = 4596,
    CODE_FOR_one_cmplv16hi2 = 4597,
    CODE_FOR_one_cmplv8hi2 = 4598,
    CODE_FOR_one_cmplv8si2 = 4599,
    CODE_FOR_one_cmplv4si2 = 4600,
    CODE_FOR_one_cmplv4di2 = 4601,
    CODE_FOR_one_cmplv2di2 = 4602,
    CODE_FOR_avx2_andnotv32qi3 = 4603,
    CODE_FOR_sse2_andnotv16qi3 = 4604,
  #define CODE_FOR_sse2_andnotv16qi3_mask CODE_FOR_nothing
    CODE_FOR_avx2_andnotv16hi3 = 4605,
  #define CODE_FOR_avx2_andnotv16hi3_mask CODE_FOR_nothing
    CODE_FOR_sse2_andnotv8hi3 = 4606,
  #define CODE_FOR_sse2_andnotv8hi3_mask CODE_FOR_nothing
    CODE_FOR_avx512f_andnotv16si3 = 4607,
    CODE_FOR_avx512f_andnotv16si3_mask = 4608,
    CODE_FOR_avx2_andnotv8si3 = 4609,
  #define CODE_FOR_avx2_andnotv8si3_mask CODE_FOR_nothing
    CODE_FOR_sse2_andnotv4si3 = 4610,
  #define CODE_FOR_sse2_andnotv4si3_mask CODE_FOR_nothing
    CODE_FOR_avx512f_andnotv8di3 = 4611,
    CODE_FOR_avx512f_andnotv8di3_mask = 4612,
    CODE_FOR_avx2_andnotv4di3 = 4613,
  #define CODE_FOR_avx2_andnotv4di3_mask CODE_FOR_nothing
    CODE_FOR_sse2_andnotv2di3 = 4614,
  #define CODE_FOR_sse2_andnotv2di3_mask CODE_FOR_nothing
    CODE_FOR_andv16si3 = 4615,
    CODE_FOR_iorv16si3 = 4616,
    CODE_FOR_xorv16si3 = 4617,
    CODE_FOR_andv8di3 = 4618,
    CODE_FOR_iorv8di3 = 4619,
    CODE_FOR_xorv8di3 = 4620,
    CODE_FOR_andv32qi3 = 4621,
    CODE_FOR_iorv32qi3 = 4622,
    CODE_FOR_xorv32qi3 = 4623,
    CODE_FOR_andv16qi3 = 4624,
    CODE_FOR_iorv16qi3 = 4625,
    CODE_FOR_xorv16qi3 = 4626,
    CODE_FOR_andv16hi3 = 4627,
    CODE_FOR_iorv16hi3 = 4628,
    CODE_FOR_xorv16hi3 = 4629,
    CODE_FOR_andv8hi3 = 4630,
    CODE_FOR_iorv8hi3 = 4631,
    CODE_FOR_xorv8hi3 = 4632,
    CODE_FOR_andv8si3 = 4633,
    CODE_FOR_iorv8si3 = 4634,
    CODE_FOR_xorv8si3 = 4635,
    CODE_FOR_andv4si3 = 4636,
    CODE_FOR_iorv4si3 = 4637,
    CODE_FOR_xorv4si3 = 4638,
    CODE_FOR_andv4di3 = 4639,
    CODE_FOR_iorv4di3 = 4640,
    CODE_FOR_xorv4di3 = 4641,
    CODE_FOR_andv2di3 = 4642,
    CODE_FOR_iorv2di3 = 4643,
    CODE_FOR_xorv2di3 = 4644,
    CODE_FOR_vec_pack_trunc_v16hi = 4645,
    CODE_FOR_vec_pack_trunc_v8hi = 4646,
    CODE_FOR_vec_pack_trunc_v8si = 4647,
    CODE_FOR_vec_pack_trunc_v4si = 4648,
    CODE_FOR_vec_pack_trunc_v8di = 4649,
    CODE_FOR_vec_pack_trunc_v4di = 4650,
    CODE_FOR_vec_pack_trunc_v2di = 4651,
    CODE_FOR_vec_interleave_highv32qi = 4652,
    CODE_FOR_vec_interleave_highv16hi = 4653,
    CODE_FOR_vec_interleave_highv8si = 4654,
    CODE_FOR_vec_interleave_highv4di = 4655,
    CODE_FOR_vec_interleave_lowv32qi = 4656,
    CODE_FOR_vec_interleave_lowv16hi = 4657,
    CODE_FOR_vec_interleave_lowv8si = 4658,
    CODE_FOR_vec_interleave_lowv4di = 4659,
    CODE_FOR_avx512f_vinsertf32x4_mask = 4660,
    CODE_FOR_avx512f_vinserti32x4_mask = 4661,
    CODE_FOR_avx512f_vinsertf64x4_mask = 4662,
    CODE_FOR_avx512f_vinserti64x4_mask = 4663,
    CODE_FOR_avx512f_shuf_f64x2_mask = 4664,
    CODE_FOR_avx512f_shuf_i64x2_mask = 4665,
    CODE_FOR_avx512f_shuf_f32x4_mask = 4666,
    CODE_FOR_avx512f_shuf_i32x4_mask = 4667,
    CODE_FOR_avx512f_pshufdv3_mask = 4668,
    CODE_FOR_avx2_pshufdv3 = 4669,
    CODE_FOR_sse2_pshufd = 4670,
    CODE_FOR_avx2_pshuflwv3 = 4671,
    CODE_FOR_sse2_pshuflw = 4672,
    CODE_FOR_avx2_pshufhwv3 = 4673,
    CODE_FOR_sse2_pshufhw = 4674,
    CODE_FOR_sse2_loadd = 4675,
    CODE_FOR_vec_unpacks_lo_v32qi = 4682,
    CODE_FOR_vec_unpacks_lo_v16qi = 4683,
    CODE_FOR_vec_unpacks_lo_v32hi = 4684,
    CODE_FOR_vec_unpacks_lo_v16hi = 4685,
    CODE_FOR_vec_unpacks_lo_v8hi = 4686,
    CODE_FOR_vec_unpacks_lo_v16si = 4687,
    CODE_FOR_vec_unpacks_lo_v8si = 4688,
    CODE_FOR_vec_unpacks_lo_v4si = 4689,
    CODE_FOR_vec_unpacks_hi_v32qi = 4690,
    CODE_FOR_vec_unpacks_hi_v16qi = 4691,
    CODE_FOR_vec_unpacks_hi_v32hi = 4692,
    CODE_FOR_vec_unpacks_hi_v16hi = 4693,
    CODE_FOR_vec_unpacks_hi_v8hi = 4694,
    CODE_FOR_vec_unpacks_hi_v16si = 4695,
    CODE_FOR_vec_unpacks_hi_v8si = 4696,
    CODE_FOR_vec_unpacks_hi_v4si = 4697,
    CODE_FOR_vec_unpacku_lo_v32qi = 4698,
    CODE_FOR_vec_unpacku_lo_v16qi = 4699,
    CODE_FOR_vec_unpacku_lo_v32hi = 4700,
    CODE_FOR_vec_unpacku_lo_v16hi = 4701,
    CODE_FOR_vec_unpacku_lo_v8hi = 4702,
    CODE_FOR_vec_unpacku_lo_v16si = 4703,
    CODE_FOR_vec_unpacku_lo_v8si = 4704,
    CODE_FOR_vec_unpacku_lo_v4si = 4705,
    CODE_FOR_vec_unpacku_hi_v32qi = 4706,
    CODE_FOR_vec_unpacku_hi_v16qi = 4707,
    CODE_FOR_vec_unpacku_hi_v32hi = 4708,
    CODE_FOR_vec_unpacku_hi_v16hi = 4709,
    CODE_FOR_vec_unpacku_hi_v8hi = 4710,
    CODE_FOR_vec_unpacku_hi_v16si = 4711,
    CODE_FOR_vec_unpacku_hi_v8si = 4712,
    CODE_FOR_vec_unpacku_hi_v4si = 4713,
    CODE_FOR_avx2_uavgv32qi3 = 4714,
    CODE_FOR_sse2_uavgv16qi3 = 4715,
    CODE_FOR_avx2_uavgv16hi3 = 4716,
    CODE_FOR_sse2_uavgv8hi3 = 4717,
    CODE_FOR_sse2_maskmovdqu = 4718,
    CODE_FOR_ssse3_pmulhrswv4hi3 = 4719,
    CODE_FOR_ssse3_pmulhrswv8hi3 = 4720,
    CODE_FOR_avx2_pmulhrswv16hi3 = 4721,
    CODE_FOR_absv32qi2 = 4722,
    CODE_FOR_absv16qi2 = 4723,
    CODE_FOR_absv16hi2 = 4724,
    CODE_FOR_absv8hi2 = 4725,
    CODE_FOR_absv16si2 = 4726,
    CODE_FOR_absv8si2 = 4727,
    CODE_FOR_absv4si2 = 4728,
    CODE_FOR_absv8di2 = 4729,
    CODE_FOR_avx2_pblendw = 4730,
    CODE_FOR_avx_roundps_sfix256 = 4731,
    CODE_FOR_sse4_1_roundps_sfix = 4732,
    CODE_FOR_avx512f_roundpd512 = 4733,
    CODE_FOR_avx512f_roundpd_vec_pack_sfix512 = 4734,
    CODE_FOR_avx_roundpd_vec_pack_sfix256 = 4735,
    CODE_FOR_sse4_1_roundpd_vec_pack_sfix = 4736,
    CODE_FOR_roundv16sf2 = 4737,
    CODE_FOR_roundv8sf2 = 4738,
    CODE_FOR_roundv4sf2 = 4739,
    CODE_FOR_roundv8df2 = 4740,
    CODE_FOR_roundv4df2 = 4741,
    CODE_FOR_roundv2df2 = 4742,
    CODE_FOR_roundv8sf2_sfix = 4743,
    CODE_FOR_roundv4sf2_sfix = 4744,
    CODE_FOR_roundv8df2_vec_pack_sfix = 4745,
    CODE_FOR_roundv4df2_vec_pack_sfix = 4746,
    CODE_FOR_roundv2df2_vec_pack_sfix = 4747,
    CODE_FOR_avx512pf_gatherpfv16sisf = 4752,
    CODE_FOR_avx512pf_gatherpfv8disf = 4753,
    CODE_FOR_avx512pf_gatherpfv8sidf = 4754,
    CODE_FOR_avx512pf_gatherpfv8didf = 4755,
    CODE_FOR_avx512pf_scatterpfv16sisf = 4756,
    CODE_FOR_avx512pf_scatterpfv8disf = 4757,
    CODE_FOR_avx512pf_scatterpfv8sidf = 4758,
    CODE_FOR_avx512pf_scatterpfv8didf = 4759,
    CODE_FOR_rotlv16qi3 = 4760,
    CODE_FOR_rotlv8hi3 = 4761,
    CODE_FOR_rotlv4si3 = 4762,
    CODE_FOR_rotlv2di3 = 4763,
    CODE_FOR_rotrv16qi3 = 4764,
    CODE_FOR_rotrv8hi3 = 4765,
    CODE_FOR_rotrv4si3 = 4766,
    CODE_FOR_rotrv2di3 = 4767,
    CODE_FOR_vrotrv16qi3 = 4768,
    CODE_FOR_vrotrv8hi3 = 4769,
    CODE_FOR_vrotrv4si3 = 4770,
    CODE_FOR_vrotrv2di3 = 4771,
    CODE_FOR_vrotlv16qi3 = 4772,
    CODE_FOR_vrotlv8hi3 = 4773,
    CODE_FOR_vrotlv4si3 = 4774,
    CODE_FOR_vrotlv2di3 = 4775,
    CODE_FOR_vlshrv16qi3 = 4776,
    CODE_FOR_vlshrv8hi3 = 4777,
    CODE_FOR_vlshrv4si3 = 4778,
    CODE_FOR_vlshrv2di3 = 4779,
    CODE_FOR_vlshrv16si3 = 4780,
    CODE_FOR_vlshrv8di3 = 4781,
    CODE_FOR_vlshrv8si3 = 4782,
    CODE_FOR_vlshrv4di3 = 4783,
    CODE_FOR_vashrv16qi3 = 4784,
    CODE_FOR_vashrv8hi3 = 4785,
    CODE_FOR_vashrv2di3 = 4786,
    CODE_FOR_vashrv4si3 = 4787,
    CODE_FOR_vashrv16si3 = 4788,
    CODE_FOR_vashrv8si3 = 4789,
    CODE_FOR_vashlv16qi3 = 4790,
    CODE_FOR_vashlv8hi3 = 4791,
    CODE_FOR_vashlv4si3 = 4792,
    CODE_FOR_vashlv2di3 = 4793,
    CODE_FOR_vashlv16si3 = 4794,
    CODE_FOR_vashlv8di3 = 4795,
    CODE_FOR_vashlv8si3 = 4796,
    CODE_FOR_vashlv4di3 = 4797,
    CODE_FOR_ashlv32qi3 = 4798,
    CODE_FOR_lshrv32qi3 = 4799,
    CODE_FOR_ashrv32qi3 = 4800,
    CODE_FOR_ashlv16qi3 = 4801,
    CODE_FOR_lshrv16qi3 = 4802,
    CODE_FOR_ashrv16qi3 = 4803,
    CODE_FOR_ashrv2di3 = 4804,
    CODE_FOR_xop_vmfrczv4sf2 = 4805,
    CODE_FOR_xop_vmfrczv2df2 = 4806,
    CODE_FOR_avx_vzeroall = 4807,
    CODE_FOR_avx2_permv4di = 4808,
    CODE_FOR_avx2_permv4df = 4809,
    CODE_FOR_avx512f_permv8di = 4810,
    CODE_FOR_avx512f_permv8df = 4811,
    CODE_FOR_avx512f_permv8df_mask = 4812,
    CODE_FOR_avx512f_permv8di_mask = 4813,
    CODE_FOR_avx512f_vpermilv8df = 4820,
    CODE_FOR_avx512f_vpermilv8df_mask = 4821,
    CODE_FOR_avx_vpermilv4df = 4822,
  #define CODE_FOR_avx_vpermilv4df_mask CODE_FOR_nothing
    CODE_FOR_avx_vpermilv2df = 4823,
  #define CODE_FOR_avx_vpermilv2df_mask CODE_FOR_nothing
    CODE_FOR_avx512f_vpermilv16sf = 4824,
    CODE_FOR_avx512f_vpermilv16sf_mask = 4825,
    CODE_FOR_avx_vpermilv8sf = 4826,
  #define CODE_FOR_avx_vpermilv8sf_mask CODE_FOR_nothing
    CODE_FOR_avx_vpermilv4sf = 4827,
  #define CODE_FOR_avx_vpermilv4sf_mask CODE_FOR_nothing
    CODE_FOR_avx512f_vpermi2varv16si3_maskz = 4828,
    CODE_FOR_avx512f_vpermi2varv16sf3_maskz = 4829,
    CODE_FOR_avx512f_vpermi2varv8di3_maskz = 4830,
    CODE_FOR_avx512f_vpermi2varv8df3_maskz = 4831,
    CODE_FOR_avx512f_vpermt2varv16si3_maskz = 4832,
    CODE_FOR_avx512f_vpermt2varv16sf3_maskz = 4833,
    CODE_FOR_avx512f_vpermt2varv8di3_maskz = 4834,
    CODE_FOR_avx512f_vpermt2varv8df3_maskz = 4835,
    CODE_FOR_avx_vperm2f128v8si3 = 4836,
    CODE_FOR_avx_vperm2f128v8sf3 = 4837,
    CODE_FOR_avx_vperm2f128v4df3 = 4838,
    CODE_FOR_avx_vinsertf128v32qi = 4839,
    CODE_FOR_avx_vinsertf128v16hi = 4840,
    CODE_FOR_avx_vinsertf128v8si = 4841,
    CODE_FOR_avx_vinsertf128v4di = 4842,
    CODE_FOR_avx_vinsertf128v8sf = 4843,
    CODE_FOR_avx_vinsertf128v4df = 4844,
    CODE_FOR_maskloadv4sf = 4845,
    CODE_FOR_maskloadv2df = 4846,
    CODE_FOR_maskloadv8sf = 4847,
    CODE_FOR_maskloadv4df = 4848,
    CODE_FOR_maskloadv4si = 4849,
    CODE_FOR_maskloadv2di = 4850,
    CODE_FOR_maskloadv8si = 4851,
    CODE_FOR_maskloadv4di = 4852,
    CODE_FOR_maskstorev4sf = 4853,
    CODE_FOR_maskstorev2df = 4854,
    CODE_FOR_maskstorev8sf = 4855,
    CODE_FOR_maskstorev4df = 4856,
    CODE_FOR_maskstorev4si = 4857,
    CODE_FOR_maskstorev2di = 4858,
    CODE_FOR_maskstorev8si = 4859,
    CODE_FOR_maskstorev4di = 4860,
    CODE_FOR_vec_initv32qi = 4864,
    CODE_FOR_vec_initv16hi = 4865,
    CODE_FOR_vec_initv8si = 4866,
    CODE_FOR_vec_initv4di = 4867,
    CODE_FOR_vec_initv8sf = 4868,
    CODE_FOR_vec_initv4df = 4869,
    CODE_FOR_vec_initv16si = 4870,
    CODE_FOR_vec_initv16sf = 4871,
    CODE_FOR_vec_initv8di = 4872,
    CODE_FOR_vec_initv8df = 4873,
    CODE_FOR_avx2_extracti128 = 4874,
    CODE_FOR_avx2_inserti128 = 4875,
    CODE_FOR_vcvtps2ph = 4876,
    CODE_FOR_avx2_gathersiv2di = 4877,
    CODE_FOR_avx2_gathersiv2df = 4878,
    CODE_FOR_avx2_gathersiv4di = 4879,
    CODE_FOR_avx2_gathersiv4df = 4880,
    CODE_FOR_avx2_gathersiv4si = 4881,
    CODE_FOR_avx2_gathersiv4sf = 4882,
    CODE_FOR_avx2_gathersiv8si = 4883,
    CODE_FOR_avx2_gathersiv8sf = 4884,
    CODE_FOR_avx2_gatherdiv2di = 4885,
    CODE_FOR_avx2_gatherdiv2df = 4886,
    CODE_FOR_avx2_gatherdiv4di = 4887,
    CODE_FOR_avx2_gatherdiv4df = 4888,
    CODE_FOR_avx2_gatherdiv4si = 4889,
    CODE_FOR_avx2_gatherdiv4sf = 4890,
    CODE_FOR_avx2_gatherdiv8si = 4891,
    CODE_FOR_avx2_gatherdiv8sf = 4892,
    CODE_FOR_avx512f_gathersiv16si = 4893,
    CODE_FOR_avx512f_gathersiv16sf = 4894,
    CODE_FOR_avx512f_gathersiv8di = 4895,
    CODE_FOR_avx512f_gathersiv8df = 4896,
    CODE_FOR_avx512f_gatherdiv16si = 4897,
    CODE_FOR_avx512f_gatherdiv16sf = 4898,
    CODE_FOR_avx512f_gatherdiv8di = 4899,
    CODE_FOR_avx512f_gatherdiv8df = 4900,
    CODE_FOR_avx512f_scattersiv16si = 4901,
    CODE_FOR_avx512f_scattersiv16sf = 4902,
    CODE_FOR_avx512f_scattersiv8di = 4903,
    CODE_FOR_avx512f_scattersiv8df = 4904,
    CODE_FOR_avx512f_scatterdiv16si = 4905,
    CODE_FOR_avx512f_scatterdiv16sf = 4906,
    CODE_FOR_avx512f_scatterdiv8di = 4907,
    CODE_FOR_avx512f_scatterdiv8df = 4908,
    CODE_FOR_avx512f_expandv16si_maskz = 4909,
    CODE_FOR_avx512f_expandv16sf_maskz = 4910,
    CODE_FOR_avx512f_expandv8di_maskz = 4911,
    CODE_FOR_avx512f_expandv8df_maskz = 4912,
    CODE_FOR_sse2_lfence = 4913,
    CODE_FOR_sse_sfence = 4914,
    CODE_FOR_sse2_mfence = 4915,
    CODE_FOR_mem_thread_fence = 4916,
    CODE_FOR_atomic_loadqi = 4917,
    CODE_FOR_atomic_loadhi = 4918,
    CODE_FOR_atomic_loadsi = 4919,
    CODE_FOR_atomic_loaddi = 4920,
    CODE_FOR_atomic_storeqi = 4922,
    CODE_FOR_atomic_storehi = 4923,
    CODE_FOR_atomic_storesi = 4924,
    CODE_FOR_atomic_storedi = 4925,
    CODE_FOR_atomic_compare_and_swapqi = 4927,
    CODE_FOR_atomic_compare_and_swaphi = 4928,
    CODE_FOR_atomic_compare_and_swapsi = 4929,
    CODE_FOR_atomic_compare_and_swapdi = 4930,
  #define CODE_FOR_atomic_compare_and_swapti CODE_FOR_nothing
    LAST_INSN_CODE
  };
  
  #endif /* GCC_INSN_CODES_H */
  