text: #ifndef INCLUDED_CYFITTER_H
  #define INCLUDED_CYFITTER_H
  #include "cydevice.h"
  #include "cydevice_trm.h"
  
  /* DMA_1 */
  #define DMA_1__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
  #define DMA_1__DRQ_NUMBER 0u
  #define DMA_1__NUMBEROF_TDS 0u
  #define DMA_1__PRIORITY 2u
  #define DMA_1__TERMIN_EN 0u
  #define DMA_1__TERMIN_SEL 0u
  #define DMA_1__TERMOUT0_EN 0u
  #define DMA_1__TERMOUT0_SEL 0u
  #define DMA_1__TERMOUT1_EN 0u
  #define DMA_1__TERMOUT1_SEL 0u
  
  /* Clock_1 */
  #define Clock_1__CFG0 CYREG_CLKDIST_DCFG0_CFG0
  #define Clock_1__CFG1 CYREG_CLKDIST_DCFG0_CFG1
  #define Clock_1__CFG2 CYREG_CLKDIST_DCFG0_CFG2
  #define Clock_1__CFG2_SRC_SEL_MASK 0x07u
  #define Clock_1__INDEX 0x00u
  #define Clock_1__PM_ACT_CFG CYREG_PM_ACT_CFG2
  #define Clock_1__PM_ACT_MSK 0x01u
  #define Clock_1__PM_STBY_CFG CYREG_PM_STBY_CFG2
  #define Clock_1__PM_STBY_MSK 0x01u
  
  /* Status_Reg_1 */
  #define Status_Reg_1_sts_sts_reg__0__MASK 0x01u
  #define Status_Reg_1_sts_sts_reg__0__POS 0
  #define Status_Reg_1_sts_sts_reg__1__MASK 0x02u
  #define Status_Reg_1_sts_sts_reg__1__POS 1
  #define Status_Reg_1_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
  #define Status_Reg_1_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST
  #define Status_Reg_1_sts_sts_reg__2__MASK 0x04u
  #define Status_Reg_1_sts_sts_reg__2__POS 2
  #define Status_Reg_1_sts_sts_reg__MASK 0x07u
  #define Status_Reg_1_sts_sts_reg__MASK_REG CYREG_B0_UDB10_MSK
  #define Status_Reg_1_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL
  #define Status_Reg_1_sts_sts_reg__STATUS_REG CYREG_B0_UDB10_ST
  
  /* STC_Datapath16_v1_00 */
  #define STC_Datapath16_v1_00_datapath_u0__16BIT_A0_REG CYREG_B0_UDB10_11_A0
  #define STC_Datapath16_v1_00_datapath_u0__16BIT_A1_REG CYREG_B0_UDB10_11_A1
  #define STC_Datapath16_v1_00_datapath_u0__16BIT_D0_REG CYREG_B0_UDB10_11_D0
  #define STC_Datapath16_v1_00_datapath_u0__16BIT_D1_REG CYREG_B0_UDB10_11_D1
  #define STC_Datapath16_v1_00_datapath_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
  #define STC_Datapath16_v1_00_datapath_u0__16BIT_F0_REG CYREG_B0_UDB10_11_F0
  #define STC_Datapath16_v1_00_datapath_u0__16BIT_F1_REG CYREG_B0_UDB10_11_F1
  #define STC_Datapath16_v1_00_datapath_u0__A0_A1_REG CYREG_B0_UDB10_A0_A1
  #define STC_Datapath16_v1_00_datapath_u0__A0_REG CYREG_B0_UDB10_A0
  #define STC_Datapath16_v1_00_datapath_u0__A1_REG CYREG_B0_UDB10_A1
  #define STC_Datapath16_v1_00_datapath_u0__D0_D1_REG CYREG_B0_UDB10_D0_D1
  #define STC_Datapath16_v1_00_datapath_u0__D0_REG CYREG_B0_UDB10_D0
  #define STC_Datapath16_v1_00_datapath_u0__D1_REG CYREG_B0_UDB10_D1
  #define STC_Datapath16_v1_00_datapath_u0__DP_AUX_CTL_REG CYREG_B0_UDB10_ACTL
  #define STC_Datapath16_v1_00_datapath_u0__F0_F1_REG CYREG_B0_UDB10_F0_F1
  #define STC_Datapath16_v1_00_datapath_u0__F0_REG CYREG_B0_UDB10_F0
  #define STC_Datapath16_v1_00_datapath_u0__F1_REG CYREG_B0_UDB10_F1
  #define STC_Datapath16_v1_00_datapath_u1__16BIT_A0_REG CYREG_B0_UDB11_12_A0
  #define STC_Datapath16_v1_00_datapath_u1__16BIT_A1_REG CYREG_B0_UDB11_12_A1
  #define STC_Datapath16_v1_00_datapath_u1__16BIT_D0_REG CYREG_B0_UDB11_12_D0
  #define STC_Datapath16_v1_00_datapath_u1__16BIT_D1_REG CYREG_B0_UDB11_12_D1
  #define STC_Datapath16_v1_00_datapath_u1__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
  #define STC_Datapath16_v1_00_datapath_u1__16BIT_F0_REG CYREG_B0_UDB11_12_F0
  #define STC_Datapath16_v1_00_datapath_u1__16BIT_F1_REG CYREG_B0_UDB11_12_F1
  #define STC_Datapath16_v1_00_datapath_u1__A0_A1_REG CYREG_B0_UDB11_A0_A1
  #define STC_Datapath16_v1_00_datapath_u1__A0_REG CYREG_B0_UDB11_A0
  #define STC_Datapath16_v1_00_datapath_u1__A1_REG CYREG_B0_UDB11_A1
  #define STC_Datapath16_v1_00_datapath_u1__D0_D1_REG CYREG_B0_UDB11_D0_D1
  #define STC_Datapath16_v1_00_datapath_u1__D0_REG CYREG_B0_UDB11_D0
  #define STC_Datapath16_v1_00_datapath_u1__D1_REG CYREG_B0_UDB11_D1
  #define STC_Datapath16_v1_00_datapath_u1__DP_AUX_CTL_REG CYREG_B0_UDB11_ACTL
  #define STC_Datapath16_v1_00_datapath_u1__F0_F1_REG CYREG_B0_UDB11_F0_F1
  #define STC_Datapath16_v1_00_datapath_u1__F0_REG CYREG_B0_UDB11_F0
  #define STC_Datapath16_v1_00_datapath_u1__F1_REG CYREG_B0_UDB11_F1
  
  /* Miscellaneous */
  #define BCLK__BUS_CLK__HZ 24000000U
  #define BCLK__BUS_CLK__KHZ 24000U
  #define BCLK__BUS_CLK__MHZ 24U
  #define CY_PROJECT_NAME "Design01"
  #define CY_VERSION "PSoC Creator  3.2 SP1"
  #define CYDEV_CHIP_DIE_GEN4 2u
  #define CYDEV_CHIP_DIE_LEOPARD 1u
  #define CYDEV_CHIP_DIE_PANTHER 13u
  #define CYDEV_CHIP_DIE_PSOC4A 6u
  #define CYDEV_CHIP_DIE_PSOC5LP 12u
  #define CYDEV_CHIP_DIE_UNKNOWN 0u
  #define CYDEV_CHIP_FAMILY_PSOC3 1u
  #define CYDEV_CHIP_FAMILY_PSOC4 2u
  #define CYDEV_CHIP_FAMILY_PSOC5 3u
  #define CYDEV_CHIP_FAMILY_UNKNOWN 0u
  #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
  #define CYDEV_CHIP_JTAG_ID 0x2E123069u
  #define CYDEV_CHIP_MEMBER_3A 1u
  #define CYDEV_CHIP_MEMBER_4A 6u
  #define CYDEV_CHIP_MEMBER_4C 10u
  #define CYDEV_CHIP_MEMBER_4D 3u
  #define CYDEV_CHIP_MEMBER_4E 5u
  #define CYDEV_CHIP_MEMBER_4F 7u
  #define CYDEV_CHIP_MEMBER_4G 2u
  #define CYDEV_CHIP_MEMBER_4H 4u
  #define CYDEV_CHIP_MEMBER_4L 9u
  #define CYDEV_CHIP_MEMBER_4M 8u
  #define CYDEV_CHIP_MEMBER_5A 12u
  #define CYDEV_CHIP_MEMBER_5B 11u
  #define CYDEV_CHIP_MEMBER_UNKNOWN 0u
  #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
  #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
  #define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
  #define CYDEV_CHIP_REV_GEN4_ES 17u
  #define CYDEV_CHIP_REV_GEN4_ES2 33u
  #define CYDEV_CHIP_REV_GEN4_PRODUCTION 17u
  #define CYDEV_CHIP_REV_LEOPARD_ES1 0u
  #define CYDEV_CHIP_REV_LEOPARD_ES2 1u
  #define CYDEV_CHIP_REV_LEOPARD_ES3 3u
  #define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
  #define CYDEV_CHIP_REV_PANTHER_ES0 0u
  #define CYDEV_CHIP_REV_PANTHER_ES1 1u
  #define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
  #define CYDEV_CHIP_REV_PSOC4A_ES0 17u
  #define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
  #define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
  #define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
  #define CYDEV_CHIP_REVISION_3A_ES1 0u
  #define CYDEV_CHIP_REVISION_3A_ES2 1u
  #define CYDEV_CHIP_REVISION_3A_ES3 3u
  #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
  #define CYDEV_CHIP_REVISION_4A_ES0 17u
  #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
  #define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u
  #define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
  #define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
  #define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
  #define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
  #define CYDEV_CHIP_REVISION_4G_ES 17u
  #define CYDEV_CHIP_REVISION_4G_ES2 33u
  #define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
  #define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u
  #define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
  #define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
  #define CYDEV_CHIP_REVISION_5A_ES0 0u
  #define CYDEV_CHIP_REVISION_5A_ES1 1u
  #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
  #define CYDEV_CHIP_REVISION_5B_ES0 0u
  #define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
  #define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION
  #define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
  #define CYDEV_CONFIG_FASTBOOT_ENABLED 1
  #define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
  #define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
  #define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
  #define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
  #define CYDEV_CONFIGURATION_COMPRESSED 1
  #define CYDEV_CONFIGURATION_DMA 0
  #define CYDEV_CONFIGURATION_ECC 1
  #define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
  #define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
  #define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
  #define CYDEV_CONFIGURATION_MODE_DMA 2
  #define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
  #define CYDEV_DEBUG_ENABLE_MASK 0x20u
  #define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
  #define CYDEV_DEBUGGING_DPS_Disable 3
  #define CYDEV_DEBUGGING_DPS_JTAG_4 1
  #define CYDEV_DEBUGGING_DPS_JTAG_5 0
  #define CYDEV_DEBUGGING_DPS_SWD 2
  #define CYDEV_DEBUGGING_DPS_SWD_SWV 6
  #define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
  #define CYDEV_DEBUGGING_ENABLE 1
  #define CYDEV_DEBUGGING_XRES 0
  #define CYDEV_DMA_CHANNELS_AVAILABLE 24u
  #define CYDEV_ECC_ENABLE 0
  #define CYDEV_HEAP_SIZE 0x80
  #define CYDEV_INSTRUCT_CACHE_ENABLED 1
  #define CYDEV_INTR_RISING 0x00000000u
  #define CYDEV_PROJ_TYPE 0
  #define CYDEV_PROJ_TYPE_BOOTLOADER 1
  #define CYDEV_PROJ_TYPE_LAUNCHER 5
  #define CYDEV_PROJ_TYPE_LOADABLE 2
  #define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
  #define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
  #define CYDEV_PROJ_TYPE_STANDARD 0
  #define CYDEV_PROTECTION_ENABLE 0
  #define CYDEV_STACK_SIZE 0x0800
  #define CYDEV_USE_BUNDLED_CMSIS 1
  #define CYDEV_VARIABLE_VDDA 0
  #define CYDEV_VDDA 5.0
  #define CYDEV_VDDA_MV 5000
  #define CYDEV_VDDD 5.0
  #define CYDEV_VDDD_MV 5000
  #define CYDEV_VDDIO0 5.0
  #define CYDEV_VDDIO0_MV 5000
  #define CYDEV_VDDIO1 5.0
  #define CYDEV_VDDIO1_MV 5000
  #define CYDEV_VDDIO2 5.0
  #define CYDEV_VDDIO2_MV 5000
  #define CYDEV_VDDIO3 5.0
  #define CYDEV_VDDIO3_MV 5000
  #define CYDEV_VIO0 5.0
  #define CYDEV_VIO0_MV 5000
  #define CYDEV_VIO1 5.0
  #define CYDEV_VIO1_MV 5000
  #define CYDEV_VIO2 5.0
  #define CYDEV_VIO2_MV 5000
  #define CYDEV_VIO3 5.0
  #define CYDEV_VIO3_MV 5000
  #define CYIPBLOCK_ARM_CM3_VERSION 0
  #define CYIPBLOCK_P3_ANAIF_VERSION 0
  #define CYIPBLOCK_P3_CAN_VERSION 0
  #define CYIPBLOCK_P3_CAPSENSE_VERSION 0
  #define CYIPBLOCK_P3_COMP_VERSION 0
  #define CYIPBLOCK_P3_DECIMATOR_VERSION 0
  #define CYIPBLOCK_P3_DFB_VERSION 0
  #define CYIPBLOCK_P3_DMA_VERSION 0
  #define CYIPBLOCK_P3_DRQ_VERSION 0
  #define CYIPBLOCK_P3_DSM_VERSION 0
  #define CYIPBLOCK_P3_EMIF_VERSION 0
  #define CYIPBLOCK_P3_I2C_VERSION 0
  #define CYIPBLOCK_P3_LCD_VERSION 0
  #define CYIPBLOCK_P3_LPF_VERSION 0
  #define CYIPBLOCK_P3_OPAMP_VERSION 0
  #define CYIPBLOCK_P3_PM_VERSION 0
  #define CYIPBLOCK_P3_SCCT_VERSION 0
  #define CYIPBLOCK_P3_TIMER_VERSION 0
  #define CYIPBLOCK_P3_USB_VERSION 0
  #define CYIPBLOCK_P3_VIDAC_VERSION 0
  #define CYIPBLOCK_P3_VREF_VERSION 0
  #define CYIPBLOCK_S8_GPIO_VERSION 0
  #define CYIPBLOCK_S8_IRQ_VERSION 0
  #define CYIPBLOCK_S8_SAR_VERSION 0
  #define CYIPBLOCK_S8_SIO_VERSION 0
  #define CYIPBLOCK_S8_UDB_VERSION 0
  #define DMA_CHANNELS_USED__MASK0 0x00000001u
  #define CYDEV_BOOTLOADER_ENABLE 0
  
  #endif /* INCLUDED_CYFITTER_H */
  