text: /*
   * Copyright (c) 2012, Freescale Semiconductor, Inc.
   * All rights reserved.
   *
   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
   * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
   * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
   * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
   * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
   * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   */
  
  // File: eim_iomux_config.c
  
  /* ------------------------------------------------------------------------------
   * <auto-generated>
   *     This code was generated by a tool.
   *     Runtime Version:3.4.0.0
   *
   *     Changes to this file may cause incorrect behavior and will be lost if
   *     the code is regenerated.
   * </auto-generated>
   * ------------------------------------------------------------------------------
  */
  
  #include "iomux_config.h"
  #include "registers/regsiomuxc.h"
  
  // Function to configure IOMUXC for eim module.
  void eim_iomux_config(void)
  {
      // Config eim.EIM_AD00 to pad EIM_AD00(L20)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD00(0x020E0184)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD00
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA09
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA09
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO00
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG00
      //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCLK_N
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD00(0x020E0554)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00_SRE_V(FAST));
  
      // Config eim.EIM_AD01 to pad EIM_AD01(J25)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD01(0x020E0188)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD01
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA08
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA08
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO01
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG01
      //     ALT8 (8) - Select instance: epdc signal: EPDC_SDLE
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD01(0x020E0558)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01_SRE_V(FAST));
  
      // Config eim.EIM_AD02 to pad EIM_AD02(L21)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD02(0x020E01A4)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD02
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA07
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA07
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO02
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG02
      //     ALT8 (8) - Select instance: epdc signal: EPDC_BDR0
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD02(0x020E0574)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02_SRE_V(FAST));
  
      // Config eim.EIM_AD03 to pad EIM_AD03(K24)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD03(0x020E01A8)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD03
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA06
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA06
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO03
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG03
      //     ALT8 (8) - Select instance: epdc signal: EPDC_BDR1
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD03(0x020E0578)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03_SRE_V(FAST));
  
      // Config eim.EIM_AD04 to pad EIM_AD04(L22)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD04(0x020E01AC)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD04
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA05
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA05
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO04
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG04
      //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE0
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD04(0x020E057C)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04_SRE_V(FAST));
  
      // Config eim.EIM_AD05 to pad EIM_AD05(L23)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD05(0x020E01B0)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD05
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA04
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA04
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO05
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG05
      //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE1
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD05(0x020E0580)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05_SRE_V(FAST));
  
      // Config eim.EIM_AD06 to pad EIM_AD06(K25)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD06(0x020E01B4)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD06
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA03
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA03
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO06
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG06
      //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE2
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD06(0x020E0584)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06_SRE_V(FAST));
  
      // Config eim.EIM_AD07 to pad EIM_AD07(L25)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD07(0x020E01B8)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD07
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA02
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA02
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO07
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG07
      //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE3
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD07(0x020E0588)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07_SRE_V(FAST));
  
      // Config eim.EIM_AD08 to pad EIM_AD08(L24)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD08(0x020E01BC)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD08
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA01
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA01
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO08
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG08
      //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE4
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD08(0x020E058C)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08_SRE_V(FAST));
  
      // Config eim.EIM_AD09 to pad EIM_AD09(M21)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD09(0x020E01C0)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD09
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA00
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA00
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO09
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG09
      //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE5
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD09(0x020E0590)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09_SRE_V(FAST));
  
      // Config eim.EIM_AD10 to pad EIM_AD10(M22)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD10(0x020E018C)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD10
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN15
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA_EN
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO10
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG10
      //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA01
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD10(0x020E055C)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10_SRE_V(FAST));
  
      // Config eim.EIM_AD11 to pad EIM_AD11(M20)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD11(0x020E0190)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD11
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN02
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_HSYNC
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO11
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG11
      //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA03
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD11(0x020E0560)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11_SRE_V(FAST));
  
      // Config eim.EIM_AD12 to pad EIM_AD12(M24)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD12(0x020E0194)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD12
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN03
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_VSYNC
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO12
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG12
      //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA02
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD12(0x020E0564)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12_SRE_V(FAST));
  
      // Config eim.EIM_AD13 to pad EIM_AD13(M23)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD13(0x020E0198)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD13
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_D0_CS
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO13
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG13
      //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA13
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD13(0x020E0568)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13_SRE_V(FAST));
  
      // Config eim.EIM_AD14 to pad EIM_AD14(N23)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD14(0x020E019C)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD14
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_D1_CS
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO14
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG14
      //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA14
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD14(0x020E056C)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14_SRE_V(FAST));
  
      // Config eim.EIM_AD15 to pad EIM_AD15(N24)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_AD15(0x020E01A0)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_AD15
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN01
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI1_PIN04
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO15
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG15
      //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA09
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_AD15(0x020E0570)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15_SRE_V(FAST));
  
      // Config eim.EIM_ADDR16 to pad EIM_ADDR16(H25)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16(0x020E0110)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_ADDR16
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_DISP_CLK
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_PIXCLK
      //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO22
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG16
      //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA00
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16(0x020E04E0)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16_SRE_V(FAST));
  
      // Config eim.EIM_ADDR17 to pad EIM_ADDR17(G24)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17(0x020E0114)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_ADDR17
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA12
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA12
      //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO21
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG17
      //     ALT8 (8) - Select instance: epdc signal: EPDC_PWR_STAT
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17(0x020E04E4)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17_SRE_V(FAST));
  
      // Config eim.EIM_ADDR18 to pad EIM_ADDR18(J22)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18(0x020E0118)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_ADDR18
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA13
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA13
      //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO20
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG18
      //     ALT8 (8) - Select instance: epdc signal: EPDC_PWR_CTRL0
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18(0x020E04E8)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18_SRE_V(FAST));
  
      // Config eim.EIM_ADDR19 to pad EIM_ADDR19(G25)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19(0x020E011C)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_ADDR19
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA14
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA14
      //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO19
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG19
      //     ALT8 (8) - Select instance: epdc signal: EPDC_PWR_CTRL1
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19(0x020E04EC)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19_SRE_V(FAST));
  
      // Config eim.EIM_ADDR20 to pad EIM_ADDR20(H22)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20(0x020E0120)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_ADDR20
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA15
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA15
      //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO18
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG20
      //     ALT8 (8) - Select instance: epdc signal: EPDC_PWR_CTRL2
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20(0x020E04F0)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20_SRE_V(FAST));
  
      // Config eim.EIM_ADDR21 to pad EIM_ADDR21(H23)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21(0x020E0124)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_ADDR21
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA16
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA16
      //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO17
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG21
      //     ALT8 (8) - Select instance: epdc signal: EPDC_GDCLK
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21(0x020E04F4)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21_SRE_V(FAST));
  
      // Config eim.EIM_ADDR22 to pad EIM_ADDR22(F24)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22(0x020E0128)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_ADDR22
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA17
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA17
      //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO16
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG22
      //     ALT8 (8) - Select instance: epdc signal: EPDC_GDSP
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22(0x020E04F8)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22_SRE_V(FAST));
  
      // Config eim.EIM_ADDR23 to pad EIM_ADDR23(J21)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23(0x020E012C)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_ADDR23
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA18
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI1_DATA18
      //     ALT4 (4) - Select instance: ipu1 signal: IPU1_SISG3
      //     ALT5 (5) - Select instance: gpio6 signal: GPIO6_IO06
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG23
      //     ALT8 (8) - Select instance: epdc signal: EPDC_GDOE
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23(0x020E04FC)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23_SRE_V(FAST));
  
      // Config eim.EIM_CS0 to pad EIM_CS0(H24)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_CS0(0x020E013C)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_CS0
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN05
      //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_SCLK
      //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO23
      //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA06
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_CS0(0x020E050C)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_SRE_V(FAST));
  
      // Config eim.EIM_DATA16 to pad EIM_DATA16(C25)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16(0x020E0144)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA16
      //     ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_SCLK
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN05
      //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA18
      //     ALT4 (4) - Select instance: hdmi signal: HDMI_TX_DDC_SDA
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO16
      //     ALT6 (6) - Select instance: i2c2 signal: I2C2_SDA
      //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA10
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16(0x020E0514)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16_SRE_V(SLOW));
  
      // Config eim.EIM_DATA17 to pad EIM_DATA17(F21)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17(0x020E0148)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA17
      //     ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_MISO
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN06
      //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_PIXCLK
      //     ALT4 (4) - Select instance: dcic1 signal: DCIC1_OUT
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO17
      //     ALT6 (6) - Select instance: i2c3 signal: I2C3_SCL
      //     ALT8 (8) - Select instance: epdc signal: EPDC_VCOM0
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17(0x020E0518)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17_SRE_V(SLOW));
  
      // Config eim.EIM_DATA18 to pad EIM_DATA18(D24)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18(0x020E014C)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA18
      //     ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_MOSI
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN07
      //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA17
      //     ALT4 (4) - Select instance: ipu1 signal: IPU1_DI1_D0_CS
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO18
      //     ALT6 (6) - Select instance: i2c3 signal: I2C3_SDA
      //     ALT8 (8) - Select instance: epdc signal: EPDC_VCOM1
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18(0x020E051C)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18_SRE_V(SLOW));
  
      // Config eim.EIM_DATA19 to pad EIM_DATA19(G21)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19(0x020E0150)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA19
      //     ALT1 (1) - Select instance: ecspi1 signal: ECSPI1_SS1
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN08
      //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA16
      //     ALT4 (4) - Select instance: uart1 signal: UART1_CTS_B
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO19
      //     ALT6 (6) - Select instance: epit1 signal: EPIT1_OUT
      //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA12
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19(0x020E0520)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19_SRE_V(SLOW));
  
      // Config eim.EIM_DATA20 to pad EIM_DATA20(G20)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20(0x020E0154)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA20
      //     ALT1 (1) - Select instance: ecspi4 signal: ECSPI4_SS0
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN16
      //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA15
      //     ALT4 (4) - Select instance: uart1 signal: UART1_RTS_B
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO20
      //     ALT6 (6) - Select instance: epit2 signal: EPIT2_OUT
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20(0x020E0524)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20_SRE_V(SLOW));
  
      // Config eim.EIM_DATA21 to pad EIM_DATA21(H20)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21(0x020E0158)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA21
      //     ALT1 (1) - Select instance: ecspi4 signal: ECSPI4_SCLK
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN17
      //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA11
      //     ALT4 (4) - Select instance: usb signal: USB_OTG_OC
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO21
      //     ALT6 (6) - Select instance: i2c1 signal: I2C1_SCL
      //     ALT7 (7) - Select instance: spdif signal: SPDIF_IN
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21(0x020E0528)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21_SRE_V(SLOW));
  
      // Config eim.EIM_DATA22 to pad EIM_DATA22(E23)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22(0x020E015C)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA22
      //     ALT1 (1) - Select instance: ecspi4 signal: ECSPI4_MISO
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN01
      //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA10
      //     ALT4 (4) - Select instance: usb signal: USB_OTG_PWR
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO22
      //     ALT6 (6) - Select instance: spdif signal: SPDIF_OUT
      //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE6
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22(0x020E052C)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22_SRE_V(SLOW));
  
      // Config eim.EIM_DATA23 to pad EIM_DATA23(D25)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23(0x020E0160)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA23
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI0_D0_CS
      //     ALT2 (2) - Select instance: uart3 signal: UART3_CTS_B
      //     ALT3 (3) - Select instance: uart1 signal: UART1_DCD_B
      //     ALT4 (4) - Select instance: ipu1 signal: IPU1_CSI1_DATA_EN
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO23
      //     ALT6 (6) - Select instance: ipu1 signal: IPU1_DI1_PIN02
      //     ALT7 (7) - Select instance: ipu1 signal: IPU1_DI1_PIN14
      //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA11
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23(0x020E0530)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23_SRE_V(SLOW));
  
      // Config eim.EIM_DATA24 to pad EIM_DATA24(F22)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24(0x020E0164)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA24
      //     ALT1 (1) - Select instance: ecspi4 signal: ECSPI4_SS2
      //     ALT2 (2) - Select instance: uart3 signal: UART3_TX_DATA
      //     ALT3 (3) - Select instance: ecspi1 signal: ECSPI1_SS2
      //     ALT4 (4) - Select instance: ecspi2 signal: ECSPI2_SS2
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO24
      //     ALT6 (6) - Select instance: audmux signal: AUD5_RXFS
      //     ALT7 (7) - Select instance: uart1 signal: UART1_DTR_B
      //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE7
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24(0x020E0534)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24_SRE_V(SLOW));
  
      // Config eim.EIM_DATA25 to pad EIM_DATA25(G22)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25(0x020E0168)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA25
      //     ALT1 (1) - Select instance: ecspi4 signal: ECSPI4_SS3
      //     ALT2 (2) - Select instance: uart3 signal: UART3_RX_DATA
      //     ALT3 (3) - Select instance: ecspi1 signal: ECSPI1_SS3
      //     ALT4 (4) - Select instance: ecspi2 signal: ECSPI2_SS3
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO25
      //     ALT6 (6) - Select instance: audmux signal: AUD5_RXC
      //     ALT7 (7) - Select instance: uart1 signal: UART1_DSR_B
      //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCE8
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25(0x020E0538)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25_SRE_V(SLOW));
  
      // Config eim.EIM_DATA26 to pad EIM_DATA26(E24)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26(0x020E016C)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA26
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN11
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI0_DATA01
      //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA14
      //     ALT4 (4) - Select instance: uart2 signal: UART2_TX_DATA
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO26
      //     ALT6 (6) - Select instance: ipu1 signal: IPU1_SISG2
      //     ALT7 (7) - Select instance: ipu1 signal: IPU1_DISP1_DATA22
      //     ALT8 (8) - Select instance: epdc signal: EPDC_SDOED
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26(0x020E053C)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26_SRE_V(SLOW));
  
      // Config eim.EIM_DATA27 to pad EIM_DATA27(E25)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27(0x020E0170)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA27
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN13
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_CSI0_DATA00
      //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA13
      //     ALT4 (4) - Select instance: uart2 signal: UART2_RX_DATA
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO27
      //     ALT6 (6) - Select instance: ipu1 signal: IPU1_SISG3
      //     ALT7 (7) - Select instance: ipu1 signal: IPU1_DISP1_DATA23
      //     ALT8 (8) - Select instance: epdc signal: EPDC_SDOE
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27(0x020E0540)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27_SRE_V(SLOW));
  
      // Config eim.EIM_DATA28 to pad EIM_DATA28(G23)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28(0x020E0174)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA28
      //     ALT1 (1) - Select instance: i2c1 signal: I2C1_SDA
      //     ALT2 (2) - Select instance: ecspi4 signal: ECSPI4_MOSI
      //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI1_DATA12
      //     ALT4 (4) - Select instance: uart2 signal: UART2_CTS_B
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO28
      //     ALT6 (6) - Select instance: ipu1 signal: IPU1_EXT_TRIG
      //     ALT7 (7) - Select instance: ipu1 signal: IPU1_DI0_PIN13
      //     ALT8 (8) - Select instance: epdc signal: EPDC_PWR_CTRL3
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28(0x020E0544)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28_SRE_V(SLOW));
  
      // Config eim.EIM_DATA29 to pad EIM_DATA29(J19)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29(0x020E0178)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA29
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN15
      //     ALT2 (2) - Select instance: ecspi4 signal: ECSPI4_SS0
      //     ALT4 (4) - Select instance: uart2 signal: UART2_RTS_B
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO29
      //     ALT6 (6) - Select instance: ipu1 signal: IPU1_CSI1_VSYNC
      //     ALT7 (7) - Select instance: ipu1 signal: IPU1_DI0_PIN14
      //     ALT8 (8) - Select instance: epdc signal: EPDC_PWR_WAKE
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29(0x020E0548)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29_SRE_V(SLOW));
  
      // Config eim.EIM_DATA30 to pad EIM_DATA30(J20)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30(0x020E017C)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA30
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA21
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN11
      //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI0_DATA03
      //     ALT4 (4) - Select instance: uart3 signal: UART3_CTS_B
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO30
      //     ALT6 (6) - Select instance: usb signal: USB_H1_OC
      //     ALT8 (8) - Select instance: epdc signal: EPDC_SDOEZ
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30(0x020E054C)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30_SRE_V(SLOW));
  
      // Config eim.EIM_DATA31 to pad EIM_DATA31(H21)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR(0x0001B0B0);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31(0x020E0180)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT5
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_DATA31
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DISP1_DATA20
      //     ALT2 (2) - Select instance: ipu1 signal: IPU1_DI0_PIN12
      //     ALT3 (3) - Select instance: ipu1 signal: IPU1_CSI0_DATA02
      //     ALT4 (4) - Select instance: uart3 signal: UART3_RTS_B
      //     ALT5 (5) - Select instance: gpio3 signal: GPIO3_IO31
      //     ALT6 (6) - Select instance: usb signal: USB_H1_PWR
      //     ALT8 (8) - Select instance: epdc signal: EPDC_SDCLK_P
      //     ALT9 (9) - Select instance: eim signal: EIM_ACLK_FREERUN
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31(0x020E0550)
      //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_HYS_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31_SRE_V(SLOW));
  
      // Config eim.EIM_OE to pad EIM_OE(J24)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_OE(0x020E01D8)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_OE
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN07
      //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_MISO
      //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO25
      //     ALT8 (8) - Select instance: epdc signal: EPDC_PWR_IRQ
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_OE(0x020E05A8)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_SRE_V(FAST));
  
      // Config eim.EIM_RW to pad EIM_RW(K20)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR(0x0000B0B1);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_RW(0x020E01DC)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [3:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_RW
      //     ALT1 (1) - Select instance: ipu1 signal: IPU1_DI1_PIN08
      //     ALT2 (2) - Select instance: ecspi2 signal: ECSPI2_SS0
      //     ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO26
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG29
      //     ALT8 (8) - Select instance: epdc signal: EPDC_DATA07
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_RW_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_RW(0x020E05AC)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 100MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: FAST
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SPEED_V(100MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_DSE_V(40_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_RW_SRE_V(FAST));
  
      // Config eim.EIM_WAIT to pad EIM_WAIT(M25)
      // HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_WR(0x00000000);
      // HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR(0x0000B060);
      // Mux Register:
      // IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT(0x020E01E0)
      //   SION [4] - Software Input On Field Reset: DISABLED
      //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
      //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
      //     ENABLED (1) - Force input path of pad.
      //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT0
      //                    Select iomux modes to be used for pad.
      //     ALT0 (0) - Select instance: eim signal: EIM_WAIT
      //     ALT1 (1) - Select instance: eim signal: EIM_DTACK_B
      //     ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO00
      //     ALT7 (7) - Select instance: src signal: SRC_BOOT_CFG25
      HW_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_WR(
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_SION_V(DISABLED) | 
              BF_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_MUX_MODE_V(ALT0));
      // Pad Control Register:
      // IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT(0x020E05B0)
      //   HYS [16] - Hysteresis Enable Field Reset: DISABLED
      //     DISABLED (0) - CMOS input
      //     ENABLED (1) - Schmitt trigger input
      //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
      //     100K_OHM_PD (0) - 100K Ohm Pull Down
      //     47K_OHM_PU (1) - 47K Ohm Pull Up
      //     100K_OHM_PU (2) - 100K Ohm Pull Up
      //     22K_OHM_PU (3) - 22K Ohm Pull Up
      //   PUE [13] - Pull / Keep Select Field Reset: PULL
      //     KEEP (0) - Keeper Enabled
      //     PULL (1) - Pull Enabled
      //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
      //     DISABLED (0) - Pull/Keeper Disabled
      //     ENABLED (1) - Pull/Keeper Enabled
      //   ODE [11] - Open Drain Enable Field Reset: DISABLED
      //              Enables open drain of the pin.
      //     DISABLED (0) - Output is CMOS.
      //     ENABLED (1) - Output is Open Drain.
      //   SPEED [7:6] - Speed Field Reset: 50MHZ
      //     RESERVED0 (0) - Reserved
      //     50MHZ (1) - Low (50 MHz)
      //     100MHZ (2) - Medium (100 MHz)
      //     200MHZ (3) - Maximum (200 MHz)
      //   DSE [5:3] - Drive Strength Field Reset: 60_OHM
      //     HIZ (0) - HI-Z
      //     240_OHM (1) - 240 Ohm
      //     120_OHM (2) - 120 Ohm
      //     80_OHM (3) - 80 Ohm
      //     60_OHM (4) - 60 Ohm
      //     48_OHM (5) - 48 Ohm
      //     40_OHM (6) - 40 Ohm
      //     34_OHM (7) - 34 Ohm
      //   SRE [0] - Slew Rate Field Reset: SLOW
      //             Slew rate control.
      //     SLOW (0) - Slow Slew Rate
      //     FAST (1) - Fast Slew Rate
      HW_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_WR(
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_HYS_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUS_V(100K_OHM_PU) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PUE_V(PULL) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_PKE_V(ENABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_ODE_V(DISABLED) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SPEED_V(50MHZ) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_DSE_V(60_OHM) | 
              BF_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_SRE_V(SLOW));
  }
  