text: /* SPDX-License-Identifier: GPL-2.0
   *
   * Copyright 2016-2018 HabanaLabs, Ltd.
   * All Rights Reserved.
   *
   */
  
  /************************************
   ** This is an auto-generated file **
   **       DO NOT EDIT BELOW        **
   ************************************/
  
  #ifndef ASIC_REG_PSOC_SPI_REGS_H_
  #define ASIC_REG_PSOC_SPI_REGS_H_
  
  /*
   *****************************************
   *   PSOC_SPI (Prototype: SPI)
   *****************************************
   */
  
  #define mmPSOC_SPI_CTRLR0                                            0xC43000
  
  #define mmPSOC_SPI_CTRLR1                                            0xC43004
  
  #define mmPSOC_SPI_SSIENR                                            0xC43008
  
  #define mmPSOC_SPI_MWCR                                              0xC4300C
  
  #define mmPSOC_SPI_SER                                               0xC43010
  
  #define mmPSOC_SPI_BAUDR                                             0xC43014
  
  #define mmPSOC_SPI_TXFTLR                                            0xC43018
  
  #define mmPSOC_SPI_RXFTLR                                            0xC4301C
  
  #define mmPSOC_SPI_TXFLR                                             0xC43020
  
  #define mmPSOC_SPI_RXFLR                                             0xC43024
  
  #define mmPSOC_SPI_SR                                                0xC43028
  
  #define mmPSOC_SPI_IMR                                               0xC4302C
  
  #define mmPSOC_SPI_ISR                                               0xC43030
  
  #define mmPSOC_SPI_RISR                                              0xC43034
  
  #define mmPSOC_SPI_TXOICR                                            0xC43038
  
  #define mmPSOC_SPI_RXOICR                                            0xC4303C
  
  #define mmPSOC_SPI_RXUICR                                            0xC43040
  
  #define mmPSOC_SPI_MSTICR                                            0xC43044
  
  #define mmPSOC_SPI_ICR                                               0xC43048
  
  #define mmPSOC_SPI_IDR                                               0xC43058
  
  #define mmPSOC_SPI_SSI_VERSION_ID                                    0xC4305C
  
  #define mmPSOC_SPI_DR0                                               0xC43060
  
  #define mmPSOC_SPI_DR1                                               0xC43064
  
  #define mmPSOC_SPI_DR2                                               0xC43068
  
  #define mmPSOC_SPI_DR3                                               0xC4306C
  
  #define mmPSOC_SPI_DR4                                               0xC43070
  
  #define mmPSOC_SPI_DR5                                               0xC43074
  
  #define mmPSOC_SPI_DR6                                               0xC43078
  
  #define mmPSOC_SPI_DR7                                               0xC4307C
  
  #define mmPSOC_SPI_DR8                                               0xC43080
  
  #define mmPSOC_SPI_DR9                                               0xC43084
  
  #define mmPSOC_SPI_DR10                                              0xC43088
  
  #define mmPSOC_SPI_DR11                                              0xC4308C
  
  #define mmPSOC_SPI_DR12                                              0xC43090
  
  #define mmPSOC_SPI_DR13                                              0xC43094
  
  #define mmPSOC_SPI_DR14                                              0xC43098
  
  #define mmPSOC_SPI_DR15                                              0xC4309C
  
  #define mmPSOC_SPI_DR16                                              0xC430A0
  
  #define mmPSOC_SPI_DR17                                              0xC430A4
  
  #define mmPSOC_SPI_DR18                                              0xC430A8
  
  #define mmPSOC_SPI_DR19                                              0xC430AC
  
  #define mmPSOC_SPI_DR20                                              0xC430B0
  
  #define mmPSOC_SPI_DR21                                              0xC430B4
  
  #define mmPSOC_SPI_DR22                                              0xC430B8
  
  #define mmPSOC_SPI_DR23                                              0xC430BC
  
  #define mmPSOC_SPI_DR24                                              0xC430C0
  
  #define mmPSOC_SPI_DR25                                              0xC430C4
  
  #define mmPSOC_SPI_DR26                                              0xC430C8
  
  #define mmPSOC_SPI_DR27                                              0xC430CC
  
  #define mmPSOC_SPI_DR28                                              0xC430D0
  
  #define mmPSOC_SPI_DR29                                              0xC430D4
  
  #define mmPSOC_SPI_DR30                                              0xC430D8
  
  #define mmPSOC_SPI_DR31                                              0xC430DC
  
  #define mmPSOC_SPI_DR32                                              0xC430E0
  
  #define mmPSOC_SPI_DR33                                              0xC430E4
  
  #define mmPSOC_SPI_DR34                                              0xC430E8
  
  #define mmPSOC_SPI_DR35                                              0xC430EC
  
  #define mmPSOC_SPI_RX_SAMPLE_DLY                                     0xC430F0
  
  #define mmPSOC_SPI_RSVD_1                                            0xC430F8
  
  #define mmPSOC_SPI_RSVD_2                                            0xC430FC
  
  #endif /* ASIC_REG_PSOC_SPI_REGS_H_ */
  