text: 
  void dump_verilog_top_netlist(char* circuit_name,
                                char* top_netlist_name,
                                char* include_dir_path,
                                char* subckt_dir_path,
                                int LL_num_rr_nodes,
                                t_rr_node* LL_rr_node,
                                t_ivec*** LL_rr_node_indices,
                                int num_clock,
                                t_spice spice);
  
  void dump_verilog_top_netlist_tile_orgz(char* circuit_name,
                                          char* top_netlist_name,
                                          char* include_dir_path,
                                          char* subckt_dir_path,
                                          int LL_num_rr_nodes,
                                          t_rr_node* LL_rr_node,
                                          t_ivec*** LL_rr_node_indices,
                                          int num_clock,
                                          t_spice verilog);
  
  void dump_verilog_top_testbench(char* circuit_name,
                                  char* top_netlist_name,
                                  int num_clock,
                                  t_syn_verilog_opts syn_verilog_opts,
                                  t_spice verilog);
  
  void dump_verilog_input_blif_testbench(char* circuit_name,
                                         char* top_netlist_name,
                                         int num_clock,
                                         t_syn_verilog_opts syn_verilog_opts,
                                         t_spice verilog);
  
  void dump_verilog_top_testbench_stimuli(FILE* fp,
                                          int num_clock,
                                          t_syn_verilog_opts syn_verilog_opts,
                                          t_spice verilog);
  