text: # Copyright (c) 2021 The Regents of the University of California
  # All rights reserved.
  #
  # Redistribution and use in source and binary forms, with or without
  # modification, are permitted provided that the following conditions are
  # met: redistributions of source code must retain the above copyright
  # notice, this list of conditions and the following disclaimer;
  # redistributions in binary form must reproduce the above copyright
  # notice, this list of conditions and the following disclaimer in the
  # documentation and/or other materials provided with the distribution;
  # neither the name of the copyright holders nor the names of its
  # contributors may be used to endorse or promote products derived from
  # this software without specific prior written permission.
  #
  # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  
  from typing import Optional
  
  from m5.objects import Cache, BasePrefetcher, StridePrefetcher
  
  from ....utils.override import *
  
  
  class L1ICache(Cache):
      """
      A simple L1 instruction cache with default values.
      """
  
      def __init__(
          self,
          size: str,
          assoc: Optional[int] = 8,
          tag_latency: Optional[int] = 1,
          data_latency: Optional[int] = 1,
          response_latency: Optional[int] = 1,
          mshrs: Optional[int] = 16,
          tgts_per_mshr: Optional[int] = 20,
          writeback_clean: Optional[bool] = True,
          prefetcher: BasePrefetcher = StridePrefetcher(),
      ):
          super(L1ICache, self).__init__()
          self.size = size
          self.assoc = assoc
          self.tag_latency = tag_latency
          self.data_latency = data_latency
          self.response_latency = response_latency
          self.mshrs = mshrs
          self.tgts_per_mshr = tgts_per_mshr
          self.writeback_clean = writeback_clean
          self.prefetcher = prefetcher
  