text: from __future__ import absolute_import
  from __future__ import print_function
  import veriloggen
  import dataflow_mac
  
  expected_verilog = """
  
  module test
  (
  
  );
  
    reg CLK;
    reg RST;
    reg signed [32-1:0] xdata;
    reg xvalid;
    wire xready;
    reg signed [32-1:0] ydata;
    reg yvalid;
    wire yready;
    reg signed [32-1:0] resetdata;
    reg resetvalid;
    wire resetready;
    wire signed [32-1:0] zdata;
    wire zvalid;
    reg zready;
  
    main
    uut
    (
      .CLK(CLK),
      .RST(RST),
      .xdata(xdata),
      .xvalid(xvalid),
      .xready(xready),
      .ydata(ydata),
      .yvalid(yvalid),
      .yready(yready),
      .resetdata(resetdata),
      .resetvalid(resetvalid),
      .resetready(resetready),
      .zdata(zdata),
      .zvalid(zvalid),
      .zready(zready)
    );
  
    reg reset_done;
  
    initial begin
      $dumpfile("uut.vcd");
      $dumpvars(0, uut);
    end
  
  
    initial begin
      CLK = 0;
      forever begin
        #5 CLK = !CLK;
      end
    end
  
  
    initial begin
      RST = 0;
      reset_done = 0;
      xdata = 0;
      xvalid = 0;
      ydata = 0;
      yvalid = 0;
      zready = 0;
      #100;
      RST = 1;
      #100;
      RST = 0;
      #1000;
      reset_done = 1;
      @(posedge CLK);
      #1;
      #10000;
      $finish;
    end
  
    reg [32-1:0] xfsm;
    localparam xfsm_init = 0;
    reg [32-1:0] _tmp_0;
    localparam xfsm_1 = 1;
    localparam xfsm_2 = 2;
    localparam xfsm_3 = 3;
    localparam xfsm_4 = 4;
    localparam xfsm_5 = 5;
    localparam xfsm_6 = 6;
    localparam xfsm_7 = 7;
    localparam xfsm_8 = 8;
    localparam xfsm_9 = 9;
    localparam xfsm_10 = 10;
    localparam xfsm_11 = 11;
    localparam xfsm_12 = 12;
    localparam xfsm_13 = 13;
    localparam xfsm_14 = 14;
    localparam xfsm_15 = 15;
    localparam xfsm_16 = 16;
    localparam xfsm_17 = 17;
    localparam xfsm_18 = 18;
    localparam xfsm_19 = 19;
    localparam xfsm_20 = 20;
    localparam xfsm_21 = 21;
    localparam xfsm_22 = 22;
    localparam xfsm_23 = 23;
    localparam xfsm_24 = 24;
  
    always @(posedge CLK) begin
      if(RST) begin
        xfsm <= xfsm_init;
        _tmp_0 <= 0;
      end else begin
        case(xfsm)
          xfsm_init: begin
            xvalid <= 0;
            if(reset_done) begin
              xfsm <= xfsm_1;
            end 
          end
          xfsm_1: begin
            xfsm <= xfsm_2;
          end
          xfsm_2: begin
            xfsm <= xfsm_3;
          end
          xfsm_3: begin
            xfsm <= xfsm_4;
          end
          xfsm_4: begin
            xfsm <= xfsm_5;
          end
          xfsm_5: begin
            xfsm <= xfsm_6;
          end
          xfsm_6: begin
            xfsm <= xfsm_7;
          end
          xfsm_7: begin
            xfsm <= xfsm_8;
          end
          xfsm_8: begin
            xfsm <= xfsm_9;
          end
          xfsm_9: begin
            xfsm <= xfsm_10;
          end
          xfsm_10: begin
            xfsm <= xfsm_11;
          end
          xfsm_11: begin
            xvalid <= 1;
            xfsm <= xfsm_12;
          end
          xfsm_12: begin
            if(xready) begin
              xdata <= xdata + 1;
            end 
            if(xready) begin
              _tmp_0 <= _tmp_0 + 1;
            end 
            if((_tmp_0 == 5) && xready) begin
              xvalid <= 0;
            end 
            if((_tmp_0 == 5) && xready) begin
              xfsm <= xfsm_13;
            end 
          end
          xfsm_13: begin
            xfsm <= xfsm_14;
          end
          xfsm_14: begin
            xfsm <= xfsm_15;
          end
          xfsm_15: begin
            xfsm <= xfsm_16;
          end
          xfsm_16: begin
            xfsm <= xfsm_17;
          end
          xfsm_17: begin
            xfsm <= xfsm_18;
          end
          xfsm_18: begin
            xfsm <= xfsm_19;
          end
          xfsm_19: begin
            xfsm <= xfsm_20;
          end
          xfsm_20: begin
            xfsm <= xfsm_21;
          end
          xfsm_21: begin
            xfsm <= xfsm_22;
          end
          xfsm_22: begin
            xfsm <= xfsm_23;
          end
          xfsm_23: begin
            xvalid <= 1;
            if(xready) begin
              xdata <= xdata + 1;
            end 
            if(xready) begin
              _tmp_0 <= _tmp_0 + 1;
            end 
            if((_tmp_0 == 20) && xready) begin
              xvalid <= 0;
            end 
            if((_tmp_0 == 20) && xready) begin
              xfsm <= xfsm_24;
            end 
          end
        endcase
      end
    end
  
    reg [32-1:0] yfsm;
    localparam yfsm_init = 0;
    reg [32-1:0] _tmp_1;
    localparam yfsm_1 = 1;
    localparam yfsm_2 = 2;
    localparam yfsm_3 = 3;
    localparam yfsm_4 = 4;
    localparam yfsm_5 = 5;
    localparam yfsm_6 = 6;
    localparam yfsm_7 = 7;
    localparam yfsm_8 = 8;
    localparam yfsm_9 = 9;
    localparam yfsm_10 = 10;
    localparam yfsm_11 = 11;
    localparam yfsm_12 = 12;
    localparam yfsm_13 = 13;
    localparam yfsm_14 = 14;
    localparam yfsm_15 = 15;
    localparam yfsm_16 = 16;
    localparam yfsm_17 = 17;
    localparam yfsm_18 = 18;
    localparam yfsm_19 = 19;
    localparam yfsm_20 = 20;
    localparam yfsm_21 = 21;
    localparam yfsm_22 = 22;
    localparam yfsm_23 = 23;
    localparam yfsm_24 = 24;
    localparam yfsm_25 = 25;
    localparam yfsm_26 = 26;
    localparam yfsm_27 = 27;
    localparam yfsm_28 = 28;
    localparam yfsm_29 = 29;
    localparam yfsm_30 = 30;
    localparam yfsm_31 = 31;
    localparam yfsm_32 = 32;
    localparam yfsm_33 = 33;
    localparam yfsm_34 = 34;
    localparam yfsm_35 = 35;
    localparam yfsm_36 = 36;
    localparam yfsm_37 = 37;
    localparam yfsm_38 = 38;
    localparam yfsm_39 = 39;
    localparam yfsm_40 = 40;
    localparam yfsm_41 = 41;
    localparam yfsm_42 = 42;
    localparam yfsm_43 = 43;
    localparam yfsm_44 = 44;
  
    always @(posedge CLK) begin
      if(RST) begin
        yfsm <= yfsm_init;
        _tmp_1 <= 0;
      end else begin
        case(yfsm)
          yfsm_init: begin
            yvalid <= 0;
            if(reset_done) begin
              yfsm <= yfsm_1;
            end 
          end
          yfsm_1: begin
            yfsm <= yfsm_2;
          end
          yfsm_2: begin
            yfsm <= yfsm_3;
          end
          yfsm_3: begin
            yfsm <= yfsm_4;
          end
          yfsm_4: begin
            yfsm <= yfsm_5;
          end
          yfsm_5: begin
            yfsm <= yfsm_6;
          end
          yfsm_6: begin
            yfsm <= yfsm_7;
          end
          yfsm_7: begin
            yfsm <= yfsm_8;
          end
          yfsm_8: begin
            yfsm <= yfsm_9;
          end
          yfsm_9: begin
            yfsm <= yfsm_10;
          end
          yfsm_10: begin
            yfsm <= yfsm_11;
          end
          yfsm_11: begin
            yfsm <= yfsm_12;
          end
          yfsm_12: begin
            yfsm <= yfsm_13;
          end
          yfsm_13: begin
            yfsm <= yfsm_14;
          end
          yfsm_14: begin
            yfsm <= yfsm_15;
          end
          yfsm_15: begin
            yfsm <= yfsm_16;
          end
          yfsm_16: begin
            yfsm <= yfsm_17;
          end
          yfsm_17: begin
            yfsm <= yfsm_18;
          end
          yfsm_18: begin
            yfsm <= yfsm_19;
          end
          yfsm_19: begin
            yfsm <= yfsm_20;
          end
          yfsm_20: begin
            yfsm <= yfsm_21;
          end
          yfsm_21: begin
            yvalid <= 1;
            yfsm <= yfsm_22;
          end
          yfsm_22: begin
            if(yready) begin
              ydata <= ydata + 1;
            end 
            if(yready) begin
              _tmp_1 <= _tmp_1 + 1;
            end 
            if((_tmp_1 == 5) && yready) begin
              yvalid <= 0;
            end 
            if((_tmp_1 == 5) && yready) begin
              yfsm <= yfsm_23;
            end 
          end
          yfsm_23: begin
            yfsm <= yfsm_24;
          end
          yfsm_24: begin
            yfsm <= yfsm_25;
          end
          yfsm_25: begin
            yfsm <= yfsm_26;
          end
          yfsm_26: begin
            yfsm <= yfsm_27;
          end
          yfsm_27: begin
            yfsm <= yfsm_28;
          end
          yfsm_28: begin
            yfsm <= yfsm_29;
          end
          yfsm_29: begin
            yfsm <= yfsm_30;
          end
          yfsm_30: begin
            yfsm <= yfsm_31;
          end
          yfsm_31: begin
            yfsm <= yfsm_32;
          end
          yfsm_32: begin
            yfsm <= yfsm_33;
          end
          yfsm_33: begin
            yfsm <= yfsm_34;
          end
          yfsm_34: begin
            yfsm <= yfsm_35;
          end
          yfsm_35: begin
            yfsm <= yfsm_36;
          end
          yfsm_36: begin
            yfsm <= yfsm_37;
          end
          yfsm_37: begin
            yfsm <= yfsm_38;
          end
          yfsm_38: begin
            yfsm <= yfsm_39;
          end
          yfsm_39: begin
            yfsm <= yfsm_40;
          end
          yfsm_40: begin
            yfsm <= yfsm_41;
          end
          yfsm_41: begin
            yfsm <= yfsm_42;
          end
          yfsm_42: begin
            yfsm <= yfsm_43;
          end
          yfsm_43: begin
            yvalid <= 1;
            if(yready) begin
              ydata <= ydata + 1;
            end 
            if(yready) begin
              _tmp_1 <= _tmp_1 + 1;
            end 
            if((_tmp_1 == 20) && yready) begin
              yvalid <= 0;
            end 
            if((_tmp_1 == 20) && yready) begin
              yfsm <= yfsm_44;
            end 
          end
        endcase
      end
    end
  
    reg [32-1:0] zfsm;
    localparam zfsm_init = 0;
    localparam zfsm_1 = 1;
    localparam zfsm_2 = 2;
    localparam zfsm_3 = 3;
    localparam zfsm_4 = 4;
    localparam zfsm_5 = 5;
    localparam zfsm_6 = 6;
    localparam zfsm_7 = 7;
    localparam zfsm_8 = 8;
    localparam zfsm_9 = 9;
    localparam zfsm_10 = 10;
    localparam zfsm_11 = 11;
    localparam zfsm_12 = 12;
    localparam zfsm_13 = 13;
    localparam zfsm_14 = 14;
    localparam zfsm_15 = 15;
    localparam zfsm_16 = 16;
    localparam zfsm_17 = 17;
    localparam zfsm_18 = 18;
    localparam zfsm_19 = 19;
    localparam zfsm_20 = 20;
    localparam zfsm_21 = 21;
    localparam zfsm_22 = 22;
    localparam zfsm_23 = 23;
    localparam zfsm_24 = 24;
    localparam zfsm_25 = 25;
    localparam zfsm_26 = 26;
    localparam zfsm_27 = 27;
    localparam zfsm_28 = 28;
    localparam zfsm_29 = 29;
    localparam zfsm_30 = 30;
    localparam zfsm_31 = 31;
    localparam zfsm_32 = 32;
    localparam zfsm_33 = 33;
    localparam zfsm_34 = 34;
    localparam zfsm_35 = 35;
    localparam zfsm_36 = 36;
    localparam zfsm_37 = 37;
    localparam zfsm_38 = 38;
    localparam zfsm_39 = 39;
    localparam zfsm_40 = 40;
    localparam zfsm_41 = 41;
    localparam zfsm_42 = 42;
    localparam zfsm_43 = 43;
    localparam zfsm_44 = 44;
    localparam zfsm_45 = 45;
    localparam zfsm_46 = 46;
    localparam zfsm_47 = 47;
    localparam zfsm_48 = 48;
    localparam zfsm_49 = 49;
    localparam zfsm_50 = 50;
    localparam zfsm_51 = 51;
    localparam zfsm_52 = 52;
    localparam zfsm_53 = 53;
  
    always @(posedge CLK) begin
      if(RST) begin
        zfsm <= zfsm_init;
      end else begin
        case(zfsm)
          zfsm_init: begin
            zready <= 0;
            if(reset_done) begin
              zfsm <= zfsm_1;
            end 
          end
          zfsm_1: begin
            zfsm <= zfsm_2;
          end
          zfsm_2: begin
            if(zvalid) begin
              zready <= 1;
            end 
            if(zvalid) begin
              zfsm <= zfsm_3;
            end 
          end
          zfsm_3: begin
            zready <= 0;
            zfsm <= zfsm_4;
          end
          zfsm_4: begin
            zready <= 0;
            zfsm <= zfsm_5;
          end
          zfsm_5: begin
            zready <= 0;
            zfsm <= zfsm_6;
          end
          zfsm_6: begin
            zready <= 0;
            zfsm <= zfsm_7;
          end
          zfsm_7: begin
            zready <= 0;
            zfsm <= zfsm_8;
          end
          zfsm_8: begin
            zready <= 0;
            zfsm <= zfsm_9;
          end
          zfsm_9: begin
            zready <= 0;
            zfsm <= zfsm_10;
          end
          zfsm_10: begin
            zready <= 0;
            zfsm <= zfsm_11;
          end
          zfsm_11: begin
            zready <= 0;
            zfsm <= zfsm_12;
          end
          zfsm_12: begin
            zready <= 0;
            zfsm <= zfsm_13;
          end
          zfsm_13: begin
            zready <= 0;
            zfsm <= zfsm_14;
          end
          zfsm_14: begin
            zready <= 0;
            zfsm <= zfsm_15;
          end
          zfsm_15: begin
            zready <= 0;
            zfsm <= zfsm_16;
          end
          zfsm_16: begin
            zready <= 0;
            zfsm <= zfsm_17;
          end
          zfsm_17: begin
            zready <= 0;
            zfsm <= zfsm_18;
          end
          zfsm_18: begin
            zready <= 0;
            zfsm <= zfsm_19;
          end
          zfsm_19: begin
            zready <= 0;
            zfsm <= zfsm_20;
          end
          zfsm_20: begin
            zready <= 0;
            zfsm <= zfsm_21;
          end
          zfsm_21: begin
            zready <= 0;
            zfsm <= zfsm_22;
          end
          zfsm_22: begin
            zready <= 0;
            zfsm <= zfsm_23;
          end
          zfsm_23: begin
            zready <= 0;
            zfsm <= zfsm_24;
          end
          zfsm_24: begin
            zready <= 0;
            zfsm <= zfsm_25;
          end
          zfsm_25: begin
            zready <= 0;
            zfsm <= zfsm_26;
          end
          zfsm_26: begin
            zready <= 0;
            zfsm <= zfsm_27;
          end
          zfsm_27: begin
            zready <= 0;
            zfsm <= zfsm_28;
          end
          zfsm_28: begin
            zready <= 0;
            zfsm <= zfsm_29;
          end
          zfsm_29: begin
            zready <= 0;
            zfsm <= zfsm_30;
          end
          zfsm_30: begin
            zready <= 0;
            zfsm <= zfsm_31;
          end
          zfsm_31: begin
            zready <= 0;
            zfsm <= zfsm_32;
          end
          zfsm_32: begin
            zready <= 0;
            zfsm <= zfsm_33;
          end
          zfsm_33: begin
            zready <= 0;
            zfsm <= zfsm_34;
          end
          zfsm_34: begin
            zready <= 0;
            zfsm <= zfsm_35;
          end
          zfsm_35: begin
            zready <= 0;
            zfsm <= zfsm_36;
          end
          zfsm_36: begin
            zready <= 0;
            zfsm <= zfsm_37;
          end
          zfsm_37: begin
            zready <= 0;
            zfsm <= zfsm_38;
          end
          zfsm_38: begin
            zready <= 0;
            zfsm <= zfsm_39;
          end
          zfsm_39: begin
            zready <= 0;
            zfsm <= zfsm_40;
          end
          zfsm_40: begin
            zready <= 0;
            zfsm <= zfsm_41;
          end
          zfsm_41: begin
            zready <= 0;
            zfsm <= zfsm_42;
          end
          zfsm_42: begin
            zready <= 0;
            zfsm <= zfsm_43;
          end
          zfsm_43: begin
            zready <= 0;
            zfsm <= zfsm_44;
          end
          zfsm_44: begin
            zready <= 0;
            zfsm <= zfsm_45;
          end
          zfsm_45: begin
            zready <= 0;
            zfsm <= zfsm_46;
          end
          zfsm_46: begin
            zready <= 0;
            zfsm <= zfsm_47;
          end
          zfsm_47: begin
            zready <= 0;
            zfsm <= zfsm_48;
          end
          zfsm_48: begin
            zready <= 0;
            zfsm <= zfsm_49;
          end
          zfsm_49: begin
            zready <= 0;
            zfsm <= zfsm_50;
          end
          zfsm_50: begin
            zready <= 0;
            zfsm <= zfsm_51;
          end
          zfsm_51: begin
            zready <= 0;
            zfsm <= zfsm_52;
          end
          zfsm_52: begin
            zready <= 0;
            zfsm <= zfsm_53;
          end
          zfsm_53: begin
            zfsm <= zfsm_2;
          end
        endcase
      end
    end
  
    reg [32-1:0] reset;
    localparam reset_init = 0;
    reg [32-1:0] reset_count;
    localparam reset_1 = 1;
    localparam reset_2 = 2;
  
    always @(posedge CLK) begin
      if(RST) begin
        reset <= reset_init;
        reset_count <= 0;
      end else begin
        case(reset)
          reset_init: begin
            if(reset_done) begin
              reset <= reset_1;
            end 
          end
          reset_1: begin
            resetvalid <= 1;
            if(resetvalid && resetready) begin
              reset_count <= reset_count + 1;
            end 
            if(resetvalid && resetready && (reset_count == 2)) begin
              resetdata <= 1;
            end 
            if(resetvalid && resetready && (reset_count == 2)) begin
              reset <= reset_2;
            end 
          end
          reset_2: begin
            if(resetvalid && resetready) begin
              resetdata <= 0;
            end 
            reset_count <= 0;
            if(resetvalid && resetready) begin
              reset <= reset_1;
            end 
          end
        endcase
      end
    end
  
  
    always @(posedge CLK) begin
      if(reset_done) begin
        if(xvalid && xready) begin
          $display("xdata=%d", xdata);
        end 
        if(yvalid && yready) begin
          $display("ydata=%d", ydata);
        end 
        if(zvalid && zready) begin
          $display("zdata=%d", zdata);
        end 
      end 
    end
  
  
  endmodule
  
  
  
  module main
  (
    input CLK,
    input RST,
    input signed [32-1:0] xdata,
    input xvalid,
    output xready,
    input signed [32-1:0] ydata,
    input yvalid,
    output yready,
    input signed [32-1:0] resetdata,
    input resetvalid,
    output resetready,
    output signed [32-1:0] zdata,
    output zvalid,
    input zready
  );
  
    wire signed [32-1:0] _dataflow_times_data_3;
    wire _dataflow_times_valid_3;
    wire _dataflow_times_ready_3;
    wire signed [64-1:0] _dataflow_times_mul_odata_3;
    reg signed [64-1:0] _dataflow_times_mul_odata_reg_3;
    assign _dataflow_times_data_3 = _dataflow_times_mul_odata_reg_3;
    wire _dataflow_times_mul_ovalid_3;
    reg _dataflow_times_mul_valid_reg_3;
    assign _dataflow_times_valid_3 = _dataflow_times_mul_valid_reg_3;
    wire _dataflow_times_mul_enable_3;
    wire _dataflow_times_mul_update_3;
    assign _dataflow_times_mul_enable_3 = (_dataflow_times_ready_3 || !_dataflow_times_valid_3) && (xready && yready) && (xvalid && yvalid);
    assign _dataflow_times_mul_update_3 = _dataflow_times_ready_3 || !_dataflow_times_valid_3;
  
    multiplier_0
    _dataflow_times_mul_3
    (
      .CLK(CLK),
      .RST(RST),
      .update(_dataflow_times_mul_update_3),
      .enable(_dataflow_times_mul_enable_3),
      .valid(_dataflow_times_mul_ovalid_3),
      .a(xdata),
      .b(ydata),
      .c(_dataflow_times_mul_odata_3)
    );
  
    assign xready = (_dataflow_times_ready_3 || !_dataflow_times_valid_3) && (xvalid && yvalid);
    assign yready = (_dataflow_times_ready_3 || !_dataflow_times_valid_3) && (xvalid && yvalid);
    reg signed [32-1:0] _dataflow__delay_data_6;
    reg _dataflow__delay_valid_6;
    wire _dataflow__delay_ready_6;
    assign resetready = (_dataflow__delay_ready_6 || !_dataflow__delay_valid_6) && resetvalid;
    reg signed [32-1:0] _dataflow__delay_data_7;
    reg _dataflow__delay_valid_7;
    wire _dataflow__delay_ready_7;
    assign _dataflow__delay_ready_6 = (_dataflow__delay_ready_7 || !_dataflow__delay_valid_7) && _dataflow__delay_valid_6;
    reg signed [32-1:0] _dataflow__delay_data_8;
    reg _dataflow__delay_valid_8;
    wire _dataflow__delay_ready_8;
    assign _dataflow__delay_ready_7 = (_dataflow__delay_ready_8 || !_dataflow__delay_valid_8) && _dataflow__delay_valid_7;
    reg signed [32-1:0] _dataflow__delay_data_9;
    reg _dataflow__delay_valid_9;
    wire _dataflow__delay_ready_9;
    assign _dataflow__delay_ready_8 = (_dataflow__delay_ready_9 || !_dataflow__delay_valid_9) && _dataflow__delay_valid_8;
    reg signed [32-1:0] _dataflow__delay_data_10;
    reg _dataflow__delay_valid_10;
    wire _dataflow__delay_ready_10;
    assign _dataflow__delay_ready_9 = (_dataflow__delay_ready_10 || !_dataflow__delay_valid_10) && _dataflow__delay_valid_9;
    reg signed [32-1:0] _dataflow__delay_data_11;
    reg _dataflow__delay_valid_11;
    wire _dataflow__delay_ready_11;
    assign _dataflow__delay_ready_10 = (_dataflow__delay_ready_11 || !_dataflow__delay_valid_11) && _dataflow__delay_valid_10;
    reg signed [32-1:0] _dataflow__delay_data_12;
    reg _dataflow__delay_valid_12;
    wire _dataflow__delay_ready_12;
    assign _dataflow__delay_ready_11 = (_dataflow__delay_ready_12 || !_dataflow__delay_valid_12) && _dataflow__delay_valid_11;
    reg signed [32-1:0] _dataflow_reduceadd_data_5;
    reg _dataflow_reduceadd_valid_5;
    wire _dataflow_reduceadd_ready_5;
    assign _dataflow_times_ready_3 = (_dataflow_reduceadd_ready_5 || !_dataflow_reduceadd_valid_5) && (_dataflow_times_valid_3 && _dataflow__delay_valid_12);
    assign _dataflow__delay_ready_12 = (_dataflow_reduceadd_ready_5 || !_dataflow_reduceadd_valid_5) && (_dataflow_times_valid_3 && _dataflow__delay_valid_12);
    assign zdata = _dataflow_reduceadd_data_5;
    assign zvalid = _dataflow_reduceadd_valid_5;
    assign _dataflow_reduceadd_ready_5 = zready;
  
    always @(posedge CLK) begin
      if(RST) begin
        _dataflow_times_mul_odata_reg_3 <= 0;
        _dataflow_times_mul_valid_reg_3 <= 0;
        _dataflow__delay_data_6 <= 0;
        _dataflow__delay_valid_6 <= 0;
        _dataflow__delay_data_7 <= 0;
        _dataflow__delay_valid_7 <= 0;
        _dataflow__delay_data_8 <= 0;
        _dataflow__delay_valid_8 <= 0;
        _dataflow__delay_data_9 <= 0;
        _dataflow__delay_valid_9 <= 0;
        _dataflow__delay_data_10 <= 0;
        _dataflow__delay_valid_10 <= 0;
        _dataflow__delay_data_11 <= 0;
        _dataflow__delay_valid_11 <= 0;
        _dataflow__delay_data_12 <= 0;
        _dataflow__delay_valid_12 <= 0;
        _dataflow_reduceadd_data_5 <= 1'sd0;
        _dataflow_reduceadd_valid_5 <= 0;
      end else begin
        if(_dataflow_times_ready_3 || !_dataflow_times_valid_3) begin
          _dataflow_times_mul_odata_reg_3 <= _dataflow_times_mul_odata_3;
        end 
        if(_dataflow_times_ready_3 || !_dataflow_times_valid_3) begin
          _dataflow_times_mul_valid_reg_3 <= _dataflow_times_mul_ovalid_3;
        end 
        if((_dataflow__delay_ready_6 || !_dataflow__delay_valid_6) && resetready && resetvalid) begin
          _dataflow__delay_data_6 <= resetdata;
        end 
        if(_dataflow__delay_valid_6 && _dataflow__delay_ready_6) begin
          _dataflow__delay_valid_6 <= 0;
        end 
        if((_dataflow__delay_ready_6 || !_dataflow__delay_valid_6) && resetready) begin
          _dataflow__delay_valid_6 <= resetvalid;
        end 
        if((_dataflow__delay_ready_7 || !_dataflow__delay_valid_7) && _dataflow__delay_ready_6 && _dataflow__delay_valid_6) begin
          _dataflow__delay_data_7 <= _dataflow__delay_data_6;
        end 
        if(_dataflow__delay_valid_7 && _dataflow__delay_ready_7) begin
          _dataflow__delay_valid_7 <= 0;
        end 
        if((_dataflow__delay_ready_7 || !_dataflow__delay_valid_7) && _dataflow__delay_ready_6) begin
          _dataflow__delay_valid_7 <= _dataflow__delay_valid_6;
        end 
        if((_dataflow__delay_ready_8 || !_dataflow__delay_valid_8) && _dataflow__delay_ready_7 && _dataflow__delay_valid_7) begin
          _dataflow__delay_data_8 <= _dataflow__delay_data_7;
        end 
        if(_dataflow__delay_valid_8 && _dataflow__delay_ready_8) begin
          _dataflow__delay_valid_8 <= 0;
        end 
        if((_dataflow__delay_ready_8 || !_dataflow__delay_valid_8) && _dataflow__delay_ready_7) begin
          _dataflow__delay_valid_8 <= _dataflow__delay_valid_7;
        end 
        if((_dataflow__delay_ready_9 || !_dataflow__delay_valid_9) && _dataflow__delay_ready_8 && _dataflow__delay_valid_8) begin
          _dataflow__delay_data_9 <= _dataflow__delay_data_8;
        end 
        if(_dataflow__delay_valid_9 && _dataflow__delay_ready_9) begin
          _dataflow__delay_valid_9 <= 0;
        end 
        if((_dataflow__delay_ready_9 || !_dataflow__delay_valid_9) && _dataflow__delay_ready_8) begin
          _dataflow__delay_valid_9 <= _dataflow__delay_valid_8;
        end 
        if((_dataflow__delay_ready_10 || !_dataflow__delay_valid_10) && _dataflow__delay_ready_9 && _dataflow__delay_valid_9) begin
          _dataflow__delay_data_10 <= _dataflow__delay_data_9;
        end 
        if(_dataflow__delay_valid_10 && _dataflow__delay_ready_10) begin
          _dataflow__delay_valid_10 <= 0;
        end 
        if((_dataflow__delay_ready_10 || !_dataflow__delay_valid_10) && _dataflow__delay_ready_9) begin
          _dataflow__delay_valid_10 <= _dataflow__delay_valid_9;
        end 
        if((_dataflow__delay_ready_11 || !_dataflow__delay_valid_11) && _dataflow__delay_ready_10 && _dataflow__delay_valid_10) begin
          _dataflow__delay_data_11 <= _dataflow__delay_data_10;
        end 
        if(_dataflow__delay_valid_11 && _dataflow__delay_ready_11) begin
          _dataflow__delay_valid_11 <= 0;
        end 
        if((_dataflow__delay_ready_11 || !_dataflow__delay_valid_11) && _dataflow__delay_ready_10) begin
          _dataflow__delay_valid_11 <= _dataflow__delay_valid_10;
        end 
        if((_dataflow__delay_ready_12 || !_dataflow__delay_valid_12) && _dataflow__delay_ready_11 && _dataflow__delay_valid_11) begin
          _dataflow__delay_data_12 <= _dataflow__delay_data_11;
        end 
        if(_dataflow__delay_valid_12 && _dataflow__delay_ready_12) begin
          _dataflow__delay_valid_12 <= 0;
        end 
        if((_dataflow__delay_ready_12 || !_dataflow__delay_valid_12) && _dataflow__delay_ready_11) begin
          _dataflow__delay_valid_12 <= _dataflow__delay_valid_11;
        end 
        if((_dataflow_reduceadd_ready_5 || !_dataflow_reduceadd_valid_5) && (_dataflow_times_ready_3 && _dataflow__delay_ready_12) && (_dataflow_times_valid_3 && _dataflow__delay_valid_12)) begin
          _dataflow_reduceadd_data_5 <= _dataflow_reduceadd_data_5 + _dataflow_times_data_3;
        end 
        if(_dataflow_reduceadd_valid_5 && _dataflow_reduceadd_ready_5) begin
          _dataflow_reduceadd_valid_5 <= 0;
        end 
        if((_dataflow_reduceadd_ready_5 || !_dataflow_reduceadd_valid_5) && (_dataflow_times_ready_3 && _dataflow__delay_ready_12)) begin
          _dataflow_reduceadd_valid_5 <= _dataflow_times_valid_3 && _dataflow__delay_valid_12;
        end 
        if((_dataflow_reduceadd_ready_5 || !_dataflow_reduceadd_valid_5) && (_dataflow_times_ready_3 && _dataflow__delay_ready_12) && (_dataflow_times_valid_3 && _dataflow__delay_valid_12) && _dataflow__delay_data_12) begin
          _dataflow_reduceadd_data_5 <= 1'sd0 + _dataflow_times_data_3;
        end 
      end
    end
  
  
  endmodule
  
  
  
  module multiplier_0
  (
    input CLK,
    input RST,
    input update,
    input enable,
    output valid,
    input [32-1:0] a,
    input [32-1:0] b,
    output [64-1:0] c
  );
  
    reg valid_reg0;
    reg valid_reg1;
    reg valid_reg2;
    reg valid_reg3;
    reg valid_reg4;
    reg valid_reg5;
    assign valid = valid_reg5;
  
    always @(posedge CLK) begin
      if(RST) begin
        valid_reg0 <= 0;
        valid_reg1 <= 0;
        valid_reg2 <= 0;
        valid_reg3 <= 0;
        valid_reg4 <= 0;
        valid_reg5 <= 0;
      end else begin
        if(update) begin
          valid_reg0 <= enable;
          valid_reg1 <= valid_reg0;
          valid_reg2 <= valid_reg1;
          valid_reg3 <= valid_reg2;
          valid_reg4 <= valid_reg3;
          valid_reg5 <= valid_reg4;
        end 
      end
    end
  
  
    multiplier_core_0
    mult
    (
      .CLK(CLK),
      .update(update),
      .a(a),
      .b(b),
      .c(c)
    );
  
  
  endmodule
  
  
  
  module multiplier_core_0
  (
    input CLK,
    input update,
    input [32-1:0] a,
    input [32-1:0] b,
    output [64-1:0] c
  );
  
    reg signed [32-1:0] _a;
    reg signed [32-1:0] _b;
    wire signed [64-1:0] _mul;
    reg signed [64-1:0] _pipe_mul0;
    reg signed [64-1:0] _pipe_mul1;
    reg signed [64-1:0] _pipe_mul2;
    reg signed [64-1:0] _pipe_mul3;
    reg signed [64-1:0] _pipe_mul4;
    assign _mul = _a * _b;
    assign c = _pipe_mul4;
  
    always @(posedge CLK) begin
      if(update) begin
        _a <= a;
        _b <= b;
        _pipe_mul0 <= _mul;
        _pipe_mul1 <= _pipe_mul0;
        _pipe_mul2 <= _pipe_mul1;
        _pipe_mul3 <= _pipe_mul2;
        _pipe_mul4 <= _pipe_mul3;
      end 
    end
  
  
  endmodule
  
  """
  
  def test():
      veriloggen.reset()
      test_module = dataflow_mac.mkTest()
      code = test_module.to_verilog()
  
      from pyverilog.vparser.parser import VerilogParser
      from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
      parser = VerilogParser()
      expected_ast = parser.parse(expected_verilog)
      codegen = ASTCodeGenerator()
      expected_code = codegen.visit(expected_ast)
  
      assert(expected_code == code)
  