text: // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
  // REQUIRES: riscv-registered-target
  // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-feature +experimental-v \
  // RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
  // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
  // RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
  // RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
  // RUN:   -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
  
  // ASM-NOT: warning
  #include <riscv_vector.h>
  
  // CHECK-RV32-LABEL: @test_vfmerge_vfm_f32mf2(
  // CHECK-RV32-NEXT:  entry:
  // CHECK-RV32-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i32(<vscale x 1 x float> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR6:#.*]]
  // CHECK-RV32-NEXT:    ret <vscale x 1 x float> [[TMP0]]
  //
  // CHECK-RV64-LABEL: @test_vfmerge_vfm_f32mf2(
  // CHECK-RV64-NEXT:  entry:
  // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32.i64(<vscale x 1 x float> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR6:#.*]]
  // CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]
  //
  vfloat32mf2_t test_vfmerge_vfm_f32mf2(vbool64_t mask, vfloat32mf2_t op1,
                                        float op2, size_t vl) {
    return vfmerge(mask, op1, op2, vl);
  }
  
  // CHECK-RV32-LABEL: @test_vfmerge_vfm_f32m1(
  // CHECK-RV32-NEXT:  entry:
  // CHECK-RV32-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i32(<vscale x 2 x float> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV32-NEXT:    ret <vscale x 2 x float> [[TMP0]]
  //
  // CHECK-RV64-LABEL: @test_vfmerge_vfm_f32m1(
  // CHECK-RV64-NEXT:  entry:
  // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32.i64(<vscale x 2 x float> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]
  //
  vfloat32m1_t test_vfmerge_vfm_f32m1(vbool32_t mask, vfloat32m1_t op1, float op2,
                                      size_t vl) {
    return vfmerge(mask, op1, op2, vl);
  }
  
  // CHECK-RV32-LABEL: @test_vfmerge_vfm_f32m2(
  // CHECK-RV32-NEXT:  entry:
  // CHECK-RV32-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.f32.i32(<vscale x 4 x float> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV32-NEXT:    ret <vscale x 4 x float> [[TMP0]]
  //
  // CHECK-RV64-LABEL: @test_vfmerge_vfm_f32m2(
  // CHECK-RV64-NEXT:  entry:
  // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.f32.i64(<vscale x 4 x float> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]
  //
  vfloat32m2_t test_vfmerge_vfm_f32m2(vbool16_t mask, vfloat32m2_t op1, float op2,
                                      size_t vl) {
    return vfmerge(mask, op1, op2, vl);
  }
  
  // CHECK-RV32-LABEL: @test_vfmerge_vfm_f32m4(
  // CHECK-RV32-NEXT:  entry:
  // CHECK-RV32-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.f32.i32(<vscale x 8 x float> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV32-NEXT:    ret <vscale x 8 x float> [[TMP0]]
  //
  // CHECK-RV64-LABEL: @test_vfmerge_vfm_f32m4(
  // CHECK-RV64-NEXT:  entry:
  // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.f32.i64(<vscale x 8 x float> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
  //
  vfloat32m4_t test_vfmerge_vfm_f32m4(vbool8_t mask, vfloat32m4_t op1, float op2,
                                      size_t vl) {
    return vfmerge(mask, op1, op2, vl);
  }
  
  // CHECK-RV32-LABEL: @test_vfmerge_vfm_f32m8(
  // CHECK-RV32-NEXT:  entry:
  // CHECK-RV32-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.f32.i32(<vscale x 16 x float> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV32-NEXT:    ret <vscale x 16 x float> [[TMP0]]
  //
  // CHECK-RV64-LABEL: @test_vfmerge_vfm_f32m8(
  // CHECK-RV64-NEXT:  entry:
  // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.f32.i64(<vscale x 16 x float> [[OP1:%.*]], float [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
  //
  vfloat32m8_t test_vfmerge_vfm_f32m8(vbool4_t mask, vfloat32m8_t op1, float op2,
                                      size_t vl) {
    return vfmerge(mask, op1, op2, vl);
  }
  
  // CHECK-RV32-LABEL: @test_vfmerge_vfm_f64m1(
  // CHECK-RV32-NEXT:  entry:
  // CHECK-RV32-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmerge.nxv1f64.f64.i32(<vscale x 1 x double> [[OP1:%.*]], double [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV32-NEXT:    ret <vscale x 1 x double> [[TMP0]]
  //
  // CHECK-RV64-LABEL: @test_vfmerge_vfm_f64m1(
  // CHECK-RV64-NEXT:  entry:
  // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmerge.nxv1f64.f64.i64(<vscale x 1 x double> [[OP1:%.*]], double [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]
  //
  vfloat64m1_t test_vfmerge_vfm_f64m1(vbool64_t mask, vfloat64m1_t op1,
                                      double op2, size_t vl) {
    return vfmerge(mask, op1, op2, vl);
  }
  
  // CHECK-RV32-LABEL: @test_vfmerge_vfm_f64m2(
  // CHECK-RV32-NEXT:  entry:
  // CHECK-RV32-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmerge.nxv2f64.f64.i32(<vscale x 2 x double> [[OP1:%.*]], double [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV32-NEXT:    ret <vscale x 2 x double> [[TMP0]]
  //
  // CHECK-RV64-LABEL: @test_vfmerge_vfm_f64m2(
  // CHECK-RV64-NEXT:  entry:
  // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmerge.nxv2f64.f64.i64(<vscale x 2 x double> [[OP1:%.*]], double [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]
  //
  vfloat64m2_t test_vfmerge_vfm_f64m2(vbool32_t mask, vfloat64m2_t op1,
                                      double op2, size_t vl) {
    return vfmerge(mask, op1, op2, vl);
  }
  
  // CHECK-RV32-LABEL: @test_vfmerge_vfm_f64m4(
  // CHECK-RV32-NEXT:  entry:
  // CHECK-RV32-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmerge.nxv4f64.f64.i32(<vscale x 4 x double> [[OP1:%.*]], double [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV32-NEXT:    ret <vscale x 4 x double> [[TMP0]]
  //
  // CHECK-RV64-LABEL: @test_vfmerge_vfm_f64m4(
  // CHECK-RV64-NEXT:  entry:
  // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmerge.nxv4f64.f64.i64(<vscale x 4 x double> [[OP1:%.*]], double [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]
  //
  vfloat64m4_t test_vfmerge_vfm_f64m4(vbool16_t mask, vfloat64m4_t op1,
                                      double op2, size_t vl) {
    return vfmerge(mask, op1, op2, vl);
  }
  
  // CHECK-RV32-LABEL: @test_vfmerge_vfm_f64m8(
  // CHECK-RV32-NEXT:  entry:
  // CHECK-RV32-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.f64.i32(<vscale x 8 x double> [[OP1:%.*]], double [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i32 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV32-NEXT:    ret <vscale x 8 x double> [[TMP0]]
  //
  // CHECK-RV64-LABEL: @test_vfmerge_vfm_f64m8(
  // CHECK-RV64-NEXT:  entry:
  // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.f64.i64(<vscale x 8 x double> [[OP1:%.*]], double [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) [[ATTR6]]
  // CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
  //
  vfloat64m8_t test_vfmerge_vfm_f64m8(vbool8_t mask, vfloat64m8_t op1, double op2,
                                      size_t vl) {
    return vfmerge(mask, op1, op2, vl);
  }
  