text: /**
   * (c) 2013 Xilinx Inc.
   * XREGDB v0.91
   * XREGCHDR v0.15
   *
   * Generated on: 2018-05-06
   *
   * @file: psm_global_reg.h
   *
   *
   * This file contains confidential and proprietary information
   * of Xilinx, Inc. and is protected under U.S. and
   * international copyright and other intellectual property
   * laws.
   *
   * DISCLAIMER
   * This disclaimer is not a license and does not grant any
   * rights to the materials distributed herewith. Except as
   * otherwise provided in a valid license issued to you by
   * Xilinx, and to the maximum extent permitted by applicable
   * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
   * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
   * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
   * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
   * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
   * (2) Xilinx shall not be liable (whether in contract or tort,
   * including negligence, or under any other theory of
   * liability) for any loss or damage of any kind or nature
   * related to, arising under or in connection with these
   * materials, including for any direct, or any indirect,
   * special, incidental, or consequential loss or damage
   * (including loss of data, profits, goodwill, or any type of
   * loss or damage suffered as a result of any action brought
   * by a third party) even if such damage or loss was
   * reasonably foreseeable or Xilinx had been advised of the
   * possibility of the same.
   *
   * CRITICAL APPLICATIONS
   * Xilinx products are not designed or intended to be fail-
   * safe, or for use in any application requiring fail-safe
   * performance, such as life-support or safety devices or
   * systems, Class III medical devices, nuclear facilities,
   * applications related to the deployment of airbags, or any
   * other applications that could lead to death, personal
   * injury, or severe property or environmental damage
   * (individually and collectively, "Critical
   * Applications"). Customer assumes the sole risk and
   * liability of any use of Xilinx products in Critical
   * Applications, subject only to applicable laws and
   * regulations governing limitations on product liability.
   *
   * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
   * PART OF THIS FILE AT ALL TIMES.
   *
   * Naming Convention: <MODULE>_<REGISTER>[_<FIELD>[_<DESC>]]
   *     <MODULE>       Module name (e.g. can or usb)
   *     <REGISTER>     Register within the current module
   *     [_<FIELD>]     Bit field within a register
   *     [_<DESC>]      Type of bit field define:
   *         SHIFT:     Least significant bit for the field
   *         WIDTH:     Size of field in bites
   *         MASK:      A masking over a range of bits or a bit to
   *                    be used for setting or clearing
   *
   */
  
  #ifndef _PSM_GLOBAL_REG_H_
  #define _PSM_GLOBAL_REG_H_
  
  #ifdef __cplusplus
  extern "C" {
  #endif
  
  /**
   * PSM_GLOBAL_REG Base Address
   */
  #define PSM_GLOBAL_REG_BASEADDR      0XFFC90000
  
  /**
   * Register: PSM_GLOBAL_REG_GLOBAL_CNTRL
   */
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000000 )
  
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_MB_CLK_EN_FORCE_SHIFT   18
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_MB_CLK_EN_FORCE_WIDTH   1
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_MB_CLK_EN_FORCE_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_MB_DBG_WAKE_SHIFT   17
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_MB_DBG_WAKE_WIDTH   1
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_MB_DBG_WAKE_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_MB_SLEEP_SHIFT   16
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_MB_SLEEP_WIDTH   1
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_MB_SLEEP_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_WRITE_QOS_SHIFT   12
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_WRITE_QOS_WIDTH   4
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_WRITE_QOS_MASK    0X0000F000
  
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_READ_QOS_SHIFT   8
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_READ_QOS_WIDTH   4
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_READ_QOS_MASK    0X00000F00
  
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_FW_IS_PRESENT_SHIFT   4
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_FW_IS_PRESENT_WIDTH   1
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_FW_IS_PRESENT_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_SLVERR_ENABLE_SHIFT   1
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_SLVERR_ENABLE_WIDTH   1
  #define PSM_GLOBAL_REG_GLOBAL_CNTRL_SLVERR_ENABLE_MASK    0X00000002
  
  /**
   * Register: PSM_GLOBAL_REG_APU_PWR_STATUS_INIT
   */
  #define PSM_GLOBAL_REG_APU_PWR_STATUS_INIT    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000008 )
  
  #define PSM_GLOBAL_REG_APU_PWR_STATUS_INIT_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_APU_PWR_STATUS_INIT_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_APU_PWR_STATUS_INIT_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_APU_PWR_STATUS_INIT_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_APU_PWR_STATUS_INIT_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_APU_PWR_STATUS_INIT_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_ADDR_ERROR_STATUS
   */
  #define PSM_GLOBAL_REG_ADDR_ERROR_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000010 )
  
  #define PSM_GLOBAL_REG_ADDR_ERROR_STATUS_STATUS_SHIFT   0
  #define PSM_GLOBAL_REG_ADDR_ERROR_STATUS_STATUS_WIDTH   1
  #define PSM_GLOBAL_REG_ADDR_ERROR_STATUS_STATUS_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_ADDR_ERROR_INT_MASK
   */
  #define PSM_GLOBAL_REG_ADDR_ERROR_INT_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000014 )
  
  #define PSM_GLOBAL_REG_ADDR_ERROR_INT_MASK_MASK_SHIFT   0
  #define PSM_GLOBAL_REG_ADDR_ERROR_INT_MASK_MASK_WIDTH   1
  #define PSM_GLOBAL_REG_ADDR_ERROR_INT_MASK_MASK_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_ADDR_ERROR_INT_EN
   */
  #define PSM_GLOBAL_REG_ADDR_ERROR_INT_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000018 )
  
  #define PSM_GLOBAL_REG_ADDR_ERROR_INT_EN_ENABLE_SHIFT   0
  #define PSM_GLOBAL_REG_ADDR_ERROR_INT_EN_ENABLE_WIDTH   1
  #define PSM_GLOBAL_REG_ADDR_ERROR_INT_EN_ENABLE_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_ADDR_ERROR_INT_DIS
   */
  #define PSM_GLOBAL_REG_ADDR_ERROR_INT_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000001C )
  
  #define PSM_GLOBAL_REG_ADDR_ERROR_INT_DIS_DISABLE_SHIFT   0
  #define PSM_GLOBAL_REG_ADDR_ERROR_INT_DIS_DISABLE_WIDTH   1
  #define PSM_GLOBAL_REG_ADDR_ERROR_INT_DIS_DISABLE_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PS_SW_ERR
   */
  #define PSM_GLOBAL_REG_PS_SW_ERR    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000020 )
  
  #define PSM_GLOBAL_REG_PS_SW_ERR_NCR_FLAG_SHIFT   31
  #define PSM_GLOBAL_REG_PS_SW_ERR_NCR_FLAG_WIDTH   1
  #define PSM_GLOBAL_REG_PS_SW_ERR_NCR_FLAG_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PS_SW_ERR_CR_FLAG_SHIFT   30
  #define PSM_GLOBAL_REG_PS_SW_ERR_CR_FLAG_WIDTH   1
  #define PSM_GLOBAL_REG_PS_SW_ERR_CR_FLAG_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PS_SW_ERR_DATA_SHIFT   0
  #define PSM_GLOBAL_REG_PS_SW_ERR_DATA_WIDTH   30
  #define PSM_GLOBAL_REG_PS_SW_ERR_DATA_MASK    0X3FFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_BOOT_SERV_ERR
   */
  #define PSM_GLOBAL_REG_PSM_BOOT_SERV_ERR    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000024 )
  
  #define PSM_GLOBAL_REG_PSM_BOOT_SERV_ERR_NCR_FLAG_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_BOOT_SERV_ERR_NCR_FLAG_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_BOOT_SERV_ERR_NCR_FLAG_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_BOOT_SERV_ERR_CR_FLAG_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_BOOT_SERV_ERR_CR_FLAG_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_BOOT_SERV_ERR_CR_FLAG_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_BOOT_SERV_ERR_DATA_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_BOOT_SERV_ERR_DATA_WIDTH   30
  #define PSM_GLOBAL_REG_PSM_BOOT_SERV_ERR_DATA_MASK    0X3FFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE0
   */
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE0    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000030 )
  
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE0_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE0_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE0_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE1
   */
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE1    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000034 )
  
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE1_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE1_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE1_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE2
   */
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE2    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000038 )
  
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE2_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE2_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE2_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE3
   */
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE3    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000003C )
  
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE3_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE3_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE3_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE4
   */
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE4    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000040 )
  
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE4_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE4_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE4_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE5
   */
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE5    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000044 )
  
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE5_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE5_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE5_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE6
   */
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE6    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000048 )
  
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE6_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE6_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE6_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE7
   */
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE7    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000004C )
  
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE7_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE7_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_GLOBAL_GEN_STORAGE7_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE0
   */
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE0    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000050 )
  
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE0_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE0_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE0_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE1
   */
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE1    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000054 )
  
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE1_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE1_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE1_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE2
   */
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE2    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000058 )
  
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE2_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE2_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE2_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE3
   */
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE3    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000005C )
  
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE3_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE3_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE3_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE4
   */
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE4    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000060 )
  
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE4_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE4_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE4_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE5
   */
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE5    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000064 )
  
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE5_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE5_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE5_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE6
   */
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE6    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000068 )
  
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE6_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE6_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE6_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE7
   */
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE7    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000006C )
  
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE7_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE7_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_PERS_GLOB_GEN_STORAGE7_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_PWR_STATE
   */
  #define PSM_GLOBAL_REG_PWR_STATE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000100 )
  
  #define PSM_GLOBAL_REG_PWR_STATE_FP_SHIFT   22
  #define PSM_GLOBAL_REG_PWR_STATE_FP_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_FP_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PWR_STATE_GEM0_SHIFT   21
  #define PSM_GLOBAL_REG_PWR_STATE_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_GEM0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PWR_STATE_GEM1_SHIFT   20
  #define PSM_GLOBAL_REG_PWR_STATE_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_GEM1_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PWR_STATE_OCM_BANK3_SHIFT   19
  #define PSM_GLOBAL_REG_PWR_STATE_OCM_BANK3_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_OCM_BANK3_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PWR_STATE_OCM_BANK2_SHIFT   18
  #define PSM_GLOBAL_REG_PWR_STATE_OCM_BANK2_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_OCM_BANK2_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PWR_STATE_OCM_BANK1_SHIFT   17
  #define PSM_GLOBAL_REG_PWR_STATE_OCM_BANK1_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_OCM_BANK1_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PWR_STATE_OCM_BANK0_SHIFT   16
  #define PSM_GLOBAL_REG_PWR_STATE_OCM_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_OCM_BANK0_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PWR_STATE_TCM1B_SHIFT   15
  #define PSM_GLOBAL_REG_PWR_STATE_TCM1B_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_TCM1B_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PWR_STATE_TCM1A_SHIFT   14
  #define PSM_GLOBAL_REG_PWR_STATE_TCM1A_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_TCM1A_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PWR_STATE_TCM0B_SHIFT   13
  #define PSM_GLOBAL_REG_PWR_STATE_TCM0B_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_TCM0B_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PWR_STATE_TCM0A_SHIFT   12
  #define PSM_GLOBAL_REG_PWR_STATE_TCM0A_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_TCM0A_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PWR_STATE_R5_1_SHIFT   11
  #define PSM_GLOBAL_REG_PWR_STATE_R5_1_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_R5_1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PWR_STATE_R5_0_SHIFT   10
  #define PSM_GLOBAL_REG_PWR_STATE_R5_0_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_R5_0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PWR_STATE_L2_BANK0_SHIFT   7
  #define PSM_GLOBAL_REG_PWR_STATE_L2_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_L2_BANK0_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PWR_STATE_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_PWR_STATE_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PWR_STATE_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_PWR_STATE_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_STATE_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_AUX_PWR_STATE
   */
  #define PSM_GLOBAL_REG_AUX_PWR_STATE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000104 )
  
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_ACPU1_EMULATION_SHIFT   29
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_ACPU1_EMULATION_WIDTH   1
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_ACPU1_EMULATION_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_ACPU0_EMULATION_SHIFT   28
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_ACPU0_EMULATION_WIDTH   1
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_ACPU0_EMULATION_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_RPU_EMULATION_SHIFT   27
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_RPU_EMULATION_WIDTH   1
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_RPU_EMULATION_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_OCM_BANK3_SHIFT   19
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_OCM_BANK3_WIDTH   1
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_OCM_BANK3_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_OCM_BANK2_SHIFT   18
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_OCM_BANK2_WIDTH   1
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_OCM_BANK2_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_OCM_BANK1_SHIFT   17
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_OCM_BANK1_WIDTH   1
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_OCM_BANK1_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_OCM_BANK0_SHIFT   16
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_OCM_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_OCM_BANK0_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_TCM1B_SHIFT   15
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_TCM1B_WIDTH   1
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_TCM1B_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_TCM1A_SHIFT   14
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_TCM1A_WIDTH   1
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_TCM1A_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_TCM0B_SHIFT   13
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_TCM0B_WIDTH   1
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_TCM0B_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_TCM0A_SHIFT   12
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_TCM0A_WIDTH   1
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_TCM0A_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_L2_BANK0_SHIFT   7
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_L2_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_AUX_PWR_STATE_L2_BANK0_MASK    0X00000080
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_PWRUP_STATUS
   */
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000110 )
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_FP_SHIFT   22
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_FP_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_GEM0_SHIFT   21
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_GEM0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_GEM1_SHIFT   20
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_GEM1_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_OCM_BANK3_SHIFT   19
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_OCM_BANK3_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_OCM_BANK3_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_OCM_BANK2_SHIFT   18
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_OCM_BANK2_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_OCM_BANK2_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_OCM_BANK1_SHIFT   17
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_OCM_BANK1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_OCM_BANK1_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_OCM_BANK0_SHIFT   16
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_OCM_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_OCM_BANK0_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_TCM1B_SHIFT   15
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_TCM1B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_TCM1B_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_TCM1A_SHIFT   14
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_TCM1A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_TCM1A_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_TCM0B_SHIFT   13
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_TCM0B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_TCM0B_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_TCM0A_SHIFT   12
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_TCM0A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_TCM0A_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_RPU_SHIFT   10
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_RPU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_RPU_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_L2_BANK0_SHIFT   7
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_L2_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_L2_BANK0_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_STATUS_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK
   */
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000114 )
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_FP_SHIFT   22
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_FP_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_GEM0_SHIFT   21
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_GEM0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_GEM1_SHIFT   20
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_GEM1_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_OCM_BANK3_SHIFT   19
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_OCM_BANK3_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_OCM_BANK3_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_OCM_BANK2_SHIFT   18
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_OCM_BANK2_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_OCM_BANK2_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_OCM_BANK1_SHIFT   17
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_OCM_BANK1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_OCM_BANK1_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_OCM_BANK0_SHIFT   16
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_OCM_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_OCM_BANK0_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_TCM1B_SHIFT   15
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_TCM1B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_TCM1B_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_TCM1A_SHIFT   14
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_TCM1A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_TCM1A_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_TCM0B_SHIFT   13
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_TCM0B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_TCM0B_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_TCM0A_SHIFT   12
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_TCM0A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_TCM0A_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_RPU_SHIFT   10
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_RPU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_RPU_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_L2_BANK0_SHIFT   7
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_L2_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_L2_BANK0_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_MASK_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_PWRUP_INT_EN
   */
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000118 )
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_FP_SHIFT   22
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_FP_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_GEM0_SHIFT   21
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_GEM0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_GEM1_SHIFT   20
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_GEM1_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_OCM_BANK3_SHIFT   19
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_OCM_BANK3_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_OCM_BANK3_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_OCM_BANK2_SHIFT   18
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_OCM_BANK2_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_OCM_BANK2_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_OCM_BANK1_SHIFT   17
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_OCM_BANK1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_OCM_BANK1_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_OCM_BANK0_SHIFT   16
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_OCM_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_OCM_BANK0_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_TCM1B_SHIFT   15
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_TCM1B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_TCM1B_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_TCM1A_SHIFT   14
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_TCM1A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_TCM1A_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_TCM0B_SHIFT   13
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_TCM0B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_TCM0B_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_TCM0A_SHIFT   12
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_TCM0A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_TCM0A_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_RPU_SHIFT   10
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_RPU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_RPU_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_L2_BANK0_SHIFT   7
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_L2_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_L2_BANK0_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_EN_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS
   */
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000011C )
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_FP_SHIFT   22
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_FP_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_GEM0_SHIFT   21
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_GEM0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_GEM1_SHIFT   20
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_GEM1_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_OCM_BANK3_SHIFT   19
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_OCM_BANK3_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_OCM_BANK3_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_OCM_BANK2_SHIFT   18
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_OCM_BANK2_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_OCM_BANK2_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_OCM_BANK1_SHIFT   17
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_OCM_BANK1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_OCM_BANK1_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_OCM_BANK0_SHIFT   16
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_OCM_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_OCM_BANK0_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_TCM1B_SHIFT   15
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_TCM1B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_TCM1B_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_TCM1A_SHIFT   14
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_TCM1A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_TCM1A_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_TCM0B_SHIFT   13
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_TCM0B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_TCM0B_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_TCM0A_SHIFT   12
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_TCM0A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_TCM0A_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_RPU_SHIFT   10
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_RPU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_RPU_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_L2_BANK0_SHIFT   7
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_L2_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_L2_BANK0_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_INT_DIS_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_PWRUP_TRIG
   */
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000120 )
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_FP_SHIFT   22
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_FP_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_GEM0_SHIFT   21
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_GEM0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_GEM1_SHIFT   20
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_GEM1_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_OCM_BANK3_SHIFT   19
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_OCM_BANK3_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_OCM_BANK3_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_OCM_BANK2_SHIFT   18
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_OCM_BANK2_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_OCM_BANK2_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_OCM_BANK1_SHIFT   17
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_OCM_BANK1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_OCM_BANK1_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_OCM_BANK0_SHIFT   16
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_OCM_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_OCM_BANK0_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_TCM1B_SHIFT   15
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_TCM1B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_TCM1B_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_TCM1A_SHIFT   14
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_TCM1A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_TCM1A_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_TCM0B_SHIFT   13
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_TCM0B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_TCM0B_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_TCM0A_SHIFT   12
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_TCM0A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_TCM0A_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_RPU_SHIFT   10
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_RPU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_RPU_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_L2_BANK0_SHIFT   7
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_L2_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_L2_BANK0_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRUP_TRIG_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_PWRDWN_STATUS
   */
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000210 )
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_FP_SHIFT   22
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_FP_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_GEM0_SHIFT   21
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_GEM0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_GEM1_SHIFT   20
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_GEM1_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_OCM_BANK3_SHIFT   19
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_OCM_BANK3_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_OCM_BANK3_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_OCM_BANK2_SHIFT   18
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_OCM_BANK2_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_OCM_BANK2_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_OCM_BANK1_SHIFT   17
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_OCM_BANK1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_OCM_BANK1_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_OCM_BANK0_SHIFT   16
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_OCM_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_OCM_BANK0_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_TCM1B_SHIFT   15
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_TCM1B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_TCM1B_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_TCM1A_SHIFT   14
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_TCM1A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_TCM1A_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_TCM0B_SHIFT   13
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_TCM0B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_TCM0B_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_TCM0A_SHIFT   12
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_TCM0A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_TCM0A_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_RPU_SHIFT   10
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_RPU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_RPU_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_L2_BANK0_SHIFT   7
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_L2_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_L2_BANK0_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_STATUS_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK
   */
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000214 )
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_FP_SHIFT   22
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_FP_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_GEM0_SHIFT   21
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_GEM0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_GEM1_SHIFT   20
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_GEM1_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_OCM_BANK3_SHIFT   19
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_OCM_BANK3_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_OCM_BANK3_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_OCM_BANK2_SHIFT   18
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_OCM_BANK2_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_OCM_BANK2_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_OCM_BANK1_SHIFT   17
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_OCM_BANK1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_OCM_BANK1_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_OCM_BANK0_SHIFT   16
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_OCM_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_OCM_BANK0_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_TCM1B_SHIFT   15
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_TCM1B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_TCM1B_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_TCM1A_SHIFT   14
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_TCM1A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_TCM1A_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_TCM0B_SHIFT   13
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_TCM0B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_TCM0B_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_TCM0A_SHIFT   12
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_TCM0A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_TCM0A_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_RPU_SHIFT   10
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_RPU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_RPU_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_L2_BANK0_SHIFT   7
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_L2_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_L2_BANK0_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_MASK_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN
   */
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000218 )
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_FP_SHIFT   22
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_FP_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_GEM0_SHIFT   21
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_GEM0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_GEM1_SHIFT   20
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_GEM1_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_OCM_BANK3_SHIFT   19
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_OCM_BANK3_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_OCM_BANK3_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_OCM_BANK2_SHIFT   18
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_OCM_BANK2_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_OCM_BANK2_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_OCM_BANK1_SHIFT   17
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_OCM_BANK1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_OCM_BANK1_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_OCM_BANK0_SHIFT   16
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_OCM_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_OCM_BANK0_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_TCM1B_SHIFT   15
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_TCM1B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_TCM1B_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_TCM1A_SHIFT   14
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_TCM1A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_TCM1A_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_TCM0B_SHIFT   13
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_TCM0B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_TCM0B_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_TCM0A_SHIFT   12
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_TCM0A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_TCM0A_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_RPU_SHIFT   10
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_RPU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_RPU_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_L2_BANK0_SHIFT   7
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_L2_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_L2_BANK0_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_EN_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS
   */
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000021C )
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_FP_SHIFT   22
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_FP_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_GEM0_SHIFT   21
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_GEM0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_GEM1_SHIFT   20
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_GEM1_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_OCM_BANK3_SHIFT   19
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_OCM_BANK3_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_OCM_BANK3_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_OCM_BANK2_SHIFT   18
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_OCM_BANK2_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_OCM_BANK2_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_OCM_BANK1_SHIFT   17
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_OCM_BANK1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_OCM_BANK1_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_OCM_BANK0_SHIFT   16
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_OCM_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_OCM_BANK0_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_TCM1B_SHIFT   15
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_TCM1B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_TCM1B_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_TCM1A_SHIFT   14
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_TCM1A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_TCM1A_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_TCM0B_SHIFT   13
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_TCM0B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_TCM0B_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_TCM0A_SHIFT   12
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_TCM0A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_TCM0A_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_RPU_SHIFT   10
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_RPU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_RPU_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_L2_BANK0_SHIFT   7
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_L2_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_L2_BANK0_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_INT_DIS_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_PWRDWN_TRIG
   */
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000220 )
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_FP_SHIFT   22
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_FP_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_GEM0_SHIFT   21
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_GEM0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_GEM1_SHIFT   20
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_GEM1_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_OCM_BANK3_SHIFT   19
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_OCM_BANK3_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_OCM_BANK3_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_OCM_BANK2_SHIFT   18
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_OCM_BANK2_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_OCM_BANK2_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_OCM_BANK1_SHIFT   17
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_OCM_BANK1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_OCM_BANK1_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_OCM_BANK0_SHIFT   16
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_OCM_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_OCM_BANK0_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_TCM1B_SHIFT   15
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_TCM1B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_TCM1B_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_TCM1A_SHIFT   14
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_TCM1A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_TCM1A_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_TCM0B_SHIFT   13
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_TCM0B_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_TCM0B_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_TCM0A_SHIFT   12
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_TCM0A_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_TCM0A_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_RPU_SHIFT   10
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_RPU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_RPU_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_L2_BANK0_SHIFT   7
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_L2_BANK0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_L2_BANK0_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_PWRDWN_TRIG_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_ISO_STATUS
   */
  #define PSM_GLOBAL_REG_REQ_ISO_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000310 )
  
  #define PSM_GLOBAL_REG_REQ_ISO_STATUS_FP_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_ISO_STATUS_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_ISO_STATUS_FP_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_ISO_INT_MASK
   */
  #define PSM_GLOBAL_REG_REQ_ISO_INT_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000314 )
  
  #define PSM_GLOBAL_REG_REQ_ISO_INT_MASK_FP_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_ISO_INT_MASK_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_ISO_INT_MASK_FP_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_ISO_INT_EN
   */
  #define PSM_GLOBAL_REG_REQ_ISO_INT_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000318 )
  
  #define PSM_GLOBAL_REG_REQ_ISO_INT_EN_FP_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_ISO_INT_EN_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_ISO_INT_EN_FP_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_ISO_INT_DIS
   */
  #define PSM_GLOBAL_REG_REQ_ISO_INT_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000031C )
  
  #define PSM_GLOBAL_REG_REQ_ISO_INT_DIS_FP_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_ISO_INT_DIS_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_ISO_INT_DIS_FP_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_ISO_TRIG
   */
  #define PSM_GLOBAL_REG_REQ_ISO_TRIG    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000320 )
  
  #define PSM_GLOBAL_REG_REQ_ISO_TRIG_FP_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_ISO_TRIG_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_ISO_TRIG_FP_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_SWRST_STATUS
   */
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000410 )
  
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_FP_SHIFT   30
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_FP_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_LP_SHIFT   29
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_LP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_LP_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_PS_ONLY_SHIFT   28
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_PS_ONLY_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_PS_ONLY_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_IOU_SHIFT   27
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_IOU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_IOU_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_USB0_SHIFT   24
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_USB0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_USB0_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_GEM1_SHIFT   21
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_GEM1_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_GEM0_SHIFT   20
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_GEM0_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_LS_R5_SHIFT   18
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_LS_R5_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_LS_R5_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_APU_SHIFT   4
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_APU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_APU_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_STATUS_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_SWRST_INT_MASK
   */
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000414 )
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_FP_SHIFT   30
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_FP_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_LP_SHIFT   29
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_LP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_LP_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_PS_ONLY_SHIFT   28
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_PS_ONLY_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_PS_ONLY_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_IOU_SHIFT   27
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_IOU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_IOU_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_USB0_SHIFT   24
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_USB0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_USB0_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_GEM1_SHIFT   21
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_GEM1_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_GEM0_SHIFT   20
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_GEM0_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_LS_R5_SHIFT   18
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_LS_R5_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_LS_R5_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_APU_SHIFT   4
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_APU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_APU_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_MASK_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_SWRST_INT_EN
   */
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000418 )
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_FP_SHIFT   30
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_FP_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_LP_SHIFT   29
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_LP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_LP_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_PS_ONLY_SHIFT   28
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_PS_ONLY_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_PS_ONLY_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_IOU_SHIFT   27
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_IOU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_IOU_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_USB0_SHIFT   24
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_USB0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_USB0_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_GEM1_SHIFT   21
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_GEM1_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_GEM0_SHIFT   20
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_GEM0_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_LS_R5_SHIFT   18
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_LS_R5_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_LS_R5_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_APU_SHIFT   4
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_APU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_APU_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_EN_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_SWRST_INT_DIS
   */
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000041C )
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_FP_SHIFT   30
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_FP_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_LP_SHIFT   29
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_LP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_LP_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_PS_ONLY_SHIFT   28
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_PS_ONLY_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_PS_ONLY_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_IOU_SHIFT   27
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_IOU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_IOU_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_USB0_SHIFT   24
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_USB0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_USB0_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_GEM1_SHIFT   21
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_GEM1_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_GEM0_SHIFT   20
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_GEM0_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_LS_R5_SHIFT   18
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_LS_R5_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_LS_R5_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_APU_SHIFT   4
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_APU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_APU_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_INT_DIS_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_SWRST_TRIG
   */
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000420 )
  
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_FP_SHIFT   30
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_FP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_FP_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_LP_SHIFT   29
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_LP_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_LP_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_PS_ONLY_SHIFT   28
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_PS_ONLY_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_PS_ONLY_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_IOU_SHIFT   27
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_IOU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_IOU_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_USB0_SHIFT   24
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_USB0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_USB0_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_GEM1_SHIFT   21
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_GEM1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_GEM1_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_GEM0_SHIFT   20
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_GEM0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_GEM0_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_LS_R5_SHIFT   18
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_LS_R5_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_LS_R5_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_APU_SHIFT   4
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_APU_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_APU_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_SWRST_TRIG_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_AUX_STATUS
   */
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000510 )
  
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_10_SHIFT   17
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_10_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_10_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_9_SHIFT   16
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_9_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_9_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_8_SHIFT   13
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_8_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_8_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_7_SHIFT   12
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_7_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_7_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_6_SHIFT   10
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_6_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_6_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_5_SHIFT   7
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_5_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_4_SHIFT   6
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_4_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_3_SHIFT   3
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_3_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_2_SHIFT   2
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_2_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_STATUS_SERV_REQ_0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_AUX_INT_MASK
   */
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000514 )
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_10_SHIFT   17
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_10_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_10_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_9_SHIFT   16
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_9_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_9_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_8_SHIFT   13
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_8_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_8_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_7_SHIFT   12
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_7_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_7_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_6_SHIFT   10
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_6_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_6_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_5_SHIFT   7
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_5_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_4_SHIFT   6
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_4_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_3_SHIFT   3
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_3_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_2_SHIFT   2
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_2_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_MASK_SERV_REQ_0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_AUX_INT_EN
   */
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000518 )
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_10_SHIFT   17
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_10_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_10_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_9_SHIFT   16
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_9_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_9_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_8_SHIFT   13
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_8_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_8_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_7_SHIFT   12
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_7_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_7_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_6_SHIFT   10
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_6_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_6_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_5_SHIFT   7
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_5_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_4_SHIFT   6
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_4_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_3_SHIFT   3
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_3_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_2_SHIFT   2
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_2_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_EN_SERV_REQ_0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_AUX_INT_DIS
   */
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000051C )
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_10_SHIFT   17
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_10_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_10_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_9_SHIFT   16
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_9_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_9_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_8_SHIFT   13
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_8_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_8_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_7_SHIFT   12
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_7_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_7_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_6_SHIFT   10
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_6_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_6_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_5_SHIFT   7
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_5_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_4_SHIFT   6
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_4_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_3_SHIFT   3
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_3_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_2_SHIFT   2
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_2_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_INT_DIS_SERV_REQ_0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_REQ_AUX_TRIG
   */
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000520 )
  
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_10_SHIFT   17
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_10_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_10_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_9_SHIFT   16
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_9_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_9_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_8_SHIFT   13
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_8_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_8_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_7_SHIFT   12
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_7_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_7_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_6_SHIFT   10
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_6_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_6_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_5_SHIFT   7
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_5_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_4_SHIFT   6
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_4_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_3_SHIFT   3
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_3_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_2_SHIFT   2
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_2_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_1_SHIFT   1
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_1_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_0_SHIFT   0
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_0_WIDTH   1
  #define PSM_GLOBAL_REG_REQ_AUX_TRIG_SERV_REQ_0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_MB_FATAL
   */
  #define PSM_GLOBAL_REG_MB_FATAL    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000052C )
  
  #define PSM_GLOBAL_REG_MB_FATAL_CPU3_SHIFT   2
  #define PSM_GLOBAL_REG_MB_FATAL_CPU3_WIDTH   1
  #define PSM_GLOBAL_REG_MB_FATAL_CPU3_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_MB_FATAL_CPU2_SHIFT   1
  #define PSM_GLOBAL_REG_MB_FATAL_CPU2_WIDTH   1
  #define PSM_GLOBAL_REG_MB_FATAL_CPU2_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_MB_FATAL_CPU1_SHIFT   0
  #define PSM_GLOBAL_REG_MB_FATAL_CPU1_WIDTH   1
  #define PSM_GLOBAL_REG_MB_FATAL_CPU1_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_MB1_FAULT_STATUS
   */
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000530 )
  
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_CPU3_SHIFT   14
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_CPU3_WIDTH   1
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_CPU3_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_CPU2_SHIFT   13
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_CPU2_WIDTH   1
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_CPU2_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_CPU1_SHIFT   12
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_CPU1_WIDTH   1
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_CPU1_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_FT_STATE_SHIFT   10
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_FT_STATE_WIDTH   2
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_FT_STATE_MASK    0X00000C00
  
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_WDT_EXP_SHIFT   9
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_WDT_EXP_WIDTH   1
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_WDT_EXP_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_UNCORR_ERR_SHIFT   8
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_UNCORR_ERR_WIDTH   1
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_UNCORR_ERR_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_VOTER_ERR_SHIFT   7
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_VOTER_ERR_WIDTH   1
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_VOTER_ERR_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_FTL_MISMATCH_SHIFT   4
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_FTL_MISMATCH_WIDTH   3
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_FTL_MISMATCH_MASK    0X00000070
  
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_LS_RECOVER_SHIFT   3
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_LS_RECOVER_WIDTH   1
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_LS_RECOVER_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_LS_MISMATCH_SHIFT   0
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_LS_MISMATCH_WIDTH   3
  #define PSM_GLOBAL_REG_MB1_FAULT_STATUS_LS_MISMATCH_MASK    0X00000007
  
  /**
   * Register: PSM_GLOBAL_REG_MB2_FAULT_STATUS
   */
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000534 )
  
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_CPU3_SHIFT   14
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_CPU3_WIDTH   1
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_CPU3_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_CPU2_SHIFT   13
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_CPU2_WIDTH   1
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_CPU2_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_CPU1_SHIFT   12
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_CPU1_WIDTH   1
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_CPU1_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_FT_STATE_SHIFT   10
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_FT_STATE_WIDTH   2
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_FT_STATE_MASK    0X00000C00
  
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_WDT_EXP_SHIFT   9
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_WDT_EXP_WIDTH   1
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_WDT_EXP_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_UNCORR_ERR_SHIFT   8
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_UNCORR_ERR_WIDTH   1
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_UNCORR_ERR_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_VOTER_ERR_SHIFT   7
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_VOTER_ERR_WIDTH   1
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_VOTER_ERR_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_FTL_MISMATCH_SHIFT   4
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_FTL_MISMATCH_WIDTH   3
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_FTL_MISMATCH_MASK    0X00000070
  
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_LS_RECOVER_SHIFT   3
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_LS_RECOVER_WIDTH   1
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_LS_RECOVER_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_LS_MISMATCH_SHIFT   0
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_LS_MISMATCH_WIDTH   3
  #define PSM_GLOBAL_REG_MB2_FAULT_STATUS_LS_MISMATCH_MASK    0X00000007
  
  /**
   * Register: PSM_GLOBAL_REG_MB3_FAULT_STATUS
   */
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000538 )
  
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_CPU3_SHIFT   14
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_CPU3_WIDTH   1
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_CPU3_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_CPU2_SHIFT   13
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_CPU2_WIDTH   1
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_CPU2_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_CPU1_SHIFT   12
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_CPU1_WIDTH   1
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_CPU1_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_FT_STATE_SHIFT   10
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_FT_STATE_WIDTH   2
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_FT_STATE_MASK    0X00000C00
  
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_WDT_EXP_SHIFT   9
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_WDT_EXP_WIDTH   1
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_WDT_EXP_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_UNCORR_ERR_SHIFT   8
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_UNCORR_ERR_WIDTH   1
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_UNCORR_ERR_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_VOTER_ERR_SHIFT   7
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_VOTER_ERR_WIDTH   1
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_VOTER_ERR_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_FTL_MISMATCH_SHIFT   4
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_FTL_MISMATCH_WIDTH   3
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_FTL_MISMATCH_MASK    0X00000070
  
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_LS_RECOVER_SHIFT   3
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_LS_RECOVER_WIDTH   1
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_LS_RECOVER_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_LS_MISMATCH_SHIFT   0
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_LS_MISMATCH_WIDTH   3
  #define PSM_GLOBAL_REG_MB3_FAULT_STATUS_LS_MISMATCH_MASK    0X00000007
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_DEBUG_CTRL
   */
  #define PSM_GLOBAL_REG_PSM_DEBUG_CTRL    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000540 )
  
  #define PSM_GLOBAL_REG_PSM_DEBUG_CTRL_EN_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_DEBUG_CTRL_EN_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_DEBUG_CTRL_EN_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS
   */
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000700 )
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_INTFPD_SHIFT   27
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_INTFPD_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_INTFPD_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_INTLPD_SHIFT   26
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_INTLPD_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_INTLPD_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_FPD_DBG_SHIFT   25
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_FPD_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_FPD_DBG_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_R5S_DBG_SHIFT   24
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_R5S_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_R5S_DBG_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU1_DBG_SHIFT   21
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU1_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU1_DBG_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU0_DBG_SHIFT   20
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU0_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU0_DBG_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU1_CORESIGHT_SHIFT   17
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU1_CORESIGHT_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU1_CORESIGHT_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU0_CORESIGHT_SHIFT   16
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU0_CORESIGHT_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU0_CORESIGHT_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO5_SHIFT   15
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO5_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO4_SHIFT   14
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO4_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO3_SHIFT   13
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO3_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO2_SHIFT   12
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO2_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO1_SHIFT   11
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO1_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO0_SHIFT   10
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO0_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_MIO0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_USB0_SHIFT   6
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_USB0_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_USB0_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_R51_SHIFT   5
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_R51_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_R51_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_R50_SHIFT   4
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_R50_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_R50_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_STATUS_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_WAKEUP_IRQ_MASK
   */
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000704 )
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_INTFPD_SHIFT   27
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_INTFPD_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_INTFPD_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_INTLPD_SHIFT   26
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_INTLPD_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_INTLPD_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_FPD_DBG_SHIFT   25
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_FPD_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_FPD_DBG_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_R5S_DBG_SHIFT   24
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_R5S_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_R5S_DBG_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU1_DBG_SHIFT   21
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU1_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU1_DBG_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU0_DBG_SHIFT   20
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU0_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU0_DBG_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU1_CORESIGHT_SHIFT   17
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU1_CORESIGHT_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU1_CORESIGHT_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU0_CORESIGHT_SHIFT   16
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU0_CORESIGHT_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU0_CORESIGHT_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO5_SHIFT   15
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO5_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO4_SHIFT   14
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO4_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO3_SHIFT   13
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO3_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO2_SHIFT   12
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO2_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO1_SHIFT   11
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO1_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO0_SHIFT   10
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO0_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_MIO0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_USB0_SHIFT   6
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_USB0_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_USB0_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_R51_SHIFT   5
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_R51_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_R51_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_R50_SHIFT   4
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_R50_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_R50_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_MASK_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_WAKEUP_IRQ_EN
   */
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000708 )
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_INTFPD_SHIFT   27
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_INTFPD_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_INTFPD_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_INTLPD_SHIFT   26
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_INTLPD_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_INTLPD_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_FPD_DBG_SHIFT   25
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_FPD_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_FPD_DBG_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_R5S_DBG_SHIFT   24
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_R5S_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_R5S_DBG_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU1_DBG_SHIFT   21
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU1_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU1_DBG_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU0_DBG_SHIFT   20
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU0_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU0_DBG_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU1_CORESIGHT_SHIFT   17
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU1_CORESIGHT_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU1_CORESIGHT_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU0_CORESIGHT_SHIFT   16
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU0_CORESIGHT_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU0_CORESIGHT_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO5_SHIFT   15
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO5_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO4_SHIFT   14
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO4_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO3_SHIFT   13
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO3_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO2_SHIFT   12
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO2_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO1_SHIFT   11
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO1_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO0_SHIFT   10
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO0_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_MIO0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_USB0_SHIFT   6
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_USB0_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_USB0_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_R51_SHIFT   5
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_R51_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_R51_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_R50_SHIFT   4
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_R50_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_R50_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_EN_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_WAKEUP_IRQ_DIS
   */
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000070C )
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_INTFPD_SHIFT   27
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_INTFPD_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_INTFPD_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_INTLPD_SHIFT   26
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_INTLPD_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_INTLPD_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_FPD_DBG_SHIFT   25
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_FPD_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_FPD_DBG_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_R5S_DBG_SHIFT   24
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_R5S_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_R5S_DBG_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU1_DBG_SHIFT   21
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU1_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU1_DBG_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU0_DBG_SHIFT   20
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU0_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU0_DBG_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU1_CORESIGHT_SHIFT   17
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU1_CORESIGHT_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU1_CORESIGHT_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU0_CORESIGHT_SHIFT   16
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU0_CORESIGHT_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU0_CORESIGHT_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO5_SHIFT   15
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO5_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO4_SHIFT   14
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO4_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO3_SHIFT   13
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO3_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO2_SHIFT   12
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO2_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO1_SHIFT   11
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO1_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO0_SHIFT   10
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO0_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_MIO0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_USB0_SHIFT   6
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_USB0_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_USB0_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_R51_SHIFT   5
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_R51_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_R51_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_R50_SHIFT   4
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_R50_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_R50_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_DIS_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG
   */
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000710 )
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_INTFPD_SHIFT   27
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_INTFPD_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_INTFPD_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_INTLPD_SHIFT   26
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_INTLPD_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_INTLPD_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_FPD_DBG_SHIFT   25
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_FPD_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_FPD_DBG_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_R5S_DBG_SHIFT   24
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_R5S_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_R5S_DBG_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU1_DBG_SHIFT   21
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU1_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU1_DBG_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU0_DBG_SHIFT   20
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU0_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU0_DBG_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU1_CORESIGHT_SHIFT   17
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU1_CORESIGHT_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU1_CORESIGHT_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU0_CORESIGHT_SHIFT   16
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU0_CORESIGHT_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU0_CORESIGHT_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO5_SHIFT   15
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO5_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO4_SHIFT   14
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO4_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO3_SHIFT   13
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO3_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO2_SHIFT   12
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO2_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO1_SHIFT   11
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO1_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO0_SHIFT   10
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO0_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_MIO0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_USB0_SHIFT   6
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_USB0_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_USB0_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_R51_SHIFT   5
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_R51_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_R51_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_R50_SHIFT   4
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_R50_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_R50_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_WAKEUP_IRQ_TRIG_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS
   */
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000714 )
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_FPD_SUPPLY_SHIFT   24
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_FPD_SUPPLY_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_FPD_SUPPLY_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_APU1_DBG_RST_SHIFT   21
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_APU1_DBG_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_APU1_DBG_RST_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_APU0_DBG_RST_SHIFT   20
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_APU0_DBG_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_APU0_DBG_RST_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_APU1_RST_SHIFT   17
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_APU1_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_APU1_RST_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_APU0_RST_SHIFT   16
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_APU0_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_APU0_RST_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_RPU0_DBG_SHIFT   8
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_RPU0_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_RPU0_DBG_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_R51_SHIFT   5
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_R51_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_R51_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_R50_SHIFT   4
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_R50_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_R50_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_STATUS_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK
   */
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000718 )
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_FPD_SUPPLY_SHIFT   24
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_FPD_SUPPLY_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_FPD_SUPPLY_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_APU1_DBG_RST_SHIFT   21
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_APU1_DBG_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_APU1_DBG_RST_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_APU0_DBG_RST_SHIFT   20
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_APU0_DBG_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_APU0_DBG_RST_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_APU1_RST_SHIFT   17
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_APU1_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_APU1_RST_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_APU0_RST_SHIFT   16
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_APU0_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_APU0_RST_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_RPU0_DBG_SHIFT   8
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_RPU0_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_RPU0_DBG_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_R51_SHIFT   5
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_R51_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_R51_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_R50_SHIFT   4
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_R50_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_R50_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_MASK_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN
   */
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000071C )
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_FPD_SUPPLY_SHIFT   24
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_FPD_SUPPLY_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_FPD_SUPPLY_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_APU1_DBG_RST_SHIFT   21
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_APU1_DBG_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_APU1_DBG_RST_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_APU0_DBG_RST_SHIFT   20
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_APU0_DBG_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_APU0_DBG_RST_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_APU1_RST_SHIFT   17
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_APU1_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_APU1_RST_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_APU0_RST_SHIFT   16
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_APU0_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_APU0_RST_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_RPU0_DBG_SHIFT   8
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_RPU0_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_RPU0_DBG_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_R51_SHIFT   5
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_R51_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_R51_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_R50_SHIFT   4
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_R50_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_R50_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_EN_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS
   */
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000720 )
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_FPD_SUPPLY_SHIFT   24
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_FPD_SUPPLY_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_FPD_SUPPLY_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_APU1_DBG_RST_SHIFT   21
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_APU1_DBG_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_APU1_DBG_RST_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_APU0_DBG_RST_SHIFT   20
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_APU0_DBG_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_APU0_DBG_RST_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_APU1_RST_SHIFT   17
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_APU1_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_APU1_RST_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_APU0_RST_SHIFT   16
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_APU0_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_APU0_RST_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_RPU0_DBG_SHIFT   8
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_RPU0_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_RPU0_DBG_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_R51_SHIFT   5
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_R51_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_R51_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_R50_SHIFT   4
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_R50_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_R50_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_DIS_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG
   */
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000724 )
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_FPD_SUPPLY_SHIFT   24
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_FPD_SUPPLY_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_FPD_SUPPLY_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_APU1_DBG_RST_SHIFT   21
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_APU1_DBG_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_APU1_DBG_RST_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_APU0_DBG_RST_SHIFT   20
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_APU0_DBG_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_APU0_DBG_RST_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_APU1_RST_SHIFT   17
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_APU1_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_APU1_RST_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_APU0_RST_SHIFT   16
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_APU0_RST_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_APU0_RST_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_RPU0_DBG_SHIFT   8
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_RPU0_DBG_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_RPU0_DBG_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_R51_SHIFT   5
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_R51_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_R51_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_R50_SHIFT   4
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_R50_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_R50_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_ACPU1_SHIFT   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_ACPU1_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_ACPU1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_ACPU0_SHIFT   0
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_ACPU0_WIDTH   1
  #define PSM_GLOBAL_REG_PWR_CTRL_IRQ_TRIG_ACPU0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_MB_TEST
   */
  #define PSM_GLOBAL_REG_PSM_MB_TEST    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000800 )
  
  #define PSM_GLOBAL_REG_PSM_MB_TEST_TMR_DISABLE_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_MB_TEST_TMR_DISABLE_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_MB_TEST_TMR_DISABLE_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_SAFETY_GATE
   */
  #define PSM_GLOBAL_REG_SAFETY_GATE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000804 )
  
  #define PSM_GLOBAL_REG_SAFETY_GATE_PSM_LOGCLR_ENABLE_SHIFT   2
  #define PSM_GLOBAL_REG_SAFETY_GATE_PSM_LOGCLR_ENABLE_WIDTH   1
  #define PSM_GLOBAL_REG_SAFETY_GATE_PSM_LOGCLR_ENABLE_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_SAFETY_GATE_LBIST_ENABLE_SHIFT   1
  #define PSM_GLOBAL_REG_SAFETY_GATE_LBIST_ENABLE_WIDTH   1
  #define PSM_GLOBAL_REG_SAFETY_GATE_LBIST_ENABLE_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_SAFETY_GATE_SCAN_ENABLE_SHIFT   0
  #define PSM_GLOBAL_REG_SAFETY_GATE_SCAN_ENABLE_WIDTH   1
  #define PSM_GLOBAL_REG_SAFETY_GATE_SCAN_ENABLE_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_DBG_PWR_ACK
   */
  #define PSM_GLOBAL_REG_DBG_PWR_ACK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000808 )
  
  #define PSM_GLOBAL_REG_DBG_PWR_ACK_FPD_SHIFT   3
  #define PSM_GLOBAL_REG_DBG_PWR_ACK_FPD_WIDTH   1
  #define PSM_GLOBAL_REG_DBG_PWR_ACK_FPD_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_DBG_PWR_ACK_R5S_SHIFT   2
  #define PSM_GLOBAL_REG_DBG_PWR_ACK_R5S_WIDTH   1
  #define PSM_GLOBAL_REG_DBG_PWR_ACK_R5S_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_DBG_PWR_ACK_A72_1_SHIFT   1
  #define PSM_GLOBAL_REG_DBG_PWR_ACK_A72_1_WIDTH   1
  #define PSM_GLOBAL_REG_DBG_PWR_ACK_A72_1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_DBG_PWR_ACK_A72_0_SHIFT   0
  #define PSM_GLOBAL_REG_DBG_PWR_ACK_A72_0_WIDTH   1
  #define PSM_GLOBAL_REG_DBG_PWR_ACK_A72_0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_MBIST_RSTN
   */
  #define PSM_GLOBAL_REG_MBIST_RSTN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000900 )
  
  #define PSM_GLOBAL_REG_MBIST_RSTN_INT_FPD_SHIFT   4
  #define PSM_GLOBAL_REG_MBIST_RSTN_INT_FPD_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_RSTN_INT_FPD_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_MBIST_RSTN_CCI_SHIFT   3
  #define PSM_GLOBAL_REG_MBIST_RSTN_CCI_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_RSTN_CCI_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_MBIST_RSTN_CPU1_SHIFT   2
  #define PSM_GLOBAL_REG_MBIST_RSTN_CPU1_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_RSTN_CPU1_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_MBIST_RSTN_CPU0_SHIFT   1
  #define PSM_GLOBAL_REG_MBIST_RSTN_CPU0_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_RSTN_CPU0_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_MBIST_RSTN_APU_SHIFT   0
  #define PSM_GLOBAL_REG_MBIST_RSTN_APU_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_RSTN_APU_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_MBIST_PG_EN
   */
  #define PSM_GLOBAL_REG_MBIST_PG_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000904 )
  
  #define PSM_GLOBAL_REG_MBIST_PG_EN_INT_FPD_SHIFT   4
  #define PSM_GLOBAL_REG_MBIST_PG_EN_INT_FPD_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_PG_EN_INT_FPD_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_MBIST_PG_EN_CCI_SHIFT   3
  #define PSM_GLOBAL_REG_MBIST_PG_EN_CCI_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_PG_EN_CCI_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_MBIST_PG_EN_CPU1_SHIFT   2
  #define PSM_GLOBAL_REG_MBIST_PG_EN_CPU1_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_PG_EN_CPU1_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_MBIST_PG_EN_CPU0_SHIFT   1
  #define PSM_GLOBAL_REG_MBIST_PG_EN_CPU0_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_PG_EN_CPU0_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_MBIST_PG_EN_APU_SHIFT   0
  #define PSM_GLOBAL_REG_MBIST_PG_EN_APU_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_PG_EN_APU_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_MBIST_SETUP
   */
  #define PSM_GLOBAL_REG_MBIST_SETUP    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000908 )
  
  #define PSM_GLOBAL_REG_MBIST_SETUP_INT_FPD_SHIFT   4
  #define PSM_GLOBAL_REG_MBIST_SETUP_INT_FPD_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_SETUP_INT_FPD_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_MBIST_SETUP_CCI_SHIFT   3
  #define PSM_GLOBAL_REG_MBIST_SETUP_CCI_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_SETUP_CCI_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_MBIST_SETUP_CPU1_SHIFT   2
  #define PSM_GLOBAL_REG_MBIST_SETUP_CPU1_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_SETUP_CPU1_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_MBIST_SETUP_CPU0_SHIFT   1
  #define PSM_GLOBAL_REG_MBIST_SETUP_CPU0_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_SETUP_CPU0_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_MBIST_SETUP_APU_SHIFT   0
  #define PSM_GLOBAL_REG_MBIST_SETUP_APU_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_SETUP_APU_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_MBIST_DONE
   */
  #define PSM_GLOBAL_REG_MBIST_DONE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000910 )
  
  #define PSM_GLOBAL_REG_MBIST_DONE_INT_FPD_SHIFT   4
  #define PSM_GLOBAL_REG_MBIST_DONE_INT_FPD_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_DONE_INT_FPD_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_MBIST_DONE_CCI_SHIFT   3
  #define PSM_GLOBAL_REG_MBIST_DONE_CCI_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_DONE_CCI_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_MBIST_DONE_CPU1_SHIFT   2
  #define PSM_GLOBAL_REG_MBIST_DONE_CPU1_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_DONE_CPU1_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_MBIST_DONE_CPU0_SHIFT   1
  #define PSM_GLOBAL_REG_MBIST_DONE_CPU0_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_DONE_CPU0_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_MBIST_DONE_APU_SHIFT   0
  #define PSM_GLOBAL_REG_MBIST_DONE_APU_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_DONE_APU_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_MBIST_GO
   */
  #define PSM_GLOBAL_REG_MBIST_GO    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000914 )
  
  #define PSM_GLOBAL_REG_MBIST_GO_INT_FPD_SHIFT   4
  #define PSM_GLOBAL_REG_MBIST_GO_INT_FPD_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_GO_INT_FPD_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_MBIST_GO_CCI_SHIFT   3
  #define PSM_GLOBAL_REG_MBIST_GO_CCI_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_GO_CCI_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_MBIST_GO_CPU1_SHIFT   2
  #define PSM_GLOBAL_REG_MBIST_GO_CPU1_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_GO_CPU1_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_MBIST_GO_CPU0_SHIFT   1
  #define PSM_GLOBAL_REG_MBIST_GO_CPU0_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_GO_CPU0_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_MBIST_GO_APU_SHIFT   0
  #define PSM_GLOBAL_REG_MBIST_GO_APU_WIDTH   1
  #define PSM_GLOBAL_REG_MBIST_GO_APU_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_SCAN_CLEAR_CPU0
   */
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU0    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000920 )
  
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU0_PASS_SHIFT   2
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU0_PASS_WIDTH   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU0_PASS_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU0_DONE_SHIFT   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU0_DONE_WIDTH   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU0_DONE_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU0_TRIGGER_SHIFT   0
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU0_TRIGGER_WIDTH   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU0_TRIGGER_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_SCAN_CLEAR_CPU1
   */
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU1    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000924 )
  
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU1_PASS_SHIFT   2
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU1_PASS_WIDTH   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU1_PASS_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU1_DONE_SHIFT   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU1_DONE_WIDTH   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU1_DONE_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU1_TRIGGER_SHIFT   0
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU1_TRIGGER_WIDTH   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_CPU1_TRIGGER_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_SCAN_CLEAR_APU
   */
  #define PSM_GLOBAL_REG_SCAN_CLEAR_APU    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000928 )
  
  #define PSM_GLOBAL_REG_SCAN_CLEAR_APU_PASS_SHIFT   2
  #define PSM_GLOBAL_REG_SCAN_CLEAR_APU_PASS_WIDTH   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_APU_PASS_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_SCAN_CLEAR_APU_DONE_SHIFT   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_APU_DONE_WIDTH   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_APU_DONE_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_SCAN_CLEAR_APU_TRIGGER_SHIFT   0
  #define PSM_GLOBAL_REG_SCAN_CLEAR_APU_TRIGGER_WIDTH   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_APU_TRIGGER_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_SCAN_CLEAR_FPD
   */
  #define PSM_GLOBAL_REG_SCAN_CLEAR_FPD    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000092C )
  
  #define PSM_GLOBAL_REG_SCAN_CLEAR_FPD_PASS_SHIFT   2
  #define PSM_GLOBAL_REG_SCAN_CLEAR_FPD_PASS_WIDTH   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_FPD_PASS_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_SCAN_CLEAR_FPD_DONE_SHIFT   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_FPD_DONE_WIDTH   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_FPD_DONE_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_SCAN_CLEAR_FPD_TRIGGER_SHIFT   0
  #define PSM_GLOBAL_REG_SCAN_CLEAR_FPD_TRIGGER_WIDTH   1
  #define PSM_GLOBAL_REG_SCAN_CLEAR_FPD_TRIGGER_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_SAFETY_CHK
   */
  #define PSM_GLOBAL_REG_SAFETY_CHK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000A00 )
  
  #define PSM_GLOBAL_REG_SAFETY_CHK_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_SAFETY_CHK_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_SAFETY_CHK_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_ECO_1
   */
  #define PSM_GLOBAL_REG_ECO_1    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000A04 )
  
  #define PSM_GLOBAL_REG_ECO_1_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_ECO_1_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_ECO_1_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_ECO_2
   */
  #define PSM_GLOBAL_REG_ECO_2    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00000A08 )
  
  #define PSM_GLOBAL_REG_ECO_2_VALUE_SHIFT   0
  #define PSM_GLOBAL_REG_ECO_2_VALUE_WIDTH   32
  #define PSM_GLOBAL_REG_ECO_2_VALUE_MASK    0XFFFFFFFF
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_ERR1_STATUS
   */
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001000 )
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RSRV_ERR6_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RSRV_ERR6_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RSRV_ERR5_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RSRV_ERR5_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RSRV_ERR4_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RSRV_ERR4_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RSRV_ERR3_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RSRV_ERR3_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RSRV_ERR2_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RSRV_ERR2_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_TO_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_TO_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_FPD_TO_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_FPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_FPD_TO_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_LPD_TO_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_LPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_LPD_TO_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_PAR_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_PAR_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_IOU_PAR_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_IOU_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_IOU_PAR_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_FPD_PAR_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_FPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_FPD_PAR_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_LPD_PAR_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_LPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_LPD_PAR_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_FPD_APB_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_FPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_FPD_APB_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_LPD_APB_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_LPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_LPD_APB_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_CPM_NCR_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_CPM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_CPM_NCR_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_CPM_CR_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_CPM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_CPM_CR_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RPLL_LOCK_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RPLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RPLL_LOCK_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_APLL_LOCK_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_APLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_APLL_LOCK_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_GIC_ECC_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_GIC_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_GIC_ECC_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_GIC_AXI_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_GIC_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_GIC_AXI_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RPU_CCF_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RPU_CCF_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RPU_CCF_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RPU_LS_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RPU_LS_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RPU_LS_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RPU_ECC_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RPU_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_RPU_ECC_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_L2_ECC_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_L2_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_L2_ECC_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_OCM_ECC_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_OCM_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_OCM_ECC_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_NCR_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_NCR_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_CR_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_CR_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_MB_FATAL_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_MB_FATAL_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_MB_FATAL_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_B_NCR_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_B_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_B_NCR_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_B_CR_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_B_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PSM_B_CR_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PS_SW_NCR_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PS_SW_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PS_SW_NCR_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PS_SW_CR_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PS_SW_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_STATUS_PS_SW_CR_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_ERR2_STATUS
   */
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001004 )
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR9_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR9_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR9_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR8_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR8_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR8_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR7_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR7_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR6_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR6_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR5_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR5_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR4_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR4_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR3_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR3_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR2_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR2_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR1_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR1_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR10_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR10_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR10_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR0_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_RSRV_ERR0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_XMPU_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_XMPU_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_XPPU_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_XPPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_XPPU_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_XMPU_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_XMPU_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON7_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON7_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON6_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON6_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON5_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON4_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON3_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON2_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON1_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON0_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SMON0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON7_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON7_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON6_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON6_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON5_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON4_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON3_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON3_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON2_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON2_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON1_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON1_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON0_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SMON0_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SWDT_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_FPD_SWDT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SWDT_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_STATUS_LPD_SWDT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_ERR1_TRIG
   */
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001010 )
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RSRV_ERR6_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RSRV_ERR6_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RSRV_ERR5_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RSRV_ERR5_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RSRV_ERR4_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RSRV_ERR4_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RSRV_ERR3_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RSRV_ERR3_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RSRV_ERR2_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RSRV_ERR2_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_TO_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_TO_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_FPD_TO_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_FPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_FPD_TO_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_LPD_TO_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_LPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_LPD_TO_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_PAR_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_PAR_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_IOU_PAR_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_IOU_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_IOU_PAR_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_FPD_PAR_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_FPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_FPD_PAR_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_LPD_PAR_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_LPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_LPD_PAR_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_FPD_APB_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_FPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_FPD_APB_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_LPD_APB_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_LPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_LPD_APB_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_CPM_NCR_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_CPM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_CPM_NCR_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_CPM_CR_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_CPM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_CPM_CR_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RPLL_LOCK_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RPLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RPLL_LOCK_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_APLL_LOCK_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_APLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_APLL_LOCK_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_GIC_ECC_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_GIC_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_GIC_ECC_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_GIC_AXI_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_GIC_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_GIC_AXI_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RPU_CCF_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RPU_CCF_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RPU_CCF_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RPU_LS_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RPU_LS_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RPU_LS_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RPU_ECC_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RPU_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_RPU_ECC_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_L2_ECC_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_L2_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_L2_ECC_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_OCM_ECC_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_OCM_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_OCM_ECC_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_NCR_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_NCR_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_CR_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_CR_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_MB_FATAL_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_MB_FATAL_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_MB_FATAL_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_B_NCR_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_B_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_B_NCR_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_B_CR_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_B_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PSM_B_CR_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PS_SW_NCR_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PS_SW_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PS_SW_NCR_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PS_SW_CR_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PS_SW_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR1_TRIG_PS_SW_CR_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_ERR2_TRIG
   */
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001014 )
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR9_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR9_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR9_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR8_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR8_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR8_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR7_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR7_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR6_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR6_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR5_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR5_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR4_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR4_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR3_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR3_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR2_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR2_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR1_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR1_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR10_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR10_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR10_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR0_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_RSRV_ERR0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_XMPU_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_XMPU_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_XPPU_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_XPPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_XPPU_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_XMPU_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_XMPU_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON7_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON7_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON6_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON6_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON5_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON4_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON3_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON2_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON1_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON0_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SMON0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON7_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON7_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON6_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON6_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON5_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON4_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON3_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON3_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON2_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON2_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON1_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON1_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON0_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SMON0_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SWDT_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_FPD_SWDT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SWDT_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_ERR2_TRIG_LPD_SWDT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_CR_ERR1_MASK
   */
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001020 )
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RSRV_ERR6_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RSRV_ERR6_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RSRV_ERR5_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RSRV_ERR5_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RSRV_ERR4_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RSRV_ERR4_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RSRV_ERR3_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RSRV_ERR3_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RSRV_ERR2_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RSRV_ERR2_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_TO_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_TO_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_FPD_TO_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_FPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_FPD_TO_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_LPD_TO_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_LPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_LPD_TO_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_PAR_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_PAR_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_IOU_PAR_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_IOU_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_IOU_PAR_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_FPD_PAR_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_FPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_FPD_PAR_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_LPD_PAR_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_LPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_LPD_PAR_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_FPD_APB_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_FPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_FPD_APB_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_LPD_APB_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_LPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_LPD_APB_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_CPM_NCR_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_CPM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_CPM_NCR_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_CPM_CR_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_CPM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_CPM_CR_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RPLL_LOCK_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RPLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RPLL_LOCK_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_APLL_LOCK_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_APLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_APLL_LOCK_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_GIC_ECC_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_GIC_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_GIC_ECC_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_GIC_AXI_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_GIC_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_GIC_AXI_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RPU_CCF_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RPU_CCF_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RPU_CCF_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RPU_LS_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RPU_LS_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RPU_LS_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RPU_ECC_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RPU_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_RPU_ECC_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_L2_ECC_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_L2_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_L2_ECC_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_OCM_ECC_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_OCM_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_OCM_ECC_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_NCR_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_NCR_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_CR_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_CR_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_MB_FATAL_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_MB_FATAL_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_MB_FATAL_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_B_NCR_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_B_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_B_NCR_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_B_CR_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_B_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PSM_B_CR_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PS_SW_NCR_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PS_SW_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PS_SW_NCR_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PS_SW_CR_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PS_SW_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_MASK_PS_SW_CR_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_CR_ERR1_EN
   */
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001024 )
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RSRV_ERR6_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RSRV_ERR6_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RSRV_ERR5_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RSRV_ERR5_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RSRV_ERR4_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RSRV_ERR4_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RSRV_ERR3_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RSRV_ERR3_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RSRV_ERR2_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RSRV_ERR2_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_TO_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_TO_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_FPD_TO_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_FPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_FPD_TO_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_LPD_TO_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_LPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_LPD_TO_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_PAR_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_PAR_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_IOU_PAR_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_IOU_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_IOU_PAR_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_FPD_PAR_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_FPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_FPD_PAR_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_LPD_PAR_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_LPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_LPD_PAR_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_FPD_APB_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_FPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_FPD_APB_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_LPD_APB_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_LPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_LPD_APB_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_CPM_NCR_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_CPM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_CPM_NCR_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_CPM_CR_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_CPM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_CPM_CR_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RPLL_LOCK_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RPLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RPLL_LOCK_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_APLL_LOCK_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_APLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_APLL_LOCK_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_GIC_ECC_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_GIC_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_GIC_ECC_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_GIC_AXI_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_GIC_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_GIC_AXI_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RPU_CCF_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RPU_CCF_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RPU_CCF_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RPU_LS_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RPU_LS_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RPU_LS_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RPU_ECC_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RPU_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_RPU_ECC_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_L2_ECC_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_L2_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_L2_ECC_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_OCM_ECC_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_OCM_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_OCM_ECC_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_NCR_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_NCR_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_CR_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_CR_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_MB_FATAL_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_MB_FATAL_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_MB_FATAL_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_B_NCR_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_B_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_B_NCR_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_B_CR_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_B_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PSM_B_CR_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PS_SW_NCR_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PS_SW_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PS_SW_NCR_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PS_SW_CR_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PS_SW_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_EN_PS_SW_CR_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_CR_ERR1_DIS
   */
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001028 )
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RSRV_ERR6_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RSRV_ERR6_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RSRV_ERR5_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RSRV_ERR5_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RSRV_ERR4_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RSRV_ERR4_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RSRV_ERR3_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RSRV_ERR3_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RSRV_ERR2_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RSRV_ERR2_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_TO_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_TO_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_FPD_TO_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_FPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_FPD_TO_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_LPD_TO_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_LPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_LPD_TO_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_PAR_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_PAR_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_IOU_PAR_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_IOU_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_IOU_PAR_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_FPD_PAR_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_FPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_FPD_PAR_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_LPD_PAR_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_LPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_LPD_PAR_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_FPD_APB_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_FPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_FPD_APB_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_LPD_APB_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_LPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_LPD_APB_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_CPM_NCR_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_CPM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_CPM_NCR_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_CPM_CR_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_CPM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_CPM_CR_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RPLL_LOCK_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RPLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RPLL_LOCK_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_APLL_LOCK_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_APLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_APLL_LOCK_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_GIC_ECC_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_GIC_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_GIC_ECC_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_GIC_AXI_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_GIC_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_GIC_AXI_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RPU_CCF_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RPU_CCF_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RPU_CCF_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RPU_LS_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RPU_LS_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RPU_LS_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RPU_ECC_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RPU_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_RPU_ECC_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_L2_ECC_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_L2_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_L2_ECC_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_OCM_ECC_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_OCM_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_OCM_ECC_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_NCR_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_NCR_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_CR_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_CR_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_MB_FATAL_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_MB_FATAL_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_MB_FATAL_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_B_NCR_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_B_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_B_NCR_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_B_CR_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_B_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PSM_B_CR_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PS_SW_NCR_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PS_SW_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PS_SW_NCR_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PS_SW_CR_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PS_SW_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR1_DIS_PS_SW_CR_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_CR_ERR2_MASK
   */
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001030 )
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR9_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR9_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR9_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR8_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR8_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR8_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR7_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR7_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR6_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR6_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR5_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR5_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR4_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR4_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR3_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR3_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR2_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR2_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR1_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR1_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR10_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR10_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR10_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR0_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_RSRV_ERR0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_XMPU_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_XMPU_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_XPPU_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_XPPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_XPPU_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_XMPU_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_XMPU_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON7_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON7_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON6_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON6_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON5_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON4_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON3_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON2_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON1_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON0_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SMON0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON7_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON7_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON6_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON6_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON5_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON4_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON3_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON3_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON2_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON2_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON1_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON1_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON0_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SMON0_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SWDT_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_FPD_SWDT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SWDT_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_MASK_LPD_SWDT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_CR_ERR2_EN
   */
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001034 )
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR9_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR9_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR9_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR8_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR8_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR8_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR7_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR7_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR6_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR6_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR5_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR5_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR4_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR4_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR3_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR3_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR2_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR2_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR1_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR1_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR10_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR10_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR10_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR0_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_RSRV_ERR0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_XMPU_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_XMPU_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_XPPU_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_XPPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_XPPU_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_XMPU_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_XMPU_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON7_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON7_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON6_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON6_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON5_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON4_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON3_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON2_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON1_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON0_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SMON0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON7_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON7_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON6_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON6_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON5_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON4_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON3_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON3_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON2_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON2_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON1_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON1_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON0_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SMON0_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SWDT_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_FPD_SWDT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SWDT_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_EN_LPD_SWDT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_CR_ERR2_DIS
   */
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001038 )
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR9_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR9_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR9_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR8_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR8_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR8_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR7_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR7_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR6_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR6_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR5_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR5_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR4_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR4_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR3_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR3_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR2_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR2_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR1_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR1_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR10_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR10_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR10_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR0_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_RSRV_ERR0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_XMPU_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_XMPU_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_XPPU_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_XPPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_XPPU_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_XMPU_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_XMPU_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON7_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON7_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON6_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON6_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON5_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON4_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON3_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON2_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON1_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON0_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SMON0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON7_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON7_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON6_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON6_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON5_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON4_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON3_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON3_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON2_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON2_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON1_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON1_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON0_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SMON0_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SWDT_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_FPD_SWDT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SWDT_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_CR_ERR2_DIS_LPD_SWDT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK
   */
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001040 )
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RSRV_ERR6_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RSRV_ERR6_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RSRV_ERR5_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RSRV_ERR5_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RSRV_ERR4_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RSRV_ERR4_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RSRV_ERR3_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RSRV_ERR3_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RSRV_ERR2_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RSRV_ERR2_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_TO_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_TO_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_FPD_TO_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_FPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_FPD_TO_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_LPD_TO_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_LPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_LPD_TO_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_PAR_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_PAR_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_IOU_PAR_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_IOU_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_IOU_PAR_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_FPD_PAR_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_FPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_FPD_PAR_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_LPD_PAR_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_LPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_LPD_PAR_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_FPD_APB_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_FPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_FPD_APB_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_LPD_APB_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_LPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_LPD_APB_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_CPM_NCR_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_CPM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_CPM_NCR_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_CPM_CR_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_CPM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_CPM_CR_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RPLL_LOCK_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RPLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RPLL_LOCK_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_APLL_LOCK_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_APLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_APLL_LOCK_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_GIC_ECC_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_GIC_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_GIC_ECC_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_GIC_AXI_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_GIC_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_GIC_AXI_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RPU_CCF_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RPU_CCF_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RPU_CCF_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RPU_LS_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RPU_LS_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RPU_LS_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RPU_ECC_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RPU_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_RPU_ECC_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_L2_ECC_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_L2_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_L2_ECC_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_OCM_ECC_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_OCM_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_OCM_ECC_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_NCR_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_NCR_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_CR_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_CR_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_MB_FATAL_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_MB_FATAL_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_MB_FATAL_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_B_NCR_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_B_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_B_NCR_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_B_CR_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_B_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PSM_B_CR_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PS_SW_NCR_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PS_SW_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PS_SW_NCR_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PS_SW_CR_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PS_SW_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_MASK_PS_SW_CR_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_NCR_ERR1_EN
   */
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001044 )
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RSRV_ERR6_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RSRV_ERR6_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RSRV_ERR5_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RSRV_ERR5_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RSRV_ERR4_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RSRV_ERR4_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RSRV_ERR3_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RSRV_ERR3_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RSRV_ERR2_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RSRV_ERR2_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_TO_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_TO_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_FPD_TO_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_FPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_FPD_TO_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_LPD_TO_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_LPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_LPD_TO_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_PAR_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_PAR_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_IOU_PAR_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_IOU_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_IOU_PAR_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_FPD_PAR_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_FPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_FPD_PAR_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_LPD_PAR_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_LPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_LPD_PAR_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_FPD_APB_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_FPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_FPD_APB_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_LPD_APB_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_LPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_LPD_APB_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_CPM_NCR_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_CPM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_CPM_NCR_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_CPM_CR_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_CPM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_CPM_CR_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RPLL_LOCK_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RPLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RPLL_LOCK_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_APLL_LOCK_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_APLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_APLL_LOCK_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_GIC_ECC_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_GIC_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_GIC_ECC_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_GIC_AXI_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_GIC_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_GIC_AXI_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RPU_CCF_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RPU_CCF_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RPU_CCF_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RPU_LS_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RPU_LS_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RPU_LS_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RPU_ECC_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RPU_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_RPU_ECC_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_L2_ECC_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_L2_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_L2_ECC_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_OCM_ECC_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_OCM_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_OCM_ECC_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_NCR_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_NCR_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_CR_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_CR_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_MB_FATAL_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_MB_FATAL_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_MB_FATAL_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_B_NCR_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_B_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_B_NCR_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_B_CR_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_B_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PSM_B_CR_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PS_SW_NCR_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PS_SW_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PS_SW_NCR_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PS_SW_CR_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PS_SW_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_EN_PS_SW_CR_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS
   */
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001048 )
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RSRV_ERR6_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RSRV_ERR6_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RSRV_ERR5_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RSRV_ERR5_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RSRV_ERR4_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RSRV_ERR4_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RSRV_ERR3_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RSRV_ERR3_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RSRV_ERR2_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RSRV_ERR2_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_TO_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_TO_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_FPD_TO_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_FPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_FPD_TO_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_LPD_TO_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_LPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_LPD_TO_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_PAR_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_PAR_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_IOU_PAR_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_IOU_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_IOU_PAR_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_FPD_PAR_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_FPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_FPD_PAR_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_LPD_PAR_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_LPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_LPD_PAR_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_FPD_APB_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_FPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_FPD_APB_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_LPD_APB_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_LPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_LPD_APB_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_CPM_NCR_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_CPM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_CPM_NCR_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_CPM_CR_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_CPM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_CPM_CR_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RPLL_LOCK_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RPLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RPLL_LOCK_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_APLL_LOCK_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_APLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_APLL_LOCK_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_GIC_ECC_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_GIC_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_GIC_ECC_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_GIC_AXI_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_GIC_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_GIC_AXI_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RPU_CCF_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RPU_CCF_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RPU_CCF_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RPU_LS_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RPU_LS_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RPU_LS_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RPU_ECC_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RPU_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_RPU_ECC_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_L2_ECC_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_L2_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_L2_ECC_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_OCM_ECC_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_OCM_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_OCM_ECC_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_NCR_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_NCR_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_CR_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_CR_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_MB_FATAL_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_MB_FATAL_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_MB_FATAL_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_B_NCR_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_B_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_B_NCR_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_B_CR_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_B_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PSM_B_CR_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PS_SW_NCR_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PS_SW_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PS_SW_NCR_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PS_SW_CR_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PS_SW_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR1_DIS_PS_SW_CR_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK
   */
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001050 )
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR9_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR9_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR9_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR8_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR8_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR8_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR7_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR7_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR6_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR6_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR5_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR5_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR4_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR4_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR3_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR3_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR2_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR2_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR1_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR1_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR10_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR10_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR10_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR0_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_RSRV_ERR0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_XMPU_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_XMPU_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_XPPU_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_XPPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_XPPU_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_XMPU_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_XMPU_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON7_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON7_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON6_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON6_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON5_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON4_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON3_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON2_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON1_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON0_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SMON0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON7_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON7_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON6_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON6_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON5_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON4_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON3_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON3_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON2_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON2_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON1_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON1_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON0_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SMON0_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SWDT_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_FPD_SWDT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SWDT_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_MASK_LPD_SWDT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_NCR_ERR2_EN
   */
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001054 )
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR9_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR9_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR9_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR8_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR8_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR8_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR7_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR7_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR6_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR6_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR5_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR5_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR4_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR4_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR3_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR3_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR2_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR2_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR1_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR1_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR10_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR10_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR10_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR0_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_RSRV_ERR0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_XMPU_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_XMPU_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_XPPU_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_XPPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_XPPU_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_XMPU_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_XMPU_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON7_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON7_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON6_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON6_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON5_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON4_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON3_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON2_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON1_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON0_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SMON0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON7_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON7_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON6_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON6_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON5_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON4_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON3_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON3_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON2_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON2_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON1_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON1_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON0_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SMON0_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SWDT_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_FPD_SWDT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SWDT_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_EN_LPD_SWDT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS
   */
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001058 )
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR9_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR9_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR9_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR8_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR8_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR8_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR7_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR7_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR6_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR6_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR5_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR5_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR4_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR4_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR3_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR3_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR2_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR2_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR1_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR1_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR10_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR10_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR10_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR0_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_RSRV_ERR0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_XMPU_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_XMPU_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_XPPU_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_XPPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_XPPU_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_XMPU_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_XMPU_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON7_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON7_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON6_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON6_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON5_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON4_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON3_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON2_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON1_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON0_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SMON0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON7_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON7_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON6_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON6_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON5_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON4_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON3_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON3_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON2_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON2_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON1_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON1_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON0_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SMON0_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SWDT_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_FPD_SWDT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SWDT_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_NCR_ERR2_DIS_LPD_SWDT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_IRQ1_MASK
   */
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001060 )
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RSRV_ERR6_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RSRV_ERR6_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RSRV_ERR5_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RSRV_ERR5_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RSRV_ERR4_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RSRV_ERR4_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RSRV_ERR3_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RSRV_ERR3_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RSRV_ERR2_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RSRV_ERR2_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_TO_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_TO_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_FPD_TO_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_FPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_FPD_TO_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_LPD_TO_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_LPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_LPD_TO_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_PAR_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_PAR_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_IOU_PAR_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_IOU_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_IOU_PAR_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_FPD_PAR_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_FPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_FPD_PAR_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_LPD_PAR_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_LPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_LPD_PAR_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_FPD_APB_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_FPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_FPD_APB_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_LPD_APB_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_LPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_LPD_APB_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_CPM_NCR_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_CPM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_CPM_NCR_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_CPM_CR_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_CPM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_CPM_CR_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RPLL_LOCK_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RPLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RPLL_LOCK_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_APLL_LOCK_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_APLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_APLL_LOCK_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_GIC_ECC_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_GIC_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_GIC_ECC_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_GIC_AXI_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_GIC_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_GIC_AXI_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RPU_CCF_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RPU_CCF_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RPU_CCF_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RPU_LS_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RPU_LS_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RPU_LS_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RPU_ECC_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RPU_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_RPU_ECC_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_L2_ECC_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_L2_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_L2_ECC_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_OCM_ECC_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_OCM_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_OCM_ECC_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_NCR_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_NCR_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_CR_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_CR_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_MB_FATAL_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_MB_FATAL_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_MB_FATAL_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_B_NCR_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_B_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_B_NCR_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_B_CR_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_B_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PSM_B_CR_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PS_SW_NCR_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PS_SW_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PS_SW_NCR_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PS_SW_CR_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PS_SW_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_MASK_PS_SW_CR_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_IRQ1_EN
   */
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001064 )
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RSRV_ERR6_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RSRV_ERR6_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RSRV_ERR5_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RSRV_ERR5_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RSRV_ERR4_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RSRV_ERR4_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RSRV_ERR3_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RSRV_ERR3_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RSRV_ERR2_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RSRV_ERR2_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_TO_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_TO_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_FPD_TO_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_FPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_FPD_TO_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_LPD_TO_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_LPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_LPD_TO_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_PAR_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_PAR_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_IOU_PAR_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_IOU_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_IOU_PAR_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_FPD_PAR_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_FPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_FPD_PAR_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_LPD_PAR_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_LPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_LPD_PAR_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_FPD_APB_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_FPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_FPD_APB_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_LPD_APB_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_LPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_LPD_APB_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_CPM_NCR_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_CPM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_CPM_NCR_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_CPM_CR_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_CPM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_CPM_CR_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RPLL_LOCK_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RPLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RPLL_LOCK_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_APLL_LOCK_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_APLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_APLL_LOCK_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_GIC_ECC_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_GIC_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_GIC_ECC_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_GIC_AXI_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_GIC_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_GIC_AXI_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RPU_CCF_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RPU_CCF_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RPU_CCF_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RPU_LS_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RPU_LS_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RPU_LS_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RPU_ECC_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RPU_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_RPU_ECC_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_L2_ECC_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_L2_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_L2_ECC_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_OCM_ECC_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_OCM_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_OCM_ECC_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_NCR_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_NCR_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_CR_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_CR_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_MB_FATAL_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_MB_FATAL_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_MB_FATAL_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_B_NCR_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_B_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_B_NCR_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_B_CR_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_B_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PSM_B_CR_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PS_SW_NCR_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PS_SW_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PS_SW_NCR_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PS_SW_CR_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PS_SW_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_EN_PS_SW_CR_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_IRQ1_DIS
   */
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001068 )
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RSRV_ERR6_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RSRV_ERR6_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RSRV_ERR5_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RSRV_ERR5_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RSRV_ERR4_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RSRV_ERR4_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RSRV_ERR3_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RSRV_ERR3_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RSRV_ERR2_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RSRV_ERR2_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_TO_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_TO_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_FPD_TO_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_FPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_FPD_TO_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_LPD_TO_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_LPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_LPD_TO_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_PAR_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_PAR_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_IOU_PAR_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_IOU_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_IOU_PAR_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_FPD_PAR_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_FPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_FPD_PAR_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_LPD_PAR_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_LPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_LPD_PAR_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_FPD_APB_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_FPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_FPD_APB_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_LPD_APB_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_LPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_LPD_APB_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_CPM_NCR_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_CPM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_CPM_NCR_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_CPM_CR_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_CPM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_CPM_CR_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RPLL_LOCK_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RPLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RPLL_LOCK_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_APLL_LOCK_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_APLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_APLL_LOCK_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_GIC_ECC_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_GIC_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_GIC_ECC_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_GIC_AXI_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_GIC_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_GIC_AXI_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RPU_CCF_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RPU_CCF_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RPU_CCF_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RPU_LS_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RPU_LS_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RPU_LS_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RPU_ECC_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RPU_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_RPU_ECC_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_L2_ECC_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_L2_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_L2_ECC_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_OCM_ECC_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_OCM_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_OCM_ECC_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_NCR_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_NCR_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_CR_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_CR_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_MB_FATAL_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_MB_FATAL_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_MB_FATAL_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_B_NCR_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_B_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_B_NCR_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_B_CR_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_B_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PSM_B_CR_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PS_SW_NCR_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PS_SW_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PS_SW_NCR_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PS_SW_CR_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PS_SW_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ1_DIS_PS_SW_CR_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_IRQ2_MASK
   */
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001070 )
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR9_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR9_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR9_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR8_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR8_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR8_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR7_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR7_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR6_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR6_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR5_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR5_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR4_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR4_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR3_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR3_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR2_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR2_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR1_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR1_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR10_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR10_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR10_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR0_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_RSRV_ERR0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_XMPU_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_XMPU_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_XPPU_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_XPPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_XPPU_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_XMPU_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_XMPU_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON7_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON7_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON6_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON6_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON5_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON4_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON3_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON2_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON1_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON0_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SMON0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON7_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON7_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON6_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON6_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON5_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON4_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON3_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON3_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON2_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON2_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON1_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON1_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON0_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SMON0_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SWDT_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_FPD_SWDT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SWDT_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_MASK_LPD_SWDT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_IRQ2_EN
   */
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001074 )
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR9_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR9_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR9_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR8_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR8_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR8_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR7_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR7_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR6_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR6_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR5_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR5_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR4_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR4_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR3_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR3_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR2_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR2_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR1_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR1_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR10_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR10_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR10_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR0_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_RSRV_ERR0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_XMPU_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_XMPU_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_XPPU_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_XPPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_XPPU_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_XMPU_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_XMPU_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON7_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON7_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON6_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON6_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON5_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON4_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON3_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON2_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON1_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON0_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SMON0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON7_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON7_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON6_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON6_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON5_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON4_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON3_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON3_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON2_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON2_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON1_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON1_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON0_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SMON0_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SWDT_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_FPD_SWDT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SWDT_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_EN_LPD_SWDT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_IRQ2_DIS
   */
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001078 )
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR9_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR9_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR9_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR8_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR8_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR8_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR7_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR7_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR6_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR6_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR5_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR5_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR4_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR4_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR3_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR3_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR2_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR2_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR1_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR1_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR10_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR10_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR10_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR0_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_RSRV_ERR0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_XMPU_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_XMPU_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_XPPU_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_XPPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_XPPU_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_XMPU_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_XMPU_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON7_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON7_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON6_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON6_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON5_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON4_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON3_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON2_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON1_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON0_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SMON0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON7_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON7_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON6_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON6_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON5_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON4_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON3_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON3_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON2_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON2_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON1_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON1_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON0_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SMON0_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SWDT_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_FPD_SWDT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SWDT_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_IRQ2_DIS_LPD_SWDT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_SRST1_MASK
   */
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001080 )
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RSRV_ERR6_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RSRV_ERR6_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RSRV_ERR5_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RSRV_ERR5_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RSRV_ERR4_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RSRV_ERR4_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RSRV_ERR3_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RSRV_ERR3_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RSRV_ERR2_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RSRV_ERR2_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_TO_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_TO_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_FPD_TO_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_FPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_FPD_TO_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_LPD_TO_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_LPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_LPD_TO_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_PAR_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_PAR_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_IOU_PAR_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_IOU_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_IOU_PAR_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_FPD_PAR_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_FPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_FPD_PAR_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_LPD_PAR_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_LPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_LPD_PAR_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_FPD_APB_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_FPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_FPD_APB_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_LPD_APB_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_LPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_LPD_APB_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_CPM_NCR_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_CPM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_CPM_NCR_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_CPM_CR_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_CPM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_CPM_CR_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RPLL_LOCK_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RPLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RPLL_LOCK_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_APLL_LOCK_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_APLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_APLL_LOCK_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_GIC_ECC_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_GIC_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_GIC_ECC_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_GIC_AXI_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_GIC_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_GIC_AXI_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RPU_CCF_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RPU_CCF_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RPU_CCF_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RPU_LS_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RPU_LS_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RPU_LS_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RPU_ECC_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RPU_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_RPU_ECC_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_L2_ECC_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_L2_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_L2_ECC_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_OCM_ECC_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_OCM_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_OCM_ECC_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_NCR_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_NCR_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_CR_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_CR_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_MB_FATAL_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_MB_FATAL_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_MB_FATAL_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_B_NCR_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_B_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_B_NCR_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_B_CR_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_B_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PSM_B_CR_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PS_SW_NCR_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PS_SW_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PS_SW_NCR_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PS_SW_CR_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PS_SW_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_MASK_PS_SW_CR_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_SRST1_EN
   */
  #define PSM_GLOBAL_REG_PSM_SRST1_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001084 )
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RSRV_ERR6_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RSRV_ERR6_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RSRV_ERR5_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RSRV_ERR5_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RSRV_ERR4_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RSRV_ERR4_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RSRV_ERR3_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RSRV_ERR3_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RSRV_ERR2_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RSRV_ERR2_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_TO_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_TO_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_FPD_TO_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_FPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_FPD_TO_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_LPD_TO_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_LPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_LPD_TO_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_PAR_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_PAR_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_IOU_PAR_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_IOU_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_IOU_PAR_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_FPD_PAR_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_FPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_FPD_PAR_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_LPD_PAR_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_LPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_LPD_PAR_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_FPD_APB_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_FPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_FPD_APB_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_LPD_APB_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_LPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_LPD_APB_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_CPM_NCR_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_CPM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_CPM_NCR_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_CPM_CR_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_CPM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_CPM_CR_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RPLL_LOCK_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RPLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RPLL_LOCK_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_APLL_LOCK_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_APLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_APLL_LOCK_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_GIC_ECC_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_GIC_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_GIC_ECC_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_GIC_AXI_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_GIC_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_GIC_AXI_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RPU_CCF_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RPU_CCF_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RPU_CCF_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RPU_LS_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RPU_LS_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RPU_LS_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RPU_ECC_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RPU_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_RPU_ECC_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_L2_ECC_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_L2_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_L2_ECC_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_OCM_ECC_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_OCM_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_OCM_ECC_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_NCR_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_NCR_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_CR_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_CR_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_MB_FATAL_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_MB_FATAL_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_MB_FATAL_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_B_NCR_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_B_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_B_NCR_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_B_CR_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_B_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PSM_B_CR_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PS_SW_NCR_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PS_SW_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PS_SW_NCR_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PS_SW_CR_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PS_SW_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_EN_PS_SW_CR_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_SRST1_DIS
   */
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001088 )
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RSRV_ERR6_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RSRV_ERR6_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RSRV_ERR5_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RSRV_ERR5_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RSRV_ERR4_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RSRV_ERR4_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RSRV_ERR3_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RSRV_ERR3_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RSRV_ERR2_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RSRV_ERR2_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_TO_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_TO_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_FPD_TO_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_FPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_FPD_TO_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_LPD_TO_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_LPD_TO_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_LPD_TO_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_PAR_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_PAR_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_IOU_PAR_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_IOU_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_IOU_PAR_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_FPD_PAR_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_FPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_FPD_PAR_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_LPD_PAR_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_LPD_PAR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_LPD_PAR_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_FPD_APB_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_FPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_FPD_APB_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_LPD_APB_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_LPD_APB_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_LPD_APB_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_CPM_NCR_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_CPM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_CPM_NCR_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_CPM_CR_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_CPM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_CPM_CR_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RPLL_LOCK_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RPLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RPLL_LOCK_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_APLL_LOCK_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_APLL_LOCK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_APLL_LOCK_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_GIC_ECC_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_GIC_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_GIC_ECC_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_GIC_AXI_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_GIC_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_GIC_AXI_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RPU_CCF_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RPU_CCF_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RPU_CCF_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RPU_LS_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RPU_LS_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RPU_LS_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RPU_ECC_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RPU_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_RPU_ECC_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_L2_ECC_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_L2_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_L2_ECC_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_OCM_ECC_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_OCM_ECC_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_OCM_ECC_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_NCR_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_NCR_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_CR_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_CR_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_MB_FATAL_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_MB_FATAL_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_MB_FATAL_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_B_NCR_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_B_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_B_NCR_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_B_CR_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_B_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PSM_B_CR_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PS_SW_NCR_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PS_SW_NCR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PS_SW_NCR_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PS_SW_CR_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PS_SW_CR_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST1_DIS_PS_SW_CR_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_SRST2_MASK
   */
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001090 )
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR9_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR9_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR9_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR8_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR8_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR8_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR7_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR7_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR6_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR6_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR5_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR5_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR4_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR4_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR3_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR3_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR2_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR2_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR1_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR1_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR10_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR10_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR10_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR0_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_RSRV_ERR0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_XMPU_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_XMPU_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_XPPU_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_XPPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_XPPU_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_XMPU_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_XMPU_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON7_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON7_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON6_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON6_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON5_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON4_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON3_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON2_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON1_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON0_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SMON0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON7_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON7_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON6_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON6_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON5_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON4_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON3_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON3_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON2_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON2_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON1_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON1_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON0_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SMON0_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SWDT_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_FPD_SWDT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SWDT_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_MASK_LPD_SWDT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_SRST2_EN
   */
  #define PSM_GLOBAL_REG_PSM_SRST2_EN    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001094 )
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR9_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR9_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR9_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR8_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR8_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR8_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR7_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR7_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR6_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR6_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR5_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR5_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR4_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR4_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR3_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR3_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR2_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR2_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR1_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR1_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR10_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR10_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR10_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR0_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_RSRV_ERR0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_XMPU_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_XMPU_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_XPPU_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_XPPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_XPPU_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_XMPU_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_XMPU_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON7_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON7_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON6_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON6_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON5_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON4_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON3_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON2_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON1_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON0_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SMON0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON7_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON7_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON6_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON6_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON5_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON4_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON3_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON3_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON2_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON2_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON1_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON1_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON0_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SMON0_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SWDT_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_FPD_SWDT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SWDT_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_EN_LPD_SWDT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_SRST2_DIS
   */
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00001098 )
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR9_SHIFT   31
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR9_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR9_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR8_SHIFT   30
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR8_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR8_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR7_SHIFT   29
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR7_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR6_SHIFT   28
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR6_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR5_SHIFT   27
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR5_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR4_SHIFT   26
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR4_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR3_SHIFT   25
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR3_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR2_SHIFT   24
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR2_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR1_SHIFT   23
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR1_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR10_SHIFT   22
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR10_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR10_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR0_SHIFT   21
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_RSRV_ERR0_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_XMPU_SHIFT   20
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_XMPU_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_XPPU_SHIFT   19
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_XPPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_XPPU_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_XMPU_SHIFT   18
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_XMPU_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_XMPU_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON7_SHIFT   17
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON7_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON6_SHIFT   16
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON6_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON5_SHIFT   15
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON5_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON4_SHIFT   14
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON4_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON3_SHIFT   13
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON3_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON2_SHIFT   12
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON2_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON1_SHIFT   11
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON1_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON0_SHIFT   10
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SMON0_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON7_SHIFT   9
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON7_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON7_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON6_SHIFT   8
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON6_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON6_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON5_SHIFT   7
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON5_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON5_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON4_SHIFT   6
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON4_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON4_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON3_SHIFT   5
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON3_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON3_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON2_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON2_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON2_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON1_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON1_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON1_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON0_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON0_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SMON0_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SWDT_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_FPD_SWDT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SWDT_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SWDT_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_SRST2_DIS_LPD_SWDT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP0_IRQ_STATUS
   */
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002000 )
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_STATUS_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP0_IRQ_MASK
   */
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002004 )
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_MASK_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP0_IRQ_ENABLE
   */
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002008 )
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_ENABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP0_IRQ_DISABLE
   */
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000200C )
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_DISABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER
   */
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002010 )
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP0_IRQ_TRIGGER_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP1_IRQ_STATUS
   */
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002014 )
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_STATUS_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP1_IRQ_MASK
   */
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002018 )
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_MASK_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP1_IRQ_ENABLE
   */
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000201C )
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_ENABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP1_IRQ_DISABLE
   */
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002020 )
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_DISABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER
   */
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002024 )
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP1_IRQ_TRIGGER_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP2_IRQ_STATUS
   */
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002028 )
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_STATUS_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP2_IRQ_MASK
   */
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000202C )
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_MASK_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP2_IRQ_ENABLE
   */
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002030 )
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_ENABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP2_IRQ_DISABLE
   */
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002034 )
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_DISABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER
   */
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002038 )
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP2_IRQ_TRIGGER_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP3_IRQ_STATUS
   */
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000203C )
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_STATUS_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP3_IRQ_MASK
   */
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002040 )
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_MASK_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP3_IRQ_ENABLE
   */
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002044 )
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_ENABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP3_IRQ_DISABLE
   */
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002048 )
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_DISABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER
   */
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000204C )
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP3_IRQ_TRIGGER_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP4_IRQ_STATUS
   */
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002050 )
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_STATUS_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP4_IRQ_MASK
   */
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002054 )
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_MASK_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP4_IRQ_ENABLE
   */
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002058 )
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_ENABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP4_IRQ_DISABLE
   */
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000205C )
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_DISABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER
   */
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002060 )
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP4_IRQ_TRIGGER_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP5_IRQ_STATUS
   */
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002064 )
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_STATUS_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP5_IRQ_MASK
   */
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002068 )
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_MASK_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP5_IRQ_ENABLE
   */
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000206C )
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_ENABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP5_IRQ_DISABLE
   */
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002070 )
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_DISABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER
   */
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002074 )
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP5_IRQ_TRIGGER_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP6_IRQ_STATUS
   */
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002078 )
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_STATUS_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP6_IRQ_MASK
   */
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000207C )
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_MASK_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP6_IRQ_ENABLE
   */
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002080 )
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_ENABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP6_IRQ_DISABLE
   */
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002084 )
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_DISABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER
   */
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002088 )
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP6_IRQ_TRIGGER_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP7_IRQ_STATUS
   */
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000208C )
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_STATUS_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP7_IRQ_MASK
   */
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002090 )
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_MASK_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP7_IRQ_ENABLE
   */
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002094 )
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_ENABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP7_IRQ_DISABLE
   */
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00002098 )
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_DISABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER
   */
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000209C )
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC31_SHIFT   31
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC31_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC31_MASK    0X80000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC30_SHIFT   30
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC30_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC30_MASK    0X40000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC29_SHIFT   29
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC29_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC29_MASK    0X20000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC28_SHIFT   28
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC28_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC28_MASK    0X10000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC27_SHIFT   27
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC27_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC27_MASK    0X08000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC26_SHIFT   26
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC26_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC26_MASK    0X04000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC25_SHIFT   25
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC25_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC25_MASK    0X02000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC24_SHIFT   24
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC24_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC24_MASK    0X01000000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC23_SHIFT   23
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC23_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC23_MASK    0X00800000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC22_SHIFT   22
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC22_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC22_MASK    0X00400000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC21_SHIFT   21
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC21_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC21_MASK    0X00200000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC20_SHIFT   20
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC20_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC20_MASK    0X00100000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC19_SHIFT   19
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC19_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC19_MASK    0X00080000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC18_SHIFT   18
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC18_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC18_MASK    0X00040000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC17_SHIFT   17
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC17_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC17_MASK    0X00020000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC16_SHIFT   16
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC16_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC16_MASK    0X00010000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC15_SHIFT   15
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC15_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC15_MASK    0X00008000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC14_SHIFT   14
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC14_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC14_MASK    0X00004000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC13_SHIFT   13
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC13_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC13_MASK    0X00002000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC12_SHIFT   12
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC12_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC12_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC11_SHIFT   11
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC11_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC11_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC10_SHIFT   10
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC10_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC10_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC9_SHIFT   9
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC9_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC9_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC8_SHIFT   8
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC8_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC8_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP7_IRQ_TRIGGER_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS
   */
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X000020A0 )
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_STATUS_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK
   */
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X000020A4 )
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_MASK_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE
   */
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X000020A8 )
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_ENABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE
   */
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X000020AC )
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_DISABLE_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER
   */
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X000020B0 )
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC7_SHIFT   7
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC7_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC7_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC6_SHIFT   6
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC6_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC6_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC5_SHIFT   5
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC5_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC5_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC4_SHIFT   4
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC4_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC4_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC3_SHIFT   3
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC3_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC3_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC2_SHIFT   2
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC2_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC2_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC1_SHIFT   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC1_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC1_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC0_SHIFT   0
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC0_WIDTH   1
  #define PSM_GLOBAL_REG_GICP_PSM_IRQ_TRIGGER_SRC0_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_IR_STATUS
   */
  #define PSM_GLOBAL_REG_IR_STATUS    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00003000 )
  
  #define PSM_GLOBAL_REG_IR_STATUS_MDM_APB_MAINMISSIONINT_SHIFT   12
  #define PSM_GLOBAL_REG_IR_STATUS_MDM_APB_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_MDM_APB_MAINMISSIONINT_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_IR_STATUS_MDM_APB_MAINLATENTINT_SHIFT   11
  #define PSM_GLOBAL_REG_IR_STATUS_MDM_APB_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_MDM_APB_MAINLATENTINT_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_GLOBAL_APB_MAINMISSIONINT_SHIFT   10
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_GLOBAL_APB_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_GLOBAL_APB_MAINMISSIONINT_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_GLOBAL_APB_MAINLATENTINT_SHIFT   9
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_GLOBAL_APB_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_GLOBAL_APB_MAINLATENTINT_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_IR_STATUS_APB_POWER_MAINMISSIONINT_SHIFT   8
  #define PSM_GLOBAL_REG_IR_STATUS_APB_POWER_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_APB_POWER_MAINMISSIONINT_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_IR_STATUS_APB_POWER_MAINLATENTINT_SHIFT   7
  #define PSM_GLOBAL_REG_IR_STATUS_APB_POWER_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_APB_POWER_MAINLATENTINT_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_IR_STATUS_PSM_MAINMISSIONINT_SHIFT   6
  #define PSM_GLOBAL_REG_IR_STATUS_PSM_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_PSM_MAINMISSIONINT_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_IR_STATUS_PSM_MAINLATENTINT_SHIFT   5
  #define PSM_GLOBAL_REG_IR_STATUS_PSM_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_PSM_MAINLATENTINT_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_INTLPD_MAINMISSIONINT_SHIFT   4
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_INTLPD_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_INTLPD_MAINMISSIONINT_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_INTLPD_MAINLATENTINT_SHIFT   3
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_INTLPD_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_INTLPD_MAINLATENTINT_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_IR_STATUS_PSM_APB_MAINTIMEOUT_SHIFT   2
  #define PSM_GLOBAL_REG_IR_STATUS_PSM_APB_MAINTIMEOUT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_PSM_APB_MAINTIMEOUT_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_MDM_MAINTIMEOUT_SHIFT   1
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_MDM_MAINTIMEOUT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_MDM_MAINTIMEOUT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_INTLPD_MAINTIMEOUT_SHIFT   0
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_INTLPD_MAINTIMEOUT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_INTPSM_INTLPD_MAINTIMEOUT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_IR_MASK
   */
  #define PSM_GLOBAL_REG_IR_MASK    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00003004 )
  
  #define PSM_GLOBAL_REG_IR_MASK_MDM_APB_MAINMISSIONINT_SHIFT   12
  #define PSM_GLOBAL_REG_IR_MASK_MDM_APB_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_MDM_APB_MAINMISSIONINT_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_IR_MASK_MDM_APB_MAINLATENTINT_SHIFT   11
  #define PSM_GLOBAL_REG_IR_MASK_MDM_APB_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_MDM_APB_MAINLATENTINT_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_GLOBAL_APB_MAINMISSIONINT_SHIFT   10
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_GLOBAL_APB_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_GLOBAL_APB_MAINMISSIONINT_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_GLOBAL_APB_MAINLATENTINT_SHIFT   9
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_GLOBAL_APB_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_GLOBAL_APB_MAINLATENTINT_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_IR_MASK_APB_POWER_MAINMISSIONINT_SHIFT   8
  #define PSM_GLOBAL_REG_IR_MASK_APB_POWER_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_APB_POWER_MAINMISSIONINT_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_IR_MASK_APB_POWER_MAINLATENTINT_SHIFT   7
  #define PSM_GLOBAL_REG_IR_MASK_APB_POWER_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_APB_POWER_MAINLATENTINT_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_IR_MASK_PSM_MAINMISSIONINT_SHIFT   6
  #define PSM_GLOBAL_REG_IR_MASK_PSM_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_PSM_MAINMISSIONINT_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_IR_MASK_PSM_MAINLATENTINT_SHIFT   5
  #define PSM_GLOBAL_REG_IR_MASK_PSM_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_PSM_MAINLATENTINT_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_INTLPD_MAINMISSIONINT_SHIFT   4
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_INTLPD_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_INTLPD_MAINMISSIONINT_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_INTLPD_MAINLATENTINT_SHIFT   3
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_INTLPD_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_INTLPD_MAINLATENTINT_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_IR_MASK_PSM_APB_MAINTIMEOUT_SHIFT   2
  #define PSM_GLOBAL_REG_IR_MASK_PSM_APB_MAINTIMEOUT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_PSM_APB_MAINTIMEOUT_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_MDM_MAINTIMEOUT_SHIFT   1
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_MDM_MAINTIMEOUT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_MDM_MAINTIMEOUT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_INTLPD_MAINTIMEOUT_SHIFT   0
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_INTLPD_MAINTIMEOUT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_INTPSM_INTLPD_MAINTIMEOUT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_IR_ENABLE
   */
  #define PSM_GLOBAL_REG_IR_ENABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00003008 )
  
  #define PSM_GLOBAL_REG_IR_ENABLE_MDM_APB_MAINMISSIONINT_SHIFT   12
  #define PSM_GLOBAL_REG_IR_ENABLE_MDM_APB_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_MDM_APB_MAINMISSIONINT_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_IR_ENABLE_MDM_APB_MAINLATENTINT_SHIFT   11
  #define PSM_GLOBAL_REG_IR_ENABLE_MDM_APB_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_MDM_APB_MAINLATENTINT_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_GLOBAL_APB_MAINMISSIONINT_SHIFT   10
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_GLOBAL_APB_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_GLOBAL_APB_MAINMISSIONINT_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_GLOBAL_APB_MAINLATENTINT_SHIFT   9
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_GLOBAL_APB_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_GLOBAL_APB_MAINLATENTINT_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_IR_ENABLE_APB_POWER_MAINMISSIONINT_SHIFT   8
  #define PSM_GLOBAL_REG_IR_ENABLE_APB_POWER_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_APB_POWER_MAINMISSIONINT_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_IR_ENABLE_APB_POWER_MAINLATENTINT_SHIFT   7
  #define PSM_GLOBAL_REG_IR_ENABLE_APB_POWER_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_APB_POWER_MAINLATENTINT_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_IR_ENABLE_PSM_MAINMISSIONINT_SHIFT   6
  #define PSM_GLOBAL_REG_IR_ENABLE_PSM_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_PSM_MAINMISSIONINT_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_IR_ENABLE_PSM_MAINLATENTINT_SHIFT   5
  #define PSM_GLOBAL_REG_IR_ENABLE_PSM_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_PSM_MAINLATENTINT_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_INTLPD_MAINMISSIONINT_SHIFT   4
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_INTLPD_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_INTLPD_MAINMISSIONINT_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_INTLPD_MAINLATENTINT_SHIFT   3
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_INTLPD_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_INTLPD_MAINLATENTINT_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_IR_ENABLE_PSM_APB_MAINTIMEOUT_SHIFT   2
  #define PSM_GLOBAL_REG_IR_ENABLE_PSM_APB_MAINTIMEOUT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_PSM_APB_MAINTIMEOUT_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_MDM_MAINTIMEOUT_SHIFT   1
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_MDM_MAINTIMEOUT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_MDM_MAINTIMEOUT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_INTLPD_MAINTIMEOUT_SHIFT   0
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_INTLPD_MAINTIMEOUT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_INTPSM_INTLPD_MAINTIMEOUT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_IR_DISABLE
   */
  #define PSM_GLOBAL_REG_IR_DISABLE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000300C )
  
  #define PSM_GLOBAL_REG_IR_DISABLE_MDM_APB_MAINMISSIONINT_SHIFT   12
  #define PSM_GLOBAL_REG_IR_DISABLE_MDM_APB_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_MDM_APB_MAINMISSIONINT_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_IR_DISABLE_MDM_APB_MAINLATENTINT_SHIFT   11
  #define PSM_GLOBAL_REG_IR_DISABLE_MDM_APB_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_MDM_APB_MAINLATENTINT_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_GLOBAL_APB_MAINMISSIONINT_SHIFT   10
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_GLOBAL_APB_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_GLOBAL_APB_MAINMISSIONINT_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_GLOBAL_APB_MAINLATENTINT_SHIFT   9
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_GLOBAL_APB_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_GLOBAL_APB_MAINLATENTINT_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_IR_DISABLE_APB_POWER_MAINMISSIONINT_SHIFT   8
  #define PSM_GLOBAL_REG_IR_DISABLE_APB_POWER_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_APB_POWER_MAINMISSIONINT_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_IR_DISABLE_APB_POWER_MAINLATENTINT_SHIFT   7
  #define PSM_GLOBAL_REG_IR_DISABLE_APB_POWER_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_APB_POWER_MAINLATENTINT_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_IR_DISABLE_PSM_MAINMISSIONINT_SHIFT   6
  #define PSM_GLOBAL_REG_IR_DISABLE_PSM_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_PSM_MAINMISSIONINT_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_IR_DISABLE_PSM_MAINLATENTINT_SHIFT   5
  #define PSM_GLOBAL_REG_IR_DISABLE_PSM_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_PSM_MAINLATENTINT_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_INTLPD_MAINMISSIONINT_SHIFT   4
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_INTLPD_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_INTLPD_MAINMISSIONINT_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_INTLPD_MAINLATENTINT_SHIFT   3
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_INTLPD_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_INTLPD_MAINLATENTINT_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_IR_DISABLE_PSM_APB_MAINTIMEOUT_SHIFT   2
  #define PSM_GLOBAL_REG_IR_DISABLE_PSM_APB_MAINTIMEOUT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_PSM_APB_MAINTIMEOUT_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_MDM_MAINTIMEOUT_SHIFT   1
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_MDM_MAINTIMEOUT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_MDM_MAINTIMEOUT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_INTLPD_MAINTIMEOUT_SHIFT   0
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_INTLPD_MAINTIMEOUT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_INTPSM_INTLPD_MAINTIMEOUT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_IR_TRIGGER
   */
  #define PSM_GLOBAL_REG_IR_TRIGGER    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00003010 )
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_MDM_APB_MAINMISSIONINT_SHIFT   12
  #define PSM_GLOBAL_REG_IR_TRIGGER_MDM_APB_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_MDM_APB_MAINMISSIONINT_MASK    0X00001000
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_MDM_APB_MAINLATENTINT_SHIFT   11
  #define PSM_GLOBAL_REG_IR_TRIGGER_MDM_APB_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_MDM_APB_MAINLATENTINT_MASK    0X00000800
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_GLOBAL_APB_MAINMISSIONINT_SHIFT   10
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_GLOBAL_APB_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_GLOBAL_APB_MAINMISSIONINT_MASK    0X00000400
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_GLOBAL_APB_MAINLATENTINT_SHIFT   9
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_GLOBAL_APB_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_GLOBAL_APB_MAINLATENTINT_MASK    0X00000200
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_APB_POWER_MAINMISSIONINT_SHIFT   8
  #define PSM_GLOBAL_REG_IR_TRIGGER_APB_POWER_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_APB_POWER_MAINMISSIONINT_MASK    0X00000100
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_APB_POWER_MAINLATENTINT_SHIFT   7
  #define PSM_GLOBAL_REG_IR_TRIGGER_APB_POWER_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_APB_POWER_MAINLATENTINT_MASK    0X00000080
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_PSM_MAINMISSIONINT_SHIFT   6
  #define PSM_GLOBAL_REG_IR_TRIGGER_PSM_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_PSM_MAINMISSIONINT_MASK    0X00000040
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_PSM_MAINLATENTINT_SHIFT   5
  #define PSM_GLOBAL_REG_IR_TRIGGER_PSM_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_PSM_MAINLATENTINT_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_INTLPD_MAINMISSIONINT_SHIFT   4
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_INTLPD_MAINMISSIONINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_INTLPD_MAINMISSIONINT_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_INTLPD_MAINLATENTINT_SHIFT   3
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_INTLPD_MAINLATENTINT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_INTLPD_MAINLATENTINT_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_PSM_APB_MAINTIMEOUT_SHIFT   2
  #define PSM_GLOBAL_REG_IR_TRIGGER_PSM_APB_MAINTIMEOUT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_PSM_APB_MAINTIMEOUT_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_MDM_MAINTIMEOUT_SHIFT   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_MDM_MAINTIMEOUT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_MDM_MAINTIMEOUT_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_INTLPD_MAINTIMEOUT_SHIFT   0
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_INTLPD_MAINTIMEOUT_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_INTPSM_INTLPD_MAINTIMEOUT_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSMUBLAZE
   */
  #define PSM_GLOBAL_REG_PSMUBLAZE    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00003020 )
  
  #define PSM_GLOBAL_REG_PSMUBLAZE_ROUTING_SHIFT   0
  #define PSM_GLOBAL_REG_PSMUBLAZE_ROUTING_WIDTH   1
  #define PSM_GLOBAL_REG_PSMUBLAZE_ROUTING_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_INTPSM_INTLPD
   */
  #define PSM_GLOBAL_REG_INTPSM_INTLPD    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00003030 )
  
  #define PSM_GLOBAL_REG_INTPSM_INTLPD_RST_N_SHIFT   4
  #define PSM_GLOBAL_REG_INTPSM_INTLPD_RST_N_WIDTH   1
  #define PSM_GLOBAL_REG_INTPSM_INTLPD_RST_N_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_INTPSM_INTLPD_POWER_IDLEREQ_SHIFT   3
  #define PSM_GLOBAL_REG_INTPSM_INTLPD_POWER_IDLEREQ_WIDTH   1
  #define PSM_GLOBAL_REG_INTPSM_INTLPD_POWER_IDLEREQ_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_INTPSM_INTLPD_POWER_IDLEACK_SHIFT   2
  #define PSM_GLOBAL_REG_INTPSM_INTLPD_POWER_IDLEACK_WIDTH   1
  #define PSM_GLOBAL_REG_INTPSM_INTLPD_POWER_IDLEACK_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_INTPSM_INTLPD_POWER_IDLE_SHIFT   1
  #define PSM_GLOBAL_REG_INTPSM_INTLPD_POWER_IDLE_WIDTH   1
  #define PSM_GLOBAL_REG_INTPSM_INTLPD_POWER_IDLE_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_INTPSM_INTLPD_MAINEXTEN_SHIFT   0
  #define PSM_GLOBAL_REG_INTPSM_INTLPD_MAINEXTEN_WIDTH   1
  #define PSM_GLOBAL_REG_INTPSM_INTLPD_MAINEXTEN_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_INTPSM_MDM
   */
  #define PSM_GLOBAL_REG_INTPSM_MDM    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00003034 )
  
  #define PSM_GLOBAL_REG_INTPSM_MDM_RST_N_SHIFT   4
  #define PSM_GLOBAL_REG_INTPSM_MDM_RST_N_WIDTH   1
  #define PSM_GLOBAL_REG_INTPSM_MDM_RST_N_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_INTPSM_MDM_POWER_IDLEREQ_SHIFT   3
  #define PSM_GLOBAL_REG_INTPSM_MDM_POWER_IDLEREQ_WIDTH   1
  #define PSM_GLOBAL_REG_INTPSM_MDM_POWER_IDLEREQ_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_INTPSM_MDM_POWER_IDLEACK_SHIFT   2
  #define PSM_GLOBAL_REG_INTPSM_MDM_POWER_IDLEACK_WIDTH   1
  #define PSM_GLOBAL_REG_INTPSM_MDM_POWER_IDLEACK_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_INTPSM_MDM_POWER_IDLE_SHIFT   1
  #define PSM_GLOBAL_REG_INTPSM_MDM_POWER_IDLE_WIDTH   1
  #define PSM_GLOBAL_REG_INTPSM_MDM_POWER_IDLE_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_INTPSM_MDM_MAINEXTEN_SHIFT   0
  #define PSM_GLOBAL_REG_INTPSM_MDM_MAINEXTEN_WIDTH   1
  #define PSM_GLOBAL_REG_INTPSM_MDM_MAINEXTEN_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_PSM_APB
   */
  #define PSM_GLOBAL_REG_PSM_APB    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00003038 )
  
  #define PSM_GLOBAL_REG_PSM_APB_RST_N_SHIFT   4
  #define PSM_GLOBAL_REG_PSM_APB_RST_N_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_APB_RST_N_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_PSM_APB_POWER_IDLEREQ_SHIFT   3
  #define PSM_GLOBAL_REG_PSM_APB_POWER_IDLEREQ_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_APB_POWER_IDLEREQ_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_PSM_APB_POWER_IDLEACK_SHIFT   2
  #define PSM_GLOBAL_REG_PSM_APB_POWER_IDLEACK_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_APB_POWER_IDLEACK_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_PSM_APB_POWER_IDLE_SHIFT   1
  #define PSM_GLOBAL_REG_PSM_APB_POWER_IDLE_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_APB_POWER_IDLE_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_PSM_APB_MAINEXTEN_SHIFT   0
  #define PSM_GLOBAL_REG_PSM_APB_MAINEXTEN_WIDTH   1
  #define PSM_GLOBAL_REG_PSM_APB_MAINEXTEN_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_IR_STATUS_PERR
   */
  #define PSM_GLOBAL_REG_IR_STATUS_PERR    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00003040 )
  
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSM_LOCAL_APB_SHIFT   5
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSM_LOCAL_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSM_LOCAL_APB_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSM_GLOBAL_APB_SHIFT   4
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSM_GLOBAL_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSM_GLOBAL_APB_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSM_MISCOMPARETRACE_APB_SHIFT   3
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSM_MISCOMPARETRACE_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSM_MISCOMPARETRACE_APB_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSM_PSMUBLAZERAM_APB_SHIFT   2
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSM_PSMUBLAZERAM_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSM_PSMUBLAZERAM_APB_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSM_MDM_AXI_SHIFT   1
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSM_MDM_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSM_MDM_AXI_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSMUBLAZE_INTPSM_AXI_SHIFT   0
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSMUBLAZE_INTPSM_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_IR_STATUS_PERR_INTPSMUBLAZE_INTPSM_AXI_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_IR_MASK_PERR
   */
  #define PSM_GLOBAL_REG_IR_MASK_PERR    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00003044 )
  
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSM_LOCAL_APB_SHIFT   5
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSM_LOCAL_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSM_LOCAL_APB_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSM_GLOBAL_APB_SHIFT   4
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSM_GLOBAL_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSM_GLOBAL_APB_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSM_MISCOMPARETRACE_APB_SHIFT   3
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSM_MISCOMPARETRACE_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSM_MISCOMPARETRACE_APB_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSM_PSMUBLAZERAM_APB_SHIFT   2
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSM_PSMUBLAZERAM_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSM_PSMUBLAZERAM_APB_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSM_MDM_AXI_SHIFT   1
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSM_MDM_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSM_MDM_AXI_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSMUBLAZE_INTPSM_AXI_SHIFT   0
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSMUBLAZE_INTPSM_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_IR_MASK_PERR_INTPSMUBLAZE_INTPSM_AXI_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_IR_ENABLE_PERR
   */
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00003048 )
  
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSM_LOCAL_APB_SHIFT   5
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSM_LOCAL_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSM_LOCAL_APB_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSM_GLOBAL_APB_SHIFT   4
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSM_GLOBAL_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSM_GLOBAL_APB_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSM_MISCOMPARETRACE_APB_SHIFT   3
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSM_MISCOMPARETRACE_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSM_MISCOMPARETRACE_APB_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSM_PSMUBLAZERAM_APB_SHIFT   2
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSM_PSMUBLAZERAM_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSM_PSMUBLAZERAM_APB_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSM_MDM_AXI_SHIFT   1
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSM_MDM_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSM_MDM_AXI_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSMUBLAZE_INTPSM_AXI_SHIFT   0
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSMUBLAZE_INTPSM_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_IR_ENABLE_PERR_INTPSMUBLAZE_INTPSM_AXI_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_IR_DISABLE_PERR
   */
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X0000304C )
  
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSM_LOCAL_APB_SHIFT   5
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSM_LOCAL_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSM_LOCAL_APB_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSM_GLOBAL_APB_SHIFT   4
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSM_GLOBAL_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSM_GLOBAL_APB_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSM_MISCOMPARETRACE_APB_SHIFT   3
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSM_MISCOMPARETRACE_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSM_MISCOMPARETRACE_APB_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSM_PSMUBLAZERAM_APB_SHIFT   2
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSM_PSMUBLAZERAM_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSM_PSMUBLAZERAM_APB_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSM_MDM_AXI_SHIFT   1
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSM_MDM_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSM_MDM_AXI_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSMUBLAZE_INTPSM_AXI_SHIFT   0
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSMUBLAZE_INTPSM_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_IR_DISABLE_PERR_INTPSMUBLAZE_INTPSM_AXI_MASK    0X00000001
  
  /**
   * Register: PSM_GLOBAL_REG_IR_TRIGGER_PERR
   */
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR    ( ( PSM_GLOBAL_REG_BASEADDR ) + 0X00003050 )
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSM_LOCAL_APB_SHIFT   5
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSM_LOCAL_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSM_LOCAL_APB_MASK    0X00000020
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSM_GLOBAL_APB_SHIFT   4
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSM_GLOBAL_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSM_GLOBAL_APB_MASK    0X00000010
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSM_MISCOMPARETRACE_APB_SHIFT   3
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSM_MISCOMPARETRACE_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSM_MISCOMPARETRACE_APB_MASK    0X00000008
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSM_PSMUBLAZERAM_APB_SHIFT   2
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSM_PSMUBLAZERAM_APB_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSM_PSMUBLAZERAM_APB_MASK    0X00000004
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSM_MDM_AXI_SHIFT   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSM_MDM_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSM_MDM_AXI_MASK    0X00000002
  
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSMUBLAZE_INTPSM_AXI_SHIFT   0
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSMUBLAZE_INTPSM_AXI_WIDTH   1
  #define PSM_GLOBAL_REG_IR_TRIGGER_PERR_INTPSMUBLAZE_INTPSM_AXI_MASK    0X00000001
  
  #ifdef __cplusplus
  }
  #endif
  
  
  #endif /* _PSM_GLOBAL_REG_H_ */
  