text: //  CCxCfg.h  Configuration settings for the chipcon CCxxxx series transceivers
  // 
  //  Copyright (c) 2010 Hans Klunder <hans.klunder (at) bigfoot.com>
  //  Author: Hans Klunder, based on the original Rfbee v1.0 firmware by Seeedstudio
  //  Version: August 18, 2010
  //
  //  This library is free software; you can redistribute it and/or
  //  modify it under the terms of the GNU Lesser General Public
  //  License as published by the Free Software Foundation; either
  //  version 2.1 of the License, or (at your option) any later version.
  //
  //  This library is distributed in the hope that it will be useful,
  //  but WITHOUT ANY WARRANTY; without even the implied warranty of
  //  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  //  Lesser General Public License for more details.
  //
  //  You should have received a copy of the GNU Lesser General Public
  //  License along with this library; if not, write to the Free Software
  //  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  
  #ifndef _RFBEECCXCFG_H_
  #define _RFBEECCXCFG_H_
  
  #include "RFBeeGlobals.h"
  
  #define CCX_NR_OF_REGISTERS 35
  // list the registers in the same order as CCxRegisterSettings
  // stored in progmem to save on RAM
  static const unsigned char CCx_registers[CCX_NR_OF_REGISTERS] PROGMEM ={
    CCx_FSCTRL1	,
    CCx_FSCTRL0	,
    CCx_FREQ2	,
    CCx_FREQ1	,
    CCx_FREQ0	,
    CCx_MDMCFG4	,
    CCx_MDMCFG3	,
    CCx_MDMCFG2	,
    CCx_MDMCFG1	,
    CCx_MDMCFG0	,
    CCx_CHANNR	,
    CCx_DEVIATN	,
    CCx_FREND1	,
    CCx_FREND0	,
    CCx_MCSM0	,
    CCx_FOCCFG	,
    CCx_BSCFG	,
    CCx_AGCCTRL2	,
    CCx_AGCCTRL1	,
    CCx_AGCCTRL0	,
    CCx_FSCAL3	,
    CCx_FSCAL2	,
    CCx_FSCAL1	,
    CCx_FSCAL0	,
    CCx_FSTEST	,
    CCx_TEST2	,
    CCx_TEST1	,
    CCx_TEST0	,
    CCx_FIFOTHR	,
    CCx_IOCFG2	,
    CCx_IOCFG0D	,
    CCx_PKTCTRL1	,
    CCx_PKTCTRL0	,
    CCx_ADDR	,
    CCx_PKTLEN	,
  };
  
  #define CCX_NR_OF_CONFIGS 6
  
  // configuration for CC1101 generated by TI's SmartRf studio
  // stored in progmem to save on RAM
  static const unsigned char CCx_registerSettings[CCX_NR_OF_CONFIGS][CCX_NR_OF_REGISTERS] PROGMEM = {
  // Chipcon
  // Product = CC1101
  // Chip version = A   (VERSION = 0x04)
  // Crystal accuracy = 10 ppm
  // X-tal frequency = 26 MHz
  // RF output power = 0 dBm
  // RX filterbandwidth = 232.142857 kHz
  // Deviation = 32 kHz
  // Datarate = 76.766968 kBaud
  // Modulation = (0) 2-FSK
  // Manchester enable = (0) Manchester disabled
  // RF Frequency = 914.999969 MHz
  // Channel spacing = 199.951172 kHz
  // Channel number = 0
  // Optimization = -
  // Sync mode = (3) 30/32 sync word bits detected
  // Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
  // CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
  // Forward Error Correction = (0) FEC disabled
  // Length configuration = (1) Variable length packets, packet length configured by the first received unsigned char after sync word.
  // Packetlength = 64
  // Preamble count = (2)  4 bytes
  // Append status = 1
  // Address check = (0) No address check
  // FIFO autoflush = 0
  // Device address = 0
  // GDO0 signal selection = ( 1) Asserts when a packet has been received with OK CRC. De-asserts when the first unsigned char is read from the RX FIFO
  // GDO2 signal selection = (46) High impedance (3-state)
    {
      0x08,   // FSCTRL1   Frequency synthesizer control.
      0x00,   // FSCTRL0   Frequency synthesizer control.
      0x23,   // FREQ2     Frequency control word, high unsigned char.
      0x31,   // FREQ1     Frequency control word, middle unsigned char.
      0x3B,   // FREQ0     Frequency control word, low unsigned char.
      0x7B,   // MDMCFG4   Modem configuration.
      0x83,   // MDMCFG3   Modem configuration.
      0x03,   // MDMCFG2   Modem configuration.
      0x22,   // MDMCFG1   Modem configuration.
      0xF8,   // MDMCFG0   Modem configuration.
      0x00,   // CHANNR    Channel number.
      0x42,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).
      0xB6,   // FREND1    Front end RX configuration.
      0x10,   // FREND0    Front end TX configuration.
      0x18,   // MCSM0     Main Radio Control State Machine configuration.
      0x1D,   // FOCCFG    Frequency Offset Compensation Configuration.
      0x1C,   // BSCFG     Bit synchronization Configuration.
      0xC7,   // AGCCTRL2  AGC control.
      0x00,   // AGCCTRL1  AGC control.
      0xB2,   // AGCCTRL0  AGC control.
      0xEA,   // FSCAL3    Frequency synthesizer calibration.
      0x2A,   // FSCAL2    Frequency synthesizer calibration.
      0x00,   // FSCAL1    Frequency synthesizer calibration.
      0x1F,   // FSCAL0    Frequency synthesizer calibration.
      0x59,   // FSTEST    Frequency synthesizer calibration.
      0x81,   // TEST2     Various test settings.
      0x35,   // TEST1     Various test settings.
      0x09,   // TEST0     Various test settings.
      0x0E,   // FIFOTHR   RXFIFO and TXFIFO thresholds.
      0x09,   // IOCFG2    GDO2 output pin configuration.0x09-CCA mode, 0x2E-High impedance
      0x01,   // IOCFG0D   GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
      0x04,   // PKTCTRL1  Packet automation control. bit2 = 1 append RSSI and LQI ,bit2 = 0 not append
      0x05,   // PKTCTRL0  Packet automation control.
      0x00,   // ADDR      Device address.
      CCx_PACKT_LEN,    // PKTLEN    Packet length.
    }, 
  
  // Chipcon
  // Product = CC1101
  // Chip version = A   (VERSION = 0x04)
  // Crystal accuracy = 10 ppm
  // X-tal frequency = 26 MHz
  // RF output power = 0 dBm
  // RX filterbandwidth = 101.562500 kHz
  // Deviation = 25 kHz
  // Datarate = 4.797935 kBaud
  // Modulation = (1) GFSK
  // Manchester enable = (0) Manchester disabled
  // RF Frequency = 914.999969 MHz
  // Channel spacing = 199.951172 kHz
  // Channel number = 0
  // Optimization = Sensitivity
  // Sync mode = (3) 30/32 sync word bits detected
  // Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
  // CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
  // Forward Error Correction = (0) FEC disabled
  // Length configuration = (1) Variable length packets, packet length configured by the first received unsigned char after sync word.
  // Packetlength = 64
  // Preamble count = (2)  4 bytes
  // Append status = 1
  // Address check = (0) No address check
  // FIFO autoflush = 0
  // Device address = 0
  // GDO0 signal selection = ( 1) Asserts when a packet has been received with OK CRC. De-asserts when the first unsigned char is read from the RX FIFO
  // GDO2 signal selection = (46) High impedance (3-state)
    {
      0x06,   // FSCTRL1   Frequency synthesizer control.
      0x00,   // FSCTRL0   Frequency synthesizer control.
      0x23,   // FREQ2     Frequency control word, high unsigned char.
      0x31,   // FREQ1     Frequency control word, middle unsigned char.
      0x3B,   // FREQ0     Frequency control word, low unsigned char.
      0xB7,   //0xC7 MDMCFG4   Modem configuration.
      0x83,   // MDMCFG3   Modem configuration.
      0x13,   // MDMCFG2   Modem configuration.
      0x22,   // MDMCFG1   Modem configuration.
      0xF8,   // MDMCFG0   Modem configuration.
      0x00,   // CHANNR    Channel number.
      0x40,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).
      0x56,   // FREND1    Front end RX configuration.
      0x10,   // FREND0    Front end TX configuration.
      0x18,   // MCSM0     Main Radio Control State Machine configuration.
      0x16,   // FOCCFG    Frequency Offset Compensation Configuration.
      0x6C,   // BSCFG     Bit synchronization Configuration.
      0x43,   // AGCCTRL2  AGC control.
      0x40,   // AGCCTRL1  AGC control.
      0x91,   // AGCCTRL0  AGC control.
      0xE9,   // FSCAL3    Frequency synthesizer calibration.
      0x2A,   // FSCAL2    Frequency synthesizer calibration.
      0x00,   // FSCAL1    Frequency synthesizer calibration.
      0x1F,   // FSCAL0    Frequency synthesizer calibration.
      0x59,   // FSTEST    Frequency synthesizer calibration.
      0x81,   // TEST2     Various test settings.
      0x35,   // TEST1     Various test settings.
      0x09,   // TEST0     Various test settings.
      0x0E,   // FIFOTHR   RXFIFO and TXFIFO thresholds.
      0x09,   // IOCFG2    GDO2 output pin configuration.0x09-CCA mode, 0x2E-High impedance
      0x01,   // IOCFG0D   GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
      0x04,   // PKTCTRL1  Packet automation control. bit2 = 1 append RSSI and LQI ,bit2 = 0 not append
      0x05,   // PKTCTRL0  Packet automation control.
      0x00,   // ADDR      Device address.
      CCx_PACKT_LEN,    // PKTLEN    Packet length.
    }, 
    
    // Chipcon
  // Product = CC1101
  // Chip version = A   (VERSION = 0x04)
  // Crystal accuracy = 10 ppm
  // X-tal frequency = 26 MHz
  // RF output power = 0 dBm
  // RX filterbandwidth = 101.562500 kHz
  // Deviation = 25 kHz
  // Datarate = 4.797935 kBaud
  // Modulation = (1) GFSK
  // Manchester enable = (0) Manchester disabled
  // RF Frequency = 914.999969 MHz
  // Channel spacing = 199.951172 kHz
  // Channel number = 0
  // Optimization = Low current
  // Sync mode = (3) 30/32 sync word bits detected
  // Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
  // CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
  // Forward Error Correction = (0) FEC disabled
  // Length configuration = (1) Variable length packets, packet length configured by the first received unsigned char after sync word.
  // Packetlength = 64
  // Preamble count = (2)  4 bytes
  // Append status = 1
  // Address check = (0) No address check
  // FIFO autoflush = 0
  // Device address = 0
  // GDO0 signal selection = ( 1) Asserts when a packet has been received with OK CRC. De-asserts when the first unsigned char is read from the RX FIFO
  // GDO2 signal selection = (46) High impedance (3-state)
    {
      0x08,   // FSCTRL1   Frequency synthesizer control.
      0x00,   // FSCTRL0   Frequency synthesizer control.
      0x23,   // FREQ2     Frequency control word, high unsigned char.
      0x31,   // FREQ1     Frequency control word, middle unsigned char.
      0x3B,   // FREQ0     Frequency control word, low unsigned char.
      0xB7,   // MDMCFG4   Modem configuration.
      0x83,   // MDMCFG3   Modem configuration.
      0x93,   // MDMCFG2   Modem configuration.
      0x22,   // MDMCFG1   Modem configuration.
      0xF8,   // MDMCFG0   Modem configuration.
      0x00,   // CHANNR    Channel number.
      0x40,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).
      0x56,   // FREND1    Front end RX configuration.
      0x10,   // FREND0    Front end TX configuration.
      0x18,   // MCSM0     Main Radio Control State Machine configuration.
      0x16,   // FOCCFG    Frequency Offset Compensation Configuration.
      0x6C,   // BSCFG     Bit synchronization Configuration.
      0x43,   // AGCCTRL2  AGC control.
      0x40,   // AGCCTRL1  AGC control.
      0x91,   // AGCCTRL0  AGC control.
      0xE9,   // FSCAL3    Frequency synthesizer calibration.
      0x2A,   // FSCAL2    Frequency synthesizer calibration.
      0x00,   // FSCAL1    Frequency synthesizer calibration.
      0x1F,   // FSCAL0    Frequency synthesizer calibration.
      0x59,   // FSTEST    Frequency synthesizer calibration.
      0x81,   // TEST2     Various test settings.
      0x35,   // TEST1     Various test settings.
      0x09,   // TEST0     Various test settings.
      0x0E,   // FIFOTHR   RXFIFO and TXFIFO thresholds.
      0x09,   // IOCFG2    GDO2 output pin configuration.0x09-CCA mode, 0x2E-High impedance
      0x01,   // IOCFG0D   GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
      0x04,   // PKTCTRL1  Packet automation control. bit2 = 1 append RSSI and LQI ,bit2 = 0 not append
      0x05,   // PKTCTRL0  Packet automation control.
      0x00,   // ADDR      Device address.
      CCx_PACKT_LEN,    // PKTLEN    Packet length.
    }, 
  // Chipcon
  // Product = CC1100
  // Chip version = F   (VERSION = 0x03)
  // Crystal accuracy = 10 ppm
  // X-tal frequency = 26 MHz
  // RF output power = 0 dBm
  // RX filterbandwidth = 232.142857 kHz
  // Deviation = 32 kHz
  // Datarate = 76.766968 kBaud
  // Modulation = (0) 2-FSK
  // Manchester enable = (0) Manchester disabled
  // RF Frequency = 867.999939 MHz
  // Channel spacing = 199.951172 kHz
  // Channel number = 0
  // Optimization = -
  // Sync mode = (3) 30/32 sync word bits detected
  // Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
  // CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
  // Forward Error Correction = (0) FEC disabled
  // Length configuration = (1) Variable length packets, packet length configured by the first received unsigned char after sync word.
  // Packetlength = 64
  // Preamble count = (2)  4 bytes
  // Append status = 1
  // Address check = (0) No address check
  // FIFO autoflush = 0
  // Device address = 0
  // GDO0 signal selection = ( 7) Asserts when a packet has been received with OK CRC. De-asserts when the first unsigned char is read from the RX FIFO
  // GDO2 signal selection = (46) High impedance (3-state)
    {
      0x06,   // FSCTRL1   Frequency synthesizer control.
      0x00,   // FSCTRL0   Frequency synthesizer control.
      0x23,   // FREQ2     Frequency control word, high unsigned char.
      0x31,   // FREQ1     Frequency control word, middle unsigned char.
      0x3B,   // FREQ0     Frequency control word, low unsigned char.
      0x7B,   // MDMCFG4   Modem configuration.
      0x83,   // MDMCFG3   Modem configuration.
      0x13,   // MDMCFG2   Modem configuration.
      0x22,   // MDMCFG1   Modem configuration.
      0xF8,   // MDMCFG0   Modem configuration.
      0x00,   // CHANNR    Channel number.
      0x34,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).
      0x56,   // FREND1    Front end RX configuration.
      0x10,   // FREND0    Front end TX configuration.
      0x18,   // MCSM0     Main Radio Control State Machine configuration.
      0x16,   // FOCCFG    Frequency Offset Compensation Configuration.
      0x6C,   // BSCFG     Bit synchronization Configuration.
      0x43,   // AGCCTRL2  AGC control.
      0x40,   // AGCCTRL1  AGC control.
      0x91,   // AGCCTRL0  AGC control.
      0xE9,   // FSCAL3    Frequency synthesizer calibration.
      0x2A,   // FSCAL2    Frequency synthesizer calibration.
      0x00,   // FSCAL1    Frequency synthesizer calibration.
      0x1F,   // FSCAL0    Frequency synthesizer calibration.
      0x59,   // FSTEST    Frequency synthesizer calibration.
      0x81,   // TEST2     Various test settings.
      0x35,   // TEST1     Various test settings.
      0x09,   // TEST0     Various test settings.
      0x0E,   // FIFOTHR   RXFIFO and TXFIFO thresholds.
      0x2E,   // IOCFG2    GDO2 output pin configuration.
      0x01,   // IOCFG0D   GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
      0x04,   // PKTCTRL1  Packet automation control.
      0x05,   // PKTCTRL0  Packet automation control.
      0x00,   // ADDR      Device address.
      CCx_PACKT_LEN    // PKTLEN    Packet length.
    },
  
  // Chipcon
  // Product = CC1101
  // Chip version = A   (VERSION = 0x04)
  // Crystal accuracy = 10 ppm
  // X-tal frequency = 26 MHz
  // RF output power = 0 dBm
  // RX filterbandwidth = 101.562500 kHz
  // Deviation = 25 kHz
  // Datarate = 4.797935 kBaud
  // Modulation = (1) GFSK
  // Manchester enable = (0) Manchester disabled
  // RF Frequency = 868.299866 MHz
  // Channel spacing = 199.951172 kHz
  // Channel number = 0
  // Optimization = Sensitivity
  // Sync mode = (3) 30/32 sync word bits detected
  // Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
  // CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
  // Forward Error Correction = (0) FEC disabled
  // Length configuration = (1) Variable length packets, packet length configured by the first received unsigned char after sync word.
  // Packetlength = 64
  // Preamble count = (2)  4 bytes
  // Append status = 1
  // Address check = (0) No address check
  // FIFO autoflush = 0
  // Device address = 0
  // GDO0 signal selection = ( 1) Asserts when a packet has been received with OK CRC. De-asserts when the first unsigned char is read from the RX FIFO
  // GDO2 signal selection = (46) High impedance (3-state)
    {
      0x06,   // FSCTRL1   Frequency synthesizer control.
      0x00,   // FSCTRL0   Frequency synthesizer control.
      0x21,   // FREQ2     Frequency control word, high unsigned char.
      0x65,   // FREQ1     Frequency control word, middle unsigned char.
      0x6A,   // FREQ0     Frequency control word, low unsigned char.
      0xB7,   // MDMCFG4   Modem configuration.
      0x83,   // MDMCFG3   Modem configuration.
      0x13,   // MDMCFG2   Modem configuration.
      0x22,   // MDMCFG1   Modem configuration.
      0xF8,   // MDMCFG0   Modem configuration.
      0x00,   // CHANNR    Channel number.
      0x40,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).
      0x56,   // FREND1    Front end RX configuration.
      0x10,   // FREND0    Front end TX configuration.
      0x18,   // MCSM0     Main Radio Control State Machine configuration.
      0x16,   // FOCCFG    Frequency Offset Compensation Configuration.
      0x6C,   // BSCFG     Bit synchronization Configuration.
      0x43,   // AGCCTRL2  AGC control.
      0x40,   // AGCCTRL1  AGC control.
      0x91,   // AGCCTRL0  AGC control.
      0xE9,   // FSCAL3    Frequency synthesizer calibration.
      0x2A,   // FSCAL2    Frequency synthesizer calibration.
      0x00,   // FSCAL1    Frequency synthesizer calibration.
      0x1F,   // FSCAL0    Frequency synthesizer calibration.
      0x59,   // FSTEST    Frequency synthesizer calibration.
      0x81,   // TEST2     Various test settings.
      0x35,   // TEST1     Various test settings.
      0x09,   // TEST0     Various test settings.
      0x0E,   // FIFOTHR   RXFIFO and TXFIFO thresholds.
      0x09,   // IOCFG2    GDO2 output pin configuration.0x09-CCA mode, 0x2E-High impedance
      0x01,   // IOCFG0D   GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
      0x04,   // PKTCTRL1  Packet automation control. bit2 = 1 append RSSI and LQI ,bit2 = 0 not append
      0x05,   // PKTCTRL0  Packet automation control.
      0x00,   // ADDR      Device address.
      CCx_PACKT_LEN,    // PKTLEN    Packet length.
    }, 
  
  // Chipcon
  // Product = CC1101
  // Chip version = A   (VERSION = 0x04)
  // Crystal accuracy = 10 ppm
  // X-tal frequency = 26 MHz
  // RF output power = 0 dBm
  // RX filterbandwidth = 101.562500 kHz
  // Deviation = 25 kHz
  // Datarate = 4.797935 kBaud
  // Modulation = (1) GFSK
  // Manchester enable = (0) Manchester disabled
  // RF Frequency = 867.999939 MHz
  // Channel spacing = 199.951172 kHz
  // Channel number = 0
  // Optimization = Low current
  // Sync mode = (3) 30/32 sync word bits detected
  // Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
  // CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
  // Forward Error Correction = (0) FEC disabled
  // Length configuration = (1) Variable length packets, packet length configured by the first received unsigned char after sync word.
  // Packetlength = 64
  // Preamble count = (2)  4 bytes
  // Append status = 1
  // Address check = (0) No address check
  // FIFO autoflush = 0
  // Device address = 0
  // GDO0 signal selection = ( 1) Asserts when a packet has been received with OK CRC. De-asserts when the first unsigned char is read from the RX FIFO
  // GDO2 signal selection = (46) High impedance (3-state)
    {
      0x08,   // FSCTRL1   Frequency synthesizer control.
      0x00,   // FSCTRL0   Frequency synthesizer control.
      0x21,   // FREQ2     Frequency control word, high unsigned char.
      0x62,   // FREQ1     Frequency control word, middle unsigned char.
      0x76,   // FREQ0     Frequency control word, low unsigned char.
      0xB7,   // MDMCFG4   Modem configuration.
      0x83,   // MDMCFG3   Modem configuration.
      0x93,   // MDMCFG2   Modem configuration.
      0x22,   // MDMCFG1   Modem configuration.
      0xF8,   // MDMCFG0   Modem configuration.
      0x00,   // CHANNR    Channel number.
      0x40,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).
      0x56,   // FREND1    Front end RX configuration.
      0x10,   // FREND0    Front end TX configuration.
      0x18,   // MCSM0     Main Radio Control State Machine configuration.
      0x16,   // FOCCFG    Frequency Offset Compensation Configuration.
      0x6C,   // BSCFG     Bit synchronization Configuration.
      0x43,   // AGCCTRL2  AGC control.
      0x40,   // AGCCTRL1  AGC control.
      0x91,   // AGCCTRL0  AGC control.
      0xE9,   // FSCAL3    Frequency synthesizer calibration.
      0x2A,   // FSCAL2    Frequency synthesizer calibration.
      0x00,   // FSCAL1    Frequency synthesizer calibration.
      0x1F,   // FSCAL0    Frequency synthesizer calibration.
      0x59,   // FSTEST    Frequency synthesizer calibration.
      0x81,   // TEST2     Various test settings.
      0x35,   // TEST1     Various test settings.
      0x09,   // TEST0     Various test settings.
      0x0E,   // FIFOTHR   RXFIFO and TXFIFO thresholds.
      0x09,   // IOCFG2    GDO2 output pin configuration.0x09-CCA mode, 0x2E-High impedance
      0x01,   // IOCFG0D   GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseudo register explanation.
      0x04,   // PKTCTRL1  Packet automation control. bit2 = 1 append RSSI and LQI ,bit2 = 0 not append
      0x05,   // PKTCTRL0  Packet automation control.
      0x00,   // ADDR      Device address.
      CCx_PACKT_LEN,    // PKTLEN    Packet length.
    }, 
  
  };
  
  // PATABLE (dBm output power)
  
  // stored in progmem to save on RAM
  static const unsigned char CCx_paTable[CCX_NR_OF_CONFIGS][CCx_PA_TABLESIZE] PROGMEM ={
  // -30  -20   -15  -10    0   5    7   10
    {0x03,0x0E,0x1E,0x27,0x8E,0xCD,0xC7,0xC0},    // Config 0 , 915 Mhz
    {0x00,0x03,0x0F,0x25,0x67,0x40,0x60,0x50},    // Config 1 , 915 Mhz
    {0x00,0x03,0x0F,0x25,0x67,0x40,0x60,0x50},    // Config 2 , 915 Mhz
    {0x03,0x0F,0x1E,0x27,0x50,0x81,0xCB,0xC2},    // Config 3 , 868 Mhz
    {0x00,0x03,0x0F,0x25,0x67,0x40,0x60,0x50},    // Config 4 , 868 Mhz
    {0x00,0x03,0x0F,0x25,0x67,0x40,0x60,0x50},    // Config 5 , 868 Mhz
  };
  
  #endif
  