text: /**
   * \file
   *
   * \brief Spi Master configuration.
   *
   * Copyright (c) 2011-2013 Atmel Corporation. All rights reserved.
   *
   * \asf_license_start
   *
   * \page License
   *
   * Redistribution and use in source and binary forms, with or without
   * modification, are permitted provided that the following conditions are met:
   *
   * 1. Redistributions of source code must retain the above copyright notice,
   *    this list of conditions and the following disclaimer.
   *
   * 2. Redistributions in binary form must reproduce the above copyright notice,
   *    this list of conditions and the following disclaimer in the documentation
   *    and/or other materials provided with the distribution.
   *
   * 3. The name of Atmel may not be used to endorse or promote products derived
   *    from this software without specific prior written permission.
   *
   * 4. This software may only be redistributed and used in connection with an
   *    Atmel microcontroller product.
   *
   * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
   * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
   * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
   * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
   * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
   * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   * POSSIBILITY OF SUCH DAMAGE.
   *
   * \asf_license_stop
   *
   */
  
  #ifndef CONF_SPI_MASTER_H_INCLUDED
  #define CONF_SPI_MASTER_H_INCLUDED
  
  /* Possibility to change low-level configurations here */
  
  //! Default Config Spi Master Delay BCS
  #define CONFIG_SPI_MASTER_DELAY_BCS            0
  
  //! Default Config Spi Master Bits per Transfer Definition
  #define CONFIG_SPI_MASTER_BITS_PER_TRANSFER    8
  
  //! Default Config Spi Master Delay BCT
  #define CONFIG_SPI_MASTER_DELAY_BCT            0
  
  //! Default Config Spi Master Delay BS
  #define CONFIG_SPI_MASTER_DELAY_BS             0
  
  //! Default Config Spi Master Dummy Field
  #define CONFIG_SPI_MASTER_DUMMY                0xFF
  
  /* Chip select. */
  #define SPI_CHIP_SEL 0
  #define SPI_CHIP_PCS spi_get_pcs(SPI_CHIP_SEL)
  
  /* Clock polarity. */
  #define SPI_CLK_POLARITY 0
  
  /* Clock phase. */
  #define SPI_CLK_PHASE 1
  
  /* Delay before SPCK. */
  #define SPI_DLYBS 0x40
  
  /* Delay between consecutive transfers. */
  #define SPI_DLYBCT 0x10
  
  /* Number of commands logged in status. */
  #define NB_STATUS_CMD   20
  
  /* Number of SPI clock configurations. */
  #define NUM_SPCK_CONFIGURATIONS 4
  
  /* SPI Communicate buffer size. */
  #define COMM_BUFFER_SIZE   64
  
  /* Max retry times. */
  #define MAX_RETRY    4
  
  #endif /* CONF_SPI_MASTER_H_INCLUDED */
  