text: #ifndef IP_BASE_S00_REGSLICE_92_H_
  #define IP_BASE_S00_REGSLICE_92_H_
  
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  #ifndef XTLM
  #include "xtlm.h"
  #endif
  #ifndef SYSTEMC_INCLUDED
  #include <systemc>
  #endif
  
  #if defined(_MSC_VER)
  #define DllExport __declspec(dllexport)
  #elif defined(__GNUC__)
  #define DllExport __attribute__ ((visibility("default")))
  #else
  #define DllExport
  #endif
  
  #include "base_s00_regslice_92_sc.h"
  
  
  
  
  #ifdef XILINX_SIMULATOR
  class DllExport base_s00_regslice_92 : public base_s00_regslice_92_sc
  {
  public:
  
    base_s00_regslice_92(const sc_core::sc_module_name& nm);
    virtual ~base_s00_regslice_92();
  
    // module pin-to-pin RTL interface
  
    sc_core::sc_in< bool > aclk;
    sc_core::sc_in< bool > aresetn;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
    sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
    sc_core::sc_in< bool > s_axi_awvalid;
    sc_core::sc_out< bool > s_axi_awready;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
    sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
    sc_core::sc_in< bool > s_axi_wvalid;
    sc_core::sc_out< bool > s_axi_wready;
    sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
    sc_core::sc_out< bool > s_axi_bvalid;
    sc_core::sc_in< bool > s_axi_bready;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
    sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
    sc_core::sc_in< bool > s_axi_arvalid;
    sc_core::sc_out< bool > s_axi_arready;
    sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
    sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
    sc_core::sc_out< bool > s_axi_rvalid;
    sc_core::sc_in< bool > s_axi_rready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
    sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
    sc_core::sc_out< bool > m_axi_awvalid;
    sc_core::sc_in< bool > m_axi_awready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
    sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
    sc_core::sc_out< bool > m_axi_wvalid;
    sc_core::sc_in< bool > m_axi_wready;
    sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
    sc_core::sc_in< bool > m_axi_bvalid;
    sc_core::sc_out< bool > m_axi_bready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
    sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
    sc_core::sc_out< bool > m_axi_arvalid;
    sc_core::sc_in< bool > m_axi_arready;
    sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
    sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
    sc_core::sc_in< bool > m_axi_rvalid;
    sc_core::sc_out< bool > m_axi_rready;
  
  protected:
  
    virtual void before_end_of_elaboration();
  
  private:
  
    xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
    xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
  
  };
  #endif // XILINX_SIMULATOR
  
  
  
  
  #ifdef XM_SYSTEMC
  class DllExport base_s00_regslice_92 : public base_s00_regslice_92_sc
  {
  public:
  
    base_s00_regslice_92(const sc_core::sc_module_name& nm);
    virtual ~base_s00_regslice_92();
  
    // module pin-to-pin RTL interface
  
    sc_core::sc_in< bool > aclk;
    sc_core::sc_in< bool > aresetn;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
    sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
    sc_core::sc_in< bool > s_axi_awvalid;
    sc_core::sc_out< bool > s_axi_awready;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
    sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
    sc_core::sc_in< bool > s_axi_wvalid;
    sc_core::sc_out< bool > s_axi_wready;
    sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
    sc_core::sc_out< bool > s_axi_bvalid;
    sc_core::sc_in< bool > s_axi_bready;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
    sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
    sc_core::sc_in< bool > s_axi_arvalid;
    sc_core::sc_out< bool > s_axi_arready;
    sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
    sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
    sc_core::sc_out< bool > s_axi_rvalid;
    sc_core::sc_in< bool > s_axi_rready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
    sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
    sc_core::sc_out< bool > m_axi_awvalid;
    sc_core::sc_in< bool > m_axi_awready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
    sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
    sc_core::sc_out< bool > m_axi_wvalid;
    sc_core::sc_in< bool > m_axi_wready;
    sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
    sc_core::sc_in< bool > m_axi_bvalid;
    sc_core::sc_out< bool > m_axi_bready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
    sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
    sc_core::sc_out< bool > m_axi_arvalid;
    sc_core::sc_in< bool > m_axi_arready;
    sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
    sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
    sc_core::sc_in< bool > m_axi_rvalid;
    sc_core::sc_out< bool > m_axi_rready;
  
  protected:
  
    virtual void before_end_of_elaboration();
  
  private:
  
    xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
    xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
  
  };
  #endif // XM_SYSTEMC
  
  
  
  
  #ifdef RIVIERA
  class DllExport base_s00_regslice_92 : public base_s00_regslice_92_sc
  {
  public:
  
    base_s00_regslice_92(const sc_core::sc_module_name& nm);
    virtual ~base_s00_regslice_92();
  
    // module pin-to-pin RTL interface
  
    sc_core::sc_in< bool > aclk;
    sc_core::sc_in< bool > aresetn;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
    sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
    sc_core::sc_in< bool > s_axi_awvalid;
    sc_core::sc_out< bool > s_axi_awready;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
    sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
    sc_core::sc_in< bool > s_axi_wvalid;
    sc_core::sc_out< bool > s_axi_wready;
    sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
    sc_core::sc_out< bool > s_axi_bvalid;
    sc_core::sc_in< bool > s_axi_bready;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
    sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
    sc_core::sc_in< bool > s_axi_arvalid;
    sc_core::sc_out< bool > s_axi_arready;
    sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
    sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
    sc_core::sc_out< bool > s_axi_rvalid;
    sc_core::sc_in< bool > s_axi_rready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
    sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
    sc_core::sc_out< bool > m_axi_awvalid;
    sc_core::sc_in< bool > m_axi_awready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
    sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
    sc_core::sc_out< bool > m_axi_wvalid;
    sc_core::sc_in< bool > m_axi_wready;
    sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
    sc_core::sc_in< bool > m_axi_bvalid;
    sc_core::sc_out< bool > m_axi_bready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
    sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
    sc_core::sc_out< bool > m_axi_arvalid;
    sc_core::sc_in< bool > m_axi_arready;
    sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
    sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
    sc_core::sc_in< bool > m_axi_rvalid;
    sc_core::sc_out< bool > m_axi_rready;
  
  protected:
  
    virtual void before_end_of_elaboration();
  
  private:
  
    xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
    xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
  
  };
  #endif // RIVIERA
  
  
  
  
  #ifdef VCSSYSTEMC
  #include "utils/xtlm_aximm_initiator_stub.h"
  
  #include "utils/xtlm_aximm_target_stub.h"
  
  class DllExport base_s00_regslice_92 : public base_s00_regslice_92_sc
  {
  public:
  
    base_s00_regslice_92(const sc_core::sc_module_name& nm);
    virtual ~base_s00_regslice_92();
  
    // module pin-to-pin RTL interface
  
    sc_core::sc_in< bool > aclk;
    sc_core::sc_in< bool > aresetn;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
    sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
    sc_core::sc_in< bool > s_axi_awvalid;
    sc_core::sc_out< bool > s_axi_awready;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
    sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
    sc_core::sc_in< bool > s_axi_wvalid;
    sc_core::sc_out< bool > s_axi_wready;
    sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
    sc_core::sc_out< bool > s_axi_bvalid;
    sc_core::sc_in< bool > s_axi_bready;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
    sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
    sc_core::sc_in< bool > s_axi_arvalid;
    sc_core::sc_out< bool > s_axi_arready;
    sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
    sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
    sc_core::sc_out< bool > s_axi_rvalid;
    sc_core::sc_in< bool > s_axi_rready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
    sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
    sc_core::sc_out< bool > m_axi_awvalid;
    sc_core::sc_in< bool > m_axi_awready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
    sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
    sc_core::sc_out< bool > m_axi_wvalid;
    sc_core::sc_in< bool > m_axi_wready;
    sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
    sc_core::sc_in< bool > m_axi_bvalid;
    sc_core::sc_out< bool > m_axi_bready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
    sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
    sc_core::sc_out< bool > m_axi_arvalid;
    sc_core::sc_in< bool > m_axi_arready;
    sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
    sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
    sc_core::sc_in< bool > m_axi_rvalid;
    sc_core::sc_out< bool > m_axi_rready;
  
  protected:
  
    virtual void before_end_of_elaboration();
  
  private:
  
    xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
    xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
  
    // Transactor stubs
    xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
    xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
    xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
    xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
  
    // Socket stubs
  
  };
  #endif // VCSSYSTEMC
  
  
  
  
  #ifdef MTI_SYSTEMC
  #include "utils/xtlm_aximm_initiator_stub.h"
  
  #include "utils/xtlm_aximm_target_stub.h"
  
  class DllExport base_s00_regslice_92 : public base_s00_regslice_92_sc
  {
  public:
  
    base_s00_regslice_92(const sc_core::sc_module_name& nm);
    virtual ~base_s00_regslice_92();
  
    // module pin-to-pin RTL interface
  
    sc_core::sc_in< bool > aclk;
    sc_core::sc_in< bool > aresetn;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_awaddr;
    sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_awprot;
    sc_core::sc_in< bool > s_axi_awvalid;
    sc_core::sc_out< bool > s_axi_awready;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_wdata;
    sc_core::sc_in< sc_dt::sc_bv<4> > s_axi_wstrb;
    sc_core::sc_in< bool > s_axi_wvalid;
    sc_core::sc_out< bool > s_axi_wready;
    sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_bresp;
    sc_core::sc_out< bool > s_axi_bvalid;
    sc_core::sc_in< bool > s_axi_bready;
    sc_core::sc_in< sc_dt::sc_bv<32> > s_axi_araddr;
    sc_core::sc_in< sc_dt::sc_bv<3> > s_axi_arprot;
    sc_core::sc_in< bool > s_axi_arvalid;
    sc_core::sc_out< bool > s_axi_arready;
    sc_core::sc_out< sc_dt::sc_bv<32> > s_axi_rdata;
    sc_core::sc_out< sc_dt::sc_bv<2> > s_axi_rresp;
    sc_core::sc_out< bool > s_axi_rvalid;
    sc_core::sc_in< bool > s_axi_rready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_awaddr;
    sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_awprot;
    sc_core::sc_out< bool > m_axi_awvalid;
    sc_core::sc_in< bool > m_axi_awready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_wdata;
    sc_core::sc_out< sc_dt::sc_bv<4> > m_axi_wstrb;
    sc_core::sc_out< bool > m_axi_wvalid;
    sc_core::sc_in< bool > m_axi_wready;
    sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_bresp;
    sc_core::sc_in< bool > m_axi_bvalid;
    sc_core::sc_out< bool > m_axi_bready;
    sc_core::sc_out< sc_dt::sc_bv<32> > m_axi_araddr;
    sc_core::sc_out< sc_dt::sc_bv<3> > m_axi_arprot;
    sc_core::sc_out< bool > m_axi_arvalid;
    sc_core::sc_in< bool > m_axi_arready;
    sc_core::sc_in< sc_dt::sc_bv<32> > m_axi_rdata;
    sc_core::sc_in< sc_dt::sc_bv<2> > m_axi_rresp;
    sc_core::sc_in< bool > m_axi_rvalid;
    sc_core::sc_out< bool > m_axi_rready;
  
  protected:
  
    virtual void before_end_of_elaboration();
  
  private:
  
    xtlm::xaximm_xtlm2pin_t<32,32,1,1,1,1,1,1>* mp_M_AXI_transactor;
    xtlm::xaximm_pin2xtlm_t<32,32,1,1,1,1,1,1>* mp_S_AXI_transactor;
  
    // Transactor stubs
    xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_rd_socket_stub;
    xtlm::xtlm_aximm_initiator_stub * M_AXI_transactor_initiator_wr_socket_stub;
    xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_rd_socket_stub;
    xtlm::xtlm_aximm_target_stub * S_AXI_transactor_target_wr_socket_stub;
  
    // Socket stubs
  
  };
  #endif // MTI_SYSTEMC
  #endif // IP_BASE_S00_REGSLICE_92_H_
  