text: #ifndef XPARAMETERS_H   /* prevent circular inclusions */
  #define XPARAMETERS_H   /* by using protection macros */
  
  /* Definition for CPU ID */
  #define XPAR_CPU_ID 0U
  
  /* Definitions for peripheral PS7_CORTEXA9_0 */
  #define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
  
  
  /******************************************************************/
  
  /* Canonical definitions for peripheral PS7_CORTEXA9_0 */
  #define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
  
  
  /******************************************************************/
  
  #include "xparameters_ps.h"
  
  #define STDIN_BASEADDRESS 0xF8800000
  #define STDOUT_BASEADDRESS 0xF8800000
  
  /******************************************************************/
  
  /* Platform specific definitions */
  #define PLATFORM_ZYNQ
   
  /* Definitions for sleep timer configuration */
  #define XSLEEP_TIMER_IS_DEFAULT_TIMER
   
   
  /******************************************************************/
  
  /* Definitions for peripheral PS7_DDR_0 */
  #define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
  #define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF
  
  
  /******************************************************************/
  
  /* Definitions for driver DEVCFG */
  #define XPAR_XDCFG_NUM_INSTANCES 1U
  
  /* Definitions for peripheral PS7_DEV_CFG_0 */
  #define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U
  #define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U
  #define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU
  
  
  /******************************************************************/
  
  /* Canonical definitions for peripheral PS7_DEV_CFG_0 */
  #define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
  #define XPAR_XDCFG_0_BASEADDR 0xF8007000U
  #define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU
  
  
  /******************************************************************/
  
  /* Definitions for driver DMAPS */
  #define XPAR_XDMAPS_NUM_INSTANCES 2
  
  /* Definitions for peripheral PS7_DMA_NS */
  #define XPAR_PS7_DMA_NS_DEVICE_ID 0
  #define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
  #define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
  
  
  /* Definitions for peripheral PS7_DMA_S */
  #define XPAR_PS7_DMA_S_DEVICE_ID 1
  #define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
  #define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
  
  
  /******************************************************************/
  
  /* Canonical definitions for peripheral PS7_DMA_NS */
  #define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
  #define XPAR_XDMAPS_0_BASEADDR 0xF8004000
  #define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
  
  /* Canonical definitions for peripheral PS7_DMA_S */
  #define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
  #define XPAR_XDMAPS_1_BASEADDR 0xF8003000
  #define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
  
  
  /******************************************************************/
  
  
  /* Definitions for peripheral PS7_AFI_0 */
  #define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
  #define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
  
  
  /* Definitions for peripheral PS7_AFI_1 */
  #define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
  #define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
  
  
  /* Definitions for peripheral PS7_AFI_2 */
  #define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
  #define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
  
  
  /* Definitions for peripheral PS7_AFI_3 */
  #define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
  #define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
  
  
  /* Definitions for peripheral PS7_DDRC_0 */
  #define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
  #define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
  
  
  /* Definitions for peripheral PS7_GLOBALTIMER_0 */
  #define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
  #define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
  
  
  /* Definitions for peripheral PS7_GPV_0 */
  #define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
  #define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
  
  
  /* Definitions for peripheral PS7_INTC_DIST_0 */
  #define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
  #define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
  
  
  /* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
  #define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
  #define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
  
  
  /* Definitions for peripheral PS7_L2CACHEC_0 */
  #define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
  #define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
  
  
  /* Definitions for peripheral PS7_OCMC_0 */
  #define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
  #define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
  
  
  /* Definitions for peripheral PS7_PL310_0 */
  #define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
  #define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
  
  
  /* Definitions for peripheral PS7_PMU_0 */
  #define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
  #define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
  #define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
  #define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
  
  
  /* Definitions for peripheral PS7_RAM_0 */
  #define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
  #define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
  
  
  /* Definitions for peripheral PS7_RAM_1 */
  #define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
  #define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
  
  
  /* Definitions for peripheral PS7_SCUC_0 */
  #define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
  #define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
  
  
  /* Definitions for peripheral PS7_SLCR_0 */
  #define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
  #define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
  
  
  /******************************************************************/
  
  /* Definitions for driver GPIO */
  #define XPAR_XGPIO_NUM_INSTANCES 1
  
  /* Definitions for peripheral AXI_GPIO_0 */
  #define XPAR_AXI_GPIO_0_BASEADDR 0x41200000
  #define XPAR_AXI_GPIO_0_HIGHADDR 0x4120FFFF
  #define XPAR_AXI_GPIO_0_DEVICE_ID 0
  #define XPAR_AXI_GPIO_0_INTERRUPT_PRESENT 0
  #define XPAR_AXI_GPIO_0_IS_DUAL 1
  
  
  /******************************************************************/
  
  /* Canonical definitions for peripheral AXI_GPIO_0 */
  #define XPAR_GPIO_0_BASEADDR 0x41200000
  #define XPAR_GPIO_0_HIGHADDR 0x4120FFFF
  #define XPAR_GPIO_0_DEVICE_ID XPAR_AXI_GPIO_0_DEVICE_ID
  #define XPAR_GPIO_0_INTERRUPT_PRESENT 0
  #define XPAR_GPIO_0_IS_DUAL 1
  
  
  /******************************************************************/
  
  /* Definitions for driver ICSUART0B */
  #define XPAR_ICSUART0B_NUM_INSTANCES 1
  
  /* Definitions for peripheral ICSUART0B_0 */
  #define XPAR_ICSUART0B_0_DEVICE_ID 0
  #define XPAR_ICSUART0B_0_S00_AXI_BASEADDR 0x43C00000
  #define XPAR_ICSUART0B_0_S00_AXI_HIGHADDR 0x43C0FFFF
  
  
  /******************************************************************/
  
  /* Definitions for driver SCUGIC */
  #define XPAR_XSCUGIC_NUM_INSTANCES 1U
  
  /* Definitions for peripheral PS7_SCUGIC_0 */
  #define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U
  #define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U
  #define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU
  #define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
  
  
  /******************************************************************/
  
  /* Canonical definitions for peripheral PS7_SCUGIC_0 */
  #define XPAR_SCUGIC_0_DEVICE_ID 0U
  #define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U
  #define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU
  #define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
  
  
  /******************************************************************/
  
  /* Definitions for driver SCUTIMER */
  #define XPAR_XSCUTIMER_NUM_INSTANCES 1
  
  /* Definitions for peripheral PS7_SCUTIMER_0 */
  #define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
  #define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
  #define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
  
  
  /******************************************************************/
  
  /* Canonical definitions for peripheral PS7_SCUTIMER_0 */
  #define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
  #define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
  #define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
  
  
  /******************************************************************/
  
  /* Definitions for driver SCUWDT */
  #define XPAR_XSCUWDT_NUM_INSTANCES 1
  
  /* Definitions for peripheral PS7_SCUWDT_0 */
  #define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
  #define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
  #define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
  
  
  /******************************************************************/
  
  /* Canonical definitions for peripheral PS7_SCUWDT_0 */
  #define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
  #define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
  #define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
  
  
  /******************************************************************/
  
  /* Definitions for driver XADCPS */
  #define XPAR_XADCPS_NUM_INSTANCES 1
  
  /* Definitions for peripheral PS7_XADC_0 */
  #define XPAR_PS7_XADC_0_DEVICE_ID 0
  #define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
  #define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
  
  
  /******************************************************************/
  
  /* Canonical definitions for peripheral PS7_XADC_0 */
  #define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
  #define XPAR_XADCPS_0_BASEADDR 0xF8007100
  #define XPAR_XADCPS_0_HIGHADDR 0xF8007120
  
  
  /******************************************************************/
  
  #endif  /* end of protection macro */
  