text: //*****************************************************************************
  //
  //! @file watchdog.c
  //!
  //! @brief Example of a basic configuration of the watchdog.
  //!
  //! This example shows a simple configuration of the watchdog. It will print
  //! a banner message, configure the watchdog for both interrupt and reset
  //! generation, and immediately start the watchdog timer.
  //! The watchdog ISR provided will 'pet' the watchdog four times, printing
  //! a notification message from the ISR each time.
  //! On the fifth interrupt, the watchdog will not be pet, so the 'reset'
  //! action will eventually be allowed to occur.
  //! On the sixth timeout event, the WDT should issue a system reset, and the
  //! program should start over from the beginning.
  //
  //*****************************************************************************
  
  //*****************************************************************************
  //
  // Copyright (c) 2019, Ambiq Micro
  // All rights reserved.
  // 
  // Redistribution and use in source and binary forms, with or without
  // modification, are permitted provided that the following conditions are met:
  // 
  // 1. Redistributions of source code must retain the above copyright notice,
  // this list of conditions and the following disclaimer.
  // 
  // 2. Redistributions in binary form must reproduce the above copyright
  // notice, this list of conditions and the following disclaimer in the
  // documentation and/or other materials provided with the distribution.
  // 
  // 3. Neither the name of the copyright holder nor the names of its
  // contributors may be used to endorse or promote products derived from this
  // software without specific prior written permission.
  // 
  // Third party software included in this distribution is subject to the
  // additional license terms as defined in the /docs/licenses directory.
  // 
  // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  // POSSIBILITY OF SUCH DAMAGE.
  //
  // This is part of revision v2.2.0-7-g63f7c2ba1 of the AmbiqSuite Development Package.
  //
  //*****************************************************************************
  
  #include "am_mcu_apollo.h"
  #include "am_bsp.h"
  #include "am_util.h"
  
  //*****************************************************************************
  //
  // Global Variables
  //
  //*****************************************************************************
  uint8_t g_ui8NumWatchdogInterrupts = 0;
  uint32_t g_ui32ResetStatus = 0;
  
  am_hal_wdt_config_t g_sWatchdogConfig =
  {
      //
      // Select the Apollo 1 Clock Rate.
      //
  #ifdef AM_PART_APOLLO
      .ui32Config = AM_HAL_WDT_ENABLE_RESET | AM_HAL_WDT_ENABLE_INTERRUPT,
  #endif
  #ifdef AM_PART_APOLLO2
      .ui32Config = AM_REG_WDT_CFG_CLKSEL_128HZ | AM_HAL_WDT_ENABLE_RESET | AM_HAL_WDT_ENABLE_INTERRUPT,
  #endif
      //
      // Set WDT interrupt timeout for 3/4 second.
      //
      .ui16InterruptCount = 128 * 3 / 4,
  
      //
      // Set WDT reset timeout for 1.5 seconds.
      //
      .ui16ResetCount = 128 * 3 / 2
  };
  
  //*****************************************************************************
  //
  // Interrupt handler for the watchdog.
  //
  //*****************************************************************************
  void
  am_watchdog_isr(void)
  {
      //
      // Clear the watchdog interrupt.
      //
      am_hal_wdt_int_clear();
  
      //
      // Catch the first four watchdog interrupts, but let the fifth through
      // untouched.
      //
      if ( g_ui8NumWatchdogInterrupts < 4 )
      {
          //
          // Restart the watchdog.
          //
          am_hal_wdt_restart();
      }
  
      //
      // Enable debug printf messages using ITM on SWO pin
      //
      am_bsp_debug_printf_enable();
  
      //
      // Send a status message and give it some time to print.
      //
      am_util_stdio_printf("Interrupt #: %d\n", g_ui8NumWatchdogInterrupts);
      am_util_delay_ms(100);
  
      //
      // Increment the number of watchdog interrupts.
      //
      g_ui8NumWatchdogInterrupts++;
  
  
  }
  
  //*****************************************************************************
  //
  // Main function.
  //
  //*****************************************************************************
  int
  main(void)
  {
      //
      // Set the clock frequency.
      //
      am_hal_clkgen_sysclk_select(AM_HAL_CLKGEN_SYSCLK_MAX);
  
      //
      // Set the default cache configuration
      //
      am_hal_cachectrl_enable(&am_hal_cachectrl_defaults);
  
      //
      // Configure the board for low power operation.
      //
      am_bsp_low_power_init();
  
      //
      // Initialize device drivers for the LEDs on the board.
      //
      am_devices_led_array_init(am_bsp_psLEDs, AM_BSP_NUM_LEDS);
  
      //
      // Initialize the printf interface for ITM/SWO output.
      //
      am_util_stdio_printf_init((am_util_stdio_print_char_t) am_bsp_itm_string_print);
  
      //
      // Initialize the SWO GPIO pin
      //
      am_bsp_pin_enable(ITM_SWO);
  
      //
      // Enable the ITM.
      //
      am_hal_itm_enable();
  
      //
      // Enable debug printf messages using ITM on SWO pin
      //
      am_bsp_debug_printf_enable();
  
      //
      // Clear the terminal screen, and print a quick message to show that we're
      // alive.
      //
      am_util_stdio_terminal_clear();
      am_util_stdio_printf("Watchdog Example.\n");
  
      //
      // Print out reset status register upon entry.
      //
      g_ui32ResetStatus = am_hal_reset_status_get();
      am_util_stdio_printf("Reset Status Register = 0x%x\n",
                            g_ui32ResetStatus);
  
      //
      // Clear reset status register for next time we reset.
      //
      am_hal_reset_status_clear();
  
      //
      // LFRC has to be turned on for this example because the watchdog only
      // runs off of the LFRC.
      //
      am_hal_clkgen_osc_start(AM_HAL_CLKGEN_OSC_LFRC);
  
      //
      // Configure the watchdog.
      //
      am_hal_wdt_init(&g_sWatchdogConfig);
  
      //
      // Enable the interrupt for the watchdog in the NVIC.
      //
      am_hal_interrupt_enable(AM_HAL_INTERRUPT_WATCHDOG);
      am_hal_interrupt_master_enable();
  
      //
      // Enable the watchdog.
      //
      am_hal_wdt_start();
  
      //
      // Loop forever.
      //
      while (1)
      {
          //
          // We are done printing. Disable debug printf messages on ITM.
          //
          am_bsp_debug_printf_disable();
  
          //
          // Disable interrupts.
          //
          am_hal_interrupt_master_disable();
  
          //
          // Turn OFF the indicator LED.
          //
          am_devices_led_off(am_bsp_psLEDs, 0);
  
          //
          // Go to deep sleep.
          //
          am_hal_sysctrl_sleep(AM_HAL_SYSCTRL_SLEEP_DEEP);
  
          //
          // Turn ON the indicator LED.
          //
          am_devices_led_on(am_bsp_psLEDs, 0);
  
          //
          // An interrupt woke us up so now enable them and take it.
          //
          am_hal_interrupt_master_enable();
      }
  }
  
  