text: #include <stdio.h>
  #include <sys/ioctl.h>
  
  #include "maplesyrup.h"
  #include "parse.h"
  #include "parse_breakout.h"
  #include "bitfield_armv7a.h"
  
  
  bitfield_info bitfield_armv7a_table[] =
  {       
      /* Identification Bitfields */ 
      { 1, 0, MS_SYSREG_PFR0, NS_PRIVILEGE_LEVEL_1, 0, 4, "State0", "ident", "PFR0", "ARM instruction set support" },
      { 1, 1, MS_SYSREG_PFR0, NS_PRIVILEGE_LEVEL_1, 4, 4, "State1", "ident", "PFR0", "Thumb instruction set support" },
      { 1, 2, MS_SYSREG_PFR0, NS_PRIVILEGE_LEVEL_1, 8, 4, "State2", "ident", "PFR0", "Jazelle extension support" },
      { 1, 3, MS_SYSREG_PFR0, NS_PRIVILEGE_LEVEL_1, 12, 4, "State3", "ident", "PFR0", "ThumbEE instruction set support" },
      { 1, 4, MS_SYSREG_PFR0, NS_PRIVILEGE_LEVEL_1, 16, 16, "Reserved", "ident", "PFR0", "Reserved" },
  
      { 1, 0, MS_SYSREG_PFR1, NS_PRIVILEGE_LEVEL_1, 0, 4, "Programmers' model", "ident", "PFR1", "Programmers' model" },
      { 1, 1, MS_SYSREG_PFR1, NS_PRIVILEGE_LEVEL_1, 4, 4, "Security", "ident", "PFR1", "Security support" },
      { 1, 2, MS_SYSREG_PFR1, NS_PRIVILEGE_LEVEL_1, 8, 4, "M profile programmers' model", "ident", "PFR1", "M profile programmers' model" },
      { 1, 3, MS_SYSREG_PFR1, NS_PRIVILEGE_LEVEL_1, 12, 4, "Virtualization Extensions", "ident", "PFR1", "Virtualization Extensions" },
      { 1, 4, MS_SYSREG_PFR1, NS_PRIVILEGE_LEVEL_1, 16, 4, "Generic Timer Extension", "ident", "PFR1", "Generic Timer Extension" },  
      { 1, 5, MS_SYSREG_PFR1, NS_PRIVILEGE_LEVEL_1, 20, 12, "Reserved", "ident", "PFR1", "Reserved" },    
      
      { 1, 0, MS_SYSREG_DFR0, NS_PRIVILEGE_LEVEL_1, 0, 4, "Coprocessor debug model", "ident", "DFR0", "Coprocessor debug model" },
      { 1, 1, MS_SYSREG_DFR0, NS_PRIVILEGE_LEVEL_1, 4, 4, "Coprocessor secure debug model", "ident", "DFR0", "Coprocessor secure debug model" },
      { 1, 2, MS_SYSREG_DFR0, NS_PRIVILEGE_LEVEL_1, 8, 4, "Memory-mapped debug model", "ident", "DFR0", " Memory-mapped debug model" },
      { 1, 3, MS_SYSREG_DFR0, NS_PRIVILEGE_LEVEL_1, 12, 4, "Coprocessor trace model", "ident", "DFR0", " Coprocessor trace model" },
      { 1, 4, MS_SYSREG_DFR0, NS_PRIVILEGE_LEVEL_1, 16, 4, "Memory-mapped trace model", "ident", "DFR0", "Memory-mapped trace model" },
      { 1, 5, MS_SYSREG_DFR0, NS_PRIVILEGE_LEVEL_1, 20, 4, "Debug model, M profile", "ident", "DFR0", "Debug model, M profile" },
      { 1, 6, MS_SYSREG_DFR0, NS_PRIVILEGE_LEVEL_1, 24, 4, "Performance Monitors Extension", "ident", "DFR0", "Performance Monitors Extension" },
      { 1, 7, MS_SYSREG_DFR0, NS_PRIVILEGE_LEVEL_1, 28, 4, "Reserved", "ident", "DFR0", "Reserved" },
      
      { 1, 0, MS_SYSREG_AFR0, NS_PRIVILEGE_LEVEL_1, 0, 4, "Implementation Defined", "ident", "AFR0", "Implementation Defined" },
      { 1, 1, MS_SYSREG_AFR0, NS_PRIVILEGE_LEVEL_1, 4, 4, "Implementation Defined", "ident", "AFR0", "Implementation Defined" },
      { 1, 2, MS_SYSREG_AFR0, NS_PRIVILEGE_LEVEL_1, 8, 4, "Implementation Defined", "ident", "AFR0", "Implementation Defined" },
      { 1, 3, MS_SYSREG_AFR0, NS_PRIVILEGE_LEVEL_1, 12, 4, "Implementation Defined", "ident", "AFR0", "Implementation Defined" },
      { 1, 4, MS_SYSREG_AFR0, NS_PRIVILEGE_LEVEL_1, 16, 16, "Reserved", "ident", "AFR0", "Reserved" },
          
      { 1, 0, MS_SYSREG_MMFR0, NS_PRIVILEGE_LEVEL_1, 0, 4, "VMSA support", "ident", "MMFR0", "VMSA Support" },
      { 1, 1, MS_SYSREG_MMFR0, NS_PRIVILEGE_LEVEL_1, 4, 4, "PMSA support", "ident", "MMFR0", "PMSA Support" },
      { 1, 2, MS_SYSREG_MMFR0, NS_PRIVILEGE_LEVEL_1, 8, 4, "Outermost shareability", "ident", "MMFR0", "Outermost shareability" },
      { 1, 3, MS_SYSREG_MMFR0, NS_PRIVILEGE_LEVEL_1, 12, 4, "Shareability levels", "ident", "MMFR0", "Shareability levels" },
      { 1, 4, MS_SYSREG_MMFR0, NS_PRIVILEGE_LEVEL_1, 16, 4, "TCM support", "ident", "MMFR0", "TCM/DMA Support" },
      { 1, 5, MS_SYSREG_MMFR0, NS_PRIVILEGE_LEVEL_1, 20, 4, "Auxiliary registers", "ident", "MMFR0", "Auxiliary registers" },
      { 1, 6, MS_SYSREG_MMFR0, NS_PRIVILEGE_LEVEL_1, 24, 4, "FCSE support", "ident", "MMFR0", "FCSE support" },
      { 1, 7, MS_SYSREG_MMFR0, NS_PRIVILEGE_LEVEL_1, 28, 4, "Innermost shareability", "ident", "MMFR0", "Innermost shareability" },
      
      { 1, 0, MS_SYSREG_MMFR1, NS_PRIVILEGE_LEVEL_1, 0, 4, "L1 Harvard cache VA", "ident", "MMFR1", "L1 Harvard cache VA" },
      { 1, 1, MS_SYSREG_MMFR1, NS_PRIVILEGE_LEVEL_1, 4, 4, "L1 unified cache VA", "ident", "MMFR1", "L1 unified cache VA" },
      { 1, 2, MS_SYSREG_MMFR1, NS_PRIVILEGE_LEVEL_1, 8, 4, "L1 Harvard cache set/way", "ident", "MMFR1", "Harvard cache set/way" },
      { 1, 3, MS_SYSREG_MMFR1, NS_PRIVILEGE_LEVEL_1, 12, 4, "L1 unified cache set/way", "ident", "MMFR1", "L1 unified cache set/way" },
      { 1, 4, MS_SYSREG_MMFR1, NS_PRIVILEGE_LEVEL_1, 16, 4, "L1 Harvard cache", "ident", "MMFR1", "L1 Harvard cache" },
      { 1, 5, MS_SYSREG_MMFR1, NS_PRIVILEGE_LEVEL_1, 20, 4, "L1 unified cache VA", "ident", "MMFR1", "L1 unified cache" },
      { 1, 6, MS_SYSREG_MMFR1, NS_PRIVILEGE_LEVEL_1, 24, 4, "L1 cache test and clean", "ident", "MMFR1", "L1 cache test and clean" },
      { 1, 7, MS_SYSREG_MMFR1, NS_PRIVILEGE_LEVEL_1, 28, 4, "Branch predictor", "ident", "MMFR1", "Branch predictor" },
      
      { 1, 0, MS_SYSREG_MMFR2, NS_PRIVILEGE_LEVEL_1, 0, 4, "L1 Harvard fg fetch", "ident", "MMFR2", "L1 Harvard fg fetch" },
      { 1, 1, MS_SYSREG_MMFR2, NS_PRIVILEGE_LEVEL_1, 4, 4, "L1 Harvard bg fetch", "ident", "MMFR2", "L1 Harvard bg fetch" },
      { 1, 2, MS_SYSREG_MMFR2, NS_PRIVILEGE_LEVEL_1, 8, 4, "L1 Harvard range", "ident", "MMFR2", "L1 Harvard range" },
      { 1, 3, MS_SYSREG_MMFR2, NS_PRIVILEGE_LEVEL_1, 12, 4, "Harvard TLB", "ident", "MMFR2", "Harvard TLB" },
      { 1, 4, MS_SYSREG_MMFR2, NS_PRIVILEGE_LEVEL_1, 16, 4, "Unified TLB", "ident", "MMFR2", "Unified TLB" },
      { 1, 5, MS_SYSREG_MMFR2, NS_PRIVILEGE_LEVEL_1, 20, 4, "Mem barrier", "ident", "MMFR2", "Mem barrier" },
      { 1, 6, MS_SYSREG_MMFR2, NS_PRIVILEGE_LEVEL_1, 24, 4, "WFI stall", "ident", "MMFR2", "WFI stall" },
      { 1, 7, MS_SYSREG_MMFR2, NS_PRIVILEGE_LEVEL_1, 28, 4, "HW Access flag", "ident", "MMFR2", "HW Access flag" },
      
      { 1, 0, MS_SYSREG_MMFR3, NS_PRIVILEGE_LEVEL_1, 0, 4, "Cache maintain MVA", "ident", "MMFR3", "Cache maintain MVA" },
      { 1, 1, MS_SYSREG_MMFR3, NS_PRIVILEGE_LEVEL_1, 4, 4, "Cache maintain set/way", "ident", "MMFR3", "Cache maintain set/way" },
      { 1, 2, MS_SYSREG_MMFR3, NS_PRIVILEGE_LEVEL_1, 8, 4, "BP maintain", "ident", "MMFR3", "BP maintain" },
      { 1, 3, MS_SYSREG_MMFR3, NS_PRIVILEGE_LEVEL_1, 12, 4, "Maintenance broadcast", "ident", "MMFR3", "Maintenance broadcast" },
      { 1, 4, MS_SYSREG_MMFR3, NS_PRIVILEGE_LEVEL_1, 16, 4, "Reserved", "ident", "MMFR3", "Reserved" },
      { 1, 5, MS_SYSREG_MMFR3, NS_PRIVILEGE_LEVEL_1, 20, 4, "Coherent walk", "ident", "MMFR3", "Coherent walk" },
      { 1, 6, MS_SYSREG_MMFR3, NS_PRIVILEGE_LEVEL_1, 24, 4, "Cached memory size", "ident", "MMFR3", "Cached memory size" },
      { 1, 7, MS_SYSREG_MMFR3, NS_PRIVILEGE_LEVEL_1, 28, 4, "Supersection support", "ident", "MMFR3", "Supersection support" },
          
      { 1, 0, MS_SYSREG_ISAR0, NS_PRIVILEGE_LEVEL_1, 0, 4, "Swap_instrs", "ident", "ISAR0", "Swap_instrs" },
      { 1, 1, MS_SYSREG_ISAR0, NS_PRIVILEGE_LEVEL_1, 4, 4, "BitCount_instrs", "ident", "ISAR0", "BitCount_instrs" },
      { 1, 2, MS_SYSREG_ISAR0, NS_PRIVILEGE_LEVEL_1, 8, 4, "Bitfield_instrs", "ident", "ISAR0", "Bitfield_instrs" },
      { 1, 3, MS_SYSREG_ISAR0, NS_PRIVILEGE_LEVEL_1, 12, 4, "CmpBranch_instrs", "ident", "ISAR0", "Compare and Branch instructions" },
      { 1, 4, MS_SYSREG_ISAR0, NS_PRIVILEGE_LEVEL_1, 16, 4, "Coproc_instrs", "ident", "ISAR0", "Coprocessor instructions" },
      { 1, 5, MS_SYSREG_ISAR0, NS_PRIVILEGE_LEVEL_1, 20, 4, "Debug_instrs", "ident", "ISAR0", "Debug instructions" },
      { 1, 6, MS_SYSREG_ISAR0, NS_PRIVILEGE_LEVEL_1, 24, 4, "Divide_instrs", "ident", "ISAR0", "Divide instructions" },
      { 1, 7, MS_SYSREG_ISAR0, NS_PRIVILEGE_LEVEL_1, 28, 4, "Reserved", "ident", "ISAR0", "Reserved" },
      
      { 1, 0, MS_SYSREG_ISAR1, NS_PRIVILEGE_LEVEL_1, 0, 4, "Ending_instrs", "ident", "ISAR1", "Endian instructions" },
      { 1, 1, MS_SYSREG_ISAR1, NS_PRIVILEGE_LEVEL_1, 4, 4, "Except_instrs", "ident", "ISAR1", "Exception-handling instructions" },
      { 1, 2, MS_SYSREG_ISAR1, NS_PRIVILEGE_LEVEL_1, 8, 4, "Except_AR_instrs", "ident", "ISAR1", "A & R profile exception-handling instructions" },
      { 1, 3, MS_SYSREG_ISAR1, NS_PRIVILEGE_LEVEL_1, 12, 4, "Extend_instrs", "ident", "ISAR1", "Extend instructions" },
      { 1, 4, MS_SYSREG_ISAR1, NS_PRIVILEGE_LEVEL_1, 16, 4, "IfThen_instrs", "ident", "ISAR1", "If-Then instructions in Thumb" },
      { 1, 5, MS_SYSREG_ISAR1, NS_PRIVILEGE_LEVEL_1, 20, 4, "Immediate_instrs", "ident", "ISAR1", "Data processing instructions on long immediates" },
      { 1, 6, MS_SYSREG_ISAR1, NS_PRIVILEGE_LEVEL_1, 24, 4, "Interwork_instrs", "ident", "ISAR1", "Interworking instructions" },
      { 1, 7, MS_SYSREG_ISAR1, NS_PRIVILEGE_LEVEL_1, 28, 4, "Jazelle_instrs", "ident", "ISAR1", "Jazelle extension instructions" },
          
      { 1, 0, MS_SYSREG_ISAR2, NS_PRIVILEGE_LEVEL_1, 0, 4, "LoadStore_instrs", "ident", "ISAR2", "Additional load/store instructions" },
      { 1, 1, MS_SYSREG_ISAR2, NS_PRIVILEGE_LEVEL_1, 4, 4, "MemHint_instrs", "ident", "ISAR2", "Memory Hint instructions" },
      { 1, 2, MS_SYSREG_ISAR2, NS_PRIVILEGE_LEVEL_1, 8, 4, "MultiAccessInt_instrs", "ident", "ISAR2", "Interruptible multi-access instructions" },
      { 1, 3, MS_SYSREG_ISAR2, NS_PRIVILEGE_LEVEL_1, 12, 4, "Mult_instrs", "ident", "ISAR2", "Additional multiply instructions" },
      { 1, 4, MS_SYSREG_ISAR2, NS_PRIVILEGE_LEVEL_1, 16, 4, "MultS_instrs", "ident", "ISAR2", "Advanced signed Multiply instructions" },
      { 1, 5, MS_SYSREG_ISAR2, NS_PRIVILEGE_LEVEL_1, 20, 4, "MultU_instrs", "ident", "ISAR2", "Advanced unsigned Multiply instructions" },
      { 1, 6, MS_SYSREG_ISAR2, NS_PRIVILEGE_LEVEL_1, 24, 4, "PSR_AR_instrs", "ident", "ISAR2", "Instructions to manipulate PSR" },
      { 1, 7, MS_SYSREG_ISAR2, NS_PRIVILEGE_LEVEL_1, 28, 4, "Reversal_instrs", "ident", "ISAR2", "Implemented Reversal instructions" },
      
      { 1, 0, MS_SYSREG_ISAR3, NS_PRIVILEGE_LEVEL_1, 0, 4, "Saturate_instrs", "ident", "ISAR3", "Implemented Saturate instructions" },
      { 1, 1, MS_SYSREG_ISAR3, NS_PRIVILEGE_LEVEL_1, 4, 4, "SIMD_instrs", "ident", "ISAR3", "Implemented SIMD instructions" },
      { 1, 2, MS_SYSREG_ISAR3, NS_PRIVILEGE_LEVEL_1, 8, 4, "SVC_instrs", "ident", "ISAR3", "Implemented SVC instructions" },
      { 1, 3, MS_SYSREG_ISAR3, NS_PRIVILEGE_LEVEL_1, 12, 4, "SynchPrim_instrs", "ident", "ISAR3", " Synchronization Primitive instructions" },
      { 1, 4, MS_SYSREG_ISAR3, NS_PRIVILEGE_LEVEL_1, 16, 4, "TabBranch_instrs", "ident", "ISAR3", "Table Branch instructions in Thumb" },
      { 1, 5, MS_SYSREG_ISAR3, NS_PRIVILEGE_LEVEL_1, 20, 4, "ThumbCopy_instrs", "ident", "ISAR3", "Thumb non-flag setting MOV instructions" },
      { 1, 6, MS_SYSREG_ISAR3, NS_PRIVILEGE_LEVEL_1, 24, 4, "TrueNOP_instrs", "ident", "ISAR3", "Implemented True NOP instructions" },
      { 1, 7, MS_SYSREG_ISAR3, NS_PRIVILEGE_LEVEL_1, 28, 4, "ThumbEE_extn_instrs", "ident", "ISAR3", "Thumb Execution Environment Extension instructions" },
      
      { 1, 0, MS_SYSREG_ISAR4, NS_PRIVILEGE_LEVEL_1, 0, 4, "Unpriv_instrs", "ident", "ISAR4", "Implemented Unprivileged instructions" },
      { 1, 1, MS_SYSREG_ISAR4, NS_PRIVILEGE_LEVEL_1, 4, 4, "WithShifts_instrs", "ident", "ISAR4", "Support for instructions with shifts" },
      { 1, 2, MS_SYSREG_ISAR4, NS_PRIVILEGE_LEVEL_1, 8, 4, "Writeback_instrs", "ident", "ISAR4", "Writeback addressing modes" },
      { 1, 3, MS_SYSREG_ISAR4, NS_PRIVILEGE_LEVEL_1, 12, 4, "SMC_instrs", "ident", "ISAR4", "SMC instructions" },
      { 1, 4, MS_SYSREG_ISAR4, NS_PRIVILEGE_LEVEL_1, 16, 4, "Barrier_instrs", "ident", "ISAR4", "Barrier instructions" },
      { 1, 5, MS_SYSREG_ISAR4, NS_PRIVILEGE_LEVEL_1, 20, 4, "SynchPrim_instrs", "ident", "ISAR4", "Implemented Synchronization Primitive instructions" },
      { 1, 6, MS_SYSREG_ISAR4, NS_PRIVILEGE_LEVEL_1, 24, 4, "PSR_M_instrs", "ident", "ISAR4", "M profile instructions to modify PSR" },
      { 1, 7, MS_SYSREG_ISAR4, NS_PRIVILEGE_LEVEL_1, 28, 4, "SWP_frac", "ident", "ISAR4", "Bus locking on SWP or SWPB" },
      
      { 1, 0, MS_SYSREG_ISAR5, NS_PRIVILEGE_LEVEL_1, 0, 32, "Reserved", "ident", "ISAR5", "Reserved" },
      
      { 1, 0, MS_SYSREG_REVIDR, NS_PRIVILEGE_LEVEL_1, 0, 32, "Reserved", "ident", "REVIDR", "Implementation Defined" },
      
      { 1, 0, MS_SYSREG_TLBTR, NS_PRIVILEGE_LEVEL_1, 0, 1, "nU", "ident", "TLBTR", "[0] Not Unified TLB" },
      { 1, 1, MS_SYSREG_TLBTR, NS_PRIVILEGE_LEVEL_1, 1, 31, "Implementation Defined", "ident", "TLBTR", "Implementation Defined" },
      
      { 1, 0, MS_SYSREG_CCSIDR, NS_PRIVILEGE_LEVEL_1, 0, 3, "LineSize", "ident", "CCSIDR", "Number of words in cache line" },
      { 1, 1, MS_SYSREG_CCSIDR, NS_PRIVILEGE_LEVEL_1, 3, 10, "Associativity", "ident", "CCSIDR", "Associativity of cache" },
      { 1, 2, MS_SYSREG_CCSIDR, NS_PRIVILEGE_LEVEL_1, 13, 15, "NumSets", "ident", "CCSIDR", "Number of sets in cache" },
      { 1, 3, MS_SYSREG_CCSIDR, NS_PRIVILEGE_LEVEL_1, 28, 1, "WA", "ident", "CCSIDR", "Write allocation" },
      { 1, 4, MS_SYSREG_CCSIDR, NS_PRIVILEGE_LEVEL_1, 29, 1, "RA", "ident", "CCSIDR", "Read allocation" },
      { 1, 5, MS_SYSREG_CCSIDR, NS_PRIVILEGE_LEVEL_1, 30, 1, "WB", "ident", "CCSIDR", "Write back" },
      { 1, 6, MS_SYSREG_CCSIDR, NS_PRIVILEGE_LEVEL_1, 31, 1, "WT", "ident", "CCSIDR", "Write through" },
      
      { 1, 0, MS_SYSREG_TCMTR, NS_PRIVILEGE_LEVEL_1, 0, 29, "Implementation Defined", "ident", "TCMTR", "Implementation Defined" },
      { 1, 1, MS_SYSREG_TCMTR, NS_PRIVILEGE_LEVEL_1, 29, 3, "Format", "ident", "TCMTR", "Implemented TCMTR format" },
          
      { 1, 0, MS_SYSREG_AIDR, NS_PRIVILEGE_LEVEL_1, 0, 32, "Implementation Defined", "ident", "AIDR", "Implementation Defined" },
      
      { 1, 0, MS_SYSREG_CLIDR, NS_PRIVILEGE_LEVEL_1, 0, 3, "Ctype1", "ident", "CLIDR", "Cache type 1" },
      { 1, 1, MS_SYSREG_CLIDR, NS_PRIVILEGE_LEVEL_1, 3, 3, "Ctype2", "ident", "CLIDR", "Cache type 2" },
      { 1, 2, MS_SYSREG_CLIDR, NS_PRIVILEGE_LEVEL_1, 6, 3, "Ctype3", "ident", "CLIDR", "Cache type 3" },
      { 1, 3, MS_SYSREG_CLIDR, NS_PRIVILEGE_LEVEL_1, 9, 3, "Ctype4", "ident", "CLIDR", "Cache type 4" },
      { 1, 4, MS_SYSREG_CLIDR, NS_PRIVILEGE_LEVEL_1, 12, 3, "Ctype5", "ident", "CLIDR", "Cache type 5" },
      { 1, 5, MS_SYSREG_CLIDR, NS_PRIVILEGE_LEVEL_1, 15, 3, "Ctype6", "ident", "CLIDR", "Cache type 6" },
      { 1, 6, MS_SYSREG_CLIDR, NS_PRIVILEGE_LEVEL_1, 18, 3, "Ctype7", "ident", "CLIDR", "Cache type 7" },
      { 1, 7, MS_SYSREG_CLIDR, NS_PRIVILEGE_LEVEL_1, 21, 3, "LoUIS", "ident", "CLIDR", "Level of Unification Inner Shareable" },
      { 1, 8, MS_SYSREG_CLIDR, NS_PRIVILEGE_LEVEL_1, 24, 3, "LoC", "ident", "CLIDR", "Level of Coherence" },
      { 1, 9, MS_SYSREG_CLIDR, NS_PRIVILEGE_LEVEL_1, 27, 3, "LoUU", "ident", "CLIDR", "Level of Unification Uniprocessor" },
      { 1, 10, MS_SYSREG_CLIDR, NS_PRIVILEGE_LEVEL_1, 30, 2, "Reserved", "ident", "CLIDR", "Reserved" },
      
      { 1, 0, MS_SYSREG_CSSELR, NS_PRIVILEGE_LEVEL_1, 0, 1, "InD", "ident", "CSSELR", "Instruction not Data bit" },
      { 1, 1, MS_SYSREG_CSSELR, NS_PRIVILEGE_LEVEL_1, 1, 3, "Level", "ident", "CSSELR", "Level" },
      { 1, 2, MS_SYSREG_CSSELR, NS_PRIVILEGE_LEVEL_1, 4, 28, "Reserved", "ident", "CSSELR", "Reserved" },
      
      { 1, 0, MS_SYSREG_CTR, NS_PRIVILEGE_LEVEL_1, 0, 4, "IminLine", "ident", "CTR", "IminLine" },
      { 1, 1, MS_SYSREG_CTR, NS_PRIVILEGE_LEVEL_1, 4, 10, "Reserved", "ident", "CTR", "Reserved" },
      { 1, 2, MS_SYSREG_CTR, NS_PRIVILEGE_LEVEL_1, 14, 2, "L1Ip", "ident", "CTR", "Level 1 instruction cache policy" },
      { 1, 3, MS_SYSREG_CTR, NS_PRIVILEGE_LEVEL_1, 16, 4, "DminLine", "ident", "CTR", "DminLine" },
      { 1, 4, MS_SYSREG_CTR, NS_PRIVILEGE_LEVEL_1, 20, 4, "ERG", "ident", "CTR", "Exclusives Reservation Granule" },
      { 1, 5, MS_SYSREG_CTR, NS_PRIVILEGE_LEVEL_1, 24, 4, "CWG", "ident", "CTR", "Cache Write-back Granule" },
      { 1, 6, MS_SYSREG_CTR, NS_PRIVILEGE_LEVEL_1, 28, 1, "Reserved", "ident", "CTR", "Reserved" },
      { 1, 7, MS_SYSREG_CTR, NS_PRIVILEGE_LEVEL_1, 29, 3, "Format", "ident", "CTR", "CTR Format" },
      
      { 1, 0, MS_SYSREG_MIDR, NS_PRIVILEGE_LEVEL_1, 0, 4, "Revision", "ident", "MIDR", "Revision" },
      { 1, 1, MS_SYSREG_MIDR, NS_PRIVILEGE_LEVEL_1, 4, 12, "Primary part number", "ident", "MIDR", "Primary part number" },
      { 1, 2, MS_SYSREG_MIDR, NS_PRIVILEGE_LEVEL_1, 16, 4, "Architecture", "ident", "MIDR", "Architecture" },
      { 1, 3, MS_SYSREG_MIDR, NS_PRIVILEGE_LEVEL_1, 20, 4, "Variant", "ident", "MIDR", "Variant" },
      { 1, 4, MS_SYSREG_MIDR, NS_PRIVILEGE_LEVEL_1, 24, 8, "Implementer", "ident", "MIDR", "Implementer" },
      
      { 1, 0, MS_SYSREG_MPIDR, NS_PRIVILEGE_LEVEL_1, 0, 8, "Aff0", "ident", "MPIDR", "Affinity level 0" },
      { 1, 1, MS_SYSREG_MPIDR, NS_PRIVILEGE_LEVEL_1, 8, 8, "Aff1", "ident", "MPIDR", "Affinity level 1" },
      { 1, 2, MS_SYSREG_MPIDR, NS_PRIVILEGE_LEVEL_1, 16, 8, "Aff2", "ident", "MPIDR", "Affinity level 2" },
      { 1, 3, MS_SYSREG_MPIDR, NS_PRIVILEGE_LEVEL_1, 24, 1, "MT", "ident", "MPIDR", "Affinity dependence" },
      { 1, 4, MS_SYSREG_MPIDR, NS_PRIVILEGE_LEVEL_1, 25, 5, "Reserved", "ident", "MPIDR", "Reserved" },
      { 1, 5, MS_SYSREG_MPIDR, NS_PRIVILEGE_LEVEL_1, 30, 1, "U", "ident", "MPIDR", "Uniprocessor system" },
      { 1, 6, MS_SYSREG_MPIDR, NS_PRIVILEGE_LEVEL_1, 31, 1, "ME", "ident", "MPIDR", "Register format" },       
                  
                  
      /* Floating Point Bitfields */
      { 1, 0, MS_SYSREG_FPSID, NS_PRIVILEGE_LEVEL_1, 0, 4, "Revision", "fp", "FPSID", "Revision number" },
      { 1, 1, MS_SYSREG_FPSID, NS_PRIVILEGE_LEVEL_1, 4, 4, "Variant", "fp", "FPSID", "Variant number" },
      { 1, 2, MS_SYSREG_FPSID, NS_PRIVILEGE_LEVEL_1, 8, 8, "Part Number", "fp", "FPSID", "Part number" },
      { 1, 3, MS_SYSREG_FPSID, NS_PRIVILEGE_LEVEL_1, 16, 6, "Subarchitecture", "fp", "FPSID", "Subarchitecture version number" },
      { 1, 4, MS_SYSREG_FPSID, NS_PRIVILEGE_LEVEL_1, 23, 1, "SW", "fp", "FPSID", "Software emulation" },
      { 1, 5, MS_SYSREG_FPSID, NS_PRIVILEGE_LEVEL_1, 24, 8, "Implementer", "fp", "FPSID", "Implementer" },
      
      { 1, 0, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 0, 1, "IOC", "fp", "FPSCR", "Invalid Operation cumulative exception" },  
      { 1, 1, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 1, 1, "DZC", "fp", "FPSCR", "Division by Zero cumulative exception" },   
      { 1, 2, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 2, 1, "OFC", "fp", "FPSCR", "Overflow cumulative exception" },   
      { 1, 3, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 3, 1, "UFC", "fp", "FPSCR", "Underflow cumulative exception" },  
      { 1, 4, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 4, 1, "IXC", "fp", "FPSCR", "Inexact cumulative exception" },
      { 1, 5, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 5, 2, "Reserved", "fp", "FPSCR", "Reserved" },
      { 1, 6, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 7, 1, "IDC", "fp", "FPSCR", "Input Denormal cumulative exception" },
      { 1, 7, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 8, 1, "IOE", "fp", "FPSCR", "Invalid Operation exception trap enable" },
      { 1, 8, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 9, 1, "DZE", "fp", "FPSCR", "Division by Zero exception trap enable" },
      { 1, 9, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 10, 1, "OFE", "fp", "FPSCR", "Overflow exception trap enable" },
      { 1, 10, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 11, 1, "UFE", "fp", "FPSCR", "Underflow exception trap enable" },
      { 1, 11, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 12, 1, "IXE", "fp", "FPSCR", "Inexact exception trap enable" },
      { 1, 12, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 13, 2, "Reserved", "fp", "FPSCR", "Reserved" },
      { 1, 13, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 15, 1, "IDE", "fp", "FPSCR", "Input Denormal exception trap enable" },
      { 1, 14, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 16, 3, "LEN", "fp", "FPSCR", "ARM deprecated field" },
      { 1, 15, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 19, 1, "Reserved", "fp", "FPSCR", "Reserved" },
      { 1, 16, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 20, 2, "Stride", "fp", "FPSCR", "ARM deprecated field" },
      { 1, 17, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 22, 2, "RMode", "fp", "FPSCR", "Rounding Mode control" },
      { 1, 18, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 24, 1, "FZ", "fp", "FPSCR", "Flush-to-zero" },
      { 1, 19, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 25, 1, "DN", "fp", "FPSCR", "Default NaN" },
      { 1, 20, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 26, 1, "AHP", "fp", "FPSCR", "Alternative half-precision" },
      { 1, 21, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 27, 1, "QC", "fp", "FPSCR", "Cumulative saturation bit" },
      { 1, 22, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 28, 1, "V", "fp", "FPSCR", "Overflow condition flag" },
      { 1, 23, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 29, 1, "C", "fp", "FPSCR", "Carry condition flag" },
      { 1, 24, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 30, 1, "Z", "fp", "FPSCR", "Zero condition flag" },
      { 1, 25, MS_SYSREG_FPSCR, NS_PRIVILEGE_LEVEL_1, 31, 1, "N", "fp", "FPSCR", "Negative condition flag" },
      
      { 1, 0, MS_SYSREG_FPEXC, NS_PRIVILEGE_LEVEL_1, 0, 29, "Implementation Defined", "fp", "FPEXC", "Subarchitecture defined" },
      { 1, 1, MS_SYSREG_FPEXC, NS_PRIVILEGE_LEVEL_1, 30, 1, "EN", "fp", "FPEXC", "Global enable for Advanced SIMD and Floating-point Extensions" },
      { 1, 2, MS_SYSREG_FPEXC, NS_PRIVILEGE_LEVEL_1, 31, 1, "EX", "fp", "FPEXC", "Extent of saved records for Advanced SIMD and Floating-point systems" },
      
      { 1, 0, MS_SYSREG_MVFR0, NS_PRIVILEGE_LEVEL_1, 0, 4, "A_SIMD registers", "fp", "MVFR0", "Support for Advanced SIMD register bank" },
      { 1, 1, MS_SYSREG_MVFR0, NS_PRIVILEGE_LEVEL_1, 4, 4, "Single-precision", "fp", "MVFR0", "Support for Floating-point Extension single-precision operations" },
      { 1, 2, MS_SYSREG_MVFR0, NS_PRIVILEGE_LEVEL_1, 8, 4, "Double-precision", "fp", "MVFR0", "Support for Floating-point Extension double-precision operations" },
      { 1, 3, MS_SYSREG_MVFR0, NS_PRIVILEGE_LEVEL_1, 12, 4, "VFP exception exception trapping", "fp", "MVFR0", "VFP support for exception handling" },
      { 1, 4, MS_SYSREG_MVFR0, NS_PRIVILEGE_LEVEL_1, 16, 4, "Divide", "fp", "MVFR0", "VFP divide support" },
      { 1, 5, MS_SYSREG_MVFR0, NS_PRIVILEGE_LEVEL_1, 20, 4, "Square root", "fp", "MVFR0", "VFP square root support" },
      { 1, 6, MS_SYSREG_MVFR0, NS_PRIVILEGE_LEVEL_1, 24, 4, "Short vectors", "fp", "MVFR0", "VFP short vector support" },
      { 1, 7, MS_SYSREG_MVFR0, NS_PRIVILEGE_LEVEL_1, 28, 4, "VFP rounding modes", "fp", "MVFR0", "VFP rounding modes support" },
      
      { 1, 0, MS_SYSREG_MVFR1, NS_PRIVILEGE_LEVEL_1, 0, 4, "FtZ mode", "fp", "MVFR1", "Flush-to-zero only" },
      { 1, 1, MS_SYSREG_MVFR1, NS_PRIVILEGE_LEVEL_1, 4, 4, "D_NaN", "fp", "MVFR1", "Default NaN only" },
      { 1, 2, MS_SYSREG_MVFR1, NS_PRIVILEGE_LEVEL_1, 8, 4, "A_SIMD load/store", "fp", "MVFR1", "A_SIMD Load/store implementation" },
      { 1, 3, MS_SYSREG_MVFR1, NS_PRIVILEGE_LEVEL_1, 12, 4, "A_SIMD integer", "fp", "MVFR1", "A_SIMD integer instructions" },
      { 1, 4, MS_SYSREG_MVFR1, NS_PRIVILEGE_LEVEL_1, 16, 4, "A_SIMD SPFP", "fp", "MVFR1", "A_SIMD single-precision floating point conversion" },
      { 1, 5, MS_SYSREG_MVFR1, NS_PRIVILEGE_LEVEL_1, 20, 4, "A_SIMD HPFP", "fp", "MVFR1", "A_SIMD half-precision floating point conversion" },
      { 1, 6, MS_SYSREG_MVFR1, NS_PRIVILEGE_LEVEL_1, 24, 4, "VFP HPFP", "fp", "MVFR1", "Floating point implements half-precision floating-point conversion" },
      { 1, 7, MS_SYSREG_MVFR1, NS_PRIVILEGE_LEVEL_1, 28, 4, "A_SIMD FMAC", "fp", "MVFR1", "FP or A_SIMD implements fused multiply accumulate" },
                  
      /* Security Extension Bitfields */
      { 1, 0, MS_SYSREG_SCR, S_ALL, 0, 1, "NS", "secext", "SCR", "Non Secure Bit" },
      { 1, 1, MS_SYSREG_SCR, S_ALL, 1, 1, "IRQ", "secext", "SCR", "IRQ Handler" },
      { 1, 2, MS_SYSREG_SCR, S_ALL, 2, 1, "FIQ", "secext", "SCR", "FIQ Handler" },
      { 1, 3, MS_SYSREG_SCR, S_ALL, 3, 1, "EA", "secext", "SCR", "External Abort Handler" },
      { 1, 4, MS_SYSREG_SCR, S_ALL, 4, 1, "FW", "secext", "SCR", "F bit writeable" },
      { 1, 5, MS_SYSREG_SCR, S_ALL, 5, 1, "AW", "secext", "SCR", "A bit writeable" },
      { 1, 6, MS_SYSREG_SCR, S_ALL, 6, 1, "nET", "secext", "SCR", "Not Early Termination" },
      { 1, 7, MS_SYSREG_SCR, S_ALL, 7, 1, "SCD", "secext", "SCR", "Secure Monitor Call disable" },
      { 1, 8, MS_SYSREG_SCR, S_ALL, 8, 1, "HCE", "secext", "SCR", "HYP call enable" },
      { 1, 9, MS_SYSREG_SCR, S_ALL, 9, 1, "SIF", "secext", "SCR", "Secure Instruction Fetch bit" },
      { 1, 10, MS_SYSREG_SCR, S_ALL, 10, 22, "Reserved", "secext", "SCR", "Reserved" },
      
      { 1, 0, MS_SYSREG_ISR, NS_PRIVILEGE_LEVEL_1, 0, 6, "Reserved", "secext", "ISR", "Reserved" },
      { 1, 1, MS_SYSREG_ISR, NS_PRIVILEGE_LEVEL_1, 6, 1, "F", "secext", "ISR", "FIQ pending bit" },
      { 1, 2, MS_SYSREG_ISR, NS_PRIVILEGE_LEVEL_1, 7, 1, "I", "secext", "ISR", "IRQ pending bit" },
      { 1, 3, MS_SYSREG_ISR, NS_PRIVILEGE_LEVEL_1, 8, 1, "A", "secext", "ISR", "External abort pending bit" },
      { 1, 4, MS_SYSREG_ISR, NS_PRIVILEGE_LEVEL_1, 9, 23, "Reserved", "secext", "ISR", "Reserved" },
      
      { 1, 0, MS_SYSREG_MVBAR, S_ALL, 0, 5, "Reserved", "secext", "MVBAR", "Reserved" },
      { 1, 1, MS_SYSREG_MVBAR, S_ALL, 5, 27, "Monitor_Vector_Base_Address", "secext", "MVBAR", "Monitor Vector Base Address" },
      
      { 1, 0, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 0, 1, "CP0", "secext", "NSACR", "Non-secure access to coprocessor 0 enable" },
      { 1, 1, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 1, 1, "CP1", "secext", "NSACR", "Non-secure access to coprocessor 1 enable" },
      { 1, 2, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 2, 1, "CP2", "secext", "NSACR", "Non-secure access to coprocessor 2 enable" },
      { 1, 3, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 3, 1, "CP3", "secext", "NSACR", "Non-secure access to coprocessor 3 enable" },
      { 1, 4, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 4, 1, "CP4", "secext", "NSACR", "Non-secure access to coprocessor 4 enable" },
      { 1, 5, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 5, 1, "CP5", "secext", "NSACR", "Non-secure access to coprocessor 5 enable" },
      { 1, 6, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 6, 1, "CP6", "secext", "NSACR", "Non-secure access to coprocessor 6 enable" },
      { 1, 7, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 7, 1, "CP7", "secext", "NSACR", "Non-secure access to coprocessor 7 enable" },
      { 1, 8, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 8, 1, "CP8", "secext", "NSACR", "Non-secure access to coprocessor 8 enable" },
      { 1, 9, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 9, 1, "CP9", "secext", "NSACR", "Non-secure access to coprocessor 9 enable" },
      { 1, 10, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 10, 1, "CP10", "secext", "NSACR", "Non-secure access to coprocessor 10 enable" },
      { 1, 11, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 11, 1, "CP11", "secext", "NSACR", "Non-secure access to coprocessor 11 enable" },
      { 1, 12, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 12, 1, "CP12", "secext", "NSACR", "Non-secure access to coprocessor 12 enable" },
      { 1, 13, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 13, 1, "CP13", "secext", "NSACR", "Non-secure access to coprocessor 13 enable" },
      { 1, 14, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 14, 1, "NSD32DIS", "secext", "NSACR", "Disable non-secure use of registers" },
      { 1, 15, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 15, 1, "NSASEDIS", "secext", "NSACR", "Disable non-secure advanced SIMD" },
      { 1, 16, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 16, 3, "Implementation Defined", "secext", "NSACR", "Implementation defined" },
      { 1, 17, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 19, 1, "RFR", "secext", "NSACR", "Reserve FIQ Resisters" },
      { 1, 18, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 20, 1, "NSTRCDIS", "secext", "NSACR", "Disable non-secure access to CP14 trace registers" },
      { 1, 19, MS_SYSREG_NSACR, NS_PRIVILEGE_LEVEL_1, 21, 11, "Reserved", "secext", "NSACR", "Reserved" },
      
      { 1, 0, MS_SYSREG_SDER, S_ALL, 0, 1, "SUIDEN", "secext", "SDER", "Secure user invasive debug" },
      { 1, 1, MS_SYSREG_SDER, S_ALL, 1, 1, "SUNIDEN", "secext", "SDER", "Secure user non-invasive debug" },
      { 1, 2, MS_SYSREG_SDER, S_ALL, 2, 30, "Reserved", "secext", "SDER", "Reserved" },
      
      { 1, 0, MS_SYSREG_VBAR, NS_PRIVILEGE_LEVEL_1, 0, 5, "Reserved", "secext", "VBAR", "Reserved" },
      { 1, 1, MS_SYSREG_VBAR, NS_PRIVILEGE_LEVEL_1, 5, 27, "Reserved", "secext", "VBAR", "Vector base address" },
      
      /* Debug Bitfields */
      { 1, 0, MS_SYSREG_DBGDIDR, NS_PRIVILEGE_LEVEL_1, 0, 4, "Revision", "debug", "DBGDIDR", "Revision" },
      { 1, 1, MS_SYSREG_DBGDIDR, NS_PRIVILEGE_LEVEL_1, 4, 4, "Variant", "debug", "DBGDIDR", "Variant" },
      { 1, 2, MS_SYSREG_DBGDIDR, NS_PRIVILEGE_LEVEL_1, 8, 4, "Reserved", "debug", "DBGDIDR", "Reserved" },
      { 1, 3, MS_SYSREG_DBGDIDR, NS_PRIVILEGE_LEVEL_1, 12, 1, "SE_imp", "debug", "DBGDIDR", "Security Extensions Implemented" },
      { 1, 4, MS_SYSREG_DBGDIDR, NS_PRIVILEGE_LEVEL_1, 13, 1, "PCSR_imp", "debug", "DBGDIDR", "Program Counter Sampling Register" },
      { 1, 5, MS_SYSREG_DBGDIDR, NS_PRIVILEGE_LEVEL_1, 14, 1, "nSUHD_imp", "debug", "DBGDIDR", "Secure User Halting Debug" },
      { 1, 6, MS_SYSREG_DBGDIDR, NS_PRIVILEGE_LEVEL_1, 15, 1, "DEVID_imp", "debug", "DBGDIDR", "Debug Device ID" },
      { 1, 7, MS_SYSREG_DBGDIDR, NS_PRIVILEGE_LEVEL_1, 16, 4, "Version", "debug", "DBGDIDR", "Version" },
      { 1, 8, MS_SYSREG_DBGDIDR, NS_PRIVILEGE_LEVEL_1, 20, 4, "CTX_CMP", "debug", "DBGDIDR", "Context Compare Breakpoints" },
      { 1, 9, MS_SYSREG_DBGDIDR, NS_PRIVILEGE_LEVEL_1, 24, 4, "BRP", "debug", "DBGDIDR", "Number of breakpoints" },
      { 1, 10, MS_SYSREG_DBGDIDR, NS_PRIVILEGE_LEVEL_1, 28, 4, "WRP", "debug", "DBGDIDR", "Number of Watchpoints Implemented" },
      
      { 1, 0, MS_SYSREG_DBGAUTHSTATUS, NS_PRIVILEGE_LEVEL_1, 0, 1, "NSE", "debug", "DBGAUTHSTATUS", "Non-secure invasive debug" },
      { 1, 1, MS_SYSREG_DBGAUTHSTATUS, NS_PRIVILEGE_LEVEL_1, 1, 1, "NSI", "debug", "DBGAUTHSTATUS", " Non-secure invasive debug features" },
      { 1, 2, MS_SYSREG_DBGAUTHSTATUS, NS_PRIVILEGE_LEVEL_1, 2, 1, "NSNE", "debug", "DBGAUTHSTATUS", "Non-secure non-invasive debug" },
      { 1, 3, MS_SYSREG_DBGAUTHSTATUS, NS_PRIVILEGE_LEVEL_1, 3, 1, "NSNI", "debug", "DBGAUTHSTATUS", "Non-secure non-invasive debug" },
      { 1, 4, MS_SYSREG_DBGAUTHSTATUS, NS_PRIVILEGE_LEVEL_1, 4, 1, "SE", "debug", "DBGAUTHSTATUS", "Secure invasive" },
      { 1, 5, MS_SYSREG_DBGAUTHSTATUS, NS_PRIVILEGE_LEVEL_1, 5, 1, "SI", "debug", "DBGAUTHSTATUS", "Secure invasive features" },
      { 1, 6, MS_SYSREG_DBGAUTHSTATUS, NS_PRIVILEGE_LEVEL_1, 6, 1, "SNE", "debug", "DBGAUTHSTATUS", "Secure non-invasive" },
      { 1, 7, MS_SYSREG_DBGAUTHSTATUS, NS_PRIVILEGE_LEVEL_1, 7, 1, "SNI", "debug", "DBGAUTHSTATUS", "Secure non-invasive features" },
      { 1, 8, MS_SYSREG_DBGAUTHSTATUS, NS_PRIVILEGE_LEVEL_1, 8, 24, "Reserved", "debug", "DBGAUTHSTATUS", "Reserved" },
      
      { 1, 0, MS_SYSREG_DBGDRAR, NS_PRIVILEGE_LEVEL_1, 0, 2, "Valid", "debug", "DBGDRAR", "ROM table address is valid" },
      { 1, 1, MS_SYSREG_DBGDRAR, NS_PRIVILEGE_LEVEL_1, 2, 10, "Reserved", "debug", "DBGDRAR", "Reserved" },
      { 1, 2, MS_SYSREG_DBGDRAR, NS_PRIVILEGE_LEVEL_1, 12, 28, "ROMADDR", "debug", "DBGDRAR", "Bits [39:12] of component physical address. [11:0] are zero." },
      { 1, 3, MS_SYSREG_DBGDRAR, NS_PRIVILEGE_LEVEL_1, 40, 24, "Reserved", "debug", "DBGDRAR", "Reserved" },
      
      { 1, 0, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 0, 1, "HALTED", "debug", "DBGDSCR", "Processor Halted" },
      { 1, 1, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 1, 1, "RESTARTED", "debug", "DBGDSCR", "Processor Restarted" },
      { 1, 2, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 2, 4, "MOE", "debug", "DBGDSCR", "Method of debug entry" },
      { 1, 3, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 6, 1, "SDABORT_L", "debug", "DBGDSCR", "Synchronous data abort exception when in debug state" },
      { 1, 4, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 7, 1, "ADABORT_L", "debug", "DBGDSCR", "Asynchronous data abort exception when in debug state" },
      { 1, 5, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 8, 1, "UND_L", "debug", "DBGDSCR", "Undefined instruction exception when in debug state" },
      { 1, 6, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 9, 1, "FS", "debug", "DBGDSCR", "Updated every data abort exception generated in debug state" },
      { 1, 7, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 10, 1, "DBGack", "debug", "DBGDSCR", "Force debug acknowledge" },
      { 1, 8, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 11, 1, "INTdis", "debug", "DBGDSCR", "Interrupts disable" },
      { 1, 9, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 12, 1, "UDCCDIS", "debug", "DBGDSCR", "User mode access to Debug Communications Channel (DBB) disable" },
      { 1, 10, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 13, 1, "ITRen", "debug", "DBGDSCR", "Enabled execution of ARM instructions through the DBGITR" },
      { 1, 11, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 14, 1, "HDBGen", "debug", "DBGDSCR", "Halting debug-mode enable" },
      { 1, 12, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 15, 1, "MDGBen", "debug", "DBGDSCR", "Monitor debug-mode enable" },
      { 1, 13, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 16, 1, "SPIDdis", "debug", "DBGDSCR", "Secure PL1 invasive debug disabled bit" },
      { 1, 14, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 17, 1, "SPNIdis", "debug", "DBGDSCR", "Secure PL1 non-invasive debug disabled bit" },
      { 1, 15, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 18, 1, "NS", "debug", "DBGDSCR", "Non-secure state status" },
      { 1, 16, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 19, 1, "ADAdiscard", "debug", "DBGDSCR", "Asynchronous aborts discarded" },
      { 1, 17, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 20, 2, "ExtDCCmode", "debug", "DBGDSCR", "External DCC access mode" },
      { 1, 18, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 22, 2, "Reserved", "debug", "DBGDSCR", "Reserved" },
      { 1, 19, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 24, 1, "InstrCompl_I", "debug", "DBGDSCR", "Latched copy of InstrCompl. Indicates completion of DBGITR" },
      { 1, 20, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 25, 1, "PipeAdv", "debug", "DBGDSCR", "Stick pipeline advance bit" },
      { 1, 21, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 26, 1, "TXfull_L", "debug", "DBGDSCR", "Controls behavior of processor on reads of DBGDTRTXext" },
      { 1, 22, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 27, 1, "RXfull_L", "debug", "DBGDSCR", "Controls behavior of processor on reads of DBGDTRRXext" },
      { 1, 23, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 28, 1, "Reserved", "debug", "DBGDSCR", "Reserved" }, 
      { 1, 24, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 29, 1, "TXfull", "debug", "DBGDSCR", "DBGDTRTX register full" },
      { 1, 25, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 30, 1, "RXfull", "debug", "DBGDSCR", "DBGDTRTX register full" },
      { 1, 26, MS_SYSREG_DBGDSCR, NS_PRIVILEGE_LEVEL_1, 31, 1, "Reserved", "debug", "DBGDSCR", "Reserved" },     
          
      /* Virtual Memory Bitfields */  
      { 1, 0, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 0, 2, "IR0", "virtmem", "NMRR", "Inner Cacheable property 0" },
      { 1, 1, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 2, 2, "IR1", "virtmem", "NMRR", "Inner Cacheable property 1" },
      { 1, 2, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 4, 2, "IR2", "virtmem", "NMRR", "Inner Cacheable property 2" },
      { 1, 3, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 6, 2, "IR3", "virtmem", "NMRR", "Inner Cacheable property 3" },
      { 1, 4, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 8, 2, "IR4", "virtmem", "NMRR", "Inner Cacheable property 4" },
      { 1, 5, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 10, 2, "IR5", "virtmem", "NMRR", "Inner Cacheable property 5" },
      { 1, 6, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 12, 2, "IR6", "virtmem", "NMRR", "Inner Cacheable property 6" },
      { 1, 7, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 14, 2, "IR7", "virtmem", "NMRR", "Inner Cacheable property 7" },
      { 1, 8, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 16, 2, "OR0", "virtmem", "NMRR", "Outer Cacheable property 0" },
      { 1, 9, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 18, 2, "OR1", "virtmem", "NMRR", "Outer Cacheable property 1" },
      { 1, 10, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 20, 2, "OR2", "virtmem", "NMRR", "Outer Cacheable property 2" },
      { 1, 11, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 22, 2, "OR3", "virtmem", "NMRR", "Outer Cacheable property 3" },
      { 1, 12, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 24, 2, "OR4", "virtmem", "NMRR", "Outer Cacheable property 4" },
      { 1, 13, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 26, 2, "OR5", "virtmem", "NMRR", "Outer Cacheable property 5" },
      { 1, 14, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 28, 2, "OR6", "virtmem", "NMRR", "Outer Cacheable property 6" },
      { 1, 15, MS_SYSREG_NMRR, NS_PRIVILEGE_LEVEL_1, 30, 2, "OR7", "virtmem", "NMRR", "Outer Cacheable property 7" },
  
      { 1, 0, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 0, 2, "TR0", "virtmem", "PRRR", "Memory TEX mapping 0" },
      { 1, 1, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 2, 2, "TR1", "virtmem", "PRRR", "Memory TEX mapping 1" },
      { 1, 2, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 4, 2, "TR2", "virtmem", "PRRR", "Memory TEX mapping 2" },
      { 1, 3, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 6, 2, "TR3", "virtmem", "PRRR", "Memory TEX mapping 3" },
      { 1, 4, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 8, 2, "TR4", "virtmem", "PRRR", "Memory TEX mapping 4" },
      { 1, 5, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 10, 2, "TR5", "virtmem", "PRRR", "Memory TEX mapping 5" },
      { 1, 6, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 12, 2, "TR6", "virtmem", "PRRR", "Memory TEX mapping 6" },
      { 1, 7, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 14, 2, "TR7", "virtmem", "PRRR", "Memory TEX mapping 7" },
      { 1, 8, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 16, 1, "DS0", "virtmem", "PRRR", "Mapping of S = 0 attribute for device memory" },
      { 1, 9, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 17, 1, "DS1", "virtmem", "PRRR", "Mapping of S = 1 attribute for device memory" },
      { 1, 10, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 18, 1, "NS0", "virtmem", "PRRR", "Mapping of S = 0 attribute for normal memory" },
      { 1, 11, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 19, 1, "NS1", "virtmem", "PRRR", "Mapping of S = 1 attribute for normal memory" },
      { 1, 12, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 20, 4, "Reserved", "virtmem", "PRRR", "Reserved" },
      { 1, 13, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 24, 1, "NOS0", "virtmem", "PRRR", "Outer Shareable property mapping 0" },
      { 1, 14, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 25, 1, "NOS1", "virtmem", "PRRR", "Outer Shareable property mapping 1" },
      { 1, 15, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 26, 1, "NOS2", "virtmem", "PRRR", "Outer Shareable property mapping 2" },
      { 1, 16, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 27, 1, "NOS3", "virtmem", "PRRR", "Outer Shareable property mapping 3" },
      { 1, 17, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 28, 1, "NOS4", "virtmem", "PRRR", "Outer Shareable property mapping 4" },
      { 1, 18, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 29, 1, "NOS5", "virtmem", "PRRR", "Outer Shareable property mapping 5" },
      { 1, 19, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 30, 1, "NOS6", "virtmem", "PRRR", "Outer Shareable property mapping 6" },
      { 1, 20, MS_SYSREG_PRRR, NS_PRIVILEGE_LEVEL_1, 31, 1, "NOS7", "virtmem", "PRRR", "Outer Shareable property mapping 7" },
      
      { 1, 0, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 0, 1, "M", "virtmem", "SCTLR", "MMU Enable" },
      { 1, 1, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 1, 1, "A", "virtmem", "SCTLR", "Alignment check enable" },
      { 1, 2, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 2, 1, "C", "virtmem", "SCTLR", "Cache enable" },
      { 1, 3, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 3, 2, "Reserved", "virtmem", "SCTLR", "Reserved" },
      { 1, 4, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 5, 1, "CP15BEN", "virtmem", "SCTLR", "CP15 barrier enable" },
      { 1, 5, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 6, 1, "Reserved", "virtmem", "SCTLR", "Reserved" },
      { 1, 6, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 7, 1, "B", "virtmem", "SCTLR", "Endianess" },
      { 1, 7, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 8, 2, "Reserved", "virtmem", "SCTLR", "Reserved" },
      { 1, 8, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 10, 1, "SW", "virtmem", "SCTLR", "SWP and SWPB enable" },
      { 1, 9, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 11, 1, "Z", "virtmem", "SCTLR", "Branch prediction enable" },
      { 1, 10, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 12, 1, "I", "virtmem", "SCTLR", "Instruction cache enable" },
      { 1, 11, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 13, 1, "V", "virtmem", "SCTLR", "Vectors bit" },
      { 1, 12, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 14, 1, "RR", "virtmem", "SCTLR", "Round Robin select" },
      { 1, 13, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 15, 1, "Reserved", "virtmem", "SCTLR", "Reserved" },
      { 1, 14, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 16, 1, "Reserved", "virtmem", "SCTLR", "Reserved" },
      { 1, 15, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 17, 1, "A", "virtmem", "SCTLR", "Hardware access flag enable" },
      { 1, 16, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 18, 1, "Reserved", "virtmem", "SCTLR", "Reserved" },
      { 1, 17, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 19, 1, "WXN", "virtmem", "SCTLR", "Write permission implies XN" },
      { 1, 18, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 20, 1, "UWXN", "virtmem", "SCTLR", "Unprivileged write permission implies PL1 XN" },
      { 1, 19, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 21, 1, "FI", "virtmem", "SCTLR", "Fast interrupts configuration enable" },
      { 1, 20, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 22, 1, "U", "virtmem", "SCTLR", "Alignment model" },
      { 1, 21, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 23, 1, "Reserved", "virtmem", "SCTLR", "Reserved" },
      { 1, 22, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 24, 1, "VE", "virtmem", "SCTLR", "Interrupt Vectors enable" },
      { 1, 23, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 25, 1, "EE", "virtmem", "SCTLR", "Exception Endianess" },
      { 1, 24, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 26, 1, "Reserved", "virtmem", "SCTLR", "Reserved" },
      { 1, 25, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 27, 1, "NMFI", "virtmem", "SCTLR", "Non-maskable FIQ support" },
      { 1, 26, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 28, 1, "TRE", "virtmem", "SCTLR", "TEX remap enable" },
      { 1, 27, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 29, 1, "AFE", "virtmem", "SCTLR", "Access flag enable" },
      { 1, 28, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 30, 1, "TE", "virtmem", "SCTLR", "Thumb Exception enable" },
      { 1, 29, MS_SYSREG_SCTLR, NS_PRIVILEGE_LEVEL_1, 31, 1, "Reserved", "virtmem", "SCTLR", "Reserved" },
      
      { 1, 0, MS_SYSREG_TTBCR, NS_PRIVILEGE_LEVEL_1, 0, 3, "N", "virtmem", "TTBCR", "Reserved" },
      { 1, 1, MS_SYSREG_TTBCR, NS_PRIVILEGE_LEVEL_1, 3, 1, "Reserved", "virtmem", "TTBCR", "Reserved" },
      { 1, 2, MS_SYSREG_TTBCR, NS_PRIVILEGE_LEVEL_1, 4, 1, "PD0", "virtmem", "TTBCR", "Reserved" },
      { 1, 3, MS_SYSREG_TTBCR, NS_PRIVILEGE_LEVEL_1, 5, 1, "PD1", "virtmem", "TTBCR", "Reserved" },
      { 1, 4, MS_SYSREG_TTBCR, NS_PRIVILEGE_LEVEL_1, 6, 25, "Reserved", "virtmem", "TTBCR", "Reserved" },
      { 1, 5, MS_SYSREG_TTBCR, NS_PRIVILEGE_LEVEL_1, 31, 1, "EAE", "virtmem", "TTBCR", "Reserved" },
      
      { 1, 0, MS_SYSREG_TTBR0, NS_PRIVILEGE_LEVEL_1, 0, 1 , "IRGN_1", "virtmem", "TTBR0", "Inner Cacheability attributes" },
      { 1, 1, MS_SYSREG_TTBR0, NS_PRIVILEGE_LEVEL_1, 1, 1 , "S", "virtmem", "TTBR0", "Shareable attribute" },
      { 1, 2, MS_SYSREG_TTBR0, NS_PRIVILEGE_LEVEL_1, 2, 1 , "Implementation Defined", "virtmem", "TTBR0", "Implementation Defined" },
      { 1, 3, MS_SYSREG_TTBR0, NS_PRIVILEGE_LEVEL_1, 3, 2 , "RGN", "virtmem", "TTBR0", "Outer Cacheability attributes" },
      { 1, 4, MS_SYSREG_TTBR0, NS_PRIVILEGE_LEVEL_1, 5, 1 , "NOS", "virtmem", "TTBR0", "Outer Shareable attributes" },
      { 1, 5, MS_SYSREG_TTBR0, NS_PRIVILEGE_LEVEL_1, 6, 1 , "IRGN_0", "virtmem", "TTBR0", "Inner Cacheability attributes" },
      { 1, 6, MS_SYSREG_TTBR0, NS_PRIVILEGE_LEVEL_1, 7, 25 , "TTB0A", "virtmem", "TTBR0", "Translation table base 0 address or Reserved" },
      
      { 1, 0, MS_SYSREG_TTBR0LPAE, NS_PRIVILEGE_LEVEL_1, 0, 64 , "Implementation Defined", "virtmem", "TTBR0", "Refer to TRM for register format" },
  
      { 1, 0, MS_SYSREG_TTBR1, NS_PRIVILEGE_LEVEL_1, 0, 1 , "IRGN_1", "virtmem", "TTBR1", "Inner Cacheability attributes" },
      { 1, 1, MS_SYSREG_TTBR1, NS_PRIVILEGE_LEVEL_1, 1, 1 , "S", "virtmem", "TTBR1", "Shareable attribute" },
      { 1, 2, MS_SYSREG_TTBR1, NS_PRIVILEGE_LEVEL_1, 2, 1 , "Implementation Defined", "virtmem", "TTBR1", "Implementation Defined" },
      { 1, 3, MS_SYSREG_TTBR1, NS_PRIVILEGE_LEVEL_1, 3, 2 , "RGN", "virtmem", "TTBR1", "Outer Cacheability attributes" },
      { 1, 4, MS_SYSREG_TTBR1, NS_PRIVILEGE_LEVEL_1, 5, 1 , "NOS", "virtmem", "TTBR1", "Outer Shareable attributes" },
      { 1, 5, MS_SYSREG_TTBR1, NS_PRIVILEGE_LEVEL_1, 6, 1 , "IRGN_0", "virtmem", "TTBR1", "Inner Cacheability attributes" },
      { 1, 6, MS_SYSREG_TTBR1, NS_PRIVILEGE_LEVEL_1, 7, 25 , "TTB1A", "virtmem", "TTBR1", "Translation table base 1 address or Reserved" },
      
      { 1, 0, MS_SYSREG_TTBR1LPAE, NS_PRIVILEGE_LEVEL_1, 0, 64 , "Implementation Defined", "virtmem", "TTBR1", "Refer to TRM for register format" },
  
      { 1, 1, MS_SYSREG_CONTEXTIDR, NS_PRIVILEGE_LEVEL_1, 0, 32, "PROCID", "virtmem", "CONTEXTIDR", "PROCID" },
      { 1, 2, MS_SYSREG_CONTEXTIDR, NS_PRIVILEGE_LEVEL_1, 0, 8, "ASID", "virtmem", "CONTEXTIDR", "ASID" },
      { 1, 3, MS_SYSREG_CONTEXTIDR, NS_PRIVILEGE_LEVEL_1, 8, 24, "PROCID", "virtmem", "CONTEXTIDR", "PROCID" }, 
      
      { 1, 0, MS_SYSREG_AMAIR0, NS_PRIVILEGE_LEVEL_1, 0, 32, "AMAIR0", "virtmem", "AMAIR0", "Implementation Defined" },   
      
      { 1, 0, MS_SYSREG_AMAIR1, NS_PRIVILEGE_LEVEL_1, 0, 32, "AMAIR1", "virtmem", "AMAIR1", "Implementation Defined" },   
      
      { 1, 0, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 0, 2, "D0", "virtmem", "DACR", "Domain 0 access permission" },
      { 1, 1, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 2, 2, "D1", "virtmem", "DACR", "Domain 1 access permission" },
      { 1, 2, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 4, 2, "D2", "virtmem", "DACR", "Domain 2 access permission" },
      { 1, 3, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 6, 2, "D3", "virtmem", "DACR", "Domain 3 access permission" },
      { 1, 4, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 8, 2, "D4", "virtmem", "DACR", "Domain 4 access permission" },
      { 1, 5, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 10, 2, "D5", "virtmem", "DACR", "Domain 5 access permission" },
      { 1, 6, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 12, 2, "D6", "virtmem", "DACR", "Domain 6 access permission" },
      { 1, 7, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 14, 2, "D7", "virtmem", "DACR", "Domain 7 access permission" },
      { 1, 8, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 16, 2, "D8", "virtmem", "DACR", "Domain 8 access permission" },
      { 1, 9, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 18, 2, "D9", "virtmem", "DACR", "Domain 9 ccess permission" },
      { 1, 10, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 20, 2, "D10", "virtmem", "DACR", "Domain 10 access permission" },
      { 1, 11, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 22, 2, "D11", "virtmem", "DACR", "Domain 11 access permission" },
      { 1, 12, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 24, 2, "D12", "virtmem", "DACR", "Domain 12 access permission" },
      { 1, 13, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 26, 2, "D13", "virtmem", "DACR", "Domain 13 access permission" },
      { 1, 14, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 28, 2, "D14", "virtmem", "DACR", "Domain 14 access permission" },
      { 1, 15, MS_SYSREG_DACR, NS_PRIVILEGE_LEVEL_1, 30, 2, "D15", "virtmem", "DACR", "Domain 15 access permission" },
      
      { 1, 0, MS_SYSREG_MAIR0, NS_PRIVILEGE_LEVEL_1, 0, 8, "Attr0", "virtmem", "MAIR0", "Memory attribute 0 encoding" },
      { 1, 1, MS_SYSREG_MAIR0, NS_PRIVILEGE_LEVEL_1, 8, 8, "Attr1", "virtmem", "MAIR0", "Memory attribute 1 encoding" },
      { 1, 2, MS_SYSREG_MAIR0, NS_PRIVILEGE_LEVEL_1, 16, 8, "Attr2", "virtmem", "MAIR0", "Memory attribute 2 encoding" },
      { 1, 3, MS_SYSREG_MAIR0, NS_PRIVILEGE_LEVEL_1, 24, 8, "Attr3", "virtmem", "MAIR0", "Memory attribute 3 encoding" },
      
      { 1, 0, MS_SYSREG_MAIR1, NS_PRIVILEGE_LEVEL_1, 0, 8, "Attr4", "virtmem", "MAIR1", "Memory attribute 4 encoding" },
      { 1, 1, MS_SYSREG_MAIR1, NS_PRIVILEGE_LEVEL_1, 8, 8, "Attr5", "virtmem", "MAIR1", "Memory attribute 5 encoding" },
      { 1, 2, MS_SYSREG_MAIR1, NS_PRIVILEGE_LEVEL_1, 16, 8, "Attr6", "virtmem", "MAIR1", "Memory attribute 6 encoding" },
      { 1, 3, MS_SYSREG_MAIR1, NS_PRIVILEGE_LEVEL_1, 24, 8, "Attr7", "virtmem", "MAIR1", "Memory attribute 7 encoding" },
      
      /* Performance Monitor Bitfields */ 
      { 1, 0, MS_SYSREG_PMCCNTR, NS_PRIVILEGE_LEVEL_1, 0, 32, "CCNT", "perfmon", "PMCCNTR", "Cycle count" },
      
      { 1, 0, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 0, 1, "0x00", "perfmon", "PMCEID0", "Software Increment" },
      { 1, 1, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 1, 1, "0x01", "perfmon", "PMCEID0", "Level 1 instruction cache refill" },
      { 1, 2, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 2, 1, "0x02", "perfmon", "PMCEID0", "Level 1 instruction TLB refill" },
      { 1, 3, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 3, 1, "0x03", "perfmon", "PMCEID0", "Level 1 data cache refill" },
      { 1, 4, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 4, 1, "0x04", "perfmon", "PMCEID0", "Level 1 data cache access" },
      { 1, 5, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 5, 1, "0x05", "perfmon", "PMCEID0", "Level 1 data TLB refill" },
      { 1, 6, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 6, 1, "0x06", "perfmon", "PMCEID0", "Load" },
      { 1, 7, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 7, 1, "0x07", "perfmon", "PMCEID0", "Store" },
      { 1, 8, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 8, 1, "0x08", "perfmon", "PMCEID0", "Instruction architecturally executed" },
      { 1, 9, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 9, 1, "0x09", "perfmon", "PMCEID0", "Exception taken" },
      { 1, 10, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 10, 1, "0x0A", "perfmon", "PMCEID0", "Exception return" },
      { 1, 11, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 11, 1, "0x0B", "perfmon", "PMCEID0", "Write to CONTEXTIDR" },
      { 1, 12, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 12, 1, "0x0C", "perfmon", "PMCEID0", "Software change of the PC" },
      { 1, 13, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 13, 1, "0x0D", "perfmon", "PMCEID0", "Immediate Branch" },
      { 1, 14, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 14, 1, "0x0E", "perfmon", "PMCEID0", "Procedure return" },
      { 1, 15, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 15, 1, "0x0F", "perfmon", "PMCEID0", "Unaligned load or store" },
      { 1, 16, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 16, 1, "0x10", "perfmon", "PMCEID0", "Speculative execution" },
      { 1, 17, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 17, 1, "0x11", "perfmon", "PMCEID0", "Cycle" },
      { 1, 18, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 18, 1, "0x12", "perfmon", "PMCEID0", "Predictable branch speculatively executed" },
      { 1, 19, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 19, 1, "0x13", "perfmon", "PMCEID0", "Data memory access" },
      { 1, 20, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 20, 1, "0x14", "perfmon", "PMCEID0", "Level 1 instruction cache access" },
      { 1, 21, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 21, 1, "0x15", "perfmon", "PMCEID0", "Level 1 data cache write-back" },
      { 1, 22, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 22, 1, "0x16", "perfmon", "PMCEID0", "Level 2 data cache access" },
      { 1, 23, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 23, 1, "0x17", "perfmon", "PMCEID0", "Level 2 data cache refill" },
      { 1, 24, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 24, 1, "0x18", "perfmon", "PMCEID0", "Level 2 data cache write-back" },
      { 1, 25, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 25, 1, "0x19", "perfmon", "PMCEID0", "Bus access" },
      { 1, 26, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 26, 1, "0x1A", "perfmon", "PMCEID0", "Local memory error" },
      { 1, 27, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 27, 1, "0x1B", "perfmon", "PMCEID0", "Instruction speculatively executed" },
      { 1, 28, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 28, 1, "0x1C", "perfmon", "PMCEID0", "Write to TTBR" },
      { 1, 29, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 29, 1, "0x1D", "perfmon", "PMCEID0", "Bus cycle" },
      { 1, 30, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 30, 1, "0x1E", "perfmon", "PMCEID0", "Reserved" },
      { 1, 31, MS_SYSREG_PMCEID0, NS_PRIVILEGE_LEVEL_1, 31, 1, "0x1F", "perfmon", "PMCEID0", "Reserved" },
      
      { 1, 0, MS_SYSREG_PMCEID1, NS_PRIVILEGE_LEVEL_1, 0, 32, "Implementation Defined", "perfmon", "PMCEID1", "Implementation Defined" },
      
      { 1, 0, MS_SYSREG_PMCNTENCLR, NS_PRIVILEGE_LEVEL_1, 0, 32, "Implementation Defined", "perfmon", "PMCNTENCLR", "Implementation Defined" },
      
      { 1, 0, MS_SYSREG_PMCNTENSET, NS_PRIVILEGE_LEVEL_1, 0, 32, "Implementation Defined", "perfmon", "PMCNTENSET", "Implementation Defined" },
      
      { 1, 0, MS_SYSREG_PMINTENSET, NS_PRIVILEGE_LEVEL_1, 0, 32, "Implementation Defined", "perfmon", "PMINTENSET", "Implementation Defined" },
      
      { 1, 0, MS_SYSREG_PMINTENCLR, NS_PRIVILEGE_LEVEL_1, 0, 32, "Implementation Defined", "perfmon", "PMINTENCLR", "Implementation Defined" },
      
      { 1, 0, MS_SYSREG_PMOVSR, NS_PRIVILEGE_LEVEL_1, 0, 32, "Implementation Defined", "perfmon", "PMOVSR", "Implementation Defined" },
      
      { 1, 0, MS_SYSREG_PMOVSSET, NS_PRIVILEGE_LEVEL_1, 0, 32, "Implementation Defined", "perfmon", "PMOVSSET", "Implementation Defined" },
          
      { 1, 0, MS_SYSREG_PMSELR, NS_PRIVILEGE_LEVEL_1, 0, 5, "SELR", "perfmon", "PMSELR", "Selects event counter" },
      { 1, 1, MS_SYSREG_PMSELR, NS_PRIVILEGE_LEVEL_1, 5, 27, "Reserved", "perfmon", "PMSELR", "Reserved" },
  
      { 1, 0, MS_SYSREG_PMSWINC, NS_PRIVILEGE_LEVEL_1, 0, 32, "Implementation Defined", "perfmon", "PMSWINC", "Implementation Defined" },
      
      { 1, 0, MS_SYSREG_PMUSERENR, NS_PRIVILEGE_LEVEL_1, 0, 1, "EN", "perfmon", "PMUSERENR", "User mode access enable bit" },
      { 1, 1, MS_SYSREG_PMUSERENR, NS_PRIVILEGE_LEVEL_1, 1, 31, "Reserved", "perfmon", "PMUSERENR", "Reserved" },
      
      { 1, 0, MS_SYSREG_PMXEVCNTR, NS_PRIVILEGE_LEVEL_1, 0, 32, "PMNx", "perfmon", "PMXEVCNTR", "Value of selected event counter" },
      
      { 1, 0, MS_SYSREG_PMXEVTYPER, NS_PRIVILEGE_LEVEL_1, 0, 8, "evtCount", "perfmon", "PMXEVTYPER", "Event to count" },
      { 1, 1, MS_SYSREG_PMXEVTYPER, NS_PRIVILEGE_LEVEL_1, 8, 19, "Reserved", "perfmon", "PMXEVTYPER", "Reserved" },
      { 1, 2, MS_SYSREG_PMXEVTYPER, NS_PRIVILEGE_LEVEL_1, 27, 1, "NSH", "perfmon", "PMXEVTYPER", "Non-secure PL2 enable" },
      { 1, 3, MS_SYSREG_PMXEVTYPER, NS_PRIVILEGE_LEVEL_1, 28, 1, "NSU", "perfmon", "PMXEVTYPER", "Non-secure unprivileged control bit" },
      { 1, 4, MS_SYSREG_PMXEVTYPER, NS_PRIVILEGE_LEVEL_1, 29, 1, "NSK", "perfmon", "PMXEVTYPER", "Non-secure PL1 control bit" },
      { 1, 5, MS_SYSREG_PMXEVTYPER, NS_PRIVILEGE_LEVEL_1, 30, 1, "U", "perfmon", "PMXEVTYPER", "Unprivileged execution filtering bit" },
      { 1, 6, MS_SYSREG_PMXEVTYPER, NS_PRIVILEGE_LEVEL_1, 31, 1, "P", "perfmon", "PMXEVTYPER", "Privileged execution filtering bit" },
      
      { 1, 0, MS_SYSREG_PMCR, NS_ALL, 0, 1, "E", "perfmon", "PMCR", "All counters enable" },
      { 1, 1, MS_SYSREG_PMCR, NS_ALL, 1, 1, "P", "perfmon", "PMCR", "Event counter reset" },
      { 1, 2, MS_SYSREG_PMCR, NS_ALL, 2, 1, "C", "perfmon", "PMCR", "Cycle counter reset" },
      { 1, 3, MS_SYSREG_PMCR, NS_ALL, 3, 1, "D", "perfmon", "PMCR", "Cycle counter clock divider" },
      { 1, 4, MS_SYSREG_PMCR, NS_ALL, 4, 1, "X", "perfmon", "PMCR", "Export enable" },
      { 1, 5, MS_SYSREG_PMCR, NS_ALL, 5, 1, "DP", "perfmon", "PMCR", "Disable PMCCNTR when event counting is prohibited" },
      { 1, 6, MS_SYSREG_PMCR, NS_ALL, 6, 5, "Rerverced", "perfmon", "PMCR", "Reserved" },
      { 1, 7, MS_SYSREG_PMCR, NS_ALL, 11, 5, "N", "perfmon", "PMCR", "Number of event counters" },
      { 1, 8, MS_SYSREG_PMCR, NS_ALL, 16, 8, "IDCODE", "perfmon", "PMCR", "Identification Code" },
      { 1, 9, MS_SYSREG_PMCR, NS_ALL, 24, 8, "Implementation Defined", "perfmon", "PMCR", "Implementer Code" },
      
      /* "other" handling bitfields */
      { 1, 0, MS_SYSREG_ACTLR, NS_PRIVILEGE_LEVEL_1, 0, 32, "Implementation Defined", "other", "ACTLR", "Implementation Defined" },
      
      { 1, 0, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 0, 2, "CP0", "other", "CPACR", "Coprocessor 0" },
      { 1, 1, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 2, 2, "CP1", "other", "CPACR", "Coprocessor 1" },
      { 1, 2, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 4, 2, "CP2", "other", "CPACR", "Coprocessor 2" },
      { 1, 3, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 6, 2, "CP3", "other", "CPACR", "Coprocessor 3" },
      { 1, 4, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 8, 2, "CP4", "other", "CPACR", "Coprocessor 4" },
      { 1, 5, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 10, 2, "CP5", "other", "CPACR", "Coprocessor 5" },
      { 1, 6, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 12, 2, "CP6", "other", "CPACR", "Coprocessor 6" },
      { 1, 7, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 14, 2, "CP7", "other", "CPACR", "Coprocessor 7" },
      { 1, 8, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 16, 2, "CP8", "other", "CPACR", "Coprocessor 8" },
      { 1, 9, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 18, 2, "CP9", "other", "CPACR", "Coprocessor 9" },
      { 1, 10, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 20, 2, "CP10", "other", "CPACR", "Coprocessor 10" },
      { 1, 11, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 22, 2, "CP11", "other", "CPACR", "Coprocessor 11" },
      { 1, 12, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 24, 2, "CP12", "other", "CPACR", "Coprocessor 12" },
      { 1, 13, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 26, 2, "CP13", "other", "CPACR", "Coprocessor 13" },
      { 1, 14, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 28, 1, "TRCDIS", "other", "CPACR", "Disable CP14 access to trace registers" },
      { 1, 15, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 29, 1, "Reserved", "other", "CPACR", "Reserved" },
      { 1, 16, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 30, 1, "D32DIS", "other", "CPACR", "Disable use of D16-D32 of FP Extension register file" },
      { 1, 17, MS_SYSREG_CPACR, NS_PRIVILEGE_LEVEL_1, 31, 1, "ASEDIS", "other", "CPACR", "Disable Advanced SIMD functionality" },
      
      { 1, 0, MS_SYSREG_FCSEIDR, NS_PRIVILEGE_LEVEL_1, 0, 25, "Reserved", "other", "FCSEIDR", "Reserved" },
      { 1, 1, MS_SYSREG_FCSEIDR, NS_PRIVILEGE_LEVEL_1, 25, 8, "PID", "other", "FCSEIDR", "Current Process ID for FCSE" },   
          
      /* Fault handling bitfields */  
      { 1, 0, MS_SYSREG_IFAR, NS_PRIVILEGE_LEVEL_1, 0, 32, "VA", "fault", "IFAR", "VA of faulting address of synchronous Prefetch Abort exception" },
      
      { 1, 0, MS_SYSREG_IFSR, NS_PRIVILEGE_LEVEL_1, 0, 4, "FS_3_0", "fault", "IFSR", "Fault status bit" },
      { 1, 1, MS_SYSREG_IFSR, NS_PRIVILEGE_LEVEL_1, 4, 5, "Reserved", "fault", "IFSR", "Reserved" },
      { 1, 2, MS_SYSREG_IFSR, NS_PRIVILEGE_LEVEL_1, 9, 1, "LPAE", "fault", "IFSR", "Descriptor table format on exception" },
      { 1, 3, MS_SYSREG_IFSR, NS_PRIVILEGE_LEVEL_1, 10, 1, "FS_4", "fault", "IFSR", "Fault status bit" },
      { 1, 4, MS_SYSREG_IFSR, NS_PRIVILEGE_LEVEL_1, 11, 1, "Reserved", "fault", "IFSR", "Reserved" },
      { 1, 5, MS_SYSREG_IFSR, NS_PRIVILEGE_LEVEL_1, 12, 1, "ExT", "fault", "IFSR", "External abort type" },
      { 1, 6, MS_SYSREG_IFSR, NS_PRIVILEGE_LEVEL_1, 13, 19, "Reserved", "fault", "IFSR", "Reserved" },
      
      { 1, 0, MS_SYSREG_ADFSR, NS_PRIVILEGE_LEVEL_1, 0, 32, "Implementation Defined", "fault", "ADFSR", "Implementation Defined" },
      
      { 1, 0, MS_SYSREG_AIFSR, NS_PRIVILEGE_LEVEL_1, 0, 32, "Implementation Defined", "fault", "AIFSR", "Implementation Defined" },
  
      { 1, 0, MS_SYSREG_DFAR, NS_PRIVILEGE_LEVEL_1, 0, 32, "VA", "fault", "DFAR", "VA of faulting address of synchronous Data Abort exception" },
      
      { 1, 0, MS_SYSREG_DFSR, NS_PRIVILEGE_LEVEL_1, 0, 4, "FS_3_0", "fault", "DFSR", "Fault status bit" },
      { 1, 1, MS_SYSREG_DFSR, NS_PRIVILEGE_LEVEL_1, 4, 4, "Domain", "fault", "DFSR", "The domain of the fault address" },
      { 1, 2, MS_SYSREG_DFSR, NS_PRIVILEGE_LEVEL_1, 8, 1, "Reserved", "fault", "DFSR", "Reserved" },
      { 1, 3, MS_SYSREG_DFSR, NS_PRIVILEGE_LEVEL_1, 9, 1, "LPAE", "fault", "DFSR", "Indicates short-descriptor table format on exception" },
      { 1, 4, MS_SYSREG_DFSR, NS_PRIVILEGE_LEVEL_1, 10, 1, "FS_4", "fault", "DFSR", "Fault status bit" },
      { 1, 5, MS_SYSREG_DFSR, NS_PRIVILEGE_LEVEL_1, 11, 1, "WnR", "fault", "DFSR", "Abort caused by read or write" },
      { 1, 6, MS_SYSREG_DFSR, NS_PRIVILEGE_LEVEL_1, 12, 1, "ExT", "fault", "DFSR", "External abort type" },
      { 1, 7, MS_SYSREG_DFSR, NS_PRIVILEGE_LEVEL_1, 13, 1, "CM", "fault", "DFSR", "Cache maintenance fault" },
      { 1, 8, MS_SYSREG_DFSR, NS_PRIVILEGE_LEVEL_1, 14, 18, "Reserved", "fault", "DFSR", "Reserved" },
      
      /* Jazelle */
      { 1, 0, MS_SYSREG_JIDR, NS_PRIVILEGE_LEVEL_1, 0, 12, "ImplementationdDefined", "jazelle", "JIDR", "Subarchitecture defined" },
      { 1, 1, MS_SYSREG_JIDR, NS_PRIVILEGE_LEVEL_1, 12, 8, "Subarchitecture", "jazelle", "JIDR", "Subarchitecture code" },
      { 1, 2, MS_SYSREG_JIDR, NS_PRIVILEGE_LEVEL_1, 20, 8, "Implementer", "jazelle", "JIDR", "Implementer code" },
      { 1, 3, MS_SYSREG_JIDR, NS_PRIVILEGE_LEVEL_1, 28, 4, "Architecture", "jazelle", "JIDR", "Architecture code" },
      
      { 1, 0, MS_SYSREG_JMCR, NS_PRIVILEGE_LEVEL_1, 0, 1, "JE", "jazelle", "JMCR", "Jazelle extensions enable" },
      { 1, 1, MS_SYSREG_JMCR, NS_PRIVILEGE_LEVEL_1, 1, 31, "Implementation defined", "jazelle", "JMCR", "Implementation defined" },
  
      { 1, 0, MS_SYSREG_JOSCR, NS_PRIVILEGE_LEVEL_1, 0, 1, "CD", "jazelle", "JOSCR", "Disable user mode access to JIDR and configuration registers" },
      { 1, 1, MS_SYSREG_JOSCR, NS_PRIVILEGE_LEVEL_1, 1, 1, "CV", "jazelle", "JOSCR", "Instruct EJVM to rewrite configuration in registers" },
      { 1, 2, MS_SYSREG_JOSCR, NS_PRIVILEGE_LEVEL_1, 2, 30, "Reserved", "jazelle", "JOSCR", "Reserved" },
      
      /* Thumb */
      { 1, 0, MS_SYSREG_TEECR, NS_ALL, 0, 1, "XED", "thumb", "TEECR", "Unprivileged Execution Environment Disable" },
      { 1, 1, MS_SYSREG_TEECR, NS_ALL, 1, 31, "Reserved", "thumb", "TEECR", "Reserved" },
      
      { 1, 0, MS_SYSREG_TEEHBR, NS_ALL, 0, 2, "Reserved", "thumb", "TEEHBR", "Reserved" },
      { 1, 1, MS_SYSREG_TEEHBR, NS_ALL, 2, 30, "HandlerBase", "thumb", "TEEHBR", "Address of ThumbEE handlers" },
      
      /* Misc */
      { 1, 0, MS_SYSREG_TPIDRPRW, NS_PRIVILEGE_LEVEL_1, 0, 32, "Implementation Defined", "misc", "TPIDRPRW", "PL1 Thread ID Storage" },
      
      { 1, 0, MS_SYSREG_TPIDRURO, NS_PRIVILEGE_LEVEL_0, 0, 32, "Implementation Defined", "misc", "TPIDRURO", "PL0 Thread ID Storage" },
      
      { 1, 0, MS_SYSREG_TPIDRURW, ALL_NS_S, 0, 32, "Implementation Defined", "misc", "TPIDRURW", "PL0 Thread ID Storage" },
      
      /* Address Translation */
      { 1, 0, MS_SYSREG_PAR, NS_PRIVILEGE_LEVEL_1, 0, 1, "F", "addrtrans", "PAR", "Conversion status" },
      { 1, 1, MS_SYSREG_PAR, NS_PRIVILEGE_LEVEL_1, 1, 1, "SS", "addrtrans", "PAR", "Result is a supersection" },
      { 1, 2, MS_SYSREG_PAR, NS_PRIVILEGE_LEVEL_1, 2, 1, "Outer_1_0", "addrtrans", "PAR", "Outer memory attributes" },
      { 1, 3, MS_SYSREG_PAR, NS_PRIVILEGE_LEVEL_1, 4, 3, "Inner_2_0", "addrtrans", "PAR", "Inner memory attributes" },
      { 1, 4, MS_SYSREG_PAR, NS_PRIVILEGE_LEVEL_1, 7, 1, "Shareable attribute", "addrtrans", "PAR", "Physical memory is shareable" },
      { 1, 5, MS_SYSREG_PAR, NS_PRIVILEGE_LEVEL_1, 8, 1, "Implementation Defined", "addrtrans", "PAR", "Implementation Defined" },
      { 1, 6, MS_SYSREG_PAR, NS_PRIVILEGE_LEVEL_1, 9, 1, "Non-secure", "addrtrans", "PAR", "NS bit from secure state" },
      { 1, 7, MS_SYSREG_PAR, NS_PRIVILEGE_LEVEL_1, 10, 1, "NOS", "addrtrans", "PAR", "Not outer shareable bit" },
      { 1, 8, MS_SYSREG_PAR, NS_PRIVILEGE_LEVEL_1, 11, 1, "LPAE", "addrtrans", "PAR", "Implementation includes LPAE" },
      { 1, 9, MS_SYSREG_PAR, NS_PRIVILEGE_LEVEL_1, 12, 20, "PA", "addrtrans", "PAR", "Physical address" },
      
      /* Program Status Register */
      { 1, 0, MS_SYSREG_APSR, NS_PRIVILEGE_LEVEL_0 | NS_PRIVILEGE_LEVEL_1, 0, 16, "Reserved", "psr", "APSR", "Reserved" },
      { 1, 1, MS_SYSREG_APSR, NS_PRIVILEGE_LEVEL_0 | NS_PRIVILEGE_LEVEL_1, 16, 4, "GE", "psr", "APSR", "Greater than or equal to" },
      { 1, 2, MS_SYSREG_APSR, NS_PRIVILEGE_LEVEL_0 | NS_PRIVILEGE_LEVEL_1, 20, 4, "Reserved", "psr", "APSR", "Reserved" },
      { 1, 3, MS_SYSREG_APSR, NS_PRIVILEGE_LEVEL_0 | NS_PRIVILEGE_LEVEL_1, 24, 3, "Reserved", "psr", "APSR", "Reserved" },
      { 1, 4, MS_SYSREG_APSR, NS_PRIVILEGE_LEVEL_0 | NS_PRIVILEGE_LEVEL_1, 27, 1, "Q", "psr", "APSR", "Overflow or saturation" },
      { 1, 5, MS_SYSREG_APSR, NS_PRIVILEGE_LEVEL_0 | NS_PRIVILEGE_LEVEL_1, 28, 1, "V", "psr", "APSR", "Overflow condition" },
      { 1, 6, MS_SYSREG_APSR, NS_PRIVILEGE_LEVEL_0 | NS_PRIVILEGE_LEVEL_1, 29, 1, "C", "psr", "APSR", "Carry condition" },
      { 1, 7, MS_SYSREG_APSR, NS_PRIVILEGE_LEVEL_0 | NS_PRIVILEGE_LEVEL_1, 30, 1, "Z", "psr", "APSR", "Zero condition" },
      { 1, 8, MS_SYSREG_APSR, NS_PRIVILEGE_LEVEL_0 | NS_PRIVILEGE_LEVEL_1, 31, 1, "N", "psr", "APSR", "Negative condition" },
      
      { 1, 0, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_1, 0, 5, "M", "psr", "CPSR", "Current mode of processor" },
      { 1, 1, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_1, 5, 1, "T", "psr", "CPSR", "Thumb execution state" },
      { 1, 2, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_1, 6, 1, "F", "psr", "CPSR", "FIQ mask" },
      { 1, 3, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_1, 7, 1, "I", "psr", "CPSR", "IRQ mask" },
      { 1, 4, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_1, 8, 1, "A", "psr", "CPSR", "Asynchronous abort mask" },
      { 1, 5, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_1, 9, 1, "E", "psr", "CPSR", "Endianess" },
      { 1, 6, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_1, 10, 6, "IT", "psr", "CPSR", "If-then execution state [7:2]" },
      { 1, 7, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_0, 16, 4, "GE", "psr", "CPSR", "Greater than or equal to" },
      { 1, 8, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_0, 20, 4, "Reserved", "psr", "CPSR", "Reserved" },
      { 1, 9, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_0, 24, 1, "J", "psr", "CPSR", "Jazelle bit" },
      { 1, 10, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_1, 25, 2, "IT", "psr", "CPSR", "If-then execution state [1:0]" },
      { 1, 11, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_0, 27, 1, "Q", "psr", "CPSR", "Cumulative saturation bit" },
      { 1, 12, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_0, 28, 1, "V", "psr", "CPSR", "Overflow condition" },
      { 1, 13, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_0, 29, 1, "C", "psr", "CPSR", "Carry condition" },
      { 1, 14, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_0, 30, 1, "Z", "psr", "CPSR", "Zero condition" },
      { 1, 15, MS_SYSREG_CPSR, NS_PRIVILEGE_LEVEL_0, 31, 1, "N", "psr", "CPSR", "Negative condition" },
  };
  
  int
  return_bitfield_armv7a_size(void)
  {
      return (sizeof(bitfield_armv7a_table) / sizeof(bitfield_info));
  }
  