text: /**********
  Copyright (c) 2018, Xilinx, Inc.
  All rights reserved.
  
  Redistribution and use in source and binary forms, with or without modification,
  are permitted provided that the following conditions are met:
  
  1. Redistributions of source code must retain the above copyright notice,
  this list of conditions and the following disclaimer.
  
  2. Redistributions in binary form must reproduce the above copyright notice,
  this list of conditions and the following disclaimer in the documentation
  and/or other materials provided with the distribution.
  
  3. Neither the name of the copyright holder nor the names of its contributors
  may be used to endorse or promote products derived from this software
  without specific prior written permission.
  
  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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  **********/
  
  /*
    Performs a simple vector addition on the input and the input
    is provided as a stream of data.
    See host code for additional details about this example
  */
  
  #include <stdlib.h>
  
  #define BUFFER_SIZE 256
  #define DATA_SIZE 1024
  
  //TRIPCOUNT indentifier
  const unsigned int c_len = DATA_SIZE/BUFFER_SIZE;
  const unsigned int c_size = BUFFER_SIZE;
  
  extern "C" {
  void vec_add(int* c,
                  int* a,
                  int* b,
                  int* result_size,
                  size_t elements)
  {
  #pragma HLS INTERFACE m_axi port=c offset=slave bundle=gmem
  #pragma HLS INTERFACE m_axi port=a offset=slave bundle=gmem
  #pragma HLS INTERFACE m_axi port=b offset=slave bundle=gmem
  #pragma HLS INTERFACE m_axi port=result_size offset=slave bundle=gmem
  
  #pragma HLS INTERFACE s_axilite port=c bundle=control
  #pragma HLS INTERFACE s_axilite port=a bundle=control
  #pragma HLS INTERFACE s_axilite port=b bundle=control
  #pragma HLS INTERFACE s_axilite port=result_size bundle=control
  #pragma HLS INTERFACE s_axilite port=elements bundle=control
  #pragma HLS INTERFACE s_axilite port=return bundle=control
  
      int arrayA[BUFFER_SIZE];
      int arrayB[BUFFER_SIZE];
      int k = 0;
      for (int i = 0 ; i < elements ; i += BUFFER_SIZE) {
      #pragma HLS LOOP_TRIPCOUNT min=c_len max=c_len
          int size = BUFFER_SIZE;
          if (i + size > elements) size = elements - i;
  
          readA: for (int j = 0 ; j < size ; j++) {
          #pragma HLS PIPELINE II=1
          #pragma HLS LOOP_TRIPCOUNT min=c_size max=c_size
                  arrayA[j] = a[i+j]; 
          }
  
          readB: for (int j = 0 ; j < size ; j++) {
          #pragma HLS PIPELINE II=1
          #pragma HLS LOOP_TRIPCOUNT min=c_size max=c_size
                  arrayB[j] = b[i+j]; 
          }
  
          writeC: for (int j = 0 ; j < (size-1)/2 + 1 ; j++) {
          #pragma HLS PIPELINE II=1
          #pragma HLS LOOP_TRIPCOUNT min=c_size max=c_size
                  c[k+j] = arrayA[2*j] + arrayB[2*j];
          }
          
          k = k + (size-1)/2 + 1;
      }
      result_size[0] = k;  
  }
  }
  