text: // ==============================================================
  // RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
  // Version: 2017.2
  // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
  // 
  // ===========================================================
  
  #ifndef _call_Loop_LB2D_buf_p_HH_
  #define _call_Loop_LB2D_buf_p_HH_
  
  #include "systemc.h"
  #include "AESL_pkg.h"
  
  #include "call_Loop_LB2D_bubkb.h"
  
  namespace ap_rtl {
  
  struct call_Loop_LB2D_buf_p : public sc_module {
      // Port declarations 16
      sc_in_clk ap_clk;
      sc_in< sc_logic > ap_rst;
      sc_in< sc_logic > ap_start;
      sc_in< sc_logic > start_full_n;
      sc_out< sc_logic > ap_ready;
      sc_out< sc_logic > ap_done;
      sc_in< sc_logic > ap_continue;
      sc_out< sc_logic > ap_idle;
      sc_out< sc_logic > start_out;
      sc_out< sc_logic > start_write;
      sc_in< sc_lv<8> > in_stream_V_value_V_dout;
      sc_in< sc_logic > in_stream_V_value_V_empty_n;
      sc_out< sc_logic > in_stream_V_value_V_read;
      sc_out< sc_lv<24> > slice_stream_V_value_V_din;
      sc_in< sc_logic > slice_stream_V_value_V_full_n;
      sc_out< sc_logic > slice_stream_V_value_V_write;
  
  
      // Module declarations
      call_Loop_LB2D_buf_p(sc_module_name name);
      SC_HAS_PROCESS(call_Loop_LB2D_buf_p);
  
      ~call_Loop_LB2D_buf_p();
  
      sc_trace_file* mVcdFile;
  
      call_Loop_LB2D_bubkb* buffer_0_value_V_U;
      call_Loop_LB2D_bubkb* buffer_1_value_V_U;
      sc_signal< sc_logic > real_start;
      sc_signal< sc_logic > real_start_status_reg;
      sc_signal< sc_logic > internal_ap_ready;
      sc_signal< sc_logic > ap_done_reg;
      sc_signal< sc_lv<4> > ap_CS_fsm;
      sc_signal< sc_logic > ap_CS_fsm_state1;
      sc_signal< sc_logic > start_once_reg;
      sc_signal< sc_logic > start_control_reg;
      sc_signal< sc_logic > in_stream_V_value_V_blk_n;
      sc_signal< sc_logic > ap_enable_reg_pp0_iter2;
      sc_signal< bool > ap_block_pp0_stage0_flag00000000;
      sc_signal< sc_lv<1> > tmp_1_reg_291;
      sc_signal< sc_lv<1> > ap_reg_pp0_iter1_tmp_1_reg_291;
      sc_signal< sc_logic > slice_stream_V_value_V_blk_n;
      sc_signal< sc_lv<1> > icmp_reg_287;
      sc_signal< sc_lv<64> > write_idx_1_1_reg_142;
      sc_signal< sc_lv<3> > col_reg_153;
      sc_signal< sc_lv<1> > tmp_fu_164_p2;
      sc_signal< sc_logic > ap_CS_fsm_state2;
      sc_signal< sc_lv<3> > row_1_fu_170_p2;
      sc_signal< sc_lv<3> > row_1_reg_282;
      sc_signal< sc_lv<1> > icmp_fu_186_p2;
      sc_signal< sc_lv<1> > tmp_1_fu_192_p2;
      sc_signal< sc_logic > ap_CS_fsm_pp0_stage0;
      sc_signal< bool > ap_block_state3_pp0_stage0_iter0;
      sc_signal< bool > ap_block_state4_pp0_stage0_iter1;
      sc_signal< bool > ap_block_state5_pp0_stage0_iter2;
      sc_signal< bool > ap_block_pp0_stage0_flag00011001;
      sc_signal< sc_lv<3> > col_1_fu_198_p2;
      sc_signal< sc_logic > ap_enable_reg_pp0_iter0;
      sc_signal< sc_lv<1> > icmp1_fu_220_p2;
      sc_signal< sc_lv<1> > icmp1_reg_300;
      sc_signal< sc_lv<2> > buffer_0_value_V_ad_reg_305;
      sc_signal< sc_lv<2> > ap_reg_pp0_iter1_buffer_0_value_V_ad_reg_305;
      sc_signal< sc_lv<2> > buffer_1_value_V_ad_reg_311;
      sc_signal< sc_lv<2> > ap_reg_pp0_iter1_buffer_1_value_V_ad_reg_311;
      sc_signal< sc_lv<64> > p_write_idx_1_1_fu_232_p3;
      sc_signal< sc_logic > ap_enable_reg_pp0_iter1;
      sc_signal< sc_lv<8> > p_Val2_2_0_phi_fu_243_p3;
      sc_signal< sc_lv<8> > p_Val2_2_0_phi_reg_322;
      sc_signal< sc_lv<8> > p_Val2_2_1_phi_fu_251_p3;
      sc_signal< sc_lv<8> > p_Val2_2_1_phi_reg_327;
      sc_signal< sc_lv<1> > tmp_9_fu_259_p1;
      sc_signal< sc_lv<1> > tmp_9_reg_332;
      sc_signal< sc_lv<64> > write_idx_1_2_fu_272_p2;
      sc_signal< sc_logic > ap_CS_fsm_state6;
      sc_signal< bool > ap_block_pp0_stage0_flag00011011;
      sc_signal< sc_logic > ap_condition_pp0_exit_iter0_state3;
      sc_signal< sc_lv<2> > buffer_0_value_V_address0;
      sc_signal< sc_logic > buffer_0_value_V_ce0;
      sc_signal< sc_lv<8> > buffer_0_value_V_q0;
      sc_signal< sc_lv<2> > buffer_0_value_V_address1;
      sc_signal< sc_logic > buffer_0_value_V_ce1;
      sc_signal< sc_logic > buffer_0_value_V_we1;
      sc_signal< sc_lv<2> > buffer_1_value_V_address0;
      sc_signal< sc_logic > buffer_1_value_V_ce0;
      sc_signal< sc_lv<8> > buffer_1_value_V_q0;
      sc_signal< sc_logic > buffer_1_value_V_ce1;
      sc_signal< sc_logic > buffer_1_value_V_we1;
      sc_signal< sc_lv<64> > write_idx_1_reg_119;
      sc_signal< bool > ap_block_state1;
      sc_signal< sc_lv<3> > row_reg_131;
      sc_signal< sc_lv<64> > write_idx_1_1_phi_fu_145_p4;
      sc_signal< sc_lv<64> > col_cast_fu_204_p1;
      sc_signal< bool > ap_block_pp0_stage0_flag00001001;
      sc_signal< sc_lv<2> > tmp_6_fu_176_p4;
      sc_signal< sc_lv<63> > tmp_7_fu_210_p4;
      sc_signal< sc_lv<64> > write_idx_1_3_fu_226_p2;
      sc_signal< sc_lv<1> > tmp_8_fu_239_p1;
      sc_signal< sc_lv<4> > ap_NS_fsm;
      sc_signal< bool > ap_block_pp0;
      sc_signal< bool > ap_enable_operation_55;
      sc_signal< bool > ap_enable_state5_pp0_iter2_stage0;
      sc_signal< bool > ap_enable_operation_35;
      sc_signal< bool > ap_enable_state3_pp0_iter0_stage0;
      sc_signal< bool > ap_enable_operation_41;
      sc_signal< bool > ap_enable_state4_pp0_iter1_stage0;
      sc_signal< sc_logic > ap_idle_pp0;
      sc_signal< sc_logic > ap_enable_pp0;
      static const sc_logic ap_const_logic_1;
      static const sc_logic ap_const_logic_0;
      static const sc_lv<4> ap_ST_fsm_state1;
      static const sc_lv<4> ap_ST_fsm_state2;
      static const sc_lv<4> ap_ST_fsm_pp0_stage0;
      static const sc_lv<4> ap_ST_fsm_state6;
      static const bool ap_const_boolean_1;
      static const sc_lv<32> ap_const_lv32_0;
      static const bool ap_const_boolean_0;
      static const sc_lv<1> ap_const_lv1_0;
      static const sc_lv<32> ap_const_lv32_1;
      static const sc_lv<32> ap_const_lv32_2;
      static const sc_lv<32> ap_const_lv32_3;
      static const sc_lv<1> ap_const_lv1_1;
      static const sc_lv<64> ap_const_lv64_0;
      static const sc_lv<3> ap_const_lv3_0;
      static const sc_lv<3> ap_const_lv3_4;
      static const sc_lv<3> ap_const_lv3_1;
      static const sc_lv<2> ap_const_lv2_0;
      static const sc_lv<32> ap_const_lv32_3F;
      static const sc_lv<63> ap_const_lv63_0;
      static const sc_lv<64> ap_const_lv64_FFFFFFFFFFFFFFFE;
      static const sc_lv<64> ap_const_lv64_1;
      // Thread declarations
      void thread_ap_clk_no_reset_();
      void thread_ap_CS_fsm_pp0_stage0();
      void thread_ap_CS_fsm_state1();
      void thread_ap_CS_fsm_state2();
      void thread_ap_CS_fsm_state6();
      void thread_ap_block_pp0();
      void thread_ap_block_pp0_stage0_flag00000000();
      void thread_ap_block_pp0_stage0_flag00001001();
      void thread_ap_block_pp0_stage0_flag00011001();
      void thread_ap_block_pp0_stage0_flag00011011();
      void thread_ap_block_state1();
      void thread_ap_block_state3_pp0_stage0_iter0();
      void thread_ap_block_state4_pp0_stage0_iter1();
      void thread_ap_block_state5_pp0_stage0_iter2();
      void thread_ap_condition_pp0_exit_iter0_state3();
      void thread_ap_done();
      void thread_ap_enable_operation_35();
      void thread_ap_enable_operation_41();
      void thread_ap_enable_operation_55();
      void thread_ap_enable_pp0();
      void thread_ap_enable_state3_pp0_iter0_stage0();
      void thread_ap_enable_state4_pp0_iter1_stage0();
      void thread_ap_enable_state5_pp0_iter2_stage0();
      void thread_ap_idle();
      void thread_ap_idle_pp0();
      void thread_ap_ready();
      void thread_buffer_0_value_V_address0();
      void thread_buffer_0_value_V_address1();
      void thread_buffer_0_value_V_ce0();
      void thread_buffer_0_value_V_ce1();
      void thread_buffer_0_value_V_we1();
      void thread_buffer_1_value_V_address0();
      void thread_buffer_1_value_V_ce0();
      void thread_buffer_1_value_V_ce1();
      void thread_buffer_1_value_V_we1();
      void thread_col_1_fu_198_p2();
      void thread_col_cast_fu_204_p1();
      void thread_icmp1_fu_220_p2();
      void thread_icmp_fu_186_p2();
      void thread_in_stream_V_value_V_blk_n();
      void thread_in_stream_V_value_V_read();
      void thread_internal_ap_ready();
      void thread_p_Val2_2_0_phi_fu_243_p3();
      void thread_p_Val2_2_1_phi_fu_251_p3();
      void thread_p_write_idx_1_1_fu_232_p3();
      void thread_real_start();
      void thread_row_1_fu_170_p2();
      void thread_slice_stream_V_value_V_blk_n();
      void thread_slice_stream_V_value_V_din();
      void thread_slice_stream_V_value_V_write();
      void thread_start_out();
      void thread_start_write();
      void thread_tmp_1_fu_192_p2();
      void thread_tmp_6_fu_176_p4();
      void thread_tmp_7_fu_210_p4();
      void thread_tmp_8_fu_239_p1();
      void thread_tmp_9_fu_259_p1();
      void thread_tmp_fu_164_p2();
      void thread_write_idx_1_1_phi_fu_145_p4();
      void thread_write_idx_1_2_fu_272_p2();
      void thread_write_idx_1_3_fu_226_p2();
      void thread_ap_NS_fsm();
  };
  
  }
  
  using namespace ap_rtl;
  
  #endif
  