text: // (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
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  #include "design_1_auto_pc_2_sc.h"
  
  #include "axi_protocol_converter.h"
  
  #include <map>
  #include <string>
  
  design_1_auto_pc_2_sc::design_1_auto_pc_2_sc(const sc_core::sc_module_name& nm) : sc_core::sc_module(nm), mp_impl(NULL)
  {
    // configure connectivity manager
    xsc::utils::xsc_sim_manager::addInstance("design_1_auto_pc_2", this);
  
    // initialize module
      xsc::common_cpp::properties model_param_props;
      model_param_props.addLong("C_M_AXI_PROTOCOL", "2");
      model_param_props.addLong("C_S_AXI_PROTOCOL", "0");
      model_param_props.addLong("C_IGNORE_ID", "0");
      model_param_props.addLong("C_AXI_ID_WIDTH", "12");
      model_param_props.addLong("C_AXI_ADDR_WIDTH", "32");
      model_param_props.addLong("C_AXI_DATA_WIDTH", "32");
      model_param_props.addLong("C_AXI_SUPPORTS_WRITE", "1");
      model_param_props.addLong("C_AXI_SUPPORTS_READ", "1");
      model_param_props.addLong("C_AXI_SUPPORTS_USER_SIGNALS", "0");
      model_param_props.addLong("C_AXI_AWUSER_WIDTH", "1");
      model_param_props.addLong("C_AXI_ARUSER_WIDTH", "1");
      model_param_props.addLong("C_AXI_WUSER_WIDTH", "1");
      model_param_props.addLong("C_AXI_RUSER_WIDTH", "1");
      model_param_props.addLong("C_AXI_BUSER_WIDTH", "1");
      model_param_props.addLong("C_TRANSLATION_MODE", "2");
      model_param_props.addString("C_FAMILY", "zynq");
  
    mp_impl = new axi_protocol_converter("inst", model_param_props);
  
    // initialize sockets
    target_rd_socket = mp_impl->target_rd_socket;
    target_wr_socket = mp_impl->target_wr_socket;
    initiator_rd_socket = mp_impl->initiator_rd_socket;
    initiator_wr_socket = mp_impl->initiator_wr_socket;
  }
  
  design_1_auto_pc_2_sc::~design_1_auto_pc_2_sc()
  {
    xsc::utils::xsc_sim_manager::clean();
  
    delete mp_impl;
  }
  
  