text: /***************************************************************************//**
  * \file cyhal_psoc4100sp256kb_48_tqfp_mc.h
  *
  * \brief
  * PSoC4100Sp256KB device GPIO HAL header for 48-TQFP-MC package
  *
  ********************************************************************************
  * \copyright
  * (c) (2016-2021), Cypress Semiconductor Corporation (an Infineon company) or
  * an affiliate of Cypress Semiconductor Corporation.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
  *     http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
  * distributed under the License is distributed on an "AS IS" BASIS,
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  *******************************************************************************/
  
  #ifndef _CYHAL_PSOC4100SP256KB_48_TQFP_MC_H_
  #define _CYHAL_PSOC4100SP256KB_48_TQFP_MC_H_
  
  #include "cyhal_hw_resources.h"
  
  /**
   * \addtogroup group_hal_impl_pin_package_psoc4100sp256kb_48_tqfp_mc PSoC4100Sp256KB 48-TQFP-MC
   * \ingroup group_hal_impl_pin_package
   * \{
   * Pin definitions and connections specific to the PSoC4100Sp256KB 48-TQFP-MC package.
   */
  
  #if defined(__cplusplus)
  extern "C" {
  #endif /* __cplusplus */
  
  /** Gets a pin definition from the provided port and pin numbers */
  #define CYHAL_GET_GPIO(port, pin)   ((((uint8_t)(port)) << 3U) + ((uint8_t)(pin)))
  
  /** Macro that, given a gpio, will extract the pin number */
  #define CYHAL_GET_PIN(pin)          ((uint8_t)(((uint8_t)pin) & 0x07U))
  /** Macro that, given a gpio, will extract the port number */
  #define CYHAL_GET_PORT(pin)         ((uint8_t)((((uint8_t)pin) >> 3U) & 0x1FU))
  
  /** Definitions for all of the pins that are bonded out on in the 48-TQFP-MC package for the PSoC4100Sp256KB series. */
  typedef enum {
      NC = 0xFF, //!< No Connect/Invalid Pin
  
      P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
      P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
      P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2
      P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3
      P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
      P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5
      P0_6 = CYHAL_GET_GPIO(CYHAL_PORT_0, 6), //!< Port 0 Pin 6
      P0_7 = CYHAL_GET_GPIO(CYHAL_PORT_0, 7), //!< Port 0 Pin 7
  
      P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0
      P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1
      P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2
      P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3
      P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4
      P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5
      P1_6 = CYHAL_GET_GPIO(CYHAL_PORT_1, 6), //!< Port 1 Pin 6
      P1_7 = CYHAL_GET_GPIO(CYHAL_PORT_1, 7), //!< Port 1 Pin 7
  
      P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0
      P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1
      P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2
      P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3
      P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4
      P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5
      P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6
      P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7
  
      P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0
      P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1
      P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2
      P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3
      P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4
      P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5
      P3_6 = CYHAL_GET_GPIO(CYHAL_PORT_3, 6), //!< Port 3 Pin 6
      P3_7 = CYHAL_GET_GPIO(CYHAL_PORT_3, 7), //!< Port 3 Pin 7
  
      P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0
      P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1
      P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2), //!< Port 4 Pin 2
      P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3), //!< Port 4 Pin 3
  
      P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5
  
      P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0
      P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1
  } cyhal_gpio_psoc4100sp256kb_48_tqfp_mc_t;
  
  /** Create generic name for the series/package specific type. */
  typedef cyhal_gpio_psoc4100sp256kb_48_tqfp_mc_t cyhal_gpio_t;
  
  /* Connection type definition */
  /** Represents an association between a pin and a resource */
  typedef struct
  {
      uint8_t         block_num;   //!< The block number of the resource with this connection
      uint8_t         channel_num; //!< The channel number of the block with this connection
      cyhal_gpio_t    pin;         //!< The GPIO pin the connection is with
      en_hsiom_sel_t  hsiom;       //!< The HSIOM configuration value
  } cyhal_resource_pin_mapping_t;
  
  /* Pin connections */
  /** Indicates that a pin map exists for lpcomp_dsi_comp*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_DSI_COMP (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the lpcomp_dsi_comp signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp[4];
  /** Indicates that a pin map exists for lpcomp_inn_comp*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INN_COMP (CY_GPIO_DM_ANALOG)
  /** List of valid pin to peripheral connections for the lpcomp_inn_comp signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[2];
  /** Indicates that a pin map exists for lpcomp_inp_comp*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_LPCOMP_INP_COMP (CY_GPIO_DM_ANALOG)
  /** List of valid pin to peripheral connections for the lpcomp_inp_comp signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2];
  /** Indicates that a pin map exists for opamp_dsi_ctb_cmp*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_DSI_CTB_CMP (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the opamp_dsi_ctb_cmp signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_dsi_ctb_cmp[2];
  /** Indicates that a pin map exists for opamp_out_10x*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_OUT_10X (CY_GPIO_DM_ANALOG)
  /** List of valid pin to peripheral connections for the opamp_out_10x signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_out_10x[2];
  /** Indicates that a pin map exists for opamp_vin_m*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_M (CY_GPIO_DM_ANALOG)
  /** List of valid pin to peripheral connections for the opamp_vin_m signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_m[2];
  /** Indicates that a pin map exists for opamp_vin_p0*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_P0 (CY_GPIO_DM_ANALOG)
  /** List of valid pin to peripheral connections for the opamp_vin_p0 signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p0[2];
  /** Indicates that a pin map exists for opamp_vin_p1*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_OPAMP_VIN_P1 (CY_GPIO_DM_ANALOG)
  /** List of valid pin to peripheral connections for the opamp_vin_p1 signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p1[3];
  /** Indicates that a pin map exists for pass_dsi_sar_data*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_DSI_SAR_DATA (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the pass_dsi_sar_data signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_sar_data[24];
  /** Indicates that a pin map exists for pass_dsi_sar_data_valid*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_DSI_SAR_DATA_VALID (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the pass_dsi_sar_data_valid signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_sar_data_valid[2];
  /** Indicates that a pin map exists for pass_dsi_sar_sample_done*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_DSI_SAR_SAMPLE_DONE (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the pass_dsi_sar_sample_done signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_sar_sample_done[2];
  /** Indicates that a pin map exists for pass_sar_ext_vref0*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_VREF0 (CY_GPIO_DM_ANALOG)
  /** List of valid pin to peripheral connections for the pass_sar_ext_vref0 signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_vref0[2];
  /** Indicates that a pin map exists for pass_sar_ext_vref1*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SAR_EXT_VREF1 (CY_GPIO_DM_ANALOG)
  /** List of valid pin to peripheral connections for the pass_sar_ext_vref1 signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_vref1[2];
  /** Indicates that a pin map exists for pass_sarmux_pads*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_SARMUX_PADS (CY_GPIO_DM_ANALOG)
  /** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[16];
  /** Indicates that a pin map exists for pass_tr_sar_out*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_PASS_TR_SAR_OUT (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the pass_tr_sar_out signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_tr_sar_out[2];
  /** Indicates that a pin map exists for scb_i2c_scl*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SCL (CY_GPIO_DM_OD_DRIVESLOW)
  /** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[9];
  /** Indicates that a pin map exists for scb_i2c_sda*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_I2C_SDA (CY_GPIO_DM_OD_DRIVESLOW)
  /** List of valid pin to peripheral connections for the scb_i2c_sda signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[10];
  /** Indicates that a pin map exists for scb_spi_m_clk*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_CLK (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[6];
  /** Indicates that a pin map exists for scb_spi_m_miso*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MISO (CY_GPIO_DM_HIGHZ)
  /** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[7];
  /** Indicates that a pin map exists for scb_spi_m_mosi*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_MOSI (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[7];
  /** Indicates that a pin map exists for scb_spi_m_select0*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT0 (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[6];
  /** Indicates that a pin map exists for scb_spi_m_select1*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT1 (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[4];
  /** Indicates that a pin map exists for scb_spi_m_select2*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT2 (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[5];
  /** Indicates that a pin map exists for scb_spi_m_select3*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_M_SELECT3 (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[5];
  /** Indicates that a pin map exists for scb_spi_s_clk*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_CLK (CY_GPIO_DM_HIGHZ)
  /** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[6];
  /** Indicates that a pin map exists for scb_spi_s_miso*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MISO (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[7];
  /** Indicates that a pin map exists for scb_spi_s_mosi*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_MOSI (CY_GPIO_DM_HIGHZ)
  /** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[7];
  /** Indicates that a pin map exists for scb_spi_s_select0*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT0 (CY_GPIO_DM_HIGHZ)
  /** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[6];
  /** Indicates that a pin map exists for scb_spi_s_select1*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT1 (CY_GPIO_DM_HIGHZ)
  /** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[4];
  /** Indicates that a pin map exists for scb_spi_s_select2*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT2 (CY_GPIO_DM_HIGHZ)
  /** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[5];
  /** Indicates that a pin map exists for scb_spi_s_select3*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_SPI_S_SELECT3 (CY_GPIO_DM_HIGHZ)
  /** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[5];
  /** Indicates that a pin map exists for scb_uart_cts*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_CTS (CY_GPIO_DM_HIGHZ)
  /** List of valid pin to peripheral connections for the scb_uart_cts signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6];
  /** Indicates that a pin map exists for scb_uart_rts*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RTS (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the scb_uart_rts signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[6];
  /** Indicates that a pin map exists for scb_uart_rx*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_RX (CY_GPIO_DM_HIGHZ)
  /** List of valid pin to peripheral connections for the scb_uart_rx signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[7];
  /** Indicates that a pin map exists for scb_uart_tx*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_SCB_UART_TX (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the scb_uart_tx signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[8];
  /** Indicates that a pin map exists for tcpwm_line*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the tcpwm_line signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[14];
  /** Indicates that a pin map exists for tcpwm_line_compl*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_LINE_COMPL (CY_GPIO_DM_STRONG_IN_OFF)
  /** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[14];
  /** Indicates that a pin map exists for tcpwm_tr_in*/
  #define CYHAL_PIN_MAP_DRIVE_MODE_TCPWM_TR_IN (CY_GPIO_DM_HIGHZ)
  /** List of valid pin to peripheral connections for the tcpwm_tr_in signal. */
  extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_in[7];
  
  #if defined(__cplusplus)
  }
  #endif /* __cplusplus */
  
  /** \} group_hal_impl_pin_package */
  
  #endif /* _CYHAL_PSOC4100SP256KB_48_TQFP_MC_H_ */
  
  
  /* [] END OF FILE */
  