text: // Copyright (c) 2015, Joe Krachey
  // All rights reserved.
  //
  // Redistribution and use in source or binary form, with or without modification, 
  // are permitted provided that the following conditions are met:
  //
  // 1. Redistributions in source form must reproduce the above copyright 
  //    notice, this list of conditions and the following disclaimer in 
  //    the documentation and/or other materials provided with the distribution.
  //
  // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
  // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 
  // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 
  // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
  // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
  // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 
  // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 
  // OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
  // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 
  // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 
  // EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  
  #ifndef __DRIVER_DEFINES_H__
  #define __DRIVER_DEFINES_H__
  
  #include <stdint.h>
  #include <stdbool.h>
  #include <stdio.h>
  #include <errno.h>
  #include "TM4C123GH6PM.h"
  
   /************************************************************************
   ************************************************************************/
   /* SYSCTRL MACROS                                                      */
   /************************************************************************
   ************************************************************************/
   
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DID0 register.
  //
  //*****************************************************************************
  #define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version
  #define SYSCTL_DID0_VER_1       0x10000000  // Second version of the DID0
                                              // register format
  #define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class
  #define SYSCTL_DID0_CLASS_BLIZZARD \
                                  0x00050000  // Stellaris(R) Blizzard-class
                                              // microcontrollers
  #define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision
  #define SYSCTL_DID0_MAJ_REVA    0x00000000  // Revision A (initial device)
  #define SYSCTL_DID0_MAJ_REVB    0x00000100  // Revision B (first base layer
                                              // revision)
  #define SYSCTL_DID0_MAJ_REVC    0x00000200  // Revision C (second base layer
                                              // revision)
  #define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision
  #define SYSCTL_DID0_MIN_0       0x00000000  // Initial device, or a major
                                              // revision update
  #define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change
  #define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DID1 register.
  //
  //*****************************************************************************
  #define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version
  #define SYSCTL_DID1_VER_0       0x00000000  // Initial DID1 register format
                                              // definition, indicating a
                                              // Stellaris LM3Snnn device
  #define SYSCTL_DID1_VER_1       0x10000000  // Second version of the DID1
                                              // register format
  #define SYSCTL_DID1_FAM_M       0x0F000000  // Family
  #define SYSCTL_DID1_FAM_STELLARIS \
                                  0x00000000  // Stellaris family of
                                              // microcontollers, that is, all
                                              // devices with external part
                                              // numbers starting with LM3S
  #define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number
  #define SYSCTL_DID1_PRTNO_LM4F120H5QR \
                                  0x00040000  // LM4F120H5QR
  #define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count
  #define SYSCTL_DID1_PINCNT_28   0x00000000  // 28-pin package
  #define SYSCTL_DID1_PINCNT_48   0x00002000  // 48-pin package
  #define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin package
  #define SYSCTL_DID1_PINCNT_64   0x00006000  // 64-pin package
  #define SYSCTL_DID1_PINCNT_144  0x00008000  // 144-pin package
  #define SYSCTL_DID1_PINCNT_157  0x0000A000  // 157-pin package
  #define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range
  #define SYSCTL_DID1_TEMP_C      0x00000000  // Commercial temperature range (0C
                                              // to 70C)
  #define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temperature range
                                              // (-40C to 85C)
  #define SYSCTL_DID1_TEMP_E      0x00000040  // Extended temperature range (-40C
                                              // to 105C)
  #define SYSCTL_DID1_PKG_M       0x00000018  // Package Type
  #define SYSCTL_DID1_PKG_SOIC    0x00000000  // SOIC package
  #define SYSCTL_DID1_PKG_QFP     0x00000008  // LQFP package
  #define SYSCTL_DID1_PKG_BGA     0x00000010  // BGA package
  #define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance
  #define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status
  #define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering Sample (unqualified)
  #define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot Production (unqualified)
  #define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully Qualified
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DC0 register.
  //
  //*****************************************************************************
  #define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size
  #define SYSCTL_DC0_SRAMSZ_2KB   0x00070000  // 2 KB of SRAM
  #define SYSCTL_DC0_SRAMSZ_4KB   0x000F0000  // 4 KB of SRAM
  #define SYSCTL_DC0_SRAMSZ_6KB   0x00170000  // 6 KB of SRAM
  #define SYSCTL_DC0_SRAMSZ_8KB   0x001F0000  // 8 KB of SRAM
  #define SYSCTL_DC0_SRAMSZ_12KB  0x002F0000  // 12 KB of SRAM
  #define SYSCTL_DC0_SRAMSZ_16KB  0x003F0000  // 16 KB of SRAM
  #define SYSCTL_DC0_SRAMSZ_20KB  0x004F0000  // 20 KB of SRAM
  #define SYSCTL_DC0_SRAMSZ_24KB  0x005F0000  // 24 KB of SRAM
  #define SYSCTL_DC0_SRAMSZ_32KB  0x007F0000  // 32 KB of SRAM
  #define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size
  #define SYSCTL_DC0_FLASHSZ_8KB  0x00000003  // 8 KB of Flash
  #define SYSCTL_DC0_FLASHSZ_16KB 0x00000007  // 16 KB of Flash
  #define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F  // 32 KB of Flash
  #define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F  // 64 KB of Flash
  #define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F  // 96 KB of Flash
  #define SYSCTL_DC0_FLASHSZ_128K 0x0000003F  // 128 KB of Flash
  #define SYSCTL_DC0_FLASHSZ_192K 0x0000005F  // 192 KB of Flash
  #define SYSCTL_DC0_FLASHSZ_256K 0x0000007F  // 256 KB of Flash
  #define SYSCTL_DC0_SRAMSZ_S     16          // SRAM size shift
  #define SYSCTL_DC0_FLASHSZ_S    0           // Flash size shift
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DC1 register.
  //
  //*****************************************************************************
  #define SYSCTL_DC1_WDT1         0x10000000  // Watchdog Timer1 Present
  #define SYSCTL_DC1_CAN1         0x02000000  // CAN Module 1 Present
  #define SYSCTL_DC1_CAN0         0x01000000  // CAN Module 0 Present
  #define SYSCTL_DC1_PWM1         0x00200000  // PWM Module 1 Present
  #define SYSCTL_DC1_PWM0         0x00100000  // PWM Module 0 Present
  #define SYSCTL_DC1_ADC1         0x00020000  // ADC Module 1 Present
  #define SYSCTL_DC1_ADC0         0x00010000  // ADC Module 0 Present
  #define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider
  #define SYSCTL_DC1_MINSYSDIV_100 \
                                  0x00001000  // Divide VCO (400MHZ) by 5 minimum
  #define SYSCTL_DC1_MINSYSDIV_66 0x00002000  // Divide VCO (400MHZ) by 2*2 + 2 =
                                              // 6 minimum
  #define SYSCTL_DC1_MINSYSDIV_50 0x00003000  // Specifies a 50-MHz CPU clock
                                              // with a PLL divider of 4
  #define SYSCTL_DC1_MINSYSDIV_40 0x00004000  // Specifies a 40-MHz CPU clock
                                              // with a PLL divider of 5
  #define SYSCTL_DC1_MINSYSDIV_25 0x00007000  // Specifies a 25-MHz clock with a
                                              // PLL divider of 8
  #define SYSCTL_DC1_MINSYSDIV_20 0x00009000  // Specifies a 20-MHz clock with a
                                              // PLL divider of 10
  #define SYSCTL_DC1_ADC1SPD_M    0x00000C00  // Max ADC1 Speed
  #define SYSCTL_DC1_ADC1SPD_125K 0x00000000  // 125K samples/second
  #define SYSCTL_DC1_ADC1SPD_250K 0x00000400  // 250K samples/second
  #define SYSCTL_DC1_ADC1SPD_500K 0x00000800  // 500K samples/second
  #define SYSCTL_DC1_ADC1SPD_1M   0x00000C00  // 1M samples/second
  #define SYSCTL_DC1_ADC0SPD_M    0x00000300  // Max ADC0 Speed
  #define SYSCTL_DC1_ADC0SPD_125K 0x00000000  // 125K samples/second
  #define SYSCTL_DC1_ADC0SPD_250K 0x00000100  // 250K samples/second
  #define SYSCTL_DC1_ADC0SPD_500K 0x00000200  // 500K samples/second
  #define SYSCTL_DC1_ADC0SPD_1M   0x00000300  // 1M samples/second
  #define SYSCTL_DC1_MPU          0x00000080  // MPU Present
  #define SYSCTL_DC1_HIB          0x00000040  // Hibernation Module Present
  #define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present
  #define SYSCTL_DC1_PLL          0x00000010  // PLL Present
  #define SYSCTL_DC1_WDT0         0x00000008  // Watchdog Timer 0 Present
  #define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present
  #define SYSCTL_DC1_SWD          0x00000002  // SWD Present
  #define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DC2 register.
  //
  //*****************************************************************************
  #define SYSCTL_DC2_EPI0         0x40000000  // EPI Module 0 Present
  #define SYSCTL_DC2_I2S0         0x10000000  // I2S Module 0 Present
  #define SYSCTL_DC2_COMP2        0x04000000  // Analog Comparator 2 Present
  #define SYSCTL_DC2_COMP1        0x02000000  // Analog Comparator 1 Present
  #define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present
  #define SYSCTL_DC2_TIMER3       0x00080000  // Timer Module 3 Present
  #define SYSCTL_DC2_TIMER2       0x00040000  // Timer Module 2 Present
  #define SYSCTL_DC2_TIMER1       0x00020000  // Timer Module 1 Present
  #define SYSCTL_DC2_TIMER0       0x00010000  // Timer Module 0 Present
  #define SYSCTL_DC2_I2C1HS       0x00008000  // I2C Module 1 Speed
  #define SYSCTL_DC2_I2C1         0x00004000  // I2C Module 1 Present
  #define SYSCTL_DC2_I2C0HS       0x00002000  // I2C Module 0 Speed
  #define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present
  #define SYSCTL_DC2_QEI1         0x00000200  // QEI Module 1 Present
  #define SYSCTL_DC2_QEI0         0x00000100  // QEI Module 0 Present
  #define SYSCTL_DC2_SSI1         0x00000020  // SSI Module 1 Present
  #define SYSCTL_DC2_SSI0         0x00000010  // SSI Module 0 Present
  #define SYSCTL_DC2_UART2        0x00000004  // UART Module 2 Present
  #define SYSCTL_DC2_UART1        0x00000002  // UART Module 1 Present
  #define SYSCTL_DC2_UART0        0x00000001  // UART Module 0 Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DC3 register.
  //
  //*****************************************************************************
  #define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available
  #define SYSCTL_DC3_CCP5         0x20000000  // CCP5 Pin Present
  #define SYSCTL_DC3_CCP4         0x10000000  // CCP4 Pin Present
  #define SYSCTL_DC3_CCP3         0x08000000  // CCP3 Pin Present
  #define SYSCTL_DC3_CCP2         0x04000000  // CCP2 Pin Present
  #define SYSCTL_DC3_CCP1         0x02000000  // CCP1 Pin Present
  #define SYSCTL_DC3_CCP0         0x01000000  // CCP0 Pin Present
  #define SYSCTL_DC3_ADC0AIN7     0x00800000  // ADC Module 0 AIN7 Pin Present
  #define SYSCTL_DC3_ADC0AIN6     0x00400000  // ADC Module 0 AIN6 Pin Present
  #define SYSCTL_DC3_ADC0AIN5     0x00200000  // ADC Module 0 AIN5 Pin Present
  #define SYSCTL_DC3_ADC0AIN4     0x00100000  // ADC Module 0 AIN4 Pin Present
  #define SYSCTL_DC3_ADC0AIN3     0x00080000  // ADC Module 0 AIN3 Pin Present
  #define SYSCTL_DC3_ADC0AIN2     0x00040000  // ADC Module 0 AIN2 Pin Present
  #define SYSCTL_DC3_ADC0AIN1     0x00020000  // ADC Module 0 AIN1 Pin Present
  #define SYSCTL_DC3_ADC0AIN0     0x00010000  // ADC Module 0 AIN0 Pin Present
  #define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present
  #define SYSCTL_DC3_C2O          0x00004000  // C2o Pin Present
  #define SYSCTL_DC3_C2PLUS       0x00002000  // C2+ Pin Present
  #define SYSCTL_DC3_C2MINUS      0x00001000  // C2- Pin Present
  #define SYSCTL_DC3_C1O          0x00000800  // C1o Pin Present
  #define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ Pin Present
  #define SYSCTL_DC3_C1MINUS      0x00000200  // C1- Pin Present
  #define SYSCTL_DC3_C0O          0x00000100  // C0o Pin Present
  #define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present
  #define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present
  #define SYSCTL_DC3_PWM5         0x00000020  // PWM5 Pin Present
  #define SYSCTL_DC3_PWM4         0x00000010  // PWM4 Pin Present
  #define SYSCTL_DC3_PWM3         0x00000008  // PWM3 Pin Present
  #define SYSCTL_DC3_PWM2         0x00000004  // PWM2 Pin Present
  #define SYSCTL_DC3_PWM1         0x00000002  // PWM1 Pin Present
  #define SYSCTL_DC3_PWM0         0x00000001  // PWM0 Pin Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DC4 register.
  //
  //*****************************************************************************
  #define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY Layer 0 Present
  #define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC Layer 0 Present
  #define SYSCTL_DC4_E1588        0x01000000  // 1588 Capable
  #define SYSCTL_DC4_PICAL        0x00040000  // PIOSC Calibrate
  #define SYSCTL_DC4_CCP7         0x00008000  // CCP7 Pin Present
  #define SYSCTL_DC4_CCP6         0x00004000  // CCP6 Pin Present
  #define SYSCTL_DC4_UDMA         0x00002000  // Micro-DMA Module Present
  #define SYSCTL_DC4_ROM          0x00001000  // Internal Code ROM Present
  #define SYSCTL_DC4_GPIOJ        0x00000100  // GPIO Port J Present
  #define SYSCTL_DC4_GPIOH        0x00000080  // GPIO Port H Present
  #define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present
  #define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present
  #define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present
  #define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present
  #define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present
  #define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present
  #define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DC5 register.
  //
  //*****************************************************************************
  #define SYSCTL_DC5_PWMFAULT3    0x08000000  // PWM Fault 3 Pin Present
  #define SYSCTL_DC5_PWMFAULT2    0x04000000  // PWM Fault 2 Pin Present
  #define SYSCTL_DC5_PWMFAULT1    0x02000000  // PWM Fault 1 Pin Present
  #define SYSCTL_DC5_PWMFAULT0    0x01000000  // PWM Fault 0 Pin Present
  #define SYSCTL_DC5_PWMEFLT      0x00200000  // PWM Extended Fault Active
  #define SYSCTL_DC5_PWMESYNC     0x00100000  // PWM Extended SYNC Active
  #define SYSCTL_DC5_PWM7         0x00000080  // PWM7 Pin Present
  #define SYSCTL_DC5_PWM6         0x00000040  // PWM6 Pin Present
  #define SYSCTL_DC5_PWM5         0x00000020  // PWM5 Pin Present
  #define SYSCTL_DC5_PWM4         0x00000010  // PWM4 Pin Present
  #define SYSCTL_DC5_PWM3         0x00000008  // PWM3 Pin Present
  #define SYSCTL_DC5_PWM2         0x00000004  // PWM2 Pin Present
  #define SYSCTL_DC5_PWM1         0x00000002  // PWM1 Pin Present
  #define SYSCTL_DC5_PWM0         0x00000001  // PWM0 Pin Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DC6 register.
  //
  //*****************************************************************************
  #define SYSCTL_DC6_USB0PHY      0x00000010  // USB Module 0 PHY Present
  #define SYSCTL_DC6_USB0_M       0x00000003  // USB Module 0 Present
  #define SYSCTL_DC6_USB0_DEV     0x00000001  // USB0 is Device Only
  #define SYSCTL_DC6_USB0_HOSTDEV 0x00000002  // USB is Device or Host
  #define SYSCTL_DC6_USB0_OTG     0x00000003  // USB0 is OTG
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DC7 register.
  //
  //*****************************************************************************
  #define SYSCTL_DC7_DMACH30      0x40000000  // SW
  #define SYSCTL_DC7_DMACH29      0x20000000  // I2S0_TX / CAN1_TX
  #define SYSCTL_DC7_DMACH28      0x10000000  // I2S0_RX / CAN1_RX
  #define SYSCTL_DC7_DMACH27      0x08000000  // CAN1_TX / ADC1_SS3
  #define SYSCTL_DC7_DMACH26      0x04000000  // CAN1_RX / ADC1_SS2
  #define SYSCTL_DC7_DMACH25      0x02000000  // SSI1_TX / ADC1_SS1
  #define SYSCTL_DC7_DMACH24      0x01000000  // SSI1_RX / ADC1_SS0
  #define SYSCTL_DC7_DMACH23      0x00800000  // UART1_TX / CAN2_TX
  #define SYSCTL_DC7_DMACH22      0x00400000  // UART1_RX / CAN2_RX
  #define SYSCTL_DC7_DMACH21      0x00200000  // Timer1B / EPI0_WFIFO
  #define SYSCTL_DC7_DMACH20      0x00100000  // Timer1A / EPI0_NBRFIFO
  #define SYSCTL_DC7_DMACH19      0x00080000  // Timer0B / Timer1B
  #define SYSCTL_DC7_DMACH18      0x00040000  // Timer0A / Timer1A
  #define SYSCTL_DC7_DMACH17      0x00020000  // ADC0_SS3
  #define SYSCTL_DC7_DMACH16      0x00010000  // ADC0_SS2
  #define SYSCTL_DC7_DMACH15      0x00008000  // ADC0_SS1 / Timer2B
  #define SYSCTL_DC7_DMACH14      0x00004000  // ADC0_SS0 / Timer2A
  #define SYSCTL_DC7_DMACH13      0x00002000  // CAN0_TX / UART2_TX
  #define SYSCTL_DC7_DMACH12      0x00001000  // CAN0_RX / UART2_RX
  #define SYSCTL_DC7_DMACH11      0x00000800  // SSI0_TX / SSI1_TX
  #define SYSCTL_DC7_DMACH10      0x00000400  // SSI0_RX / SSI1_RX
  #define SYSCTL_DC7_DMACH9       0x00000200  // UART0_TX / UART1_TX
  #define SYSCTL_DC7_DMACH8       0x00000100  // UART0_RX / UART1_RX
  #define SYSCTL_DC7_DMACH7       0x00000080  // ETH_TX / Timer2B
  #define SYSCTL_DC7_DMACH6       0x00000040  // ETH_RX / Timer2A
  #define SYSCTL_DC7_DMACH5       0x00000020  // USB_EP3_TX / Timer2B
  #define SYSCTL_DC7_DMACH4       0x00000010  // USB_EP3_RX / Timer2A
  #define SYSCTL_DC7_DMACH3       0x00000008  // USB_EP2_TX / Timer3B
  #define SYSCTL_DC7_DMACH2       0x00000004  // USB_EP2_RX / Timer3A
  #define SYSCTL_DC7_DMACH1       0x00000002  // USB_EP1_TX / UART2_TX
  #define SYSCTL_DC7_DMACH0       0x00000001  // USB_EP1_RX / UART2_RX
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DC8 register.
  //
  //*****************************************************************************
  #define SYSCTL_DC8_ADC1AIN15    0x80000000  // ADC Module 1 AIN15 Pin Present
  #define SYSCTL_DC8_ADC1AIN14    0x40000000  // ADC Module 1 AIN14 Pin Present
  #define SYSCTL_DC8_ADC1AIN13    0x20000000  // ADC Module 1 AIN13 Pin Present
  #define SYSCTL_DC8_ADC1AIN12    0x10000000  // ADC Module 1 AIN12 Pin Present
  #define SYSCTL_DC8_ADC1AIN11    0x08000000  // ADC Module 1 AIN11 Pin Present
  #define SYSCTL_DC8_ADC1AIN10    0x04000000  // ADC Module 1 AIN10 Pin Present
  #define SYSCTL_DC8_ADC1AIN9     0x02000000  // ADC Module 1 AIN9 Pin Present
  #define SYSCTL_DC8_ADC1AIN8     0x01000000  // ADC Module 1 AIN8 Pin Present
  #define SYSCTL_DC8_ADC1AIN7     0x00800000  // ADC Module 1 AIN7 Pin Present
  #define SYSCTL_DC8_ADC1AIN6     0x00400000  // ADC Module 1 AIN6 Pin Present
  #define SYSCTL_DC8_ADC1AIN5     0x00200000  // ADC Module 1 AIN5 Pin Present
  #define SYSCTL_DC8_ADC1AIN4     0x00100000  // ADC Module 1 AIN4 Pin Present
  #define SYSCTL_DC8_ADC1AIN3     0x00080000  // ADC Module 1 AIN3 Pin Present
  #define SYSCTL_DC8_ADC1AIN2     0x00040000  // ADC Module 1 AIN2 Pin Present
  #define SYSCTL_DC8_ADC1AIN1     0x00020000  // ADC Module 1 AIN1 Pin Present
  #define SYSCTL_DC8_ADC1AIN0     0x00010000  // ADC Module 1 AIN0 Pin Present
  #define SYSCTL_DC8_ADC0AIN15    0x00008000  // ADC Module 0 AIN15 Pin Present
  #define SYSCTL_DC8_ADC0AIN14    0x00004000  // ADC Module 0 AIN14 Pin Present
  #define SYSCTL_DC8_ADC0AIN13    0x00002000  // ADC Module 0 AIN13 Pin Present
  #define SYSCTL_DC8_ADC0AIN12    0x00001000  // ADC Module 0 AIN12 Pin Present
  #define SYSCTL_DC8_ADC0AIN11    0x00000800  // ADC Module 0 AIN11 Pin Present
  #define SYSCTL_DC8_ADC0AIN10    0x00000400  // ADC Module 0 AIN10 Pin Present
  #define SYSCTL_DC8_ADC0AIN9     0x00000200  // ADC Module 0 AIN9 Pin Present
  #define SYSCTL_DC8_ADC0AIN8     0x00000100  // ADC Module 0 AIN8 Pin Present
  #define SYSCTL_DC8_ADC0AIN7     0x00000080  // ADC Module 0 AIN7 Pin Present
  #define SYSCTL_DC8_ADC0AIN6     0x00000040  // ADC Module 0 AIN6 Pin Present
  #define SYSCTL_DC8_ADC0AIN5     0x00000020  // ADC Module 0 AIN5 Pin Present
  #define SYSCTL_DC8_ADC0AIN4     0x00000010  // ADC Module 0 AIN4 Pin Present
  #define SYSCTL_DC8_ADC0AIN3     0x00000008  // ADC Module 0 AIN3 Pin Present
  #define SYSCTL_DC8_ADC0AIN2     0x00000004  // ADC Module 0 AIN2 Pin Present
  #define SYSCTL_DC8_ADC0AIN1     0x00000002  // ADC Module 0 AIN1 Pin Present
  #define SYSCTL_DC8_ADC0AIN0     0x00000001  // ADC Module 0 AIN0 Pin Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PBORCTL register.
  //
  //*****************************************************************************
  #define SYSCTL_PBORCTL_BORIOR   0x00000002  // BOR Interrupt or Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRCR0 register.
  //
  //*****************************************************************************
  #define SYSCTL_SRCR0_WDT1       0x10000000  // WDT1 Reset Control
  #define SYSCTL_SRCR0_CAN1       0x02000000  // CAN1 Reset Control
  #define SYSCTL_SRCR0_CAN0       0x01000000  // CAN0 Reset Control
  #define SYSCTL_SRCR0_PWM0       0x00100000  // PWM Reset Control
  #define SYSCTL_SRCR0_ADC1       0x00020000  // ADC1 Reset Control
  #define SYSCTL_SRCR0_ADC0       0x00010000  // ADC0 Reset Control
  #define SYSCTL_SRCR0_HIB        0x00000040  // HIB Reset Control
  #define SYSCTL_SRCR0_WDT0       0x00000008  // WDT0 Reset Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRCR1 register.
  //
  //*****************************************************************************
  #define SYSCTL_SRCR1_COMP2      0x04000000  // Analog Comp 2 Reset Control
  #define SYSCTL_SRCR1_COMP1      0x02000000  // Analog Comp 1 Reset Control
  #define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control
  #define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control
  #define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control
  #define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control
  #define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control
  #define SYSCTL_SRCR1_I2C1       0x00004000  // I2C1 Reset Control
  #define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control
  #define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control
  #define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control
  #define SYSCTL_SRCR1_SSI1       0x00000020  // SSI1 Reset Control
  #define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control
  #define SYSCTL_SRCR1_UART2      0x00000004  // UART2 Reset Control
  #define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control
  #define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRCR2 register.
  //
  //*****************************************************************************
  #define SYSCTL_SRCR2_USB0       0x00010000  // USB0 Reset Control
  #define SYSCTL_SRCR2_UDMA       0x00002000  // Micro-DMA Reset Control
  #define SYSCTL_SRCR2_GPIOJ      0x00000100  // Port J Reset Control
  #define SYSCTL_SRCR2_GPIOH      0x00000080  // Port H Reset Control
  #define SYSCTL_SRCR2_GPIOG      0x00000040  // Port G Reset Control
  #define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control
  #define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control
  #define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control
  #define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control
  #define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control
  #define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RIS register.
  //
  //*****************************************************************************
  #define SYSCTL_RIS_MOSCPUPRIS   0x00000100  // MOSC Power Up Raw Interrupt
                                              // Status
  #define SYSCTL_RIS_USBPLLLRIS   0x00000080  // USB PLL Lock Raw Interrupt
                                              // Status
  #define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status
  #define SYSCTL_RIS_MOFRIS       0x00000008  // Main Oscillator Fault Raw
                                              // Interrupt Status
  #define SYSCTL_RIS_BORRIS       0x00000002  // Brown-Out Reset Raw Interrupt
                                              // Status
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_IMC register.
  //
  //*****************************************************************************
  #define SYSCTL_IMC_MOSCPUPIM    0x00000100  // MOSC Power Up Interrupt Mask
  #define SYSCTL_IMC_USBPLLLIM    0x00000080  // USB PLL Lock Interrupt Mask
  #define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask
  #define SYSCTL_IMC_MOFIM        0x00000008  // Main Oscillator Fault Interrupt
                                              // Mask
  #define SYSCTL_IMC_BORIM        0x00000002  // Brown-Out Reset Interrupt Mask
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_MISC register.
  //
  //*****************************************************************************
  #define SYSCTL_MISC_MOSCPUPMIS  0x00000100  // MOSC Power Up Masked Interrupt
                                              // Status
  #define SYSCTL_MISC_USBPLLLMIS  0x00000080  // USB PLL Lock Masked Interrupt
                                              // Status
  #define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt Status
  #define SYSCTL_MISC_MOFMIS      0x00000008  // Main Oscillator Fault Masked
                                              // Interrupt Status
  #define SYSCTL_MISC_BORMIS      0x00000002  // BOR Masked Interrupt Status
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RESC register.
  //
  //*****************************************************************************
  #define SYSCTL_RESC_MOSCFAIL    0x00010000  // MOSC Failure Reset
  #define SYSCTL_RESC_WDT1        0x00000020  // Watchdog Timer 1 Reset
  #define SYSCTL_RESC_SW          0x00000010  // Software Reset
  #define SYSCTL_RESC_WDT0        0x00000008  // Watchdog Timer 0 Reset
  #define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset
  #define SYSCTL_RESC_POR         0x00000002  // Power-On Reset
  #define SYSCTL_RESC_EXT         0x00000001  // External Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCC register.
  //
  //*****************************************************************************
  #define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating
  #define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor
  #define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider
  #define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down
  #define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass
  #define SYSCTL_RCC_XTAL_M       0x000007C0  // Crystal Value
  #define SYSCTL_RCC_XTAL_4MHZ    0x00000180  // 4 MHz
  #define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0  // 4.096 MHz
  #define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // 4.9152 MHz
  #define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // 5 MHz
  #define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // 5.12 MHz
  #define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz
  #define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // 6.144 MHz
  #define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // 7.3728 MHz
  #define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // 8 MHz
  #define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // 8.192 MHz
  #define SYSCTL_RCC_XTAL_10MHZ   0x00000400  // 10 MHz
  #define SYSCTL_RCC_XTAL_12MHZ   0x00000440  // 12 MHz
  #define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480  // 12.288 MHz
  #define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0  // 13.56 MHz
  #define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500  // 14.31818 MHz
  #define SYSCTL_RCC_XTAL_16MHZ   0x00000540  // 16 MHz
  #define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580  // 16.384 MHz
  #define SYSCTL_RCC_XTAL_18MHZ   0x000005C0  // 18.0 MHz
  #define SYSCTL_RCC_XTAL_20MHZ   0x00000600  // 20.0 MHz
  #define SYSCTL_RCC_XTAL_24MHZ   0x00000640  // 24.0 MHz
  #define SYSCTL_RCC_XTAL_25MHZ   0x00000680  // 25.0 MHz
  #define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source
  #define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // MOSC
  #define SYSCTL_RCC_OSCSRC_INT   0x00000010  // IOSC
  #define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // IOSC/4
  #define SYSCTL_RCC_OSCSRC_30    0x00000030  // 30 kHz
  #define SYSCTL_RCC_IOSCDIS      0x00000002  // Internal Oscillator Disable
  #define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable
  #define SYSCTL_RCC_SYSDIV_S     23
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_GPIOHBCTL_PORTF  0x00000020  // Port F Advanced High-Performance
                                              // Bus
  #define SYSCTL_GPIOHBCTL_PORTE  0x00000010  // Port E Advanced High-Performance
                                              // Bus
  #define SYSCTL_GPIOHBCTL_PORTD  0x00000008  // Port D Advanced High-Performance
                                              // Bus
  #define SYSCTL_GPIOHBCTL_PORTC  0x00000004  // Port C Advanced High-Performance
                                              // Bus
  #define SYSCTL_GPIOHBCTL_PORTB  0x00000002  // Port B Advanced High-Performance
                                              // Bus
  #define SYSCTL_GPIOHBCTL_PORTA  0x00000001  // Port A Advanced High-Performance
                                              // Bus
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCC2 register.
  //
  //*****************************************************************************
  #define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2
  #define SYSCTL_RCC2_DIV400      0x40000000  // Divide PLL as 400 MHz vs. 200
                                              // MHz
  #define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor 2
  #define SYSCTL_RCC2_SYSDIV2_2   0x00800000  // System clock /2
  #define SYSCTL_RCC2_SYSDIV2_3   0x01000000  // System clock /3
  #define SYSCTL_RCC2_SYSDIV2_4   0x01800000  // System clock /4
  #define SYSCTL_RCC2_SYSDIV2_5   0x02000000  // System clock /5
  #define SYSCTL_RCC2_SYSDIV2_6   0x02800000  // System clock /6
  #define SYSCTL_RCC2_SYSDIV2_7   0x03000000  // System clock /7
  #define SYSCTL_RCC2_SYSDIV2_8   0x03800000  // System clock /8
  #define SYSCTL_RCC2_SYSDIV2_9   0x04000000  // System clock /9
  #define SYSCTL_RCC2_SYSDIV2_10  0x04800000  // System clock /10
  #define SYSCTL_RCC2_SYSDIV2_11  0x05000000  // System clock /11
  #define SYSCTL_RCC2_SYSDIV2_12  0x05800000  // System clock /12
  #define SYSCTL_RCC2_SYSDIV2_13  0x06000000  // System clock /13
  #define SYSCTL_RCC2_SYSDIV2_14  0x06800000  // System clock /14
  #define SYSCTL_RCC2_SYSDIV2_15  0x07000000  // System clock /15
  #define SYSCTL_RCC2_SYSDIV2_16  0x07800000  // System clock /16
  #define SYSCTL_RCC2_SYSDIV2_17  0x08000000  // System clock /17
  #define SYSCTL_RCC2_SYSDIV2_18  0x08800000  // System clock /18
  #define SYSCTL_RCC2_SYSDIV2_19  0x09000000  // System clock /19
  #define SYSCTL_RCC2_SYSDIV2_20  0x09800000  // System clock /20
  #define SYSCTL_RCC2_SYSDIV2_21  0x0A000000  // System clock /21
  #define SYSCTL_RCC2_SYSDIV2_22  0x0A800000  // System clock /22
  #define SYSCTL_RCC2_SYSDIV2_23  0x0B000000  // System clock /23
  #define SYSCTL_RCC2_SYSDIV2_24  0x0B800000  // System clock /24
  #define SYSCTL_RCC2_SYSDIV2_25  0x0C000000  // System clock /25
  #define SYSCTL_RCC2_SYSDIV2_26  0x0C800000  // System clock /26
  #define SYSCTL_RCC2_SYSDIV2_27  0x0D000000  // System clock /27
  #define SYSCTL_RCC2_SYSDIV2_28  0x0D800000  // System clock /28
  #define SYSCTL_RCC2_SYSDIV2_29  0x0E000000  // System clock /29
  #define SYSCTL_RCC2_SYSDIV2_30  0x0E800000  // System clock /30
  #define SYSCTL_RCC2_SYSDIV2_31  0x0F000000  // System clock /31
  #define SYSCTL_RCC2_SYSDIV2_32  0x0F800000  // System clock /32
  #define SYSCTL_RCC2_SYSDIV2_33  0x10000000  // System clock /33
  #define SYSCTL_RCC2_SYSDIV2_34  0x10800000  // System clock /34
  #define SYSCTL_RCC2_SYSDIV2_35  0x11000000  // System clock /35
  #define SYSCTL_RCC2_SYSDIV2_36  0x11800000  // System clock /36
  #define SYSCTL_RCC2_SYSDIV2_37  0x12000000  // System clock /37
  #define SYSCTL_RCC2_SYSDIV2_38  0x12800000  // System clock /38
  #define SYSCTL_RCC2_SYSDIV2_39  0x13000000  // System clock /39
  #define SYSCTL_RCC2_SYSDIV2_40  0x13800000  // System clock /40
  #define SYSCTL_RCC2_SYSDIV2_41  0x14000000  // System clock /41
  #define SYSCTL_RCC2_SYSDIV2_42  0x14800000  // System clock /42
  #define SYSCTL_RCC2_SYSDIV2_43  0x15000000  // System clock /43
  #define SYSCTL_RCC2_SYSDIV2_44  0x15800000  // System clock /44
  #define SYSCTL_RCC2_SYSDIV2_45  0x16000000  // System clock /45
  #define SYSCTL_RCC2_SYSDIV2_46  0x16800000  // System clock /46
  #define SYSCTL_RCC2_SYSDIV2_47  0x17000000  // System clock /47
  #define SYSCTL_RCC2_SYSDIV2_48  0x17800000  // System clock /48
  #define SYSCTL_RCC2_SYSDIV2_49  0x18000000  // System clock /49
  #define SYSCTL_RCC2_SYSDIV2_50  0x18800000  // System clock /50
  #define SYSCTL_RCC2_SYSDIV2_51  0x19000000  // System clock /51
  #define SYSCTL_RCC2_SYSDIV2_52  0x19800000  // System clock /52
  #define SYSCTL_RCC2_SYSDIV2_53  0x1A000000  // System clock /53
  #define SYSCTL_RCC2_SYSDIV2_54  0x1A800000  // System clock /54
  #define SYSCTL_RCC2_SYSDIV2_55  0x1B000000  // System clock /55
  #define SYSCTL_RCC2_SYSDIV2_56  0x1B800000  // System clock /56
  #define SYSCTL_RCC2_SYSDIV2_57  0x1C000000  // System clock /57
  #define SYSCTL_RCC2_SYSDIV2_58  0x1C800000  // System clock /58
  #define SYSCTL_RCC2_SYSDIV2_59  0x1D000000  // System clock /59
  #define SYSCTL_RCC2_SYSDIV2_60  0x1D800000  // System clock /60
  #define SYSCTL_RCC2_SYSDIV2_61  0x1E000000  // System clock /61
  #define SYSCTL_RCC2_SYSDIV2_62  0x1E800000  // System clock /62
  #define SYSCTL_RCC2_SYSDIV2_63  0x1F000000  // System clock /63
  #define SYSCTL_RCC2_SYSDIV2_64  0x1F800000  // System clock /64
  #define SYSCTL_RCC2_SYSDIV2LSB  0x00400000  // Additional LSB for SYSDIV2
  #define SYSCTL_RCC2_USBPWRDN    0x00004000  // Power-Down USB PLL
  #define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL 2
  #define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL Bypass 2
  #define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source 2
  #define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  // MOSC
  #define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // PIOSC
  #define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // PIOSC/4
  #define SYSCTL_RCC2_OSCSRC2_30  0x00000030  // 30 kHz
  #define SYSCTL_RCC2_OSCSRC2_32  0x00000070  // 32.768 kHz
  #define SYSCTL_RCC2_SYSDIV2_S   23
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
  //
  //*****************************************************************************
  #define SYSCTL_MOSCCTL_NOXTAL   0x00000004  // No Crystal Connected
  #define SYSCTL_MOSCCTL_MOSCIM   0x00000002  // MOSC Failure Action
  #define SYSCTL_MOSCCTL_CVAL     0x00000001  // Clock Validation for MOSC
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGC0 register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
  #define SYSCTL_RCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
  #define SYSCTL_RCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
  #define SYSCTL_RCGC0_PWM0       0x00100000  // PWM Clock Gating Control
  #define SYSCTL_RCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
  #define SYSCTL_RCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
  #define SYSCTL_RCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed
  #define SYSCTL_RCGC0_ADC1SPD_125K \
                                  0x00000000  // 125K samples/second
  #define SYSCTL_RCGC0_ADC1SPD_250K \
                                  0x00000400  // 250K samples/second
  #define SYSCTL_RCGC0_ADC1SPD_500K \
                                  0x00000800  // 500K samples/second
  #define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00  // 1M samples/second
  #define SYSCTL_RCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed
  #define SYSCTL_RCGC0_ADC0SPD_125K \
                                  0x00000000  // 125K samples/second
  #define SYSCTL_RCGC0_ADC0SPD_250K \
                                  0x00000100  // 250K samples/second
  #define SYSCTL_RCGC0_ADC0SPD_500K \
                                  0x00000200  // 500K samples/second
  #define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300  // 1M samples/second
  #define SYSCTL_RCGC0_HIB        0x00000040  // HIB Clock Gating Control
  #define SYSCTL_RCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGC1 register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
  #define SYSCTL_RCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
  #define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
  #define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
  #define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
  #define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
  #define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
  #define SYSCTL_RCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
  #define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
  #define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
  #define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
  #define SYSCTL_RCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
  #define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
  #define SYSCTL_RCGC1_UART2      0x00000004  // UART2 Clock Gating Control
  #define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control
  #define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGC2 register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGC2_USB0       0x00010000  // USB0 Clock Gating Control
  #define SYSCTL_RCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
  #define SYSCTL_RCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
  #define SYSCTL_RCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
  #define SYSCTL_RCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
  #define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
  #define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
  #define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
  #define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
  #define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
  #define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGC0 register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
  #define SYSCTL_SCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
  #define SYSCTL_SCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
  #define SYSCTL_SCGC0_PWM0       0x00100000  // PWM Clock Gating Control
  #define SYSCTL_SCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
  #define SYSCTL_SCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
  #define SYSCTL_SCGC0_HIB        0x00000040  // HIB Clock Gating Control
  #define SYSCTL_SCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGC1 register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
  #define SYSCTL_SCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
  #define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
  #define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
  #define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
  #define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
  #define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
  #define SYSCTL_SCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
  #define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
  #define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
  #define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
  #define SYSCTL_SCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
  #define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
  #define SYSCTL_SCGC1_UART2      0x00000004  // UART2 Clock Gating Control
  #define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control
  #define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGC2 register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGC2_USB0       0x00010000  // USB0 Clock Gating Control
  #define SYSCTL_SCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
  #define SYSCTL_SCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
  #define SYSCTL_SCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
  #define SYSCTL_SCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
  #define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
  #define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
  #define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
  #define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
  #define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
  #define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGC0 register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
  #define SYSCTL_DCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
  #define SYSCTL_DCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
  #define SYSCTL_DCGC0_PWM0       0x00100000  // PWM Clock Gating Control
  #define SYSCTL_DCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
  #define SYSCTL_DCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
  #define SYSCTL_DCGC0_HIB        0x00000040  // HIB Clock Gating Control
  #define SYSCTL_DCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGC1 register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGC1_COMP2      0x04000000  // Analog Comparator 2 Clock Gating
  #define SYSCTL_DCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
  #define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
  #define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
  #define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
  #define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
  #define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
  #define SYSCTL_DCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
  #define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
  #define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
  #define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
  #define SYSCTL_DCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
  #define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
  #define SYSCTL_DCGC1_UART2      0x00000004  // UART2 Clock Gating Control
  #define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control
  #define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGC2 register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGC2_USB0       0x00010000  // USB0 Clock Gating Control
  #define SYSCTL_DCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
  #define SYSCTL_DCGC2_GPIOJ      0x00000100  // Port J Clock Gating Control
  #define SYSCTL_DCGC2_GPIOH      0x00000080  // Port H Clock Gating Control
  #define SYSCTL_DCGC2_GPIOG      0x00000040  // Port G Clock Gating Control
  #define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
  #define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
  #define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
  #define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
  #define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
  #define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override
  #define SYSCTL_DSLPCLKCFG_D_1   0x00000000  // System clock /1
  #define SYSCTL_DSLPCLKCFG_D_2   0x00800000  // System clock /2
  #define SYSCTL_DSLPCLKCFG_D_3   0x01000000  // System clock /3
  #define SYSCTL_DSLPCLKCFG_D_4   0x01800000  // System clock /4
  #define SYSCTL_DSLPCLKCFG_D_64  0x1F800000  // System clock /64
  #define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source
  #define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000  // MOSC
  #define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // PIOSC
  #define SYSCTL_DSLPCLKCFG_O_30  0x00000030  // 30 kHz
  #define SYSCTL_DSLPCLKCFG_O_32  0x00000070  // 32.768 kHz
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SYSPROP register.
  //
  //*****************************************************************************
  #define SYSCTL_SYSPROP_FPU      0x00000001  // FPU Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PIOSCCAL
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_PIOSCCAL_UTEN    0x80000000  // Use User Trim Value
  #define SYSCTL_PIOSCCAL_CAL     0x00000200  // Start Calibration
  #define SYSCTL_PIOSCCAL_UPDATE  0x00000100  // Update Trim
  #define SYSCTL_PIOSCCAL_UT_M    0x0000007F  // User Trim Value
  #define SYSCTL_PIOSCCAL_UT_S    0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_PIOSCSTAT_DT_M   0x007F0000  // Default Trim Value
  #define SYSCTL_PIOSCSTAT_CR_M   0x00000300  // Calibration Result
  #define SYSCTL_PIOSCSTAT_CRNONE 0x00000000  // Calibration has not been
                                              // attempted
  #define SYSCTL_PIOSCSTAT_CRPASS 0x00000100  // The last calibration operation
                                              // completed to meet 1% accuracy
  #define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200  // The last calibration operation
                                              // failed to meet 1% accuracy
  #define SYSCTL_PIOSCSTAT_CT_M   0x0000007F  // Calibration Trim Value
  #define SYSCTL_PIOSCSTAT_DT_S   16
  #define SYSCTL_PIOSCSTAT_CT_S   0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PLLFREQ0
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00  // PLL M Fractional Value
  #define SYSCTL_PLLFREQ0_MINT_M  0x000003FF  // PLL M Integer Value
  #define SYSCTL_PLLFREQ0_MFRAC_S 10
  #define SYSCTL_PLLFREQ0_MINT_S  0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PLLFREQ1
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_PLLFREQ1_Q_M     0x00001F00  // PLL Q Value
  #define SYSCTL_PLLFREQ1_N_M     0x0000001F  // PLL N Value
  #define SYSCTL_PLLFREQ1_Q_S     8
  #define SYSCTL_PLLFREQ1_N_S     0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PLLSTAT register.
  //
  //*****************************************************************************
  #define SYSCTL_PLLSTAT_LOCK     0x00000001  // PLL Lock
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DC9 register.
  //
  //*****************************************************************************
  #define SYSCTL_DC9_ADC1DC7      0x00800000  // ADC1 DC7 Present
  #define SYSCTL_DC9_ADC1DC6      0x00400000  // ADC1 DC6 Present
  #define SYSCTL_DC9_ADC1DC5      0x00200000  // ADC1 DC5 Present
  #define SYSCTL_DC9_ADC1DC4      0x00100000  // ADC1 DC4 Present
  #define SYSCTL_DC9_ADC1DC3      0x00080000  // ADC1 DC3 Present
  #define SYSCTL_DC9_ADC1DC2      0x00040000  // ADC1 DC2 Present
  #define SYSCTL_DC9_ADC1DC1      0x00020000  // ADC1 DC1 Present
  #define SYSCTL_DC9_ADC1DC0      0x00010000  // ADC1 DC0 Present
  #define SYSCTL_DC9_ADC0DC7      0x00000080  // ADC0 DC7 Present
  #define SYSCTL_DC9_ADC0DC6      0x00000040  // ADC0 DC6 Present
  #define SYSCTL_DC9_ADC0DC5      0x00000020  // ADC0 DC5 Present
  #define SYSCTL_DC9_ADC0DC4      0x00000010  // ADC0 DC4 Present
  #define SYSCTL_DC9_ADC0DC3      0x00000008  // ADC0 DC3 Present
  #define SYSCTL_DC9_ADC0DC2      0x00000004  // ADC0 DC2 Present
  #define SYSCTL_DC9_ADC0DC1      0x00000002  // ADC0 DC1 Present
  #define SYSCTL_DC9_ADC0DC0      0x00000001  // ADC0 DC0 Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
  //
  //*****************************************************************************
  #define SYSCTL_NVMSTAT_TPSW     0x00000010  // Third Party Software Present
  #define SYSCTL_NVMSTAT_FWB      0x00000001  // 32 Word Flash Write Buffer
                                              // Active
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPWD register.
  //
  //*****************************************************************************
  #define SYSCTL_PPWD_P1          0x00000002  // Watchdog Timer 1 Present
  #define SYSCTL_PPWD_P0          0x00000001  // Watchdog Timer 0 Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPTIMER register.
  //
  //*****************************************************************************
  #define SYSCTL_PPTIMER_P5       0x00000020  // Timer 5 Present
  #define SYSCTL_PPTIMER_P4       0x00000010  // Timer 4 Present
  #define SYSCTL_PPTIMER_P3       0x00000008  // Timer 3 Present
  #define SYSCTL_PPTIMER_P2       0x00000004  // Timer 2 Present
  #define SYSCTL_PPTIMER_P1       0x00000002  // Timer 1 Present
  #define SYSCTL_PPTIMER_P0       0x00000001  // Timer 0 Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPGPIO register.
  //
  //*****************************************************************************
  #define SYSCTL_PPGPIO_P14       0x00004000  // GPIO Port Q Present
  #define SYSCTL_PPGPIO_P13       0x00002000  // GPIO Port P Present
  #define SYSCTL_PPGPIO_P12       0x00001000  // GPIO Port N Present
  #define SYSCTL_PPGPIO_P11       0x00000800  // GPIO Port M Present
  #define SYSCTL_PPGPIO_P10       0x00000400  // GPIO Port L Present
  #define SYSCTL_PPGPIO_P9        0x00000200  // GPIO Port K Present
  #define SYSCTL_PPGPIO_P8        0x00000100  // GPIO Port J Present
  #define SYSCTL_PPGPIO_P7        0x00000080  // GPIO Port H Present
  #define SYSCTL_PPGPIO_P6        0x00000040  // GPIO Port G Present
  #define SYSCTL_PPGPIO_P5        0x00000020  // GPIO Port F Present
  #define SYSCTL_PPGPIO_P4        0x00000010  // GPIO Port E Present
  #define SYSCTL_PPGPIO_P3        0x00000008  // GPIO Port D Present
  #define SYSCTL_PPGPIO_P2        0x00000004  // GPIO Port C Present
  #define SYSCTL_PPGPIO_P1        0x00000002  // GPIO Port B Present
  #define SYSCTL_PPGPIO_P0        0x00000001  // GPIO Port A Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPDMA register.
  //
  //*****************************************************************************
  #define SYSCTL_PPDMA_P0         0x00000001  // uDMA Module Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPHIB register.
  //
  //*****************************************************************************
  #define SYSCTL_PPHIB_P0         0x00000001  // Hibernation Module Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPUART register.
  //
  //*****************************************************************************
  #define SYSCTL_PPUART_P7        0x00000080  // UART Module 7 Present
  #define SYSCTL_PPUART_P6        0x00000040  // UART Module 6 Present
  #define SYSCTL_PPUART_P5        0x00000020  // UART Module 5 Present
  #define SYSCTL_PPUART_P4        0x00000010  // UART Module 4 Present
  #define SYSCTL_PPUART_P3        0x00000008  // UART Module 3 Present
  #define SYSCTL_PPUART_P2        0x00000004  // UART Module 2 Present
  #define SYSCTL_PPUART_P1        0x00000002  // UART Module 1 Present
  #define SYSCTL_PPUART_P0        0x00000001  // UART Module 0 Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPSSI register.
  //
  //*****************************************************************************
  #define SYSCTL_PPSSI_P3         0x00000008  // SSI Module 3 Present
  #define SYSCTL_PPSSI_P2         0x00000004  // SSI Module 2 Present
  #define SYSCTL_PPSSI_P1         0x00000002  // SSI Module 1 Present
  #define SYSCTL_PPSSI_P0         0x00000001  // SSI Module 0 Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPI2C register.
  //
  //*****************************************************************************
  #define SYSCTL_PPI2C_P5         0x00000020  // I2C Module 5 Present
  #define SYSCTL_PPI2C_P4         0x00000010  // I2C Module 4 Present
  #define SYSCTL_PPI2C_P3         0x00000008  // I2C Module 3 Present
  #define SYSCTL_PPI2C_P2         0x00000004  // I2C Module 2 Present
  #define SYSCTL_PPI2C_P1         0x00000002  // I2C Module 1 Present
  #define SYSCTL_PPI2C_P0         0x00000001  // I2C Module 0 Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPUSB register.
  //
  //*****************************************************************************
  #define SYSCTL_PPUSB_P0         0x00000001  // USB Module Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPCAN register.
  //
  //*****************************************************************************
  #define SYSCTL_PPCAN_P1         0x00000002  // CAN Module 1 Present
  #define SYSCTL_PPCAN_P0         0x00000001  // CAN Module 0 Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPADC register.
  //
  //*****************************************************************************
  #define SYSCTL_PPADC_P1         0x00000002  // ADC Module 1 Present
  #define SYSCTL_PPADC_P0         0x00000001  // ADC Module 0 Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPACMP register.
  //
  //*****************************************************************************
  #define SYSCTL_PPACMP_P0        0x00000001  // Analog Comparator Module Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPPWM register.
  //
  //*****************************************************************************
  #define SYSCTL_PPPWM_P1         0x00000002  // PWM Module 1 Present
  #define SYSCTL_PPPWM_P0         0x00000001  // PWM Module 0 Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPQEI register.
  //
  //*****************************************************************************
  #define SYSCTL_PPQEI_P1         0x00000002  // QEI Module 1 Present
  #define SYSCTL_PPQEI_P0         0x00000001  // QEI Module 0 Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPEEPROM
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_PPEEPROM_P0      0x00000001  // EEPROM Module Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PPWTIMER
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_PPWTIMER_P5      0x00000020  // Wide Timer 5 Present
  #define SYSCTL_PPWTIMER_P4      0x00000010  // Wide Timer 4 Present
  #define SYSCTL_PPWTIMER_P3      0x00000008  // Wide Timer 3 Present
  #define SYSCTL_PPWTIMER_P2      0x00000004  // Wide Timer 2 Present
  #define SYSCTL_PPWTIMER_P1      0x00000002  // Wide Timer 1 Present
  #define SYSCTL_PPWTIMER_P0      0x00000001  // Wide Timer 0 Present
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRWD register.
  //
  //*****************************************************************************
  #define SYSCTL_SRWD_R1          0x00000002  // Watchdog Timer 1 Software Reset
  #define SYSCTL_SRWD_R0          0x00000001  // Watchdog Timer 0 Software Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRTIMER register.
  //
  //*****************************************************************************
  #define SYSCTL_SRTIMER_R5       0x00000020  // Timer 5 Software Reset
  #define SYSCTL_SRTIMER_R4       0x00000010  // Timer 4 Software Reset
  #define SYSCTL_SRTIMER_R3       0x00000008  // Timer 3 Software Reset
  #define SYSCTL_SRTIMER_R2       0x00000004  // Timer 2 Software Reset
  #define SYSCTL_SRTIMER_R1       0x00000002  // Timer 1 Software Reset
  #define SYSCTL_SRTIMER_R0       0x00000001  // Timer 0 Software Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRGPIO register.
  //
  //*****************************************************************************
  #define SYSCTL_SRGPIO_R14       0x00004000  // GPIO Port Q Software Reset
  #define SYSCTL_SRGPIO_R13       0x00002000  // GPIO Port P Software Reset
  #define SYSCTL_SRGPIO_R12       0x00001000  // GPIO Port N Software Reset
  #define SYSCTL_SRGPIO_R11       0x00000800  // GPIO Port M Software Reset
  #define SYSCTL_SRGPIO_R10       0x00000400  // GPIO Port L Software Reset
  #define SYSCTL_SRGPIO_R9        0x00000200  // GPIO Port K Software Reset
  #define SYSCTL_SRGPIO_R8        0x00000100  // GPIO Port J Software Reset
  #define SYSCTL_SRGPIO_R7        0x00000080  // GPIO Port H Software Reset
  #define SYSCTL_SRGPIO_R6        0x00000040  // GPIO Port G Software Reset
  #define SYSCTL_SRGPIO_R5        0x00000020  // GPIO Port F Software Reset
  #define SYSCTL_SRGPIO_R4        0x00000010  // GPIO Port E Software Reset
  #define SYSCTL_SRGPIO_R3        0x00000008  // GPIO Port D Software Reset
  #define SYSCTL_SRGPIO_R2        0x00000004  // GPIO Port C Software Reset
  #define SYSCTL_SRGPIO_R1        0x00000002  // GPIO Port B Software Reset
  #define SYSCTL_SRGPIO_R0        0x00000001  // GPIO Port A Software Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRDMA register.
  //
  //*****************************************************************************
  #define SYSCTL_SRDMA_R0         0x00000001  // uDMA Module Software Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRHIB register.
  //
  //*****************************************************************************
  #define SYSCTL_SRHIB_R0         0x00000001  // Hibernation Module Software
                                              // Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRUART register.
  //
  //*****************************************************************************
  #define SYSCTL_SRUART_R7        0x00000080  // UART Module 7 Software Reset
  #define SYSCTL_SRUART_R6        0x00000040  // UART Module 6 Software Reset
  #define SYSCTL_SRUART_R5        0x00000020  // UART Module 5 Software Reset
  #define SYSCTL_SRUART_R4        0x00000010  // UART Module 4 Software Reset
  #define SYSCTL_SRUART_R3        0x00000008  // UART Module 3 Software Reset
  #define SYSCTL_SRUART_R2        0x00000004  // UART Module 2 Software Reset
  #define SYSCTL_SRUART_R1        0x00000002  // UART Module 1 Software Reset
  #define SYSCTL_SRUART_R0        0x00000001  // UART Module 0 Software Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRSSI register.
  //
  //*****************************************************************************
  #define SYSCTL_SRSSI_R3         0x00000008  // SSI Module 3 Software Reset
  #define SYSCTL_SRSSI_R2         0x00000004  // SSI Module 2 Software Reset
  #define SYSCTL_SRSSI_R1         0x00000002  // SSI Module 1 Software Reset
  #define SYSCTL_SRSSI_R0         0x00000001  // SSI Module 0 Software Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRI2C register.
  //
  //*****************************************************************************
  #define SYSCTL_SRI2C_R5         0x00000020  // I2C Module 5 Software Reset
  #define SYSCTL_SRI2C_R4         0x00000010  // I2C Module 4 Software Reset
  #define SYSCTL_SRI2C_R3         0x00000008  // I2C Module 3 Software Reset
  #define SYSCTL_SRI2C_R2         0x00000004  // I2C Module 2 Software Reset
  #define SYSCTL_SRI2C_R1         0x00000002  // I2C Module 1 Software Reset
  #define SYSCTL_SRI2C_R0         0x00000001  // I2C Module 0 Software Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRUSB register.
  //
  //*****************************************************************************
  #define SYSCTL_SRUSB_R0         0x00000001  // USB Module Software Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRCAN register.
  //
  //*****************************************************************************
  #define SYSCTL_SRCAN_R1         0x00000002  // CAN Module 1 Software Reset
  #define SYSCTL_SRCAN_R0         0x00000001  // CAN Module 0 Software Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRADC register.
  //
  //*****************************************************************************
  #define SYSCTL_SRADC_R1         0x00000002  // ADC Module 1 Software Reset
  #define SYSCTL_SRADC_R0         0x00000001  // ADC Module 0 Software Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRACMP register.
  //
  //*****************************************************************************
  #define SYSCTL_SRACMP_R0        0x00000001  // Analog Comparator Module 0
                                              // Software Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SREEPROM
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_SREEPROM_R0      0x00000001  // EEPROM Module Software Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SRWTIMER
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_SRWTIMER_R5      0x00000020  // Wide Timer 5 Software Reset
  #define SYSCTL_SRWTIMER_R4      0x00000010  // Wide Timer 4 Software Reset
  #define SYSCTL_SRWTIMER_R3      0x00000008  // Wide Timer 3 Software Reset
  #define SYSCTL_SRWTIMER_R2      0x00000004  // Wide Timer 2 Software Reset
  #define SYSCTL_SRWTIMER_R1      0x00000002  // Wide Timer 1 Software Reset
  #define SYSCTL_SRWTIMER_R0      0x00000001  // Wide Timer 0 Software Reset
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCWD register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCWD_R1        0x00000002  // Watchdog Timer 1 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCWD_R0        0x00000001  // Watchdog Timer 0 Run Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCTIMER
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCTIMER_R5     0x00000020  // Timer 5 Run Mode Clock Gating
                                              // Control
  #define SYSCTL_RCGCTIMER_R4     0x00000010  // Timer 4 Run Mode Clock Gating
                                              // Control
  #define SYSCTL_RCGCTIMER_R3     0x00000008  // Timer 3 Run Mode Clock Gating
                                              // Control
  #define SYSCTL_RCGCTIMER_R2     0x00000004  // Timer 2 Run Mode Clock Gating
                                              // Control
  #define SYSCTL_RCGCTIMER_R1     0x00000002  // Timer 1 Run Mode Clock Gating
                                              // Control
  #define SYSCTL_RCGCTIMER_R0     0x00000001  // Timer 0 Run Mode Clock Gating
                                              // Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCGPIO
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCGPIO_R14     0x00004000  // GPIO Port Q Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCGPIO_R13     0x00002000  // GPIO Port P Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCGPIO_R12     0x00001000  // GPIO Port N Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCGPIO_R11     0x00000800  // GPIO Port M Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCGPIO_R10     0x00000400  // GPIO Port L Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCGPIO_R9      0x00000200  // GPIO Port K Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCGPIO_R8      0x00000100  // GPIO Port J Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCGPIO_R7      0x00000080  // GPIO Port H Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCGPIO_R6      0x00000040  // GPIO Port G Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCGPIO_R5      0x00000020  // GPIO Port F Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCGPIO_R4      0x00000010  // GPIO Port E Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCGPIO_R3      0x00000008  // GPIO Port D Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCGPIO_R2      0x00000004  // GPIO Port C Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCGPIO_R1      0x00000002  // GPIO Port B Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCGPIO_R0      0x00000001  // GPIO Port A Run Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCDMA register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCDMA_R0       0x00000001  // uDMA Module Run Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCHIB register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCHIB_R0       0x00000001  // Hibernation Module Run Mode
                                              // Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCUART
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCUART_R7      0x00000080  // UART Module 7 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCUART_R6      0x00000040  // UART Module 6 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCUART_R5      0x00000020  // UART Module 5 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCUART_R4      0x00000010  // UART Module 4 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCUART_R3      0x00000008  // UART Module 3 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCUART_R2      0x00000004  // UART Module 2 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCUART_R1      0x00000002  // UART Module 1 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCUART_R0      0x00000001  // UART Module 0 Run Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCSSI register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCSSI_R3       0x00000008  // SSI Module 3 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCSSI_R2       0x00000004  // SSI Module 2 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCSSI_R1       0x00000002  // SSI Module 1 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCSSI_R0       0x00000001  // SSI Module 0 Run Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCI2C register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCI2C_R5       0x00000020  // I2C Module 5 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCI2C_R4       0x00000010  // I2C Module 4 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCI2C_R3       0x00000008  // I2C Module 3 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCI2C_R2       0x00000004  // I2C Module 2 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCI2C_R1       0x00000002  // I2C Module 1 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCI2C_R0       0x00000001  // I2C Module 0 Run Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCUSB register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCUSB_R0       0x00000001  // USB Module Run Mode Clock Gating
                                              // Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCCAN register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCCAN_R1       0x00000002  // CAN Module 1 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCCAN_R0       0x00000001  // CAN Module 0 Run Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCADC register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCADC_R1       0x00000002  // ADC Module 1 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCADC_R0       0x00000001  // ADC Module 0 Run Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCACMP
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCACMP_R0      0x00000001  // Analog Comparator Module 0 Run
                                              // Mode Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCEEPROM
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCEEPROM_R0    0x00000001  // EEPROM Module Run Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCWTIMER
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCWTIMER_R5    0x00000020  // Wide Timer 5 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCWTIMER_R4    0x00000010  // Wide Timer 4 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCWTIMER_R3    0x00000008  // Wide Timer 3 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCWTIMER_R2    0x00000004  // Wide Timer 2 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCWTIMER_R1    0x00000002  // Wide Timer 1 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCWTIMER_R0    0x00000001  // Wide Timer 0 Run Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCPWM
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCPWM_R1    0x00000002  
  #define SYSCTL_RCGCPWM_R0    0x00000001  
                                              
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGCWD register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGCWD_S1        0x00000002  // Watchdog Timer 1 Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_SCGCWD_S0        0x00000001  // Watchdog Timer 0 Sleep Mode
                                              // Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGCTIMER
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGCTIMER_S5     0x00000020  // Timer 5 Sleep Mode Clock Gating
                                              // Control
  #define SYSCTL_SCGCTIMER_S4     0x00000010  // Timer 4 Sleep Mode Clock Gating
                                              // Control
  #define SYSCTL_SCGCTIMER_S3     0x00000008  // Timer 3 Sleep Mode Clock Gating
                                              // Control
  #define SYSCTL_SCGCTIMER_S2     0x00000004  // Timer 2 Sleep Mode Clock Gating
                                              // Control
  #define SYSCTL_SCGCTIMER_S1     0x00000002  // Timer 1 Sleep Mode Clock Gating
                                              // Control
  #define SYSCTL_SCGCTIMER_S0     0x00000001  // Timer 0 Sleep Mode Clock Gating
                                              // Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGCGPIO
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGCGPIO_S14     0x00004000  // GPIO Port Q Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCGPIO_S13     0x00002000  // GPIO Port P Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCGPIO_S12     0x00001000  // GPIO Port N Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCGPIO_S11     0x00000800  // GPIO Port M Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCGPIO_S10     0x00000400  // GPIO Port L Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCGPIO_S9      0x00000200  // GPIO Port K Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCGPIO_S8      0x00000100  // GPIO Port J Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCGPIO_S7      0x00000080  // GPIO Port H Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCGPIO_S6      0x00000040  // GPIO Port G Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCGPIO_S5      0x00000020  // GPIO Port F Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCGPIO_S4      0x00000010  // GPIO Port E Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCGPIO_S3      0x00000008  // GPIO Port D Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCGPIO_S2      0x00000004  // GPIO Port C Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCGPIO_S1      0x00000002  // GPIO Port B Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCGPIO_S0      0x00000001  // GPIO Port A Sleep Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGCDMA register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGCDMA_S0       0x00000001  // uDMA Module Sleep Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGCHIB register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGCHIB_S0       0x00000001  // Hibernation Module Sleep Mode
                                              // Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGCUART
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGCUART_S7      0x00000080  // UART Module 7 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCUART_S6      0x00000040  // UART Module 6 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCUART_S5      0x00000020  // UART Module 5 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCUART_S4      0x00000010  // UART Module 4 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCUART_S3      0x00000008  // UART Module 3 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCUART_S2      0x00000004  // UART Module 2 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCUART_S1      0x00000002  // UART Module 1 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCUART_S0      0x00000001  // UART Module 0 Sleep Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGCSSI register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGCSSI_S3       0x00000008  // SSI Module 3 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCSSI_S2       0x00000004  // SSI Module 2 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCSSI_S1       0x00000002  // SSI Module 1 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCSSI_S0       0x00000001  // SSI Module 0 Sleep Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGCI2C register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGCI2C_S5       0x00000020  // I2C Module 5 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCI2C_S4       0x00000010  // I2C Module 4 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCI2C_S3       0x00000008  // I2C Module 3 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCI2C_S2       0x00000004  // I2C Module 2 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCI2C_S1       0x00000002  // I2C Module 1 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCI2C_S0       0x00000001  // I2C Module 0 Sleep Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGCUSB register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGCUSB_S0       0x00000001  // USB Module Sleep Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGCCAN register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGCCAN_S1       0x00000002  // CAN Module 1 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCCAN_S0       0x00000001  // CAN Module 0 Sleep Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGCADC register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGCADC_S1       0x00000002  // ADC Module 1 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCADC_S0       0x00000001  // ADC Module 0 Sleep Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGCACMP
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGCACMP_S0      0x00000001  // Analog Comparator Module 0 Sleep
                                              // Mode Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGCEEPROM
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGCEEPROM_S0    0x00000001  // EEPROM Module Sleep Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_SCGCWTIMER
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_SCGCWTIMER_S5    0x00000020  // Wide Timer 5 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCWTIMER_S4    0x00000010  // Wide Timer 4 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCWTIMER_S3    0x00000008  // Wide Timer 3 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCWTIMER_S2    0x00000004  // Wide Timer 2 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCWTIMER_S1    0x00000002  // Wide Timer 1 Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_SCGCWTIMER_S0    0x00000001  // Wide Timer 0 Sleep Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGCWD register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGCWD_D1        0x00000002  // Watchdog Timer 1 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCWD_D0        0x00000001  // Watchdog Timer 0 Deep-Sleep Mode
                                              // Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGCTIMER
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGCTIMER_D5     0x00000020  // Timer 5 Deep-Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_DCGCTIMER_D4     0x00000010  // Timer 4 Deep-Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_DCGCTIMER_D3     0x00000008  // Timer 3 Deep-Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_DCGCTIMER_D2     0x00000004  // Timer 2 Deep-Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_DCGCTIMER_D1     0x00000002  // Timer 1 Deep-Sleep Mode Clock
                                              // Gating Control
  #define SYSCTL_DCGCTIMER_D0     0x00000001  // Timer 0 Deep-Sleep Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGCGPIO
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGCGPIO_D14     0x00004000  // GPIO Port Q Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCGPIO_D13     0x00002000  // GPIO Port P Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCGPIO_D12     0x00001000  // GPIO Port N Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCGPIO_D11     0x00000800  // GPIO Port M Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCGPIO_D10     0x00000400  // GPIO Port L Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCGPIO_D9      0x00000200  // GPIO Port K Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCGPIO_D8      0x00000100  // GPIO Port J Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCGPIO_D7      0x00000080  // GPIO Port H Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCGPIO_D6      0x00000040  // GPIO Port G Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCGPIO_D5      0x00000020  // GPIO Port F Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCGPIO_D4      0x00000010  // GPIO Port E Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCGPIO_D3      0x00000008  // GPIO Port D Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCGPIO_D2      0x00000004  // GPIO Port C Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCGPIO_D1      0x00000002  // GPIO Port B Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCGPIO_D0      0x00000001  // GPIO Port A Deep-Sleep Mode
                                              // Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGCDMA register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGCDMA_D0       0x00000001  // uDMA Module Deep-Sleep Mode
                                              // Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGCHIB register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGCHIB_D0       0x00000001  // Hibernation Module Deep-Sleep
                                              // Mode Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGCUART
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGCUART_D7      0x00000080  // UART Module 7 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCUART_D6      0x00000040  // UART Module 6 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCUART_D5      0x00000020  // UART Module 5 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCUART_D4      0x00000010  // UART Module 4 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCUART_D3      0x00000008  // UART Module 3 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCUART_D2      0x00000004  // UART Module 2 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCUART_D1      0x00000002  // UART Module 1 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCUART_D0      0x00000001  // UART Module 0 Deep-Sleep Mode
                                              // Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGCSSI register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGCSSI_D3       0x00000008  // SSI Module 3 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCSSI_D2       0x00000004  // SSI Module 2 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCSSI_D1       0x00000002  // SSI Module 1 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCSSI_D0       0x00000001  // SSI Module 0 Deep-Sleep Mode
                                              // Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGCI2C register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGCI2C_D5       0x00000020  // I2C Module 5 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCI2C_D4       0x00000010  // I2C Module 4 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCI2C_D3       0x00000008  // I2C Module 3 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCI2C_D2       0x00000004  // I2C Module 2 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCI2C_D1       0x00000002  // I2C Module 1 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCI2C_D0       0x00000001  // I2C Module 0 Deep-Sleep Mode
                                              // Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGCUSB register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGCUSB_D0       0x00000001  // USB Module Deep-Sleep Mode Clock
                                              // Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGCCAN register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGCCAN_D1       0x00000002  // CAN Module 1 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCCAN_D0       0x00000001  // CAN Module 0 Deep-Sleep Mode
                                              // Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGCADC register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGCADC_D1       0x00000002  // ADC Module 1 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCADC_D0       0x00000001  // ADC Module 0 Deep-Sleep Mode
                                              // Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGCACMP
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGCACMP_D0      0x00000001  // Analog Comparator Module 0
                                              // Deep-Sleep Mode Clock Gating
                                              // Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGCEEPROM
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGCEEPROM_D0    0x00000001  // EEPROM Module Deep-Sleep Mode
                                              // Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_DCGCWTIMER
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_DCGCWTIMER_D5    0x00000020  // Wide Timer 5 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCWTIMER_D4    0x00000010  // Wide Timer 4 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCWTIMER_D3    0x00000008  // Wide Timer 3 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCWTIMER_D2    0x00000004  // Wide Timer 2 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCWTIMER_D1    0x00000002  // Wide Timer 1 Deep-Sleep Mode
                                              // Clock Gating Control
  #define SYSCTL_DCGCWTIMER_D0    0x00000001  // Wide Timer 0 Deep-Sleep Mode
                                              // Clock Gating Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PCWD register.
  //
  //*****************************************************************************
  #define SYSCTL_PCWD_P1          0x00000002  // Watchdog Timer 1 Power Control
  #define SYSCTL_PCWD_P0          0x00000001  // Watchdog Timer 0 Power Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PCTIMER register.
  //
  //*****************************************************************************
  #define SYSCTL_PCTIMER_P5       0x00000020  // Timer 5 Power Control
  #define SYSCTL_PCTIMER_P4       0x00000010  // Timer 4 Power Control
  #define SYSCTL_PCTIMER_P3       0x00000008  // Timer 3 Power Control
  #define SYSCTL_PCTIMER_P2       0x00000004  // Timer 2 Power Control
  #define SYSCTL_PCTIMER_P1       0x00000002  // Timer 1 Power Control
  #define SYSCTL_PCTIMER_P0       0x00000001  // Timer 0 Power Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PCGPIO register.
  //
  //*****************************************************************************
  #define SYSCTL_PCGPIO_P14       0x00004000  // GPIO Port Q Power Control
  #define SYSCTL_PCGPIO_P13       0x00002000  // GPIO Port P Power Control
  #define SYSCTL_PCGPIO_P12       0x00001000  // GPIO Port N Power Control
  #define SYSCTL_PCGPIO_P11       0x00000800  // GPIO Port M Power Control
  #define SYSCTL_PCGPIO_P10       0x00000400  // GPIO Port L Power Control
  #define SYSCTL_PCGPIO_P9        0x00000200  // GPIO Port K Power Control
  #define SYSCTL_PCGPIO_P8        0x00000100  // GPIO Port J Power Control
  #define SYSCTL_PCGPIO_P7        0x00000080  // GPIO Port H Power Control
  #define SYSCTL_PCGPIO_P6        0x00000040  // GPIO Port G Power Control
  #define SYSCTL_PCGPIO_P5        0x00000020  // GPIO Port F Power Control
  #define SYSCTL_PCGPIO_P4        0x00000010  // GPIO Port E Power Control
  #define SYSCTL_PCGPIO_P3        0x00000008  // GPIO Port D Power Control
  #define SYSCTL_PCGPIO_P2        0x00000004  // GPIO Port C Power Control
  #define SYSCTL_PCGPIO_P1        0x00000002  // GPIO Port B Power Control
  #define SYSCTL_PCGPIO_P0        0x00000001  // GPIO Port A Power Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PCDMA register.
  //
  //*****************************************************************************
  #define SYSCTL_PCDMA_P0         0x00000001  // uDMA Module Power Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PCHIB register.
  //
  //*****************************************************************************
  #define SYSCTL_PCHIB_P0         0x00000001  // Hibernation Module Power Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PCUART register.
  //
  //*****************************************************************************
  #define SYSCTL_PCUART_P7        0x00000080  // UART Module 7 Power Control
  #define SYSCTL_PCUART_P6        0x00000040  // UART Module 6 Power Control
  #define SYSCTL_PCUART_P5        0x00000020  // UART Module 5 Power Control
  #define SYSCTL_PCUART_P4        0x00000010  // UART Module 4 Power Control
  #define SYSCTL_PCUART_P3        0x00000008  // UART Module 3 Power Control
  #define SYSCTL_PCUART_P2        0x00000004  // UART Module 2 Power Control
  #define SYSCTL_PCUART_P1        0x00000002  // UART Module 1 Power Control
  #define SYSCTL_PCUART_P0        0x00000001  // UART Module 0 Power Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PCSSI register.
  //
  //*****************************************************************************
  #define SYSCTL_PCSSI_P3         0x00000008  // SSI Module 3 Power Control
  #define SYSCTL_PCSSI_P2         0x00000004  // SSI Module 2 Power Control
  #define SYSCTL_PCSSI_P1         0x00000002  // SSI Module 1 Power Control
  #define SYSCTL_PCSSI_P0         0x00000001  // SSI Module 0 Power Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PCI2C register.
  //
  //*****************************************************************************
  #define SYSCTL_PCI2C_P5         0x00000020  // I2C Module 5 Power Control
  #define SYSCTL_PCI2C_P4         0x00000010  // I2C Module 4 Power Control
  #define SYSCTL_PCI2C_P3         0x00000008  // I2C Module 3 Power Control
  #define SYSCTL_PCI2C_P2         0x00000004  // I2C Module 2 Power Control
  #define SYSCTL_PCI2C_P1         0x00000002  // I2C Module 1 Power Control
  #define SYSCTL_PCI2C_P0         0x00000001  // I2C Module 0 Power Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PCUSB register.
  //
  //*****************************************************************************
  #define SYSCTL_PCUSB_P0         0x00000001  // USB Module Power Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PCCAN register.
  //
  //*****************************************************************************
  #define SYSCTL_PCCAN_P1         0x00000002  // CAN Module 1 Power Control
  #define SYSCTL_PCCAN_P0         0x00000001  // CAN Module 0 Power Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PCADC register.
  //
  //*****************************************************************************
  #define SYSCTL_PCADC_P1         0x00000002  // ADC Module 1 Power Control
  #define SYSCTL_PCADC_P0         0x00000001  // ADC Module 0 Power Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PCACMP register.
  //
  //*****************************************************************************
  #define SYSCTL_PCACMP_P0        0x00000001  // Analog Comparator Module 0 Power
                                              // Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PCEEPROM
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_PCEEPROM_P0      0x00000001  // EEPROM Module Power Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PCWTIMER
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_PCWTIMER_P5      0x00000020  // Wide Timer 5 Power Control
  #define SYSCTL_PCWTIMER_P4      0x00000010  // Wide Timer 4 Power Control
  #define SYSCTL_PCWTIMER_P3      0x00000008  // Wide Timer 3 Power Control
  #define SYSCTL_PCWTIMER_P2      0x00000004  // Wide Timer 2 Power Control
  #define SYSCTL_PCWTIMER_P1      0x00000002  // Wide Timer 1 Power Control
  #define SYSCTL_PCWTIMER_P0      0x00000001  // Wide Timer 0 Power Control
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PRWD register.
  //
  //*****************************************************************************
  #define SYSCTL_PRWD_R1          0x00000002  // Watchdog Timer 1 Peripheral
                                              // Ready
  #define SYSCTL_PRWD_R0          0x00000001  // Watchdog Timer 0 Peripheral
                                              // Ready
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PRTIMER register.
  //
  //*****************************************************************************
  #define SYSCTL_PRTIMER_R5       0x00000020  // Timer 5 Peripheral Ready
  #define SYSCTL_PRTIMER_R4       0x00000010  // Timer 4 Peripheral Ready
  #define SYSCTL_PRTIMER_R3       0x00000008  // Timer 3 Peripheral Ready
  #define SYSCTL_PRTIMER_R2       0x00000004  // Timer 2 Peripheral Ready
  #define SYSCTL_PRTIMER_R1       0x00000002  // Timer 1 Peripheral Ready
  #define SYSCTL_PRTIMER_R0       0x00000001  // Timer 0 Peripheral Ready
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PRGPIO register.
  //
  //*****************************************************************************
  #define SYSCTL_PRGPIO_R14       0x00004000  // GPIO Port Q Peripheral Ready
  #define SYSCTL_PRGPIO_R13       0x00002000  // GPIO Port P Peripheral Ready
  #define SYSCTL_PRGPIO_R12       0x00001000  // GPIO Port N Peripheral Ready
  #define SYSCTL_PRGPIO_R11       0x00000800  // GPIO Port M Peripheral Ready
  #define SYSCTL_PRGPIO_R10       0x00000400  // GPIO Port L Peripheral Ready
  #define SYSCTL_PRGPIO_R9        0x00000200  // GPIO Port K Peripheral Ready
  #define SYSCTL_PRGPIO_R8        0x00000100  // GPIO Port J Peripheral Ready
  #define SYSCTL_PRGPIO_R7        0x00000080  // GPIO Port H Peripheral Ready
  #define SYSCTL_PRGPIO_R6        0x00000040  // GPIO Port G Peripheral Ready
  #define SYSCTL_PRGPIO_R5        0x00000020  // GPIO Port F Peripheral Ready
  #define SYSCTL_PRGPIO_R4        0x00000010  // GPIO Port E Peripheral Ready
  #define SYSCTL_PRGPIO_R3        0x00000008  // GPIO Port D Peripheral Ready
  #define SYSCTL_PRGPIO_R2        0x00000004  // GPIO Port C Peripheral Ready
  #define SYSCTL_PRGPIO_R1        0x00000002  // GPIO Port B Peripheral Ready
  #define SYSCTL_PRGPIO_R0        0x00000001  // GPIO Port A Peripheral Ready
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PRDMA register.
  //
  //*****************************************************************************
  #define SYSCTL_PRDMA_R0         0x00000001  // uDMA Module Peripheral Ready
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PRHIB register.
  //
  //*****************************************************************************
  #define SYSCTL_PRHIB_R0         0x00000001  // Hibernation Module Peripheral
                                              // Ready
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PRUART register.
  //
  //*****************************************************************************
  #define SYSCTL_PRUART_R7        0x00000080  // UART Module 7 Peripheral Ready
  #define SYSCTL_PRUART_R6        0x00000040  // UART Module 6 Peripheral Ready
  #define SYSCTL_PRUART_R5        0x00000020  // UART Module 5 Peripheral Ready
  #define SYSCTL_PRUART_R4        0x00000010  // UART Module 4 Peripheral Ready
  #define SYSCTL_PRUART_R3        0x00000008  // UART Module 3 Peripheral Ready
  #define SYSCTL_PRUART_R2        0x00000004  // UART Module 2 Peripheral Ready
  #define SYSCTL_PRUART_R1        0x00000002  // UART Module 1 Peripheral Ready
  #define SYSCTL_PRUART_R0        0x00000001  // UART Module 0 Peripheral Ready
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PRSSI register.
  //
  //*****************************************************************************
  #define SYSCTL_PRSSI_R3         0x00000008  // SSI Module 3 Peripheral Ready
  #define SYSCTL_PRSSI_R2         0x00000004  // SSI Module 2 Peripheral Ready
  #define SYSCTL_PRSSI_R1         0x00000002  // SSI Module 1 Peripheral Ready
  #define SYSCTL_PRSSI_R0         0x00000001  // SSI Module 0 Peripheral Ready
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PRI2C register.
  //
  //*****************************************************************************
  #define SYSCTL_PRI2C_R5         0x00000020  // I2C Module 5 Peripheral Ready
  #define SYSCTL_PRI2C_R4         0x00000010  // I2C Module 4 Peripheral Ready
  #define SYSCTL_PRI2C_R3         0x00000008  // I2C Module 3 Peripheral Ready
  #define SYSCTL_PRI2C_R2         0x00000004  // I2C Module 2 Peripheral Ready
  #define SYSCTL_PRI2C_R1         0x00000002  // I2C Module 1 Peripheral Ready
  #define SYSCTL_PRI2C_R0         0x00000001  // I2C Module 0 Peripheral Ready
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PRUSB register.
  //
  //*****************************************************************************
  #define SYSCTL_PRUSB_R0         0x00000001  // USB Module Peripheral Ready
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PRCAN register.
  //
  //*****************************************************************************
  #define SYSCTL_PRCAN_R1         0x00000002  // CAN Module 1 Peripheral Ready
  #define SYSCTL_PRCAN_R0         0x00000001  // CAN Module 0 Peripheral Ready
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PRADC register.
  //
  //*****************************************************************************
  #define SYSCTL_PRADC_R1         0x00000002  // ADC Module 1 Peripheral Ready
  #define SYSCTL_PRADC_R0         0x00000001  // ADC Module 0 Peripheral Ready
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PRACMP register.
  //
  //*****************************************************************************
  #define SYSCTL_PRACMP_R0        0x00000001  // Analog Comparator Module 0
                                              // Peripheral Ready
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PREEPROM
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_PREEPROM_R0      0x00000001  // EEPROM Module Peripheral Ready
  
  #define SYSCTL_PRQEI_P1					0x00000002 //QEI1 peripheral ready	
  #define SYSCTL_PRQEI_P0					0x00000001 //QEI0 ready
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PRWTIMER
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_PRWTIMER_R5      0x00000020  // Wide Timer 5 Peripheral Ready
  #define SYSCTL_PRWTIMER_R4      0x00000010  // Wide Timer 4 Peripheral Ready
  #define SYSCTL_PRWTIMER_R3      0x00000008  // Wide Timer 3 Peripheral Ready
  #define SYSCTL_PRWTIMER_R2      0x00000004  // Wide Timer 2 Peripheral Ready
  #define SYSCTL_PRWTIMER_R1      0x00000002  // Wide Timer 1 Peripheral Ready
  #define SYSCTL_PRWTIMER_R0      0x00000001  // Wide Timer 0 Peripheral Read
  
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PRPWM
  // register.
  //
  //*****************************************************************************
  #define SYSCTL_PRPWM_R1      0x00000002  // PWM 1 Peripheral Ready
  #define SYSCTL_PRPWM_R0      0x00000001  // PWM 0 Peripheral Read
  
  
  /*************************************************************************
   ************************************************************************/
   /* GPIO MACROS                                                         */
   /************************************************************************
   ************************************************************************/
   
  #define GPIO_PORTD_LOCK_R       (*((volatile unsigned long *)0x40007520))
  #define GPIO_PORTD_CR_R         (*((volatile unsigned long *)0x40007524))
  #define GPIO_PORTF_LOCK_R       (*((volatile unsigned long *)0x40025520))
  #define GPIO_PORTF_CR_R         (*((volatile unsigned long *)0x40025524))
    
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the GPIO_O_IM register.
  //
  //*****************************************************************************
  #define GPIO_IM_GPIO_M          0x000000FF  // GPIO Interrupt Mask Enable
  #define GPIO_IM_GPIO_S          0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the GPIO_O_RIS register.
  //
  //*****************************************************************************
  #define GPIO_RIS_GPIO_M         0x000000FF  // GPIO Interrupt Raw Status
  #define GPIO_RIS_GPIO_S         0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the GPIO_O_MIS register.
  //
  //*****************************************************************************
  #define GPIO_MIS_GPIO_M         0x000000FF  // GPIO Masked Interrupt Status
  #define GPIO_MIS_GPIO_S         0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the GPIO_O_ICR register.
  //
  //*****************************************************************************
  #define GPIO_ICR_GPIO_M         0x000000FF  // GPIO Interrupt Clear
  #define GPIO_ICR_GPIO_S         0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the GPIO_O_LOCK register.
  //
  //*****************************************************************************
  #define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock
  #define GPIO_LOCK_UNLOCKED      0x00000000  // The GPIOCR register is unlocked
                                              // and may be modified
  #define GPIO_LOCK_LOCKED        0x00000001  // The GPIOCR register is locked
                                              // and may not be modified
  #define GPIO_LOCK_KEY           0x4C4F434B  // Unlocks the GPIO_CR register
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the GPIO_O_SI register.
  //
  //*****************************************************************************
  #define GPIO_SI_SUM             0x00000001  // Summary Interrupt
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the GPIO_PCTL register for
  // port A.
  //
  //*****************************************************************************
  #define GPIO_PCTL_PA7_M         0xF0000000  // PA7 mask
  #define GPIO_PCTL_PA7_I2C1SDA   0x30000000  // I2C1SDA on PA7
  #define GPIO_PCTL_PA6_M         0x0F000000  // PA6 mask
  #define GPIO_PCTL_PA6_I2C1SCL   0x03000000  // I2C1SCL on PA6
  #define GPIO_PCTL_PA5_M         0x00F00000  // PA5 mask
  #define GPIO_PCTL_PA5_SSI0TX    0x00200000  // SSI0TX on PA5
  #define GPIO_PCTL_PA4_M         0x000F0000  // PA4 mask
  #define GPIO_PCTL_PA4_SSI0RX    0x00020000  // SSI0RX on PA4
  #define GPIO_PCTL_PA3_M         0x0000F000  // PA3 mask
  #define GPIO_PCTL_PA3_SSI0FSS   0x00002000  // SSI0FSS on PA3
  #define GPIO_PCTL_PA2_M         0x00000F00  // PA2 mask
  #define GPIO_PCTL_PA2_SSI0CLK   0x00000200  // SSI0CLK on PA2
  #define GPIO_PCTL_PA1_M         0x000000F0  // PA1 mask
  #define GPIO_PCTL_PA1_U0TX      0x00000010  // U0TX on PA1
  #define GPIO_PCTL_PA0_M         0x0000000F  // PA0 mask
  #define GPIO_PCTL_PA0_U0RX      0x00000001  // U0RX on PA0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the GPIO_PCTL register for
  // port B.
  //
  //*****************************************************************************
  #define GPIO_PCTL_PB7_M         0xF0000000  // PB7 mask
  #define GPIO_PCTL_PB7_SSI2TX    0x20000000  // SSI2TX on PB7
  #define GPIO_PCTL_PB7_T0CCP1    0x70000000  // T0CCP1 on PB7
  #define GPIO_PCTL_PB6_M         0x0F000000  // PB6 mask
  #define GPIO_PCTL_PB6_SSI2RX    0x02000000  // SSI2RX on PB6
  #define GPIO_PCTL_PB6_T0CCP0    0x07000000  // T0CCP0 on PB6
  #define GPIO_PCTL_PB5_M         0x00F00000  // PB5 mask
  #define GPIO_PCTL_PB5_SSI2FSS   0x00200000  // SSI2FSS on PB5
  #define GPIO_PCTL_PB5_T1CCP1    0x00700000  // T1CCP1 on PB5
  #define GPIO_PCTL_PB5_CAN0TX    0x00800000  // CAN0TX on PB5
  #define GPIO_PCTL_PB4_M         0x000F0000  // PB4 mask
  #define GPIO_PCTL_PB4_SSI2CLK   0x00020000  // SSI2CLK on PB4
  #define GPIO_PCTL_PB4_T1CCP0    0x00070000  // T1CCP0 on PB4
  #define GPIO_PCTL_PB4_CAN0RX    0x00080000  // CAN0RX on PB4
  #define GPIO_PCTL_PB3_M         0x0000F000  // PB3 mask
  #define GPIO_PCTL_PB3_I2C0SDA   0x00003000  // I2C0SDA on PB3
  #define GPIO_PCTL_PB3_T3CCP1    0x00007000  // T3CCP1 on PB3
  #define GPIO_PCTL_PB2_M         0x00000F00  // PB2 mask
  #define GPIO_PCTL_PB2_I2C0SCL   0x00000300  // I2C0SCL on PB2
  #define GPIO_PCTL_PB2_T3CCP0    0x00000700  // T3CCP0 on PB2
  #define GPIO_PCTL_PB1_M         0x000000F0  // PB1 mask
  #define GPIO_PCTL_PB1_U1TX      0x00000010  // U1TX on PB1
  #define GPIO_PCTL_PB1_T2CCP1    0x00000070  // T2CCP1 on PB1
  #define GPIO_PCTL_PB0_M         0x0000000F  // PB0 mask
  #define GPIO_PCTL_PB0_U1RX      0x00000001  // U1RX on PB0
  #define GPIO_PCTL_PB0_T2CCP0    0x00000007  // T2CCP0 on PB0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the GPIO_PCTL register for
  // port C.
  //
  //*****************************************************************************
  #define GPIO_PCTL_PC7_M         0xF0000000  // PC7 mask
  #define GPIO_PCTL_PC7_U3TX      0x10000000  // U3TX on PC7
  #define GPIO_PCTL_PC7_WT1CCP1   0x70000000  // WT1CCP1 on PC7
  #define GPIO_PCTL_PC6_M         0x0F000000  // PC6 mask
  #define GPIO_PCTL_PC6_U3RX      0x01000000  // U3RX on PC6
  #define GPIO_PCTL_PC6_WT1CCP0   0x07000000  // WT1CCP0 on PC6
  #define GPIO_PCTL_PC5_PHA1      0x00600000	// phb on qei mod 1
  #define GPIO_PCTL_PC6_PHB1			0x06000000  // phb on pdg with qei
  #define GPIO_PCTL_PC5_M         0x00F00000  // PC5 mask
  #define GPIO_PCTL_PC5_U4TX      0x00100000  // U4TX on PC5
  #define GPIO_PCTL_PC5_U1TX      0x00200000  // U1TX on PC5
  #define GPIO_PCTL_PC5_WT0CCP1   0x00700000  // WT0CCP1 on PC5
  #define GPIO_PCTL_PC5_U1CTS     0x00800000  // U1CTS on PC5
  #define GPIO_PCTL_PC4_M         0x000F0000  // PC4 mask
  #define GPIO_PCTL_PC4_U4RX      0x00010000  // U4RX on PC4
  #define GPIO_PCTL_PC4_U1RX      0x00020000  // U1RX on PC4
  #define GPIO_PCTL_PC4_WT0CCP0   0x00070000  // WT0CCP0 on PC4
  #define GPIO_PCTL_PC4_U1RTS     0x00080000  // U1RTS on PC4
  #define GPIO_PCTL_PC3_M         0x0000F000  // PC3 mask
  #define GPIO_PCTL_PC3_TDO       0x00001000  // TDO on PC3
  #define GPIO_PCTL_PC3_T5CCP1    0x00007000  // T5CCP1 on PC3
  #define GPIO_PCTL_PC2_M         0x00000F00  // PC2 mask
  #define GPIO_PCTL_PC2_TDI       0x00000100  // TDI on PC2
  #define GPIO_PCTL_PC2_T5CCP0    0x00000700  // T5CCP0 on PC2
  #define GPIO_PCTL_PC1_M         0x000000F0  // PC1 mask
  #define GPIO_PCTL_PC1_TMS       0x00000010  // TMS on PC1
  #define GPIO_PCTL_PC1_T4CCP1    0x00000070  // T4CCP1 on PC1
  #define GPIO_PCTL_PC0_M         0x0000000F  // PC0 mask
  #define GPIO_PCTL_PC0_TCK       0x00000001  // TCK on PC0
  #define GPIO_PCTL_PC0_T4CCP0    0x00000007  // T4CCP0 on PC0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the GPIO_PCTL register for
  // port D.
  //
  //*****************************************************************************
  #define GPIO_PCTL_PD7_M         0xF0000000  // PD7 mask
  #define GPIO_PCTL_PD7_U2TX      0x10000000  // U2TX on PD7
  #define GPIO_PCTL_PD7_WT5CCP1   0x70000000  // WT5CCP1 on PD7
  #define GPIO_PCTL_PD7_NMI       0x80000000  // NMI on PD7
  #define GPIO_PCTL_PD6_M         0x0F000000  // PD6 mask
  #define GPIO_PCTL_PD6_U2RX      0x01000000  // U2RX on PD6
  #define GPIO_PCTL_PD6_WT5CCP0   0x07000000  // WT5CCP0 on PD6
  #define GPIO_PCTL_PD6_PHA1      0x06000000	// pha on qei mod 1
  #define GPIO_PCTL_PD7_PHB1			0x60000000  // phb on pdg with qei
  #define GPIO_PCTL_PD5_M         0x00F00000  // PD5 mask
  #define GPIO_PCTL_PD5_U6TX      0x00100000  // U6TX on PD5
  #define GPIO_PCTL_PD5_WT4CCP1   0x00700000  // WT4CCP1 on PD5
  #define GPIO_PCTL_PD4_M         0x000F0000  // PD4 mask
  #define GPIO_PCTL_PD4_U6RX      0x00010000  // U6RX on PD4
  #define GPIO_PCTL_PD4_WT4CCP0   0x00070000  // WT4CCP0 on PD4
  #define GPIO_PCTL_PD3_M         0x0000F000  // PD3 mask
  #define GPIO_PCTL_PD3_SSI3TX    0x00001000  // SSI3TX on PD3
  #define GPIO_PCTL_PD3_SSI1TX    0x00002000  // SSI1TX on PD3
  #define GPIO_PCTL_PD3_WT3CCP1   0x00007000  // WT3CCP1 on PD3
  #define GPIO_PCTL_PD2_M         0x00000F00  // PD2 mask
  #define GPIO_PCTL_PD2_SSI3RX    0x00000100  // SSI3RX on PD2
  #define GPIO_PCTL_PD2_SSI1RX    0x00000200  // SSI1RX on PD2
  #define GPIO_PCTL_PD2_WT3CCP0   0x00000700  // WT3CCP0 on PD2
  #define GPIO_PCTL_PD1_M         0x000000F0  // PD1 mask
  #define GPIO_PCTL_PD1_SSI3FSS   0x00000010  // SSI3FSS on PD1
  #define GPIO_PCTL_PD1_SSI1FSS   0x00000020  // SSI1FSS on PD1
  #define GPIO_PCTL_PD1_I2C3SDA   0x00000030  // I2C3SDA on PD1
  #define GPIO_PCTL_PD1_WT2CCP1   0x00000070  // WT2CCP1 on PD1
  #define GPIO_PCTL_PD0_M         0x0000000F  // PD0 mask
  #define GPIO_PCTL_PD0_SSI3CLK   0x00000001  // SSI3CLK on PD0
  #define GPIO_PCTL_PD0_SSI1CLK   0x00000002  // SSI1CLK on PD0
  #define GPIO_PCTL_PD0_I2C3SCL   0x00000003  // I2C3SCL on PD0
  #define GPIO_PCTL_PD0_WT2CCP0   0x00000007  // WT2CCP0 on PD0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the GPIO_PCTL register for
  // port E.
  //
  //*****************************************************************************
  #define GPIO_PCTL_PE5_M         0x00F00000  // PE5 mask
  #define GPIO_PCTL_PE5_U5TX      0x00100000  // U5TX on PE5
  #define GPIO_PCTL_PE5_I2C2SDA   0x00300000  // I2C2SDA on PE5
  #define GPIO_PCTL_PE5_CAN0TX    0x00800000  // CAN0TX on PE5
  #define GPIO_PCTL_PE4_M         0x000F0000  // PE4 mask
  #define GPIO_PCTL_PE4_U5RX      0x00010000  // U5RX on PE4
  #define GPIO_PCTL_PE4_I2C2SCL   0x00030000  // I2C2SCL on PE4
  #define GPIO_PCTL_PE4_CAN0RX    0x00080000  // CAN0RX on PE4
  #define GPIO_PCTL_PE3_M         0x0000F000  // PE3 mask
  #define GPIO_PCTL_PE2_M         0x00000F00  // PE2 mask
  #define GPIO_PCTL_PE1_M         0x000000F0  // PE1 mask
  #define GPIO_PCTL_PE1_U7TX      0x00000010  // U7TX on PE1
  #define GPIO_PCTL_PE0_M         0x0000000F  // PE0 mask
  #define GPIO_PCTL_PE0_U7RX      0x00000001  // U7RX on PE0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the GPIO_PCTL register for
  // port F.
  //
  //*****************************************************************************
  #define GPIO_PCTL_PF4_M         0x000F0000  // PF4 mask
  #define GPIO_PCTL_PF4_T2CCP0    0x00070000  // T2CCP0 on PF4
  #define GPIO_PCTL_PF3_M         0x0000F000  // PF3 mask
  #define GPIO_PCTL_PF3_SSI1FSS   0x00002000  // SSI1FSS on PF3
  #define GPIO_PCTL_PF3_CAN0TX    0x00003000  // CAN0TX on PF3
  #define GPIO_PCTL_PF3_T1CCP1    0x00007000  // T1CCP1 on PF3
  #define GPIO_PCTL_PF3_TRCLK     0x0000E000  // TRCLK on PF3
  #define GPIO_PCTL_PF2_M         0x00000F00  // PF2 mask
  #define GPIO_PCTL_PF2_SSI1CLK   0x00000200  // SSI1CLK on PF2
  #define GPIO_PCTL_PF2_T1CCP0    0x00000700  // T1CCP0 on PF2
  #define GPIO_PCTL_PF2_TRD0      0x00000E00  // TRD0 on PF2
  #define GPIO_PCTL_PF1_M         0x000000F0  // PF1 mask
  #define GPIO_PCTL_PF1_U1CTS     0x00000010  // U1CTS on PF1
  #define GPIO_PCTL_PF1_SSI1TX    0x00000020  // SSI1TX on PF1
  #define GPIO_PCTL_PF1_T0CCP1    0x00000070  // T0CCP1 on PF1
  #define GPIO_PCTL_PF1_C1O       0x00000090  // C1O on PF1
  #define GPIO_PCTL_PF1_TRD1      0x000000E0  // TRD1 on PF1
  #define GPIO_PCTL_PF0_M         0x0000000F  // PF0 mask
  #define GPIO_PCTL_PF0_U1RTS     0x00000001  // U1RTS on PF0
  #define GPIO_PCTL_PF0_SSI1RX    0x00000002  // SSI1RX on PF0
  #define GPIO_PCTL_PF0_CAN0RX    0x00000003  // CAN0RX on PF0
  #define GPIO_PCTL_PF0_T0CCP0    0x00000007  // T0CCP0 on PF0
  #define GPIO_PCTL_PF0_NMI       0x00000008  // NMI on PF0
  #define GPIO_PCTL_PF0_C0O       0x00000009  // C0O on PF0
  #define GPIO_PCTL_PF0_TRD2      0x0000000E  // TRD2 on PF0
  
  // Define All of the GPIO PINS
  #define PIN_0               (1 << 0)
  #define PIN_1               (1 << 1)
  #define PIN_2               (1 << 2)
  #define PIN_3               (1 << 3)
  #define PIN_4               (1 << 4)
  #define PIN_5               (1 << 5)
  #define PIN_6               (1 << 6)
  #define PIN_7               (1 << 7)
  
  
  #define     PA0     PIN_0
  #define     PA1     PIN_1
  #define     PA2     PIN_2
  #define     PA3     PIN_3
  #define     PA4     PIN_4
  #define     PA5     PIN_5
  #define     PA6     PIN_6
  #define     PA7     PIN_7
  
  
  
  #define     PB0     PIN_0
  #define     PB1     PIN_1
  #define     PB2     PIN_2
  #define     PB3     PIN_3
  #define     PB4     PIN_4
  #define     PB5     PIN_5
  #define     PB6     PIN_6
  #define     PB7     PIN_7
  
  
  #define     PC0     PIN_0
  #define     PC1     PIN_1
  #define     PC2     PIN_2
  #define     PC3     PIN_3
  #define     PC4     PIN_4
  #define     PC5     PIN_5
  #define     PC6     PIN_6
  #define     PC7     PIN_7
  
  
  #define     PD0     PIN_0
  #define     PD1     PIN_1
  #define     PD2     PIN_2
  #define     PD3     PIN_3
  #define     PD4     PIN_4
  #define     PD5     PIN_5
  #define     PD6     PIN_6
  #define     PD7     PIN_7
  
  
  #define     PE0     PIN_0
  #define     PE1     PIN_1
  #define     PE2     PIN_2
  #define     PE3     PIN_3
  #define     PE4     PIN_4
  #define     PE5     PIN_5
  #define     PE6     PIN_6
  #define     PE7     PIN_7
  
  #define     PF0     PIN_0
  #define     PF1     PIN_1
  #define     PF2     PIN_2
  #define     PF3     PIN_3
  #define     PF4     PIN_4
  #define     PF5     PIN_5
  
  #define     HIGH    1
  #define     LOW     0
  
  /*************************************************************************
   ************************************************************************/
   /* ADC MACROS                                                          */
   /************************************************************************
   ************************************************************************/
   
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_RCGCADC register.
  //
  //*****************************************************************************
  #define SYSCTL_RCGCADC_R1       0x00000002  // ADC Module 1 Run Mode Clock
                                              // Gating Control
  #define SYSCTL_RCGCADC_R0       0x00000001  // ADC Module 0 Run Mode Clock
                                              // Gating Control
                                              
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SYSCTL_PRADC register.
  //
  //*****************************************************************************
  #define SYSCTL_PRADC_R1         0x00000002  // ADC Module 1 Peripheral Ready
  #define SYSCTL_PRADC_R0         0x00000001  // ADC Module 0 Peripheral Ready
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_ACTSS register.
  //
  //*****************************************************************************
  #define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable
  #define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable
  #define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable
  #define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_RIS register.
  //
  //*****************************************************************************
  #define ADC_RIS_INRDC           0x00010000  // Digital Comparator Raw Interrupt
                                              // Status
  #define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status
  #define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status
  #define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status
  #define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_IM register.
  //
  //*****************************************************************************
  #define ADC_IM_DCONSS3          0x00080000  // Digital Comparator Interrupt on
                                              // SS3
  #define ADC_IM_DCONSS2          0x00040000  // Digital Comparator Interrupt on
                                              // SS2
  #define ADC_IM_DCONSS1          0x00020000  // Digital Comparator Interrupt on
                                              // SS1
  #define ADC_IM_DCONSS0          0x00010000  // Digital Comparator Interrupt on
                                              // SS0
  #define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask
  #define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask
  #define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask
  #define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_ISC register.
  //
  //*****************************************************************************
  #define ADC_ISC_DCINSS3         0x00080000  // Digital Comparator Interrupt
                                              // Status on SS3
  #define ADC_ISC_DCINSS2         0x00040000  // Digital Comparator Interrupt
                                              // Status on SS2
  #define ADC_ISC_DCINSS1         0x00020000  // Digital Comparator Interrupt
                                              // Status on SS1
  #define ADC_ISC_DCINSS0         0x00010000  // Digital Comparator Interrupt
                                              // Status on SS0
  #define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear
  #define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear
  #define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear
  #define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_OSTAT register.
  //
  //*****************************************************************************
  #define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow
  #define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow
  #define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow
  #define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_EMUX register.
  //
  //*****************************************************************************
  #define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select
  #define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor (default)
  #define ADC_EMUX_EM3_COMP0      0x00001000  // Analog Comparator 0
  #define ADC_EMUX_EM3_COMP1      0x00002000  // Analog Comparator 1
  #define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External (GPIO PB4)
  #define ADC_EMUX_EM3_TIMER      0x00005000  // Timer
  #define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always (continuously sample)
  #define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select
  #define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor (default)
  #define ADC_EMUX_EM2_COMP0      0x00000100  // Analog Comparator 0
  #define ADC_EMUX_EM2_COMP1      0x00000200  // Analog Comparator 1
  #define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External (GPIO PB4)
  #define ADC_EMUX_EM2_TIMER      0x00000500  // Timer
  #define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always (continuously sample)
  #define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select
  #define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor (default)
  #define ADC_EMUX_EM1_COMP0      0x00000010  // Analog Comparator 0
  #define ADC_EMUX_EM1_COMP1      0x00000020  // Analog Comparator 1
  #define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External (GPIO PB4)
  #define ADC_EMUX_EM1_TIMER      0x00000050  // Timer
  #define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always (continuously sample)
  #define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select
  #define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor (default)
  #define ADC_EMUX_EM0_COMP0      0x00000001  // Analog Comparator 0
  #define ADC_EMUX_EM0_COMP1      0x00000002  // Analog Comparator 1
  #define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External (GPIO PB4)
  #define ADC_EMUX_EM0_TIMER      0x00000005  // Timer
  #define ADC_EMUX_EM0_ALWAYS     0x0000000F  // Always (continuously sample)
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_USTAT register.
  //
  //*****************************************************************************
  #define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow
  #define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow
  #define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow
  #define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSPRI register.
  //
  //*****************************************************************************
  #define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority
  #define ADC_SSPRI_SS3_1ST       0x00000000  // First priority
  #define ADC_SSPRI_SS3_2ND       0x00001000  // Second priority
  #define ADC_SSPRI_SS3_3RD       0x00002000  // Third priority
  #define ADC_SSPRI_SS3_4TH       0x00003000  // Fourth priority
  #define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority
  #define ADC_SSPRI_SS2_1ST       0x00000000  // First priority
  #define ADC_SSPRI_SS2_2ND       0x00000100  // Second priority
  #define ADC_SSPRI_SS2_3RD       0x00000200  // Third priority
  #define ADC_SSPRI_SS2_4TH       0x00000300  // Fourth priority
  #define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority
  #define ADC_SSPRI_SS1_1ST       0x00000000  // First priority
  #define ADC_SSPRI_SS1_2ND       0x00000010  // Second priority
  #define ADC_SSPRI_SS1_3RD       0x00000020  // Third priority
  #define ADC_SSPRI_SS1_4TH       0x00000030  // Fourth priority
  #define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority
  #define ADC_SSPRI_SS0_1ST       0x00000000  // First priority
  #define ADC_SSPRI_SS0_2ND       0x00000001  // Second priority
  #define ADC_SSPRI_SS0_3RD       0x00000002  // Third priority
  #define ADC_SSPRI_SS0_4TH       0x00000003  // Fourth priority
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SPC register.
  //
  //*****************************************************************************
  #define ADC_SPC_PHASE_M         0x0000000F  // Phase Difference
  #define ADC_SPC_PHASE_0         0x00000000  // ADC sample lags by 0.0
  #define ADC_SPC_PHASE_22_5      0x00000001  // ADC sample lags by 22.5
  #define ADC_SPC_PHASE_45        0x00000002  // ADC sample lags by 45.0
  #define ADC_SPC_PHASE_67_5      0x00000003  // ADC sample lags by 67.5
  #define ADC_SPC_PHASE_90        0x00000004  // ADC sample lags by 90.0
  #define ADC_SPC_PHASE_112_5     0x00000005  // ADC sample lags by 112.5
  #define ADC_SPC_PHASE_135       0x00000006  // ADC sample lags by 135.0
  #define ADC_SPC_PHASE_157_5     0x00000007  // ADC sample lags by 157.5
  #define ADC_SPC_PHASE_180       0x00000008  // ADC sample lags by 180.0
  #define ADC_SPC_PHASE_202_5     0x00000009  // ADC sample lags by 202.5
  #define ADC_SPC_PHASE_225       0x0000000A  // ADC sample lags by 225.0
  #define ADC_SPC_PHASE_247_5     0x0000000B  // ADC sample lags by 247.5
  #define ADC_SPC_PHASE_270       0x0000000C  // ADC sample lags by 270.0
  #define ADC_SPC_PHASE_292_5     0x0000000D  // ADC sample lags by 292.5
  #define ADC_SPC_PHASE_315       0x0000000E  // ADC sample lags by 315.0
  #define ADC_SPC_PHASE_337_5     0x0000000F  // ADC sample lags by 337.5
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_PSSI register.
  //
  //*****************************************************************************
  #define ADC_PSSI_GSYNC          0x80000000  // Global Synchronize
  #define ADC_PSSI_SYNCWAIT       0x08000000  // Synchronize Wait
  #define ADC_PSSI_SS3            0x00000008  // SS3 Initiate
  #define ADC_PSSI_SS2            0x00000004  // SS2 Initiate
  #define ADC_PSSI_SS1            0x00000002  // SS1 Initiate
  #define ADC_PSSI_SS0            0x00000001  // SS0 Initiate
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SAC register.
  //
  //*****************************************************************************
  #define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control
  #define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling
  #define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
  #define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
  #define ADC_SAC_AVG_8X          0x00000003  // 8x hardware oversampling
  #define ADC_SAC_AVG_16X         0x00000004  // 16x hardware oversampling
  #define ADC_SAC_AVG_32X         0x00000005  // 32x hardware oversampling
  #define ADC_SAC_AVG_64X         0x00000006  // 64x hardware oversampling
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCISC register.
  //
  //*****************************************************************************
  #define ADC_DCISC_DCINT7        0x00000080  // Digital Comparator 7 Interrupt
                                              // Status and Clear
  #define ADC_DCISC_DCINT6        0x00000040  // Digital Comparator 6 Interrupt
                                              // Status and Clear
  #define ADC_DCISC_DCINT5        0x00000020  // Digital Comparator 5 Interrupt
                                              // Status and Clear
  #define ADC_DCISC_DCINT4        0x00000010  // Digital Comparator 4 Interrupt
                                              // Status and Clear
  #define ADC_DCISC_DCINT3        0x00000008  // Digital Comparator 3 Interrupt
                                              // Status and Clear
  #define ADC_DCISC_DCINT2        0x00000004  // Digital Comparator 2 Interrupt
                                              // Status and Clear
  #define ADC_DCISC_DCINT1        0x00000002  // Digital Comparator 1 Interrupt
                                              // Status and Clear
  #define ADC_DCISC_DCINT0        0x00000001  // Digital Comparator 0 Interrupt
                                              // Status and Clear
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSMUX0 register.
  //
  //*****************************************************************************
  #define ADC_SSMUX0_MUX7_M       0xF0000000  // 8th Sample Input Select
  #define ADC_SSMUX0_MUX6_M       0x0F000000  // 7th Sample Input Select
  #define ADC_SSMUX0_MUX5_M       0x00F00000  // 6th Sample Input Select
  #define ADC_SSMUX0_MUX4_M       0x000F0000  // 5th Sample Input Select
  #define ADC_SSMUX0_MUX3_M       0x0000F000  // 4th Sample Input Select
  #define ADC_SSMUX0_MUX2_M       0x00000F00  // 3rd Sample Input Select
  #define ADC_SSMUX0_MUX1_M       0x000000F0  // 2nd Sample Input Select
  #define ADC_SSMUX0_MUX0_M       0x0000000F  // 1st Sample Input Select
  #define ADC_SSMUX0_MUX7_S       28
  #define ADC_SSMUX0_MUX6_S       24
  #define ADC_SSMUX0_MUX5_S       20
  #define ADC_SSMUX0_MUX4_S       16
  #define ADC_SSMUX0_MUX3_S       12
  #define ADC_SSMUX0_MUX2_S       8
  #define ADC_SSMUX0_MUX1_S       4
  #define ADC_SSMUX0_MUX0_S       0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSCTL0 register.
  //
  //*****************************************************************************
  #define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select
  #define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable
  #define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence
  #define ADC_SSCTL0_D7           0x10000000  // 8th Sample Diff Input Select
  #define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select
  #define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable
  #define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence
  #define ADC_SSCTL0_D6           0x01000000  // 7th Sample Diff Input Select
  #define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select
  #define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable
  #define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence
  #define ADC_SSCTL0_D5           0x00100000  // 6th Sample Diff Input Select
  #define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select
  #define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable
  #define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence
  #define ADC_SSCTL0_D4           0x00010000  // 5th Sample Diff Input Select
  #define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select
  #define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable
  #define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence
  #define ADC_SSCTL0_D3           0x00001000  // 4th Sample Diff Input Select
  #define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select
  #define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable
  #define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence
  #define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Diff Input Select
  #define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select
  #define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable
  #define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence
  #define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Diff Input Select
  #define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select
  #define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable
  #define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence
  #define ADC_SSCTL0_D0           0x00000001  // 1st Sample Diff Input Select
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
  //
  //*****************************************************************************
  #define ADC_SSFIFO0_DATA_M      0x00000FFF  // Conversion Result Data
  #define ADC_SSFIFO0_DATA_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
  //
  //*****************************************************************************
  #define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full
  #define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty
  #define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer
  #define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer
  #define ADC_SSFSTAT0_HPTR_S     4
  #define ADC_SSFSTAT0_TPTR_S     0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSOP0 register.
  //
  //*****************************************************************************
  #define ADC_SSOP0_S7DCOP        0x10000000  // Sample 7 Digital Comparator
                                              // Operation
  #define ADC_SSOP0_S6DCOP        0x01000000  // Sample 6 Digital Comparator
                                              // Operation
  #define ADC_SSOP0_S5DCOP        0x00100000  // Sample 5 Digital Comparator
                                              // Operation
  #define ADC_SSOP0_S4DCOP        0x00010000  // Sample 4 Digital Comparator
                                              // Operation
  #define ADC_SSOP0_S3DCOP        0x00001000  // Sample 3 Digital Comparator
                                              // Operation
  #define ADC_SSOP0_S2DCOP        0x00000100  // Sample 2 Digital Comparator
                                              // Operation
  #define ADC_SSOP0_S1DCOP        0x00000010  // Sample 1 Digital Comparator
                                              // Operation
  #define ADC_SSOP0_S0DCOP        0x00000001  // Sample 0 Digital Comparator
                                              // Operation
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSDC0 register.
  //
  //*****************************************************************************
  #define ADC_SSDC0_S7DCSEL_M     0xF0000000  // Sample 7 Digital Comparator
                                              // Select
  #define ADC_SSDC0_S6DCSEL_M     0x0F000000  // Sample 6 Digital Comparator
                                              // Select
  #define ADC_SSDC0_S5DCSEL_M     0x00F00000  // Sample 5 Digital Comparator
                                              // Select
  #define ADC_SSDC0_S4DCSEL_M     0x000F0000  // Sample 4 Digital Comparator
                                              // Select
  #define ADC_SSDC0_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
                                              // Select
  #define ADC_SSDC0_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
                                              // Select
  #define ADC_SSDC0_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
                                              // Select
  #define ADC_SSDC0_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
                                              // Select
  #define ADC_SSDC0_S6DCSEL_S     24
  #define ADC_SSDC0_S5DCSEL_S     20
  #define ADC_SSDC0_S4DCSEL_S     16
  #define ADC_SSDC0_S3DCSEL_S     12
  #define ADC_SSDC0_S2DCSEL_S     8
  #define ADC_SSDC0_S1DCSEL_S     4
  #define ADC_SSDC0_S0DCSEL_S     0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSMUX1 register.
  //
  //*****************************************************************************
  #define ADC_SSMUX1_MUX3_M       0x0000F000  // 4th Sample Input Select
  #define ADC_SSMUX1_MUX2_M       0x00000F00  // 3rd Sample Input Select
  #define ADC_SSMUX1_MUX1_M       0x000000F0  // 2nd Sample Input Select
  #define ADC_SSMUX1_MUX0_M       0x0000000F  // 1st Sample Input Select
  #define ADC_SSMUX1_MUX3_S       12
  #define ADC_SSMUX1_MUX2_S       8
  #define ADC_SSMUX1_MUX1_S       4
  #define ADC_SSMUX1_MUX0_S       0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSCTL1 register.
  //
  //*****************************************************************************
  #define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select
  #define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable
  #define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence
  #define ADC_SSCTL1_D3           0x00001000  // 4th Sample Diff Input Select
  #define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select
  #define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable
  #define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence
  #define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Diff Input Select
  #define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select
  #define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable
  #define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence
  #define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Diff Input Select
  #define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select
  #define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable
  #define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence
  #define ADC_SSCTL1_D0           0x00000001  // 1st Sample Diff Input Select
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
  //
  //*****************************************************************************
  #define ADC_SSFIFO1_DATA_M      0x00000FFF  // Conversion Result Data
  #define ADC_SSFIFO1_DATA_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
  //
  //*****************************************************************************
  #define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full
  #define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty
  #define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer
  #define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer
  #define ADC_SSFSTAT1_HPTR_S     4
  #define ADC_SSFSTAT1_TPTR_S     0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSOP1 register.
  //
  //*****************************************************************************
  #define ADC_SSOP1_S3DCOP        0x00001000  // Sample 3 Digital Comparator
                                              // Operation
  #define ADC_SSOP1_S2DCOP        0x00000100  // Sample 2 Digital Comparator
                                              // Operation
  #define ADC_SSOP1_S1DCOP        0x00000010  // Sample 1 Digital Comparator
                                              // Operation
  #define ADC_SSOP1_S0DCOP        0x00000001  // Sample 0 Digital Comparator
                                              // Operation
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSDC1 register.
  //
  //*****************************************************************************
  #define ADC_SSDC1_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
                                              // Select
  #define ADC_SSDC1_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
                                              // Select
  #define ADC_SSDC1_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
                                              // Select
  #define ADC_SSDC1_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
                                              // Select
  #define ADC_SSDC1_S2DCSEL_S     8
  #define ADC_SSDC1_S1DCSEL_S     4
  #define ADC_SSDC1_S0DCSEL_S     0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSMUX2 register.
  //
  //*****************************************************************************
  #define ADC_SSMUX2_MUX3_M       0x0000F000  // 4th Sample Input Select
  #define ADC_SSMUX2_MUX2_M       0x00000F00  // 3rd Sample Input Select
  #define ADC_SSMUX2_MUX1_M       0x000000F0  // 2nd Sample Input Select
  #define ADC_SSMUX2_MUX0_M       0x0000000F  // 1st Sample Input Select
  #define ADC_SSMUX2_MUX3_S       12
  #define ADC_SSMUX2_MUX2_S       8
  #define ADC_SSMUX2_MUX1_S       4
  #define ADC_SSMUX2_MUX0_S       0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSCTL2 register.
  //
  //*****************************************************************************
  #define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select
  #define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable
  #define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence
  #define ADC_SSCTL2_D3           0x00001000  // 4th Sample Diff Input Select
  #define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select
  #define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable
  #define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence
  #define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Diff Input Select
  #define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select
  #define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable
  #define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence
  #define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Diff Input Select
  #define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select
  #define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable
  #define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence
  #define ADC_SSCTL2_D0           0x00000001  // 1st Sample Diff Input Select
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
  //
  //*****************************************************************************
  #define ADC_SSFIFO2_DATA_M      0x00000FFF  // Conversion Result Data
  #define ADC_SSFIFO2_DATA_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
  //
  //*****************************************************************************
  #define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full
  #define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty
  #define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer
  #define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer
  #define ADC_SSFSTAT2_HPTR_S     4
  #define ADC_SSFSTAT2_TPTR_S     0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSOP2 register.
  //
  //*****************************************************************************
  #define ADC_SSOP2_S3DCOP        0x00001000  // Sample 3 Digital Comparator
                                              // Operation
  #define ADC_SSOP2_S2DCOP        0x00000100  // Sample 2 Digital Comparator
                                              // Operation
  #define ADC_SSOP2_S1DCOP        0x00000010  // Sample 1 Digital Comparator
                                              // Operation
  #define ADC_SSOP2_S0DCOP        0x00000001  // Sample 0 Digital Comparator
                                              // Operation
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSDC2 register.
  //
  //*****************************************************************************
  #define ADC_SSDC2_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
                                              // Select
  #define ADC_SSDC2_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
                                              // Select
  #define ADC_SSDC2_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
                                              // Select
  #define ADC_SSDC2_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
                                              // Select
  #define ADC_SSDC2_S2DCSEL_S     8
  #define ADC_SSDC2_S1DCSEL_S     4
  #define ADC_SSDC2_S0DCSEL_S     0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSMUX3 register.
  //
  //*****************************************************************************
  #define ADC_SSMUX3_MUX0_M       0x0000000F  // 1st Sample Input Select
  #define ADC_SSMUX3_MUX0_S       0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSCTL3 register.
  //
  //*****************************************************************************
  #define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select
  #define ADC_SSCTL3_IE0          0x00000004  // 1st Sample Interrupt Enable
  #define ADC_SSCTL3_END0         0x00000002  // 1st Sample is End of Sequence
  #define ADC_SSCTL3_D0           0x00000001  // 1st Sample Diff Input Select
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
  //
  //*****************************************************************************
  #define ADC_SSFIFO3_DATA_M      0x00000FFF  // Conversion Result Data
  #define ADC_SSFIFO3_DATA_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
  //
  //*****************************************************************************
  #define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full
  #define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty
  #define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer
  #define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer
  #define ADC_SSFSTAT3_HPTR_S     4
  #define ADC_SSFSTAT3_TPTR_S     0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSOP3 register.
  //
  //*****************************************************************************
  #define ADC_SSOP3_S0DCOP        0x00000001  // Sample 0 Digital Comparator
                                              // Operation
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_SSDC3 register.
  //
  //*****************************************************************************
  #define ADC_SSDC3_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
                                              // Select
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCRIC register.
  //
  //*****************************************************************************
  #define ADC_DCRIC_DCTRIG7       0x00800000  // Digital Comparator Trigger 7
  #define ADC_DCRIC_DCTRIG6       0x00400000  // Digital Comparator Trigger 6
  #define ADC_DCRIC_DCTRIG5       0x00200000  // Digital Comparator Trigger 5
  #define ADC_DCRIC_DCTRIG4       0x00100000  // Digital Comparator Trigger 4
  #define ADC_DCRIC_DCTRIG3       0x00080000  // Digital Comparator Trigger 3
  #define ADC_DCRIC_DCTRIG2       0x00040000  // Digital Comparator Trigger 2
  #define ADC_DCRIC_DCTRIG1       0x00020000  // Digital Comparator Trigger 1
  #define ADC_DCRIC_DCTRIG0       0x00010000  // Digital Comparator Trigger 0
  #define ADC_DCRIC_DCINT7        0x00000080  // Digital Comparator Interrupt 7
  #define ADC_DCRIC_DCINT6        0x00000040  // Digital Comparator Interrupt 6
  #define ADC_DCRIC_DCINT5        0x00000020  // Digital Comparator Interrupt 5
  #define ADC_DCRIC_DCINT4        0x00000010  // Digital Comparator Interrupt 4
  #define ADC_DCRIC_DCINT3        0x00000008  // Digital Comparator Interrupt 3
  #define ADC_DCRIC_DCINT2        0x00000004  // Digital Comparator Interrupt 2
  #define ADC_DCRIC_DCINT1        0x00000002  // Digital Comparator Interrupt 1
  #define ADC_DCRIC_DCINT0        0x00000001  // Digital Comparator Interrupt 0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCTL0 register.
  //
  //*****************************************************************************
  #define ADC_DCCTL0_CIE          0x00000010  // Comparison Interrupt Enable
  #define ADC_DCCTL0_CIC_M        0x0000000C  // Comparison Interrupt Condition
  #define ADC_DCCTL0_CIC_LOW      0x00000000  // Low Band
  #define ADC_DCCTL0_CIC_MID      0x00000004  // Mid Band
  #define ADC_DCCTL0_CIC_HIGH     0x0000000C  // High Band
  #define ADC_DCCTL0_CIM_M        0x00000003  // Comparison Interrupt Mode
  #define ADC_DCCTL0_CIM_ALWAYS   0x00000000  // Always
  #define ADC_DCCTL0_CIM_ONCE     0x00000001  // Once
  #define ADC_DCCTL0_CIM_HALWAYS  0x00000002  // Hysteresis Always
  #define ADC_DCCTL0_CIM_HONCE    0x00000003  // Hysteresis Once
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCTL1 register.
  //
  //*****************************************************************************
  #define ADC_DCCTL1_CIE          0x00000010  // Comparison Interrupt Enable
  #define ADC_DCCTL1_CIC_M        0x0000000C  // Comparison Interrupt Condition
  #define ADC_DCCTL1_CIC_LOW      0x00000000  // Low Band
  #define ADC_DCCTL1_CIC_MID      0x00000004  // Mid Band
  #define ADC_DCCTL1_CIC_HIGH     0x0000000C  // High Band
  #define ADC_DCCTL1_CIM_M        0x00000003  // Comparison Interrupt Mode
  #define ADC_DCCTL1_CIM_ALWAYS   0x00000000  // Always
  #define ADC_DCCTL1_CIM_ONCE     0x00000001  // Once
  #define ADC_DCCTL1_CIM_HALWAYS  0x00000002  // Hysteresis Always
  #define ADC_DCCTL1_CIM_HONCE    0x00000003  // Hysteresis Once
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCTL2 register.
  //
  //*****************************************************************************
  #define ADC_DCCTL2_CIE          0x00000010  // Comparison Interrupt Enable
  #define ADC_DCCTL2_CIC_M        0x0000000C  // Comparison Interrupt Condition
  #define ADC_DCCTL2_CIC_LOW      0x00000000  // Low Band
  #define ADC_DCCTL2_CIC_MID      0x00000004  // Mid Band
  #define ADC_DCCTL2_CIC_HIGH     0x0000000C  // High Band
  #define ADC_DCCTL2_CIM_M        0x00000003  // Comparison Interrupt Mode
  #define ADC_DCCTL2_CIM_ALWAYS   0x00000000  // Always
  #define ADC_DCCTL2_CIM_ONCE     0x00000001  // Once
  #define ADC_DCCTL2_CIM_HALWAYS  0x00000002  // Hysteresis Always
  #define ADC_DCCTL2_CIM_HONCE    0x00000003  // Hysteresis Once
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCTL3 register.
  //
  //*****************************************************************************
  #define ADC_DCCTL3_CIE          0x00000010  // Comparison Interrupt Enable
  #define ADC_DCCTL3_CIC_M        0x0000000C  // Comparison Interrupt Condition
  #define ADC_DCCTL3_CIC_LOW      0x00000000  // Low Band
  #define ADC_DCCTL3_CIC_MID      0x00000004  // Mid Band
  #define ADC_DCCTL3_CIC_HIGH     0x0000000C  // High Band
  #define ADC_DCCTL3_CIM_M        0x00000003  // Comparison Interrupt Mode
  #define ADC_DCCTL3_CIM_ALWAYS   0x00000000  // Always
  #define ADC_DCCTL3_CIM_ONCE     0x00000001  // Once
  #define ADC_DCCTL3_CIM_HALWAYS  0x00000002  // Hysteresis Always
  #define ADC_DCCTL3_CIM_HONCE    0x00000003  // Hysteresis Once
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCTL4 register.
  //
  //*****************************************************************************
  #define ADC_DCCTL4_CIE          0x00000010  // Comparison Interrupt Enable
  #define ADC_DCCTL4_CIC_M        0x0000000C  // Comparison Interrupt Condition
  #define ADC_DCCTL4_CIC_LOW      0x00000000  // Low Band
  #define ADC_DCCTL4_CIC_MID      0x00000004  // Mid Band
  #define ADC_DCCTL4_CIC_HIGH     0x0000000C  // High Band
  #define ADC_DCCTL4_CIM_M        0x00000003  // Comparison Interrupt Mode
  #define ADC_DCCTL4_CIM_ALWAYS   0x00000000  // Always
  #define ADC_DCCTL4_CIM_ONCE     0x00000001  // Once
  #define ADC_DCCTL4_CIM_HALWAYS  0x00000002  // Hysteresis Always
  #define ADC_DCCTL4_CIM_HONCE    0x00000003  // Hysteresis Once
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCTL5 register.
  //
  //*****************************************************************************
  #define ADC_DCCTL5_CIE          0x00000010  // Comparison Interrupt Enable
  #define ADC_DCCTL5_CIC_M        0x0000000C  // Comparison Interrupt Condition
  #define ADC_DCCTL5_CIC_LOW      0x00000000  // Low Band
  #define ADC_DCCTL5_CIC_MID      0x00000004  // Mid Band
  #define ADC_DCCTL5_CIC_HIGH     0x0000000C  // High Band
  #define ADC_DCCTL5_CIM_M        0x00000003  // Comparison Interrupt Mode
  #define ADC_DCCTL5_CIM_ALWAYS   0x00000000  // Always
  #define ADC_DCCTL5_CIM_ONCE     0x00000001  // Once
  #define ADC_DCCTL5_CIM_HALWAYS  0x00000002  // Hysteresis Always
  #define ADC_DCCTL5_CIM_HONCE    0x00000003  // Hysteresis Once
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCTL6 register.
  //
  //*****************************************************************************
  #define ADC_DCCTL6_CIE          0x00000010  // Comparison Interrupt Enable
  #define ADC_DCCTL6_CIC_M        0x0000000C  // Comparison Interrupt Condition
  #define ADC_DCCTL6_CIC_LOW      0x00000000  // Low Band
  #define ADC_DCCTL6_CIC_MID      0x00000004  // Mid Band
  #define ADC_DCCTL6_CIC_HIGH     0x0000000C  // High Band
  #define ADC_DCCTL6_CIM_M        0x00000003  // Comparison Interrupt Mode
  #define ADC_DCCTL6_CIM_ALWAYS   0x00000000  // Always
  #define ADC_DCCTL6_CIM_ONCE     0x00000001  // Once
  #define ADC_DCCTL6_CIM_HALWAYS  0x00000002  // Hysteresis Always
  #define ADC_DCCTL6_CIM_HONCE    0x00000003  // Hysteresis Once
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCTL7 register.
  //
  //*****************************************************************************
  #define ADC_DCCTL7_CIE          0x00000010  // Comparison Interrupt Enable
  #define ADC_DCCTL7_CIC_M        0x0000000C  // Comparison Interrupt Condition
  #define ADC_DCCTL7_CIC_LOW      0x00000000  // Low Band
  #define ADC_DCCTL7_CIC_MID      0x00000004  // Mid Band
  #define ADC_DCCTL7_CIC_HIGH     0x0000000C  // High Band
  #define ADC_DCCTL7_CIM_M        0x00000003  // Comparison Interrupt Mode
  #define ADC_DCCTL7_CIM_ALWAYS   0x00000000  // Always
  #define ADC_DCCTL7_CIM_ONCE     0x00000001  // Once
  #define ADC_DCCTL7_CIM_HALWAYS  0x00000002  // Hysteresis Always
  #define ADC_DCCTL7_CIM_HONCE    0x00000003  // Hysteresis Once
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCMP0 register.
  //
  //*****************************************************************************
  #define ADC_DCCMP0_COMP1_M      0x0FFF0000  // Compare 1
  #define ADC_DCCMP0_COMP0_M      0x00000FFF  // Compare 0
  #define ADC_DCCMP0_COMP1_S      16
  #define ADC_DCCMP0_COMP0_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCMP1 register.
  //
  //*****************************************************************************
  #define ADC_DCCMP1_COMP1_M      0x0FFF0000  // Compare 1
  #define ADC_DCCMP1_COMP0_M      0x00000FFF  // Compare 0
  #define ADC_DCCMP1_COMP1_S      16
  #define ADC_DCCMP1_COMP0_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCMP2 register.
  //
  //*****************************************************************************
  #define ADC_DCCMP2_COMP1_M      0x0FFF0000  // Compare 1
  #define ADC_DCCMP2_COMP0_M      0x00000FFF  // Compare 0
  #define ADC_DCCMP2_COMP1_S      16
  #define ADC_DCCMP2_COMP0_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCMP3 register.
  //
  //*****************************************************************************
  #define ADC_DCCMP3_COMP1_M      0x0FFF0000  // Compare 1
  #define ADC_DCCMP3_COMP0_M      0x00000FFF  // Compare 0
  #define ADC_DCCMP3_COMP1_S      16
  #define ADC_DCCMP3_COMP0_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCMP4 register.
  //
  //*****************************************************************************
  #define ADC_DCCMP4_COMP1_M      0x0FFF0000  // Compare 1
  #define ADC_DCCMP4_COMP0_M      0x00000FFF  // Compare 0
  #define ADC_DCCMP4_COMP1_S      16
  #define ADC_DCCMP4_COMP0_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCMP5 register.
  //
  //*****************************************************************************
  #define ADC_DCCMP5_COMP1_M      0x0FFF0000  // Compare 1
  #define ADC_DCCMP5_COMP0_M      0x00000FFF  // Compare 0
  #define ADC_DCCMP5_COMP1_S      16
  #define ADC_DCCMP5_COMP0_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCMP6 register.
  //
  //*****************************************************************************
  #define ADC_DCCMP6_COMP1_M      0x0FFF0000  // Compare 1
  #define ADC_DCCMP6_COMP0_M      0x00000FFF  // Compare 0
  #define ADC_DCCMP6_COMP1_S      16
  #define ADC_DCCMP6_COMP0_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_DCCMP7 register.
  //
  //*****************************************************************************
  #define ADC_DCCMP7_COMP1_M      0x0FFF0000  // Compare 1
  #define ADC_DCCMP7_COMP0_M      0x00000FFF  // Compare 0
  #define ADC_DCCMP7_COMP1_S      16
  #define ADC_DCCMP7_COMP0_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_PP register.
  //
  //*****************************************************************************
  #define ADC_PP_TS               0x00800000  // Temperature Sensor
  #define ADC_PP_RSL_M            0x007C0000  // Resolution
  #define ADC_PP_TYPE_M           0x00030000  // ADC Architecture
  #define ADC_PP_TYPE_SAR         0x00000000  // SAR
  #define ADC_PP_DC_M             0x0000FC00  // Digital Comparator Count
  #define ADC_PP_CH_M             0x000003F0  // ADC Channel Count
  #define ADC_PP_MSR_M            0x0000000F  // Maximum ADC Sample Rate
  #define ADC_PP_MSR_125K         0x00000001  // 125 ksps
  #define ADC_PP_MSR_250K         0x00000003  // 250 ksps
  #define ADC_PP_MSR_500K         0x00000005  // 500 ksps
  #define ADC_PP_MSR_1M           0x00000007  // 1 Msps
  #define ADC_PP_RSL_S            18
  #define ADC_PP_DC_S             10
  #define ADC_PP_CH_S             4
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_PC register.
  //
  //*****************************************************************************
  #define ADC_PC_SR_M             0x0000000F  // ADC Sample Rate
  #define ADC_PC_SR_125K          0x00000001  // 125 ksps
  #define ADC_PC_SR_250K          0x00000003  // 250 ksps
  #define ADC_PC_SR_500K          0x00000005  // 500 ksps
  #define ADC_PC_SR_1M            0x00000007  // 1 Msps
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the ADC_O_CC register.
  //
  //*****************************************************************************
  #define ADC_CC_CS_M             0x0000000F  // ADC Clock Source
  #define ADC_CC_CS_SYSPLL        0x00000000  // Either the system clock (if the
                                              // PLL bypass is in effect) or the
                                              // 16 MHz clock derived from PLL /
                                              // 25 (default)
  #define ADC_CC_CS_PIOSC         0x00000001  // PIOSC
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the COMP_O_ACMIS register.
  //
  //*****************************************************************************
  #define COMP_ACMIS_IN1          0x00000002  // Comparator 1 Masked Interrupt
                                              // Status
  #define COMP_ACMIS_IN0          0x00000001  // Comparator 0 Masked Interrupt
                                              // Status
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the COMP_O_ACRIS register.
  //
  //*****************************************************************************
  #define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status
  #define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the COMP_O_ACINTEN register.
  //
  //*****************************************************************************
  #define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable
  #define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the COMP_O_ACREFCTL
  // register.
  //
  //*****************************************************************************
  #define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable
  #define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range
  #define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref
  #define COMP_ACREFCTL_VREF_S    0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
  //
  //*****************************************************************************
  #define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the COMP_O_ACCTL0 register.
  //
  //*****************************************************************************
  #define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable
  #define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive
  #define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value of Cn+
  #define COMP_ACCTL0_ASRCP_PIN0  0x00000200  // Pin value of C0+
  #define COMP_ACCTL0_ASRCP_REF   0x00000400  // Internal voltage reference
  #define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value
  #define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense
  #define COMP_ACCTL0_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
  #define COMP_ACCTL0_TSEN_FALL   0x00000020  // Falling edge
  #define COMP_ACCTL0_TSEN_RISE   0x00000040  // Rising edge
  #define COMP_ACCTL0_TSEN_BOTH   0x00000060  // Either edge
  #define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value
  #define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense
  #define COMP_ACCTL0_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
  #define COMP_ACCTL0_ISEN_FALL   0x00000004  // Falling edge
  #define COMP_ACCTL0_ISEN_RISE   0x00000008  // Rising edge
  #define COMP_ACCTL0_ISEN_BOTH   0x0000000C  // Either edge
  #define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
  //
  //*****************************************************************************
  #define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the COMP_O_ACCTL1 register.
  //
  //*****************************************************************************
  #define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable
  #define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive
  #define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value of Cn+
  #define COMP_ACCTL1_ASRCP_PIN0  0x00000200  // Pin value of C0+
  #define COMP_ACCTL1_ASRCP_REF   0x00000400  // Internal voltage reference
                                              // (VIREF)
  #define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value
  #define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense
  #define COMP_ACCTL1_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
  #define COMP_ACCTL1_TSEN_FALL   0x00000020  // Falling edge
  #define COMP_ACCTL1_TSEN_RISE   0x00000040  // Rising edge
  #define COMP_ACCTL1_TSEN_BOTH   0x00000060  // Either edge
  #define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value
  #define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense
  #define COMP_ACCTL1_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
  #define COMP_ACCTL1_ISEN_FALL   0x00000004  // Falling edge
  #define COMP_ACCTL1_ISEN_RISE   0x00000008  // Rising edge
  #define COMP_ACCTL1_ISEN_BOTH   0x0000000C  // Either edge
  #define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the COMP_O_PP register.
  //
  //*****************************************************************************
  #define COMP_PP_C2O             0x00040000  // Comparator Output 2 Present
  #define COMP_PP_C1O             0x00020000  // Comparator Output 1 Present
  #define COMP_PP_C0O             0x00010000  // Comparator Output 0 Present
  #define COMP_PP_CMP2            0x00000004  // Comparator 2 Present
  #define COMP_PP_CMP1            0x00000002  // Comparator 1 Present
  #define COMP_PP_CMP0            0x00000001  // Comparator 0 Present
  
  
  
  
  
  /*************************************************************************
   ************************************************************************/
   /* Timer MACROS                                                          */
   /************************************************************************
   ************************************************************************/
   
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_CFG register.
  //
  //*****************************************************************************
  #define TIMER_CFG_M             0x00000007  // GPTM Configuration
  #define TIMER_CFG_32_BIT_TIMER  0x00000000  // 32-bit timer configuration
  #define TIMER_CFG_32_BIT_RTC    0x00000001  // 32-bit real-time clock (RTC)
                                              // counter configuration
  #define TIMER_CFG_16_BIT        0x00000004  // 16-bit timer configuration. The
                                              // function is controlled by bits
                                              // 1:0 of GPTMTAMR and GPTMTBMR
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TAMR register.
  //
  //*****************************************************************************
  #define TIMER_TAMR_TAPLO        0x00000800  // GPTM Timer A PWM Legacy
                                              // Operation
  #define TIMER_TAMR_TAMRSU       0x00000400  // GPTM Timer A Match Register
                                              // Update
  #define TIMER_TAMR_TAPWMIE      0x00000200  // GPTM Timer A PWM Interrupt
                                              // Enable
  #define TIMER_TAMR_TAILD        0x00000100  // GPTM Timer A Interval Load Write
  #define TIMER_TAMR_TASNAPS      0x00000080  // GPTM Timer A Snap-Shot Mode
  #define TIMER_TAMR_TAWOT        0x00000040  // GPTM Timer A Wait-on-Trigger
  #define TIMER_TAMR_TAMIE        0x00000020  // GPTM Timer A Match Interrupt
                                              // Enable
  #define TIMER_TAMR_TACDIR       0x00000010  // GPTM Timer A Count Direction
  #define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode
                                              // Select
  #define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode
  #define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode
  #define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode
  #define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode
  #define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TBMR register.
  //
  //*****************************************************************************
  #define TIMER_TBMR_TBPLO        0x00000800  // GPTM Timer B PWM Legacy
                                              // Operation
  #define TIMER_TBMR_TBMRSU       0x00000400  // GPTM Timer B Match Register
                                              // Update
  #define TIMER_TBMR_TBPWMIE      0x00000200  // GPTM Timer B PWM Interrupt
                                              // Enable
  #define TIMER_TBMR_TBILD        0x00000100  // GPTM Timer B Interval Load Write
  #define TIMER_TBMR_TBSNAPS      0x00000080  // GPTM Timer B Snap-Shot Mode
  #define TIMER_TBMR_TBWOT        0x00000040  // GPTM Timer B Wait-on-Trigger
  #define TIMER_TBMR_TBMIE        0x00000020  // GPTM Timer B Match Interrupt
                                              // Enable
  #define TIMER_TBMR_TBCDIR       0x00000010  // GPTM Timer B Count Direction
  #define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode
                                              // Select
  #define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode
  #define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode
  #define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode
  #define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode
  #define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_CTL register.
  //
  //*****************************************************************************
  #define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level
  #define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger
                                              // Enable
  #define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode
  #define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge
  #define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge
  #define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges
  #define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable
  #define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable
  #define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level
  #define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger
                                              // Enable
  #define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Enable
  #define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode
  #define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge
  #define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge
  #define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges
  #define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable
  #define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_SYNC register.
  //
  //*****************************************************************************
  #define TIMER_SYNC_SYNCWT5_M    0x00C00000  // Synchronize GPTM 32/64-Bit Timer
                                              // 5
  #define TIMER_SYNC_SYNCWT5_NONE 0x00000000  // GPTM 32/64-Bit Timer 5 is not
                                              // affected
  #define TIMER_SYNC_SYNCWT5_TA   0x00400000  // A timeout event for Timer A of
                                              // GPTM 32/64-Bit Timer 5 is
                                              // triggered
  #define TIMER_SYNC_SYNCWT5_TB   0x00800000  // A timeout event for Timer B of
                                              // GPTM 32/64-Bit Timer 5 is
                                              // triggered
  #define TIMER_SYNC_SYNCWT5_TATB 0x00C00000  // A timeout event for both Timer A
                                              // and Timer B of GPTM 32/64-Bit
                                              // Timer 5 is triggered
  #define TIMER_SYNC_SYNCWT4_M    0x00300000  // Synchronize GPTM 32/64-Bit Timer
                                              // 4
  #define TIMER_SYNC_SYNCWT4_NONE 0x00000000  // GPTM 32/64-Bit Timer 4 is not
                                              // affected
  #define TIMER_SYNC_SYNCWT4_TA   0x00100000  // A timeout event for Timer A of
                                              // GPTM 32/64-Bit Timer 4 is
                                              // triggered
  #define TIMER_SYNC_SYNCWT4_TB   0x00200000  // A timeout event for Timer B of
                                              // GPTM 32/64-Bit Timer 4 is
                                              // triggered
  #define TIMER_SYNC_SYNCWT4_TATB 0x00300000  // A timeout event for both Timer A
                                              // and Timer B of GPTM 32/64-Bit
                                              // Timer 4 is triggered
  #define TIMER_SYNC_SYNCWT3_M    0x000C0000  // Synchronize GPTM 32/64-Bit Timer
                                              // 3
  #define TIMER_SYNC_SYNCWT3_NONE 0x00000000  // GPTM 32/64-Bit Timer 3 is not
                                              // affected
  #define TIMER_SYNC_SYNCWT3_TA   0x00040000  // A timeout event for Timer A of
                                              // GPTM 32/64-Bit Timer 3 is
                                              // triggered
  #define TIMER_SYNC_SYNCWT3_TB   0x00080000  // A timeout event for Timer B of
                                              // GPTM 32/64-Bit Timer 3 is
                                              // triggered
  #define TIMER_SYNC_SYNCWT3_TATB 0x000C0000  // A timeout event for both Timer A
                                              // and Timer B of GPTM 32/64-Bit
                                              // Timer 3 is triggered
  #define TIMER_SYNC_SYNCWT2_M    0x00030000  // Synchronize GPTM 32/64-Bit Timer
                                              // 2
  #define TIMER_SYNC_SYNCWT2_NONE 0x00000000  // GPTM 32/64-Bit Timer 2 is not
                                              // affected
  #define TIMER_SYNC_SYNCWT2_TA   0x00010000  // A timeout event for Timer A of
                                              // GPTM 32/64-Bit Timer 2 is
                                              // triggered
  #define TIMER_SYNC_SYNCWT2_TB   0x00020000  // A timeout event for Timer B of
                                              // GPTM 32/64-Bit Timer 2 is
                                              // triggered
  #define TIMER_SYNC_SYNCWT2_TATB 0x00030000  // A timeout event for both Timer A
                                              // and Timer B of GPTM 32/64-Bit
                                              // Timer 2 is triggered
  #define TIMER_SYNC_SYNCWT1_M    0x0000C000  // Synchronize GPTM 32/64-Bit Timer
                                              // 1
  #define TIMER_SYNC_SYNCWT1_NONE 0x00000000  // GPTM 32/64-Bit Timer 1 is not
                                              // affected
  #define TIMER_SYNC_SYNCWT1_TA   0x00004000  // A timeout event for Timer A of
                                              // GPTM 32/64-Bit Timer 1 is
                                              // triggered
  #define TIMER_SYNC_SYNCWT1_TB   0x00008000  // A timeout event for Timer B of
                                              // GPTM 32/64-Bit Timer 1 is
                                              // triggered
  #define TIMER_SYNC_SYNCWT1_TATB 0x0000C000  // A timeout event for both Timer A
                                              // and Timer B of GPTM 32/64-Bit
                                              // Timer 1 is triggered
  #define TIMER_SYNC_SYNCWT0_M    0x00003000  // Synchronize GPTM 32/64-Bit Timer
                                              // 0
  #define TIMER_SYNC_SYNCWT0_NONE 0x00000000  // GPTM 32/64-Bit Timer 0 is not
                                              // affected
  #define TIMER_SYNC_SYNCWT0_TA   0x00001000  // A timeout event for Timer A of
                                              // GPTM 32/64-Bit Timer 0 is
                                              // triggered
  #define TIMER_SYNC_SYNCWT0_TB   0x00002000  // A timeout event for Timer B of
                                              // GPTM 32/64-Bit Timer 0 is
                                              // triggered
  #define TIMER_SYNC_SYNCWT0_TATB 0x00003000  // A timeout event for both Timer A
                                              // and Timer B of GPTM 32/64-Bit
                                              // Timer 0 is triggered
  #define TIMER_SYNC_SYNCT5_M     0x00000C00  // Synchronize GPTM 16/32-Bit Timer
                                              // 5
  #define TIMER_SYNC_SYNCT5_NONE  0x00000000  // GPTM 16/32-Bit Timer 5 is not
                                              // affected
  #define TIMER_SYNC_SYNCT5_TA    0x00000400  // A timeout event for Timer A of
                                              // GPTM 16/32-Bit Timer 5 is
                                              // triggered
  #define TIMER_SYNC_SYNCT5_TB    0x00000800  // A timeout event for Timer B of
                                              // GPTM 16/32-Bit Timer 5 is
                                              // triggered
  #define TIMER_SYNC_SYNCT5_TATB  0x00000C00  // A timeout event for both Timer A
                                              // and Timer B of GPTM 16/32-Bit
                                              // Timer 5 is triggered
  #define TIMER_SYNC_SYNCT4_M     0x00000300  // Synchronize GPTM 16/32-Bit Timer
                                              // 4
  #define TIMER_SYNC_SYNCT4_NONE  0x00000000  // GPTM 16/32-Bit Timer 4 is not
                                              // affected
  #define TIMER_SYNC_SYNCT4_TA    0x00000100  // A timeout event for Timer A of
                                              // GPTM 16/32-Bit Timer 4 is
                                              // triggered
  #define TIMER_SYNC_SYNCT4_TB    0x00000200  // A timeout event for Timer B of
                                              // GPTM 16/32-Bit Timer 4 is
                                              // triggered
  #define TIMER_SYNC_SYNCT4_TATB  0x00000300  // A timeout event for both Timer A
                                              // and Timer B of GPTM 16/32-Bit
                                              // Timer 4 is triggered
  #define TIMER_SYNC_SYNCT3_M     0x000000C0  // Synchronize GPTM 16/32-Bit Timer
                                              // 3
  #define TIMER_SYNC_SYNCT3_NONE  0x00000000  // GPTM 16/32-Bit Timer 3 is not
                                              // affected
  #define TIMER_SYNC_SYNCT3_TA    0x00000040  // A timeout event for Timer A of
                                              // GPTM 16/32-Bit Timer 3 is
                                              // triggered
  #define TIMER_SYNC_SYNCT3_TB    0x00000080  // A timeout event for Timer B of
                                              // GPTM 16/32-Bit Timer 3 is
                                              // triggered
  #define TIMER_SYNC_SYNCT3_TATB  0x000000C0  // A timeout event for both Timer A
                                              // and Timer B of GPTM 16/32-Bit
                                              // Timer 3 is triggered
  #define TIMER_SYNC_SYNCT2_M     0x00000030  // Synchronize GPTM 16/32-Bit Timer
                                              // 2
  #define TIMER_SYNC_SYNCT2_NONE  0x00000000  // GPTM 16/32-Bit Timer 2 is not
                                              // affected
  #define TIMER_SYNC_SYNCT2_TA    0x00000010  // A timeout event for Timer A of
                                              // GPTM 16/32-Bit Timer 2 is
                                              // triggered
  #define TIMER_SYNC_SYNCT2_TB    0x00000020  // A timeout event for Timer B of
                                              // GPTM 16/32-Bit Timer 2 is
                                              // triggered
  #define TIMER_SYNC_SYNCT2_TATB  0x00000030  // A timeout event for both Timer A
                                              // and Timer B of GPTM 16/32-Bit
                                              // Timer 2 is triggered
  #define TIMER_SYNC_SYNCT1_M     0x0000000C  // Synchronize GPTM 16/32-Bit Timer
                                              // 1
  #define TIMER_SYNC_SYNCT1_NONE  0x00000000  // GPTM 16/32-Bit Timer 1 is not
                                              // affected
  #define TIMER_SYNC_SYNCT1_TA    0x00000004  // A timeout event for Timer A of
                                              // GPTM 16/32-Bit Timer 1 is
                                              // triggered
  #define TIMER_SYNC_SYNCT1_TB    0x00000008  // A timeout event for Timer B of
                                              // GPTM 16/32-Bit Timer 1 is
                                              // triggered
  #define TIMER_SYNC_SYNCT1_TATB  0x0000000C  // A timeout event for both Timer A
                                              // and Timer B of GPTM 16/32-Bit
                                              // Timer 1 is triggered
  #define TIMER_SYNC_SYNCT0_M     0x00000003  // Synchronize GPTM 16/32-Bit Timer
                                              // 0
  #define TIMER_SYNC_SYNCT0_NONE  0x00000000  // GPTM 16/32-Bit Timer 0 is not
                                              // affected
  #define TIMER_SYNC_SYNCT0_TA    0x00000001  // A timeout event for Timer A of
                                              // GPTM 16/32-Bit Timer 0 is
                                              // triggered
  #define TIMER_SYNC_SYNCT0_TB    0x00000002  // A timeout event for Timer B of
                                              // GPTM 16/32-Bit Timer 0 is
                                              // triggered
  #define TIMER_SYNC_SYNCT0_TATB  0x00000003  // A timeout event for both Timer A
                                              // and Timer B of GPTM 16/32-Bit
                                              // Timer 0 is triggered
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_IMR register.
  //
  //*****************************************************************************
  #define TIMER_IMR_WUEIM         0x00010000  // 32/64-Bit GPTM Write Update
                                              // Error Interrupt Mask
  #define TIMER_IMR_TBMIM         0x00000800  // GPTM Timer B Mode Match
                                              // Interrupt Mask
  #define TIMER_IMR_CBEIM         0x00000400  // GPTM Capture B Event Interrupt
                                              // Mask
  #define TIMER_IMR_CBMIM         0x00000200  // GPTM Capture B Match Interrupt
                                              // Mask
  #define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt
                                              // Mask
  #define TIMER_IMR_TAMIM         0x00000010  // GPTM Timer A Mode Match
                                              // Interrupt Mask
  #define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask
  #define TIMER_IMR_CAEIM         0x00000004  // GPTM Capture A Event Interrupt
                                              // Mask
  #define TIMER_IMR_CAMIM         0x00000002  // GPTM Capture A Match Interrupt
                                              // Mask
  #define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt
                                              // Mask
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_RIS register.
  //
  //*****************************************************************************
  #define TIMER_RIS_WUERIS        0x00010000  // 32/64-Bit GPTM Write Update
                                              // Error Raw Interrupt Status
  #define TIMER_RIS_TBMRIS        0x00000800  // GPTM Timer B Mode Match Raw
                                              // Interrupt
  #define TIMER_RIS_CBERIS        0x00000400  // GPTM Capture B Event Raw
                                              // Interrupt
  #define TIMER_RIS_CBMRIS        0x00000200  // GPTM Capture B Match Raw
                                              // Interrupt
  #define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw
                                              // Interrupt
  #define TIMER_RIS_TAMRIS        0x00000010  // GPTM Timer A Mode Match Raw
                                              // Interrupt
  #define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt
  #define TIMER_RIS_CAERIS        0x00000004  // GPTM Capture A Event Raw
                                              // Interrupt
  #define TIMER_RIS_CAMRIS        0x00000002  // GPTM Capture A Match Raw
                                              // Interrupt
  #define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw
                                              // Interrupt
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_MIS register.
  //
  //*****************************************************************************
  #define TIMER_MIS_WUEMIS        0x00010000  // 32/64-Bit GPTM Write Update
                                              // Error Masked Interrupt Status
  #define TIMER_MIS_TBMMIS        0x00000800  // GPTM Timer B Mode Match Masked
                                              // Interrupt
  #define TIMER_MIS_CBEMIS        0x00000400  // GPTM Capture B Event Masked
                                              // Interrupt
  #define TIMER_MIS_CBMMIS        0x00000200  // GPTM Capture B Match Masked
                                              // Interrupt
  #define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked
                                              // Interrupt
  #define TIMER_MIS_TAMMIS        0x00000010  // GPTM Timer A Mode Match Masked
                                              // Interrupt
  #define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt
  #define TIMER_MIS_CAEMIS        0x00000004  // GPTM Capture A Event Masked
                                              // Interrupt
  #define TIMER_MIS_CAMMIS        0x00000002  // GPTM Capture A Match Masked
                                              // Interrupt
  #define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked
                                              // Interrupt
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_ICR register.
  //
  //*****************************************************************************
  #define TIMER_ICR_WUECINT       0x00010000  // 32/64-Bit GPTM Write Update
                                              // Error Interrupt Clear
  #define TIMER_ICR_TBMCINT       0x00000800  // GPTM Timer B Mode Match
                                              // Interrupt Clear
  #define TIMER_ICR_CBECINT       0x00000400  // GPTM Capture B Event Interrupt
                                              // Clear
  #define TIMER_ICR_CBMCINT       0x00000200  // GPTM Capture B Match Interrupt
                                              // Clear
  #define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt
                                              // Clear
  #define TIMER_ICR_TAMCINT       0x00000010  // GPTM Timer A Mode Match
                                              // Interrupt Clear
  #define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear
  #define TIMER_ICR_CAECINT       0x00000004  // GPTM Capture A Event Interrupt
                                              // Clear
  #define TIMER_ICR_CAMCINT       0x00000002  // GPTM Capture A Match Interrupt
                                              // Clear
  #define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw
                                              // Interrupt
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TAILR register.
  //
  //*****************************************************************************
  #define TIMER_TAILR_M           0xFFFFFFFF  // GPTM Timer A Interval Load
                                              // Register
  #define TIMER_TAILR_S           0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TBILR register.
  //
  //*****************************************************************************
  #define TIMER_TBILR_M           0xFFFFFFFF  // GPTM Timer B Interval Load
                                              // Register
  #define TIMER_TBILR_S           0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TAMATCHR
  // register.
  //
  //*****************************************************************************
  #define TIMER_TAMATCHR_TAMR_M   0xFFFFFFFF  // GPTM Timer A Match Register
  #define TIMER_TAMATCHR_TAMR_S   0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TBMATCHR
  // register.
  //
  //*****************************************************************************
  #define TIMER_TBMATCHR_TBMR_M   0xFFFFFFFF  // GPTM Timer B Match Register
  #define TIMER_TBMATCHR_TBMR_S   0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TAPR register.
  //
  //*****************************************************************************
  #define TIMER_TAPR_TAPSRH_M     0x0000FF00  // GPTM Timer A Prescale High Byte
  #define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale
  #define TIMER_TAPR_TAPSRH_S     8
  #define TIMER_TAPR_TAPSR_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TBPR register.
  //
  //*****************************************************************************
  #define TIMER_TBPR_TBPSRH_M     0x0000FF00  // GPTM Timer B Prescale High Byte
  #define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale
  #define TIMER_TBPR_TBPSRH_S     8
  #define TIMER_TBPR_TBPSR_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TAPMR register.
  //
  //*****************************************************************************
  #define TIMER_TAPMR_TAPSMRH_M   0x0000FF00  // GPTM Timer A Prescale Match High
                                              // Byte
  #define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match
  #define TIMER_TAPMR_TAPSMRH_S   8
  #define TIMER_TAPMR_TAPSMR_S    0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TBPMR register.
  //
  //*****************************************************************************
  #define TIMER_TBPMR_TBPSMRH_M   0x0000FF00  // GPTM Timer B Prescale Match High
                                              // Byte
  #define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match
  #define TIMER_TBPMR_TBPSMRH_S   8
  #define TIMER_TBPMR_TBPSMR_S    0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TAR register.
  //
  //*****************************************************************************
  #define TIMER_TAR_M             0xFFFFFFFF  // GPTM Timer A Register
  #define TIMER_TAR_S             0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TBR register.
  //
  //*****************************************************************************
  #define TIMER_TBR_M             0xFFFFFFFF  // GPTM Timer B Register
  #define TIMER_TBR_S             0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TAV register.
  //
  //*****************************************************************************
  #define TIMER_TAV_M             0xFFFFFFFF  // GPTM Timer A Value
  #define TIMER_TAV_S             0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TBV register.
  //
  //*****************************************************************************
  #define TIMER_TBV_M             0xFFFFFFFF  // GPTM Timer B Value
  #define TIMER_TBV_S             0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_RTCPD register.
  //
  //*****************************************************************************
  #define TIMER_RTCPD_RTCPD_M     0x0000FFFF  // RTC Predivide Counter Value
  #define TIMER_RTCPD_RTCPD_S     0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TAPS register.
  //
  //*****************************************************************************
  #define TIMER_TAPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Snapshot
  #define TIMER_TAPS_PSS_S        0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TBPS register.
  //
  //*****************************************************************************
  #define TIMER_TBPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Value
  #define TIMER_TBPS_PSS_S        0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TAPV register.
  //
  //*****************************************************************************
  #define TIMER_TAPV_PSV_M        0x0000FFFF  // GPTM Timer A Prescaler Value
  #define TIMER_TAPV_PSV_S        0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_TBPV register.
  //
  //*****************************************************************************
  #define TIMER_TBPV_PSV_M        0x0000FFFF  // GPTM Timer B Prescaler Value
  #define TIMER_TBPV_PSV_S        0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the TIMER_O_PP register.
  //
  //*****************************************************************************
  #define TIMER_PP_SIZE_M         0x0000000F  // Count Size
  #define TIMER_PP_SIZE_16        0x00000000  // Timer A and Timer B counters are
                                              // 16 bits each with an 8-bit
                                              // prescale counter
  #define TIMER_PP_SIZE_32        0x00000001  // Timer A and Timer B counters are
                                              // 32 bits each with a 16-bit
                                              // prescale counter
                                              
                                              
                                              
  /*************************************************************************
   ************************************************************************/
   /* UART MACROS                                                          */
   /************************************************************************
   ************************************************************************/
   
  // SysCtrl UART Masks
  #define SYSCTL_RCGCUART_UART7      0x00000080  // UART Module 7 Run Mode Clock
  #define SYSCTL_RCGCUART_UART6      0x00000040  // UART Module 6 Run Mode Clock
  #define SYSCTL_RCGCUART_UART5      0x00000020  // UART Module 5 Run Mode Clock
  #define SYSCTL_RCGCUART_UART4      0x00000010  // UART Module 4 Run Mode Clock
  #define SYSCTL_RCGCUART_UART3      0x00000008  // UART Module 3 Run Mode Clock
  #define SYSCTL_RCGCUART_UART2      0x00000004  // UART Module 2 Run Mode Clock
  #define SYSCTL_RCGCUART_UART1      0x00000002  // UART Module 1 Run Mode Clock
  #define SYSCTL_RCGCUART_UART0      0x00000001  // UART Module 0 Run Mode Clock
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_DR register.
  //
  //*****************************************************************************
  #define UART_DR_OE              0x00000800  // UART Overrun Error
  #define UART_DR_BE              0x00000400  // UART Break Error
  #define UART_DR_PE              0x00000200  // UART Parity Error
  #define UART_DR_FE              0x00000100  // UART Framing Error
  #define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received
  #define UART_DR_DATA_S          0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_RSR register.
  //
  //*****************************************************************************
  #define UART_RSR_OE             0x00000008  // UART Overrun Error
  #define UART_RSR_BE             0x00000004  // UART Break Error
  #define UART_RSR_PE             0x00000002  // UART Parity Error
  #define UART_RSR_FE             0x00000001  // UART Framing Error
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_ECR register.
  //
  //*****************************************************************************
  #define UART_ECR_DATA_M         0x000000FF  // Error Clear
  #define UART_ECR_DATA_S         0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_FR register.
  //
  //*****************************************************************************
  #define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty
  #define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full
  #define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full
  #define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty
  #define UART_FR_BUSY            0x00000008  // UART Busy
  #define UART_FR_CTS             0x00000001  // Clear To Send
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_ILPR register.
  //
  //*****************************************************************************
  #define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor
  #define UART_ILPR_ILPDVSR_S     0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_IBRD register.
  //
  //*****************************************************************************
  #define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor
  #define UART_IBRD_DIVINT_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_FBRD register.
  //
  //*****************************************************************************
  #define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor
  #define UART_FBRD_DIVFRAC_S     0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_LCRH register.
  //
  //*****************************************************************************
  #define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select
  #define UART_LCRH_WLEN_M        0x00000060  // UART Word Length
  #define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
  #define UART_LCRH_WLEN_6        0x00000020  // 6 bits
  #define UART_LCRH_WLEN_7        0x00000040  // 7 bits
  #define UART_LCRH_WLEN_8        0x00000060  // 8 bits
  #define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs
  #define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select
  #define UART_LCRH_EPS           0x00000004  // UART Even Parity Select
  #define UART_LCRH_PEN           0x00000002  // UART Parity Enable
  #define UART_LCRH_BRK           0x00000001  // UART Send Break
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_CTL register.
  //
  //*****************************************************************************
  #define UART_CTL_RXE            0x00000200  // UART Receive Enable
  #define UART_CTL_TXE            0x00000100  // UART Transmit Enable
  #define UART_CTL_LBE            0x00000080  // UART Loop Back Enable
  #define UART_CTL_LIN            0x00000040  // LIN Mode Enable
  #define UART_CTL_HSE            0x00000020  // High-Speed Enable
  #define UART_CTL_EOT            0x00000010  // End of Transmission
  #define UART_CTL_SMART          0x00000008  // ISO 7816 Smart Card Support
  #define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode
  #define UART_CTL_SIREN          0x00000002  // UART SIR Enable
  #define UART_CTL_UARTEN         0x00000001  // UART Enable
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_IFLS register.
  //
  //*****************************************************************************
  #define UART_IFLS_RX_M          0x00000038  // UART Receive Interrupt FIFO
                                              // Level Select
  #define UART_IFLS_RX1_8         0x00000000  // RX FIFO >= 1/8 full
  #define UART_IFLS_RX2_8         0x00000008  // RX FIFO >= 1/4 full
  #define UART_IFLS_RX4_8         0x00000010  // RX FIFO >= 1/2 full (default)
  #define UART_IFLS_RX6_8         0x00000018  // RX FIFO >= 3/4 full
  #define UART_IFLS_RX7_8         0x00000020  // RX FIFO >= 7/8 full
  #define UART_IFLS_TX_M          0x00000007  // UART Transmit Interrupt FIFO
                                              // Level Select
  #define UART_IFLS_TX1_8         0x00000000  // TX FIFO <= 1/8 full
  #define UART_IFLS_TX2_8         0x00000001  // TX FIFO <= 1/4 full
  #define UART_IFLS_TX4_8         0x00000002  // TX FIFO <= 1/2 full (default)
  #define UART_IFLS_TX6_8         0x00000003  // TX FIFO <= 3/4 full
  #define UART_IFLS_TX7_8         0x00000004  // TX FIFO <= 7/8 full
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_IM register.
  //
  //*****************************************************************************
  #define UART_IM_LME5IM          0x00008000  // LIN Mode Edge 5 Interrupt Mask
  #define UART_IM_LME1IM          0x00004000  // LIN Mode Edge 1 Interrupt Mask
  #define UART_IM_LMSBIM          0x00002000  // LIN Mode Sync Break Interrupt
                                              // Mask
  #define UART_IM_9BITIM          0x00001000  // 9-Bit Mode Interrupt Mask
  #define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt
                                              // Mask
  #define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask
  #define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask
  #define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt
                                              // Mask
  #define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt
                                              // Mask
  #define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask
  #define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask
  #define UART_IM_CTSMIM          0x00000002  // UART Clear to Send Modem
                                              // Interrupt Mask
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_RIS register.
  //
  //*****************************************************************************
  #define UART_RIS_LME5RIS        0x00008000  // LIN Mode Edge 5 Raw Interrupt
                                              // Status
  #define UART_RIS_LME1RIS        0x00004000  // LIN Mode Edge 1 Raw Interrupt
                                              // Status
  #define UART_RIS_LMSBRIS        0x00002000  // LIN Mode Sync Break Raw
                                              // Interrupt Status
  #define UART_RIS_9BITRIS        0x00001000  // 9-Bit Mode Raw Interrupt Status
  #define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt
                                              // Status
  #define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt
                                              // Status
  #define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt
                                              // Status
  #define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt
                                              // Status
  #define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw
                                              // Interrupt Status
  #define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt
                                              // Status
  #define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt
                                              // Status
  #define UART_RIS_CTSRIS         0x00000002  // UART Clear to Send Modem Raw
                                              // Interrupt Status
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_MIS register.
  //
  //*****************************************************************************
  #define UART_MIS_LME5MIS        0x00008000  // LIN Mode Edge 5 Masked Interrupt
                                              // Status
  #define UART_MIS_LME1MIS        0x00004000  // LIN Mode Edge 1 Masked Interrupt
                                              // Status
  #define UART_MIS_LMSBMIS        0x00002000  // LIN Mode Sync Break Masked
                                              // Interrupt Status
  #define UART_MIS_9BITMIS        0x00001000  // 9-Bit Mode Masked Interrupt
                                              // Status
  #define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked
                                              // Interrupt Status
  #define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked
                                              // Interrupt Status
  #define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked
                                              // Interrupt Status
  #define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked
                                              // Interrupt Status
  #define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked
                                              // Interrupt Status
  #define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt
                                              // Status
  #define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt
                                              // Status
  #define UART_MIS_CTSMIS         0x00000002  // UART Clear to Send Modem Masked
                                              // Interrupt Status
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_ICR register.
  //
  //*****************************************************************************
  #define UART_ICR_LME5IC         0x00008000  // LIN Mode Edge 5 Interrupt Clear
  #define UART_ICR_LME1IC         0x00004000  // LIN Mode Edge 1 Interrupt Clear
  #define UART_ICR_LMSBIC         0x00002000  // LIN Mode Sync Break Interrupt
                                              // Clear
  #define UART_ICR_9BITIC         0x00001000  // 9-Bit Mode Interrupt Clear
  #define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
  #define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
  #define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
  #define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
  #define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear
  #define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
  #define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
  #define UART_ICR_CTSMIC         0x00000002  // UART Clear to Send Modem
                                              // Interrupt Clear
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_DMACTL register.
  //
  //*****************************************************************************
  #define UART_DMACTL_DMAERR      0x00000004  // DMA on Error
  #define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable
  #define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_LCTL register.
  //
  //*****************************************************************************
  #define UART_LCTL_BLEN_M        0x00000030  // Sync Break Length
  #define UART_LCTL_BLEN_13T      0x00000000  // Sync break length is 13T bits
                                              // (default)
  #define UART_LCTL_BLEN_14T      0x00000010  // Sync break length is 14T bits
  #define UART_LCTL_BLEN_15T      0x00000020  // Sync break length is 15T bits
  #define UART_LCTL_BLEN_16T      0x00000030  // Sync break length is 16T bits
  #define UART_LCTL_MASTER        0x00000001  // LIN Master Enable
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_LSS register.
  //
  //*****************************************************************************
  #define UART_LSS_TSS_M          0x0000FFFF  // Timer Snap Shot
  #define UART_LSS_TSS_S          0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_LTIM register.
  //
  //*****************************************************************************
  #define UART_LTIM_TIMER_M       0x0000FFFF  // Timer Value
  #define UART_LTIM_TIMER_S       0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_9BITADDR
  // register.
  //
  //*****************************************************************************
  #define UART_9BITADDR_9BITEN    0x00008000  // Enable 9-Bit Mode
  #define UART_9BITADDR_ADDR_M    0x000000FF  // Self Address for 9-Bit Mode
  #define UART_9BITADDR_ADDR_S    0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_9BITAMASK
  // register.
  //
  //*****************************************************************************
  #define UART_9BITAMASK_MASK_M   0x000000FF  // Self Address Mask for 9-Bit Mode
  #define UART_9BITAMASK_MASK_S   0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_PP register.
  //
  //*****************************************************************************
  #define UART_PP_NB              0x00000002  // 9-Bit Support
  #define UART_PP_SC              0x00000001  // Smart Card Support
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the UART_O_CC register.
  //
  //*****************************************************************************
  #define UART_CC_CS_M            0x0000000F  // UART Baud Clock Source
  #define UART_CC_CS_SYSCLK       0x00000000  // The system clock (default)
  #define UART_CC_CS_PIOSC        0x00000005  // PIOS
  
  
  /*************************************************************************
   * RX FIFO LENGTHS (RxIntFIFO)
   ************************************************************************/
  #define  RX_ONE_EIGHTH    0x0
  #define  RX_ONE_FOURTH    0x1
  #define  RX_ONE_HALF      0x2
  #define  RX_THREE_FOURTH  0x3
  #define  RX_SEVEN_EIGHTH  0x4
  
  /*************************************************************************
   * TX FIFO LENGTHS (TxIntFIFO)
   ************************************************************************/
  #define  TX_ONE_EIGHTH    0x4
  #define  TX_ONE_FOURTH    0x3
  #define  TX_ONE_HALF      0x2
  #define  TX_THREE_FOURTH  0x1
  #define  TX_SEVEN_EIGHTH  0x0
  
  
  
  /*************************************************************************
   ************************************************************************/
   /* SPI MACROS                                                          */
   /************************************************************************
   ************************************************************************/
   
  
  /*************************************************************************
   ************************************************************************/
  #define SSI_SLAVE_BYP           1
  #define SSI_END_OF_TX           1
  #define SSI_MODE_SLAVE_OD       1
  #define SSI_MASTER_EN           0
  #define SSI_SLAVE_EN            1
  #define SSI_EN                  1
  #define SSI_LOOPBK_EN           1
  
  /*************************************************************************
   ************************************************************************/
  #define SPI_CLK_CPSDVSR         10
  #define SSI_SPH_FIRST           0
  #define SSI_SPH_SECOND          1
  #define SSI_SPO_LOW             0
  #define SSI_SPO_HIGH            1
  #define SSI_FRF_SPI             0x0
  #define SSI_FRF_TI              0x1
  #define SSI_FRF_NMW             0x2
  #define SSI_DSS_8BIT            0x7
  #define SSI_DSS_16BIT           0xF
  
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SSI_O_CR0 register.
  //
  //*****************************************************************************
  #define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate
  #define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase
  #define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity
  #define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select
  #define SSI_CR0_FRF_MOTO        0x00000000  // Freescale SPI Frame Format
  #define SSI_CR0_FRF_TI          0x00000010  // Texas Instruments Synchronous
                                              // Serial Frame Format
  #define SSI_CR0_FRF_NMW         0x00000020  // MICROWIRE Frame Format
  #define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select
  #define SSI_CR0_DSS_4           0x00000003  // 4-bit data
  #define SSI_CR0_DSS_5           0x00000004  // 5-bit data
  #define SSI_CR0_DSS_6           0x00000005  // 6-bit data
  #define SSI_CR0_DSS_7           0x00000006  // 7-bit data
  #define SSI_CR0_DSS_8           0x00000007  // 8-bit data
  #define SSI_CR0_DSS_9           0x00000008  // 9-bit data
  #define SSI_CR0_DSS_10          0x00000009  // 10-bit data
  #define SSI_CR0_DSS_11          0x0000000A  // 11-bit data
  #define SSI_CR0_DSS_12          0x0000000B  // 12-bit data
  #define SSI_CR0_DSS_13          0x0000000C  // 13-bit data
  #define SSI_CR0_DSS_14          0x0000000D  // 14-bit data
  #define SSI_CR0_DSS_15          0x0000000E  // 15-bit data
  #define SSI_CR0_DSS_16          0x0000000F  // 16-bit data
  #define SSI_CR0_SCR_S           8
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SSI_O_CR1 register.
  //
  //*****************************************************************************
  #define SSI_CR1_EOT             0x00000010  // End of Transmission
  #define SSI_CR1_SOD             0x00000008  // SSI Slave Mode Output Disable
  #define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select
  #define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port
                                              // Enable
  #define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SSI_O_DR register.
  //
  //*****************************************************************************
  #define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data
  #define SSI_DR_DATA_S           0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SSI_O_SR register.
  //
  //*****************************************************************************
  #define SSI_SR_BSY              0x00000010  // SSI Busy Bit
  #define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full
  #define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty
  #define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full
  #define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SSI_O_CPSR register.
  //
  //*****************************************************************************
  #define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor
  #define SSI_CPSR_CPSDVSR_S      0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SSI_O_IM register.
  //
  //*****************************************************************************
  #define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt Mask
  #define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask
  #define SSI_IM_RTIM             0x00000002  // SSI Receive Time-Out Interrupt
                                              // Mask
  #define SSI_IM_RORIM            0x00000001  // SSI Receive Overrun Interrupt
                                              // Mask
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SSI_O_RIS register.
  //
  //*****************************************************************************
  #define SSI_RIS_TXRIS           0x00000008  // SSI Transmit FIFO Raw Interrupt
                                              // Status
  #define SSI_RIS_RXRIS           0x00000004  // SSI Receive FIFO Raw Interrupt
                                              // Status
  #define SSI_RIS_RTRIS           0x00000002  // SSI Receive Time-Out Raw
                                              // Interrupt Status
  #define SSI_RIS_RORRIS          0x00000001  // SSI Receive Overrun Raw
                                              // Interrupt Status
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SSI_O_MIS register.
  //
  //*****************************************************************************
  #define SSI_MIS_TXMIS           0x00000008  // SSI Transmit FIFO Masked
                                              // Interrupt Status
  #define SSI_MIS_RXMIS           0x00000004  // SSI Receive FIFO Masked
                                              // Interrupt Status
  #define SSI_MIS_RTMIS           0x00000002  // SSI Receive Time-Out Masked
                                              // Interrupt Status
  #define SSI_MIS_RORMIS          0x00000001  // SSI Receive Overrun Masked
                                              // Interrupt Status
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SSI_O_ICR register.
  //
  //*****************************************************************************
  #define SSI_ICR_RTIC            0x00000002  // SSI Receive Time-Out Interrupt
                                              // Clear
  #define SSI_ICR_RORIC           0x00000001  // SSI Receive Overrun Interrupt
                                              // Clear
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SSI_O_DMACTL register.
  //
  //*****************************************************************************
  #define SSI_DMACTL_TXDMAE       0x00000002  // Transmit DMA Enable
  #define SSI_DMACTL_RXDMAE       0x00000001  // Receive DMA Enable
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the SSI_O_CC register.
  //
  //*****************************************************************************
  #define SSI_CC_CS_M             0x0000000F  // SSI Baud Clock Source
  #define SSI_CC_CS_SYSPLL        0x00000000  // Either the system clock (if the
                                              // PLL bypass is in effect) or the
                                              // PLL output (default)
  #define SSI_CC_CS_PIOSC         0x00000005  // PIOSC
  
  
  
  /*************************************************************************
   ************************************************************************/
   /* I2C MACROS                                                          */
   /************************************************************************
   ************************************************************************/
   
  #define I2C_ACK_WAIT_COUNT    100000
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_MSA register.
  //
  //*****************************************************************************
  #define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address
  #define I2C_MSA_RS              0x00000001  // Receive not send
  #define I2C_MSA_SA_S            1
  #define I2C_MSA_TX              0x00000000  // Transmit Data
  #define I2C_MSA_RX              I2C_MSA_RS
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_SOAR register.
  //
  //*****************************************************************************
  #define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address
  #define I2C_SOAR_OAR_S          0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_SCSR register.
  //
  //*****************************************************************************
  #define I2C_SCSR_OAR2SEL        0x00000008  // OAR2 Address Matched
  #define I2C_SCSR_FBR            0x00000004  // First Byte Received
  #define I2C_SCSR_TREQ           0x00000002  // Transmit Request
  #define I2C_SCSR_DA             0x00000001  // Device Active
  #define I2C_SCSR_RREQ           0x00000001  // Receive Request
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_MCS register.
  //
  //*****************************************************************************
  #define I2C_MCS_CLKTO           0x00000080  // Clock Timeout Error
  #define I2C_MCS_BUSBSY          0x00000040  // Bus Busy
  #define I2C_MCS_IDLE            0x00000020  // I2C Idle
  #define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost
  #define I2C_MCS_HS              0x00000010  // High-Speed Enable
  #define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable
  #define I2C_MCS_DATACK          0x00000008  // Acknowledge Data
  #define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address
  #define I2C_MCS_STOP            0x00000004  // Generate STOP
  #define I2C_MCS_ERROR           0x00000002  // Error
  #define I2C_MCS_START           0x00000002  // Generate START
  #define I2C_MCS_RUN             0x00000001  // I2C Master Enable
  #define I2C_MCS_BUSY            0x00000001  // I2C Busy
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_SDR register.
  //
  //*****************************************************************************
  #define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer
  #define I2C_SDR_DATA_S          0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_MDR register.
  //
  //*****************************************************************************
  #define I2C_MDR_DATA_M          0x000000FF  // Data Transferred
  #define I2C_MDR_DATA_S          0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_MTPR register.
  //
  //*****************************************************************************
  #define I2C_MTPR_HS             0x00000080  // High-Speed Enable
  #define I2C_MTPR_TPR_M          0x0000007F  // SCL Clock Period
  #define I2C_MTPR_TPR_S          0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_SIMR register.
  //
  //*****************************************************************************
  #define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask
  #define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask
  #define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_SRIS register.
  //
  //*****************************************************************************
  #define I2C_SRIS_STOPRIS        0x00000004  // Stop Condition Raw Interrupt
                                              // Status
  #define I2C_SRIS_STARTRIS       0x00000002  // Start Condition Raw Interrupt
                                              // Status
  #define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_MIMR register.
  //
  //*****************************************************************************
  #define I2C_MIMR_CLKIM          0x00000002  // Clock Timeout Interrupt Mask
  #define I2C_MIMR_IM             0x00000001  // Master Interrupt Mask
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_MRIS register.
  //
  //*****************************************************************************
  #define I2C_MRIS_CLKRIS         0x00000002  // Clock Timeout Raw Interrupt
                                              // Status
  #define I2C_MRIS_RIS            0x00000001  // Master Raw Interrupt Status
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_SMIS register.
  //
  //*****************************************************************************
  #define I2C_SMIS_STOPMIS        0x00000004  // Stop Condition Masked Interrupt
                                              // Status
  #define I2C_SMIS_STARTMIS       0x00000002  // Start Condition Masked Interrupt
                                              // Status
  #define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_SICR register.
  //
  //*****************************************************************************
  #define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear
  #define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear
  #define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_MMIS register.
  //
  //*****************************************************************************
  #define I2C_MMIS_CLKMIS         0x00000002  // Clock Timeout Masked Interrupt
                                              // Status
  #define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_MICR register.
  //
  //*****************************************************************************
  #define I2C_MICR_CLKIC          0x00000002  // Clock Timeout Interrupt Clear
  #define I2C_MICR_IC             0x00000001  // Master Interrupt Clear
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_SOAR2 register.
  //
  //*****************************************************************************
  #define I2C_SOAR2_OAR2EN        0x00000080  // I2C Slave Own Address 2 Enable
  #define I2C_SOAR2_OAR2_M        0x0000007F  // I2C Slave Own Address 2
  #define I2C_SOAR2_OAR2_S        0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_MCR register.
  //
  //*****************************************************************************
  #define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable
  #define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable
  #define I2C_MCR_LPBK            0x00000001  // I2C Loopback
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_SACKCTL register.
  //
  //*****************************************************************************
  #define I2C_SACKCTL_ACKOVAL     0x00000002  // I2C Slave ACK Override Value
  #define I2C_SACKCTL_ACKOEN      0x00000001  // I2C Slave ACK Override Enable
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
  //
  //*****************************************************************************
  #define I2C_MCLKOCNT_CNTL_M     0x000000FF  // I2C Master Count
  #define I2C_MCLKOCNT_CNTL_S     0
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_MBMON register.
  //
  //*****************************************************************************
  #define I2C_MBMON_SDA           0x00000002  // I2C SDA Status
  #define I2C_MBMON_SCL           0x00000001  // I2C SCL Status
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_PP register.
  //
  //*****************************************************************************
  #define I2C_PP_HS               0x00000001  // High-Speed Capable
  
  //*****************************************************************************
  //
  // The following are defines for the bit fields in the I2C_O_PC register.
  //
  //*****************************************************************************
  #define I2C_PC_HS               0x00000001  // High-Speed Capable
  
  #endif
  