text: DECL|ACC_6490|macro|ACC_6490
  DECL|ACC_ACR_HYST_Msk|macro|ACC_ACR_HYST_Msk
  DECL|ACC_ACR_HYST_Pos|macro|ACC_ACR_HYST_Pos
  DECL|ACC_ACR_HYST|macro|ACC_ACR_HYST
  DECL|ACC_ACR_ISEL_HISP_Val|macro|ACC_ACR_ISEL_HISP_Val
  DECL|ACC_ACR_ISEL_HISP|macro|ACC_ACR_ISEL_HISP
  DECL|ACC_ACR_ISEL_LOPW_Val|macro|ACC_ACR_ISEL_LOPW_Val
  DECL|ACC_ACR_ISEL_LOPW|macro|ACC_ACR_ISEL_LOPW
  DECL|ACC_ACR_ISEL_Msk|macro|ACC_ACR_ISEL_Msk
  DECL|ACC_ACR_ISEL_Pos|macro|ACC_ACR_ISEL_Pos
  DECL|ACC_ACR_ISEL|macro|ACC_ACR_ISEL
  DECL|ACC_ACR_MASK|macro|ACC_ACR_MASK
  DECL|ACC_ACR_Msk|macro|ACC_ACR_Msk
  DECL|ACC_ACR_OFFSET|macro|ACC_ACR_OFFSET
  DECL|ACC_ACR_Type|typedef|} ACC_ACR_Type;
  DECL|ACC_ACR|member|__IO ACC_ACR_Type ACC_ACR; /**< Offset: 0x94 (R/W 32) Analog Control Register */
  DECL|ACC_ACR|member|__IO uint32_t ACC_ACR; /**< (ACC Offset: 0x94) Analog Control Register */
  DECL|ACC_CR_MASK|macro|ACC_CR_MASK
  DECL|ACC_CR_Msk|macro|ACC_CR_Msk
  DECL|ACC_CR_OFFSET|macro|ACC_CR_OFFSET
  DECL|ACC_CR_SWRST_Msk|macro|ACC_CR_SWRST_Msk
  DECL|ACC_CR_SWRST_Pos|macro|ACC_CR_SWRST_Pos
  DECL|ACC_CR_SWRST|macro|ACC_CR_SWRST
  DECL|ACC_CR_Type|typedef|} ACC_CR_Type;
  DECL|ACC_CR|member|__O ACC_CR_Type ACC_CR; /**< Offset: 0x00 ( /W 32) Control Register */
  DECL|ACC_CR|member|__O uint32_t ACC_CR; /**< (ACC Offset: 0x00) Control Register */
  DECL|ACC_IDR_CE_Msk|macro|ACC_IDR_CE_Msk
  DECL|ACC_IDR_CE_Pos|macro|ACC_IDR_CE_Pos
  DECL|ACC_IDR_CE|macro|ACC_IDR_CE
  DECL|ACC_IDR_MASK|macro|ACC_IDR_MASK
  DECL|ACC_IDR_Msk|macro|ACC_IDR_Msk
  DECL|ACC_IDR_OFFSET|macro|ACC_IDR_OFFSET
  DECL|ACC_IDR_Type|typedef|} ACC_IDR_Type;
  DECL|ACC_IDR|member|__O ACC_IDR_Type ACC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */
  DECL|ACC_IDR|member|__O uint32_t ACC_IDR; /**< (ACC Offset: 0x28) Interrupt Disable Register */
  DECL|ACC_IER_CE_Msk|macro|ACC_IER_CE_Msk
  DECL|ACC_IER_CE_Pos|macro|ACC_IER_CE_Pos
  DECL|ACC_IER_CE|macro|ACC_IER_CE
  DECL|ACC_IER_MASK|macro|ACC_IER_MASK
  DECL|ACC_IER_Msk|macro|ACC_IER_Msk
  DECL|ACC_IER_OFFSET|macro|ACC_IER_OFFSET
  DECL|ACC_IER_Type|typedef|} ACC_IER_Type;
  DECL|ACC_IER|member|__O ACC_IER_Type ACC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */
  DECL|ACC_IER|member|__O uint32_t ACC_IER; /**< (ACC Offset: 0x24) Interrupt Enable Register */
  DECL|ACC_IMR_CE_Msk|macro|ACC_IMR_CE_Msk
  DECL|ACC_IMR_CE_Pos|macro|ACC_IMR_CE_Pos
  DECL|ACC_IMR_CE|macro|ACC_IMR_CE
  DECL|ACC_IMR_MASK|macro|ACC_IMR_MASK
  DECL|ACC_IMR_Msk|macro|ACC_IMR_Msk
  DECL|ACC_IMR_OFFSET|macro|ACC_IMR_OFFSET
  DECL|ACC_IMR_Type|typedef|} ACC_IMR_Type;
  DECL|ACC_IMR|member|__I ACC_IMR_Type ACC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */
  DECL|ACC_IMR|member|__I uint32_t ACC_IMR; /**< (ACC Offset: 0x2C) Interrupt Mask Register */
  DECL|ACC_ISR_CE_Msk|macro|ACC_ISR_CE_Msk
  DECL|ACC_ISR_CE_Pos|macro|ACC_ISR_CE_Pos
  DECL|ACC_ISR_CE|macro|ACC_ISR_CE
  DECL|ACC_ISR_MASK_Msk|macro|ACC_ISR_MASK_Msk
  DECL|ACC_ISR_MASK_Pos|macro|ACC_ISR_MASK_Pos
  DECL|ACC_ISR_MASK|macro|ACC_ISR_MASK
  DECL|ACC_ISR_Msk|macro|ACC_ISR_Msk
  DECL|ACC_ISR_OFFSET|macro|ACC_ISR_OFFSET
  DECL|ACC_ISR_SCO_Msk|macro|ACC_ISR_SCO_Msk
  DECL|ACC_ISR_SCO_Pos|macro|ACC_ISR_SCO_Pos
  DECL|ACC_ISR_SCO|macro|ACC_ISR_SCO
  DECL|ACC_ISR_Type|typedef|} ACC_ISR_Type;
  DECL|ACC_ISR|member|__I ACC_ISR_Type ACC_ISR; /**< Offset: 0x30 (R/ 32) Interrupt Status Register */
  DECL|ACC_ISR|member|__I uint32_t ACC_ISR; /**< (ACC Offset: 0x30) Interrupt Status Register */
  DECL|ACC_MR_ACEN_DIS_Val|macro|ACC_MR_ACEN_DIS_Val
  DECL|ACC_MR_ACEN_DIS|macro|ACC_MR_ACEN_DIS
  DECL|ACC_MR_ACEN_EN_Val|macro|ACC_MR_ACEN_EN_Val
  DECL|ACC_MR_ACEN_EN|macro|ACC_MR_ACEN_EN
  DECL|ACC_MR_ACEN_Msk|macro|ACC_MR_ACEN_Msk
  DECL|ACC_MR_ACEN_Pos|macro|ACC_MR_ACEN_Pos
  DECL|ACC_MR_ACEN|macro|ACC_MR_ACEN
  DECL|ACC_MR_EDGETYP_ANY_Val|macro|ACC_MR_EDGETYP_ANY_Val
  DECL|ACC_MR_EDGETYP_ANY|macro|ACC_MR_EDGETYP_ANY
  DECL|ACC_MR_EDGETYP_FALLING_Val|macro|ACC_MR_EDGETYP_FALLING_Val
  DECL|ACC_MR_EDGETYP_FALLING|macro|ACC_MR_EDGETYP_FALLING
  DECL|ACC_MR_EDGETYP_Msk|macro|ACC_MR_EDGETYP_Msk
  DECL|ACC_MR_EDGETYP_Pos|macro|ACC_MR_EDGETYP_Pos
  DECL|ACC_MR_EDGETYP_RISING_Val|macro|ACC_MR_EDGETYP_RISING_Val
  DECL|ACC_MR_EDGETYP_RISING|macro|ACC_MR_EDGETYP_RISING
  DECL|ACC_MR_EDGETYP|macro|ACC_MR_EDGETYP
  DECL|ACC_MR_FE_DIS_Val|macro|ACC_MR_FE_DIS_Val
  DECL|ACC_MR_FE_DIS|macro|ACC_MR_FE_DIS
  DECL|ACC_MR_FE_EN_Val|macro|ACC_MR_FE_EN_Val
  DECL|ACC_MR_FE_EN|macro|ACC_MR_FE_EN
  DECL|ACC_MR_FE_Msk|macro|ACC_MR_FE_Msk
  DECL|ACC_MR_FE_Pos|macro|ACC_MR_FE_Pos
  DECL|ACC_MR_FE|macro|ACC_MR_FE
  DECL|ACC_MR_INV_DIS_Val|macro|ACC_MR_INV_DIS_Val
  DECL|ACC_MR_INV_DIS|macro|ACC_MR_INV_DIS
  DECL|ACC_MR_INV_EN_Val|macro|ACC_MR_INV_EN_Val
  DECL|ACC_MR_INV_EN|macro|ACC_MR_INV_EN
  DECL|ACC_MR_INV_Msk|macro|ACC_MR_INV_Msk
  DECL|ACC_MR_INV_Pos|macro|ACC_MR_INV_Pos
  DECL|ACC_MR_INV|macro|ACC_MR_INV
  DECL|ACC_MR_MASK|macro|ACC_MR_MASK
  DECL|ACC_MR_Msk|macro|ACC_MR_Msk
  DECL|ACC_MR_OFFSET|macro|ACC_MR_OFFSET
  DECL|ACC_MR_SELFS_CE_Val|macro|ACC_MR_SELFS_CE_Val
  DECL|ACC_MR_SELFS_CE|macro|ACC_MR_SELFS_CE
  DECL|ACC_MR_SELFS_Msk|macro|ACC_MR_SELFS_Msk
  DECL|ACC_MR_SELFS_OUTPUT_Val|macro|ACC_MR_SELFS_OUTPUT_Val
  DECL|ACC_MR_SELFS_OUTPUT|macro|ACC_MR_SELFS_OUTPUT
  DECL|ACC_MR_SELFS_Pos|macro|ACC_MR_SELFS_Pos
  DECL|ACC_MR_SELFS|macro|ACC_MR_SELFS
  DECL|ACC_MR_SELMINUS_AFE0_AD0_Val|macro|ACC_MR_SELMINUS_AFE0_AD0_Val
  DECL|ACC_MR_SELMINUS_AFE0_AD0|macro|ACC_MR_SELMINUS_AFE0_AD0
  DECL|ACC_MR_SELMINUS_AFE0_AD1_Val|macro|ACC_MR_SELMINUS_AFE0_AD1_Val
  DECL|ACC_MR_SELMINUS_AFE0_AD1|macro|ACC_MR_SELMINUS_AFE0_AD1
  DECL|ACC_MR_SELMINUS_AFE0_AD2_Val|macro|ACC_MR_SELMINUS_AFE0_AD2_Val
  DECL|ACC_MR_SELMINUS_AFE0_AD2|macro|ACC_MR_SELMINUS_AFE0_AD2
  DECL|ACC_MR_SELMINUS_AFE0_AD3_Val|macro|ACC_MR_SELMINUS_AFE0_AD3_Val
  DECL|ACC_MR_SELMINUS_AFE0_AD3|macro|ACC_MR_SELMINUS_AFE0_AD3
  DECL|ACC_MR_SELMINUS_DAC0_Val|macro|ACC_MR_SELMINUS_DAC0_Val
  DECL|ACC_MR_SELMINUS_DAC0|macro|ACC_MR_SELMINUS_DAC0
  DECL|ACC_MR_SELMINUS_DAC1_Val|macro|ACC_MR_SELMINUS_DAC1_Val
  DECL|ACC_MR_SELMINUS_DAC1|macro|ACC_MR_SELMINUS_DAC1
  DECL|ACC_MR_SELMINUS_Msk|macro|ACC_MR_SELMINUS_Msk
  DECL|ACC_MR_SELMINUS_Pos|macro|ACC_MR_SELMINUS_Pos
  DECL|ACC_MR_SELMINUS_TS_Val|macro|ACC_MR_SELMINUS_TS_Val
  DECL|ACC_MR_SELMINUS_TS|macro|ACC_MR_SELMINUS_TS
  DECL|ACC_MR_SELMINUS_VREFP_Val|macro|ACC_MR_SELMINUS_VREFP_Val
  DECL|ACC_MR_SELMINUS_VREFP|macro|ACC_MR_SELMINUS_VREFP
  DECL|ACC_MR_SELMINUS|macro|ACC_MR_SELMINUS
  DECL|ACC_MR_SELPLUS_AFE0_AD0_Val|macro|ACC_MR_SELPLUS_AFE0_AD0_Val
  DECL|ACC_MR_SELPLUS_AFE0_AD0|macro|ACC_MR_SELPLUS_AFE0_AD0
  DECL|ACC_MR_SELPLUS_AFE0_AD1_Val|macro|ACC_MR_SELPLUS_AFE0_AD1_Val
  DECL|ACC_MR_SELPLUS_AFE0_AD1|macro|ACC_MR_SELPLUS_AFE0_AD1
  DECL|ACC_MR_SELPLUS_AFE0_AD2_Val|macro|ACC_MR_SELPLUS_AFE0_AD2_Val
  DECL|ACC_MR_SELPLUS_AFE0_AD2|macro|ACC_MR_SELPLUS_AFE0_AD2
  DECL|ACC_MR_SELPLUS_AFE0_AD3_Val|macro|ACC_MR_SELPLUS_AFE0_AD3_Val
  DECL|ACC_MR_SELPLUS_AFE0_AD3|macro|ACC_MR_SELPLUS_AFE0_AD3
  DECL|ACC_MR_SELPLUS_AFE0_AD4_Val|macro|ACC_MR_SELPLUS_AFE0_AD4_Val
  DECL|ACC_MR_SELPLUS_AFE0_AD4|macro|ACC_MR_SELPLUS_AFE0_AD4
  DECL|ACC_MR_SELPLUS_AFE0_AD5_Val|macro|ACC_MR_SELPLUS_AFE0_AD5_Val
  DECL|ACC_MR_SELPLUS_AFE0_AD5|macro|ACC_MR_SELPLUS_AFE0_AD5
  DECL|ACC_MR_SELPLUS_AFE1_AD0_Val|macro|ACC_MR_SELPLUS_AFE1_AD0_Val
  DECL|ACC_MR_SELPLUS_AFE1_AD0|macro|ACC_MR_SELPLUS_AFE1_AD0
  DECL|ACC_MR_SELPLUS_AFE1_AD1_Val|macro|ACC_MR_SELPLUS_AFE1_AD1_Val
  DECL|ACC_MR_SELPLUS_AFE1_AD1|macro|ACC_MR_SELPLUS_AFE1_AD1
  DECL|ACC_MR_SELPLUS_Msk|macro|ACC_MR_SELPLUS_Msk
  DECL|ACC_MR_SELPLUS_Pos|macro|ACC_MR_SELPLUS_Pos
  DECL|ACC_MR_SELPLUS|macro|ACC_MR_SELPLUS
  DECL|ACC_MR_Type|typedef|} ACC_MR_Type;
  DECL|ACC_MR|member|__IO ACC_MR_Type ACC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
  DECL|ACC_MR|member|__IO uint32_t ACC_MR; /**< (ACC Offset: 0x04) Mode Register */
  DECL|ACC_WPMR_MASK|macro|ACC_WPMR_MASK
  DECL|ACC_WPMR_Msk|macro|ACC_WPMR_Msk
  DECL|ACC_WPMR_OFFSET|macro|ACC_WPMR_OFFSET
  DECL|ACC_WPMR_Type|typedef|} ACC_WPMR_Type;
  DECL|ACC_WPMR_WPEN_Msk|macro|ACC_WPMR_WPEN_Msk
  DECL|ACC_WPMR_WPEN_Pos|macro|ACC_WPMR_WPEN_Pos
  DECL|ACC_WPMR_WPEN|macro|ACC_WPMR_WPEN
  DECL|ACC_WPMR_WPKEY_Msk|macro|ACC_WPMR_WPKEY_Msk
  DECL|ACC_WPMR_WPKEY_PASSWD_Val|macro|ACC_WPMR_WPKEY_PASSWD_Val
  DECL|ACC_WPMR_WPKEY_PASSWD|macro|ACC_WPMR_WPKEY_PASSWD
  DECL|ACC_WPMR_WPKEY_Pos|macro|ACC_WPMR_WPKEY_Pos
  DECL|ACC_WPMR_WPKEY|macro|ACC_WPMR_WPKEY
  DECL|ACC_WPMR|member|__IO ACC_WPMR_Type ACC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
  DECL|ACC_WPMR|member|__IO uint32_t ACC_WPMR; /**< (ACC Offset: 0xE4) Write Protection Mode Register */
  DECL|ACC_WPSR_MASK|macro|ACC_WPSR_MASK
  DECL|ACC_WPSR_Msk|macro|ACC_WPSR_Msk
  DECL|ACC_WPSR_OFFSET|macro|ACC_WPSR_OFFSET
  DECL|ACC_WPSR_Type|typedef|} ACC_WPSR_Type;
  DECL|ACC_WPSR_WPVS_Msk|macro|ACC_WPSR_WPVS_Msk
  DECL|ACC_WPSR_WPVS_Pos|macro|ACC_WPSR_WPVS_Pos
  DECL|ACC_WPSR_WPVS|macro|ACC_WPSR_WPVS
  DECL|ACC_WPSR|member|__I ACC_WPSR_Type ACC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */
  DECL|ACC_WPSR|member|__I uint32_t ACC_WPSR; /**< (ACC Offset: 0xE8) Write Protection Status Register */
  DECL|ACEN|member|uint32_t ACEN:1; /**< bit: 8 Analog Comparator Enable */
  DECL|Acc|typedef|} Acc;
  DECL|Acc|typedef|} Acc;
  DECL|CE|member|uint32_t CE:1; /**< bit: 0 Comparison Edge (cleared on read) */
  DECL|CE|member|uint32_t CE:1; /**< bit: 0 Comparison Edge */
  DECL|CE|member|uint32_t CE:1; /**< bit: 0 Comparison Edge */
  DECL|CE|member|uint32_t CE:1; /**< bit: 0 Comparison Edge */
  DECL|COMPONENT_TYPEDEF_STYLE|macro|COMPONENT_TYPEDEF_STYLE
  DECL|EDGETYP|member|uint32_t EDGETYP:2; /**< bit: 9..10 Edge Type */
  DECL|FE|member|uint32_t FE:1; /**< bit: 14 Fault Enable */
  DECL|HYST|member|uint32_t HYST:2; /**< bit: 1..2 Hysteresis Selection */
  DECL|INV|member|uint32_t INV:1; /**< bit: 12 Invert Comparator Output */
  DECL|ISEL|member|uint32_t ISEL:1; /**< bit: 0 Current Selection */
  DECL|MASK|member|uint32_t MASK:1; /**< bit: 31 Flag Mask */
  DECL|REV_ACC|macro|REV_ACC
  DECL|Reserved1|member|RoReg8 Reserved1[0x1C];
  DECL|Reserved1|member|__I uint32_t Reserved1[7];
  DECL|Reserved2|member|RoReg8 Reserved2[0x60];
  DECL|Reserved2|member|__I uint32_t Reserved2[24];
  DECL|Reserved3|member|RoReg8 Reserved3[0x4C];
  DECL|Reserved3|member|__I uint32_t Reserved3[19];
  DECL|SCO|member|uint32_t SCO:1; /**< bit: 1 Synchronized Comparator Output */
  DECL|SELFS|member|uint32_t SELFS:1; /**< bit: 13 Selection Of Fault Source */
  DECL|SELMINUS|member|uint32_t SELMINUS:3; /**< bit: 0..2 Selection for Minus Comparator Input */
  DECL|SELPLUS|member|uint32_t SELPLUS:3; /**< bit: 4..6 Selection For Plus Comparator Input */
  DECL|SWRST|member|uint32_t SWRST:1; /**< bit: 0 Software Reset */
  DECL|WPEN|member|uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */
  DECL|WPKEY|member|uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */
  DECL|WPVS|member|uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */
  DECL|_SAME70_ACC_COMPONENT_H_|macro|_SAME70_ACC_COMPONENT_H_
  DECL|_SAME70_ACC_COMPONENT_|macro|_SAME70_ACC_COMPONENT_
  DECL|bit|member|} bit; /**< Structure used for bit access */
  DECL|bit|member|} bit; /**< Structure used for bit access */
  DECL|bit|member|} bit; /**< Structure used for bit access */
  DECL|bit|member|} bit; /**< Structure used for bit access */
  DECL|bit|member|} bit; /**< Structure used for bit access */
  DECL|bit|member|} bit; /**< Structure used for bit access */
  DECL|bit|member|} bit; /**< Structure used for bit access */
  DECL|bit|member|} bit; /**< Structure used for bit access */
  DECL|bit|member|} bit; /**< Structure used for bit access */
  DECL|reg|member|uint32_t reg; /**< Type used for register access */
  DECL|reg|member|uint32_t reg; /**< Type used for register access */
  DECL|reg|member|uint32_t reg; /**< Type used for register access */
  DECL|reg|member|uint32_t reg; /**< Type used for register access */
  DECL|reg|member|uint32_t reg; /**< Type used for register access */
  DECL|reg|member|uint32_t reg; /**< Type used for register access */
  DECL|reg|member|uint32_t reg; /**< Type used for register access */
  DECL|reg|member|uint32_t reg; /**< Type used for register access */
  DECL|reg|member|uint32_t reg; /**< Type used for register access */
  DECL|uint32_t|member|uint32_t :17; /**< bit: 15..31 Reserved */
  DECL|uint32_t|member|uint32_t :1; /**< bit: 11 Reserved */
  DECL|uint32_t|member|uint32_t :1; /**< bit: 3 Reserved */
  DECL|uint32_t|member|uint32_t :1; /**< bit: 7 Reserved */
  DECL|uint32_t|member|uint32_t :29; /**< bit: 2..30 Reserved */
  DECL|uint32_t|member|uint32_t :29; /**< bit: 3..31 Reserved */
  DECL|uint32_t|member|uint32_t :31; /**< bit: 1..31 Reserved */
  DECL|uint32_t|member|uint32_t :31; /**< bit: 1..31 Reserved */
  DECL|uint32_t|member|uint32_t :31; /**< bit: 1..31 Reserved */
  DECL|uint32_t|member|uint32_t :31; /**< bit: 1..31 Reserved */
  DECL|uint32_t|member|uint32_t :31; /**< bit: 1..31 Reserved */
  DECL|uint32_t|member|uint32_t :7; /**< bit: 1..7 Reserved */
  