text: /* $NoKeywords:$ */
  /**
   * @file
   *
   * Config Fch LPC controller
   *
   * Init LPC Controller features.
   *
   * @xrefitem bom "File Content Label" "Release Content"
   * @e project:     AGESA
   * @e sub-project: FCH
   * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
   *
   */
  /*
  *****************************************************************************
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  */
  #include "FchPlatform.h"
  #include "Filecode.h"
  
  #define FILECODE PROC_FCH_SPI_FAMILY_HUDSON2_HUDSON2LPCRESETSERVICE_FILECODE
  
  /**
   * FchInitHudson2ResetLpcPciTable - Lpc (Spi) device registers
   * initial during the power on stage.
   *
   *
   *
   *
   */
  REG8_MASK FchInitHudson2ResetLpcPciTable[] =
  {
    //
    // LPC Device (Bus 0, Dev 20, Func 3)
    //
    {0x00, LPC_BUS_DEV_FUN, 0},
  
    {FCH_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
    {FCH_LPC_REG7C, 0x00, BIT0 + BIT2},
    {0x78 , 0xF0, BIT2 + BIT3},                       /// Enable LDRQ pin
    {FCH_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},
    //
    // Set 0xBB [5:3] = 111 to improve SPI timing margin.
    // Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)
    //
    {FCH_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},
    {FCH_LPC_REGBA, 0x9F, BIT5 + BIT6},
    // Force EC_PortActive to 1 to fix possible IR non function issue when NO_EC_SUPPORT is defined
    {FCH_LPC_REGA4, (UINT8)~ BIT0, BIT0},
    {0xFF, 0xFF, 0xFF},
  };
  
  /**
   * FchInitResetLpcProgram - Config Lpc controller during Power-On
   *
   *
   *
   * @param[in] FchDataPtr Fch configuration structure pointer.
   *
   */
  VOID
  FchInitResetLpcProgram (
    IN  VOID     *FchDataPtr
    )
  {
    FCH_RESET_DATA_BLOCK      *LocalCfgPtr;
    AMD_CONFIG_PARAMS         *StdHeader;
  
    LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
    StdHeader = LocalCfgPtr->StdHeader;
    //
    // enable prefetch on Host, set LPC cfg 0xBB bit 0 to 1
    //
    RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader);
  
    RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG6C, AccessWidth32, 0xFFFFFF00, 0, StdHeader);
  
    ProgramPciByteTable ( (REG8_MASK*) (&FchInitHudson2ResetLpcPciTable[0]), sizeof (FchInitHudson2ResetLpcPciTable) / sizeof (REG8_MASK), StdHeader);
  
    //
    // Enabling ClkRun Function
    //
    RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBB, AccessWidth8, 0xFB, BIT2, StdHeader);
    RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGD0, AccessWidth8, 0xFB, 0, StdHeader);
    //
    // LPC CLK0 Power-Down Function
    //
    if (!IsImcEnabled (StdHeader)) {
      RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD2, AccessWidth8, 0xFF, BIT3);
    } else {
      RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD2, AccessWidth8, (UINT32)~ (BIT3), 0);
    }
  
    if ( LocalCfgPtr->LegacyFree ) {
      RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG44), AccessWidth32, 00, 0x0003C000, StdHeader);
    } else {
      RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG44), AccessWidth32, 00, 0xFF03FFD5, StdHeader);
    }
  }
  