text: from __future__ import absolute_import
  from __future__ import print_function
  import veriloggen
  import stream_cast
  
  expected_verilog = """
  module test;
  
    reg CLK;
    reg RST;
    reg signed [32-1:0] xdata;
    reg signed [32-1:0] ydata;
    wire signed [32-1:0] zdata;
  
    main
    uut
    (
      .CLK(CLK),
      .RST(RST),
      .xdata(xdata),
      .ydata(ydata),
      .zdata(zdata)
    );
  
    reg reset_done;
  
    initial begin
      $dumpfile("uut.vcd");
      $dumpvars(0, uut);
    end
  
  
    initial begin
      CLK = 0;
      forever begin
        #5 CLK = !CLK;
      end
    end
  
  
    initial begin
      RST = 0;
      reset_done = 0;
      xdata = 0;
      ydata = 0;
      #100;
      RST = 1;
      #100;
      RST = 0;
      #1000;
      reset_done = 1;
      @(posedge CLK);
      #1;
      #10000;
      $finish;
    end
  
    reg [32-1:0] send_fsm;
    localparam send_fsm_init = 0;
    reg [32-1:0] send_count;
    reg [32-1:0] recv_fsm;
    localparam recv_fsm_init = 0;
    reg [32-1:0] recv_count;
    localparam send_fsm_1 = 1;
    localparam send_fsm_2 = 2;
  
    always @(posedge CLK) begin
      if(RST) begin
        send_fsm <= send_fsm_init;
        send_count <= 0;
      end else begin
        case(send_fsm)
          send_fsm_init: begin
            if(reset_done) begin
              send_fsm <= send_fsm_1;
            end 
          end
          send_fsm_1: begin
            xdata <= xdata + 1;
            ydata <= ydata + 2;
            $display("xdata=%d", xdata);
            $display("ydata=%d", ydata);
            send_count <= send_count + 1;
            if(send_count == 20) begin
              send_fsm <= send_fsm_2;
            end 
          end
        endcase
      end
    end
  
    localparam recv_fsm_1 = 1;
    localparam recv_fsm_2 = 2;
  
    always @(posedge CLK) begin
      if(RST) begin
        recv_fsm <= recv_fsm_init;
        recv_count <= 0;
      end else begin
        case(recv_fsm)
          recv_fsm_init: begin
            if(reset_done) begin
              recv_fsm <= recv_fsm_1;
            end 
          end
          recv_fsm_1: begin
            $display("zdata=%d", zdata);
            recv_count <= recv_count + 1;
            if(recv_count == 30) begin
              recv_fsm <= recv_fsm_2;
            end 
          end
        endcase
      end
    end
  
  
  endmodule
  
  
  
  module main
  (
    input CLK,
    input RST,
    input signed [32-1:0] xdata,
    input signed [32-1:0] ydata,
    output signed [32-1:0] zdata
  );
  
    wire signed [32-1:0] _cast_src_2;
    assign _cast_src_2 = xdata;
    wire signed [64-1:0] _cast_data_2;
    assign _cast_data_2 = _cast_src_2 << 8;
    wire signed [32-1:0] _cast_src_3;
    assign _cast_src_3 = ydata;
    wire signed [64-1:0] _cast_data_3;
    assign _cast_data_3 = _cast_src_3 << 8;
    reg signed [64-1:0] _plus_data_4;
    wire signed [64-1:0] _cast_src_5;
    assign _cast_src_5 = _plus_data_4;
    wire signed [32-1:0] _cast_data_5;
    assign _cast_data_5 = _cast_src_5 >>> 8;
    assign zdata = _cast_data_5;
  
    always @(posedge CLK) begin
      if(RST) begin
        _plus_data_4 <= 0;
      end else begin
        _plus_data_4 <= _cast_data_2 + _cast_data_3;
      end
    end
  
  
  endmodule
  """
  
  
  def test():
      veriloggen.reset()
      test_module = stream_cast.mkTest()
      code = test_module.to_verilog()
  
      from pyverilog.vparser.parser import VerilogParser
      from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
      parser = VerilogParser()
      expected_ast = parser.parse(expected_verilog)
      codegen = ASTCodeGenerator()
      expected_code = codegen.visit(expected_ast)
  
      assert(expected_code == code)
  