text: /*
   * Copyright (c) 2015 Kai Zhang (kay21s@gmail.com)
   *
   * Permission is hereby granted, free of charge, to any person obtaining a copy
   * of this software and associated documentation files (the "Software"), to deal
   * in the Software without restriction, including without limitation the rights
   * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   * copies of the Software, and to permit persons to whom the Software is
   * furnished to do so, subject to the following conditions:
   *
   * The above copyright notice and this permission notice shall be included in
   * all copies or substantial portions of the Software.
   *
   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
   * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   * THE SOFTWARE.
   */
  
  #ifndef _MEGA_DPDK_H_
  #define _MEGA_DPDK_H_
  
  #define MBUF_SIZE (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM)
  #define NB_MBUF  1024
  
  /*
   * RX and TX Prefetch, Host, and Write-back threshold values should be
   * carefully set for optimal performance. Consult the network
   * controller's datasheet and supporting DPDK documentation for guidance
   * on how these parameters should be set.
   */
  #define RX_PTHRESH 8 /**< Default values of RX prefetch threshold reg. */
  #define RX_HTHRESH 8 /**< Default values of RX host threshold reg. */
  #define RX_WTHRESH 4 /**< Default values of RX write-back threshold reg. */
  
  /*
   * These default values are optimized for use with the Intel(R) 82599 10 GbE
   * Controller and the DPDK ixgbe PMD. Consider using other values for other
   * network controllers and/or network drivers.
   */
  #define TX_PTHRESH 36 /**< Default values of TX prefetch threshold reg. */
  #define TX_HTHRESH 0  /**< Default values of TX host threshold reg. */
  #define TX_WTHRESH 0  /**< Default values of TX write-back threshold reg. */
  
  #define MAX_PKT_BURST 1
  #define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */
  
  /*
   * Configurable number of RX/TX ring descriptors
   */
  #define RTE_TEST_RX_DESC_DEFAULT 128
  #define RTE_TEST_TX_DESC_DEFAULT 512
  struct mbuf_table {
  	unsigned len;
  	struct rte_mbuf *m_table[MAX_PKT_BURST];
  };
  
  #define MAX_RX_QUEUE_PER_LCORE 16
  #define MAX_TX_QUEUE_PER_PORT 16
  struct lcore_queue_conf {
  	struct mbuf_table tx_mbufs[MAX_TX_QUEUE_PER_PORT];
  } __rte_cache_aligned;
  
  static const struct rte_eth_conf port_conf = {
  	.rxmode = {
  		.mq_mode = ETH_MQ_RX_RSS,
  		.max_rx_pkt_len = ETHER_MAX_LEN,
  		.split_hdr_size = 0,
  		.header_split   = 0, /**< Header Split disabled */
  		.hw_ip_checksum = 0, /**< IP checksum offload disabled */
  		.hw_vlan_filter = 0, /**< VLAN filtering disabled */
  		.jumbo_frame    = 0, /**< Jumbo Frame Support disabled */
  		.hw_strip_crc   = 0, /**< CRC stripped by hardware */
  	},
  	.rx_adv_conf = {
  		.rss_conf = {
  			.rss_key = NULL,
  			.rss_hf = ETH_RSS_IP,
  		},
  	},
  	.txmode = {
  		.mq_mode = ETH_MQ_TX_NONE,
  	},
  };
  
  static const struct rte_eth_rxconf rx_conf = {
  	.rx_thresh = {
  		.pthresh = RX_PTHRESH,
  		.hthresh = RX_HTHRESH,
  		.wthresh = RX_WTHRESH,
  	},
  };
  
  static const struct rte_eth_txconf tx_conf = {
  	.tx_thresh = {
  		.pthresh = TX_PTHRESH,
  		.hthresh = TX_HTHRESH,
  		.wthresh = TX_WTHRESH,
  	},
  	.tx_free_thresh = 0, /* Use PMD default values */
  	.tx_rs_thresh = 0, /* Use PMD default values */
  	/*
  	 * As the example won't handle mult-segments and offload cases,
  	 * set the flag by default.
  	 */
  	.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS,
  };
  
  /* A tsc-based timer responsible for triggering statistics printout */
  #define TIMER_MILLISECOND 2000000ULL /* around 1ms at 2 Ghz */
  #define MAX_TIMER_PERIOD 86400 /* 1 day max */
  
  int mega_init_dpdk(int);
  
  #endif
  