text: /***********************************************************************************************************************
   * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
   * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
   **********************************************************************************************************************/
  
  /* clang-format off */
  /*
   * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
  !!GlobalInfo
  product: Pins v5.0
  processor: MK64FN1M0xxx12
  package_id: MK64FN1M0VLL12
  mcu_data: ksdk2_0
  processor_version: 5.0.0
  pin_labels:
  - {pin_num: '68', pin_signal: PTB22/SPI2_SOUT/FB_AD29/CMP2_OUT, label: LED_RED, identifier: LED_RED}
  - {pin_num: '67', pin_signal: PTB21/SPI2_SCK/FB_AD30/CMP1_OUT, label: LED_BLUE, identifier: LED_BLUE}
  - {pin_num: '33', pin_signal: PTE26/ENET_1588_CLKIN/UART4_CTS_b/RTC_CLKOUT/USB_CLKIN, label: LED_GREEN, identifier: LED_GREEN}
   * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
   */
  /* clang-format on */
  
  #include "fsl_common.h"
  #include "fsl_port.h"
  #include "fsl_gpio.h"
  #include "pin_mux.h"
  
  /* FUNCTION ************************************************************************************************************
   *
   * Function Name : BOARD_InitBootPins
   * Description   : Calls initialization functions.
   *
   * END ****************************************************************************************************************/
  void BOARD_InitBootPins(void)
  {
      BOARD_InitENET();
      BOARD_InitLEDs();
      BOARD_InitSerial();
      BOARD_InitPWM();
  }
  
  /* clang-format off */
  /*
   * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
  BOARD_InitENET:
  - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
  - pin_list:
    - {pin_num: '39', peripheral: ENET, signal: RMII_RXER, pin_signal: PTA5/USB_CLKIN/FTM0_CH2/RMII0_RXER/MII0_RXER/CMP2_OUT/I2S0_TX_BCLK/JTAG_TRST_b}
    - {pin_num: '42', peripheral: ENET, signal: RMII_RXD1, pin_signal: CMP2_IN0/PTA12/CAN0_TX/FTM1_CH0/RMII0_RXD1/MII0_RXD1/I2C2_SCL/I2S0_TXD0/FTM1_QD_PHA}
    - {pin_num: '43', peripheral: ENET, signal: RMII_RXD0, pin_signal: CMP2_IN1/PTA13/LLWU_P4/CAN0_RX/FTM1_CH1/RMII0_RXD0/MII0_RXD0/I2C2_SDA/I2S0_TX_FS/FTM1_QD_PHB}
    - {pin_num: '44', peripheral: ENET, signal: RMII_CRS_DV, pin_signal: PTA14/SPI0_PCS0/UART0_TX/RMII0_CRS_DV/MII0_RXDV/I2C2_SCL/I2S0_RX_BCLK/I2S0_TXD1}
    - {pin_num: '45', peripheral: ENET, signal: RMII_TXEN, pin_signal: PTA15/SPI0_SCK/UART0_RX/RMII0_TXEN/MII0_TXEN/I2S0_RXD0}
    - {pin_num: '46', peripheral: ENET, signal: RMII_TXD0, pin_signal: PTA16/SPI0_SOUT/UART0_CTS_b/UART0_COL_b/RMII0_TXD0/MII0_TXD0/I2S0_RX_FS/I2S0_RXD1}
    - {pin_num: '47', peripheral: ENET, signal: RMII_TXD1, pin_signal: ADC1_SE17/PTA17/SPI0_SIN/UART0_RTS_b/RMII0_TXD1/MII0_TXD1/I2S0_MCLK}
    - {pin_num: '53', peripheral: ENET, signal: RMII_MDIO, pin_signal: ADC0_SE8/ADC1_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/RMII0_MDIO/MII0_MDIO/FTM1_QD_PHA, open_drain: enable,
      pull_select: up, pull_enable: enable}
    - {pin_num: '54', peripheral: ENET, signal: RMII_MDC, pin_signal: ADC0_SE9/ADC1_SE9/PTB1/I2C0_SDA/FTM1_CH1/RMII0_MDC/MII0_MDC/FTM1_QD_PHB}
    - {pin_num: '90', peripheral: ENET, signal: 'TMR_1588, 0', pin_signal: PTC16/UART3_RX/ENET0_1588_TMR0/FB_CS5_b/FB_TSIZ1/FB_BE23_16_BLS15_8_b}
    - {pin_num: '91', peripheral: ENET, signal: 'TMR_1588, 1', pin_signal: PTC17/UART3_TX/ENET0_1588_TMR1/FB_CS4_b/FB_TSIZ0/FB_BE31_24_BLS7_0_b}
    - {pin_num: '92', peripheral: ENET, signal: 'TMR_1588, 2', pin_signal: PTC18/UART3_RTS_b/ENET0_1588_TMR2/FB_TBST_b/FB_CS2_b/FB_BE15_8_BLS23_16_b}
   * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
   */
  /* clang-format on */
  
  /* FUNCTION ************************************************************************************************************
   *
   * Function Name : BOARD_InitENET
   * Description   : Configures pin routing and optionally pin electrical features for the Ethernet.
   *
   * END ****************************************************************************************************************/
  void BOARD_InitENET(void)
  {
      /* Port A Clock Gate Control: Clock enabled */
      CLOCK_EnableClock(kCLOCK_PortA);
      /* Port B Clock Gate Control: Clock enabled */
      CLOCK_EnableClock(kCLOCK_PortB);
      /* Port C Clock Gate Control: Clock enabled */
      CLOCK_EnableClock(kCLOCK_PortC);
  
      /* PORTA12 (pin 42) is configured as RMII0_RXD1 */
      PORT_SetPinMux(PORTA, 12U, kPORT_MuxAlt4);
  
      /* PORTA13 (pin 43) is configured as RMII0_RXD0 */
      PORT_SetPinMux(PORTA, 13U, kPORT_MuxAlt4);
  
      /* PORTA14 (pin 44) is configured as RMII0_CRS_DV */
      PORT_SetPinMux(PORTA, 14U, kPORT_MuxAlt4);
  
      /* PORTA15 (pin 45) is configured as RMII0_TXEN */
      PORT_SetPinMux(PORTA, 15U, kPORT_MuxAlt4);
  
      /* PORTA16 (pin 46) is configured as RMII0_TXD0 */
      PORT_SetPinMux(PORTA, 16U, kPORT_MuxAlt4);
  
      /* PORTA17 (pin 47) is configured as RMII0_TXD1 */
      PORT_SetPinMux(PORTA, 17U, kPORT_MuxAlt4);
  
      /* PORTA5 (pin 39) is configured as RMII0_RXER */
      PORT_SetPinMux(PORTA, 5U, kPORT_MuxAlt4);
  
      /* PORTB0 (pin 53) is configured as RMII0_MDIO */
      PORT_SetPinMux(PORTB, 0U, kPORT_MuxAlt4);
  
      PORTB->PCR[0] = ((PORTB->PCR[0] &
                        /* Mask bits to zero which are setting */
                        (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
  
                       /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
                        * corresponding PE field is set. */
                       | (uint32_t)(kPORT_PullUp)
  
                       /* Open Drain Enable: Open drain output is enabled on the corresponding pin, if the pin is
                        * configured as a digital output. */
                       | PORT_PCR_ODE(kPORT_OpenDrainEnable));
  
      /* PORTB1 (pin 54) is configured as RMII0_MDC */
      PORT_SetPinMux(PORTB, 1U, kPORT_MuxAlt4);
  
      /* PORTC16 (pin 90) is configured as ENET0_1588_TMR0 */
      PORT_SetPinMux(PORTC, 16U, kPORT_MuxAlt4);
  
      /* PORTC17 (pin 91) is configured as ENET0_1588_TMR1 */
      PORT_SetPinMux(PORTC, 17U, kPORT_MuxAlt4);
  
      /* PORTC18 (pin 92) is configured as ENET0_1588_TMR2 */
      PORT_SetPinMux(PORTC, 18U, kPORT_MuxAlt4);
  }
  
  /* clang-format off */
  /*
   * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
  BOARD_InitLEDs:
  - options: {callFromInitBoot: 'true', prefix: '', coreID: core0, enableClock: 'true'}
  - pin_list:
    - {pin_num: '33', peripheral: GPIOE, signal: 'GPIO, 26', pin_signal: PTE26/ENET_1588_CLKIN/UART4_CTS_b/RTC_CLKOUT/USB_CLKIN, direction: OUTPUT, gpio_init_state: 'true'}
    - {pin_num: '67', peripheral: GPIOB, signal: 'GPIO, 21', pin_signal: PTB21/SPI2_SCK/FB_AD30/CMP1_OUT, direction: OUTPUT, gpio_init_state: 'true'}
    - {pin_num: '68', peripheral: GPIOB, signal: 'GPIO, 22', pin_signal: PTB22/SPI2_SOUT/FB_AD29/CMP2_OUT, direction: OUTPUT, gpio_init_state: 'true'}
   * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
   */
  /* clang-format on */
  
  /* FUNCTION ************************************************************************************************************
   *
   * Function Name : BOARD_InitLEDs
   * Description   : Configures pin routing and optionally pin electrical features for the LEDs.
   *
   * END ****************************************************************************************************************/
  void BOARD_InitLEDs(void)
  {
      /* Port B Clock Gate Control: Clock enabled */
      CLOCK_EnableClock(kCLOCK_PortB);
      /* Port E Clock Gate Control: Clock enabled */
      CLOCK_EnableClock(kCLOCK_PortE);
  
      gpio_pin_config_t LED_BLUE_config = {
          .pinDirection = kGPIO_DigitalOutput,
          .outputLogic = 1U
      };
      /* Initialize GPIO functionality on pin PTB21 (pin 67)  */
      GPIO_PinInit(LED_BLUE_GPIO, LED_BLUE_PIN, &LED_BLUE_config);
  
      gpio_pin_config_t LED_RED_config = {
          .pinDirection = kGPIO_DigitalOutput,
          .outputLogic = 1U
      };
      /* Initialize GPIO functionality on pin PTB22 (pin 68)  */
      GPIO_PinInit(LED_RED_GPIO, LED_RED_PIN, &LED_RED_config);
  
      gpio_pin_config_t LED_GREEN_config = {
          .pinDirection = kGPIO_DigitalOutput,
          .outputLogic = 1U
      };
      /* Initialize GPIO functionality on pin PTE26 (pin 33)  */
      GPIO_PinInit(LED_GREEN_GPIO, LED_GREEN_PIN, &LED_GREEN_config);
  
      /* PORTB21 (pin 67) is configured as PTB21 */
      PORT_SetPinMux(LED_BLUE_PORT, LED_BLUE_PIN, kPORT_MuxAsGpio);
  
      /* PORTB22 (pin 68) is configured as PTB22 */
      PORT_SetPinMux(LED_RED_PORT, LED_RED_PIN, kPORT_MuxAsGpio);
  
      /* PORTE26 (pin 33) is configured as PTE26 */
      PORT_SetPinMux(LED_GREEN_PORT, LED_GREEN_PIN, kPORT_MuxAsGpio);
  }
  
  /* clang-format off */
  /*
   * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
  BOARD_InitSerial:
  - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
  - pin_list:
    - {pin_num: '62', peripheral: UART0, signal: RX, pin_signal: PTB16/SPI1_SOUT/UART0_RX/FTM_CLKIN0/FB_AD17/EWM_IN}
    - {pin_num: '63', peripheral: UART0, signal: TX, pin_signal: PTB17/SPI1_SIN/UART0_TX/FTM_CLKIN1/FB_AD16/EWM_OUT_b}
    - {pin_num: '82', peripheral: I2C1, signal: SCL, pin_signal: ADC1_SE6b/PTC10/I2C1_SCL/FTM3_CH6/I2S0_RX_FS/FB_AD5, open_drain: enable, pull_select: up, pull_enable: enable}
    - {pin_num: '83', peripheral: I2C1, signal: SDA, pin_signal: ADC1_SE7b/PTC11/LLWU_P11/I2C1_SDA/FTM3_CH7/I2S0_RXD1/FB_RW_b, open_drain: enable, pull_select: up,
      pull_enable: enable}
   * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
   */
  /* clang-format on */
  
  /* FUNCTION ************************************************************************************************************
   *
   * Function Name : BOARD_InitSerial
   * Description   : Configures pin routing and optionally pin electrical features for serial comm.
   *
   * END ****************************************************************************************************************/
  void BOARD_InitSerial(void)
  {
      /* Port B Clock Gate Control: Clock enabled */
      CLOCK_EnableClock(kCLOCK_PortB);
      /* Port C Clock Gate Control: Clock enabled */
      CLOCK_EnableClock(kCLOCK_PortC);
  
      /* PORTB16 (pin 62) is configured as UART0_RX */
      PORT_SetPinMux(PORTB, 16U, kPORT_MuxAlt3);
  
      /* PORTB17 (pin 63) is configured as UART0_TX */
      PORT_SetPinMux(PORTB, 17U, kPORT_MuxAlt3);
  
      /* PORTC10 (pin 82) is configured as I2C1_SCL */
      PORT_SetPinMux(PORTC, 10U, kPORT_MuxAlt2);
  
      PORTC->PCR[10] = ((PORTC->PCR[10] &
                         /* Mask bits to zero which are setting */
                         (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
  
                        /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
                         * corresponding PE field is set. */
                        | (uint32_t)(kPORT_PullUp)
  
                        /* Open Drain Enable: Open drain output is enabled on the corresponding pin, if the pin is
                         * configured as a digital output. */
                        | PORT_PCR_ODE(kPORT_OpenDrainEnable));
  
      /* PORTC11 (pin 83) is configured as I2C1_SDA */
      PORT_SetPinMux(PORTC, 11U, kPORT_MuxAlt2);
  
      PORTC->PCR[11] = ((PORTC->PCR[11] &
                         /* Mask bits to zero which are setting */
                         (~(PORT_PCR_PS_MASK | PORT_PCR_PE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
  
                        /* Pull Select: Internal pullup resistor is enabled on the corresponding pin, if the
                         * corresponding PE field is set. */
                        | (uint32_t)(kPORT_PullUp)
  
                        /* Open Drain Enable: Open drain output is enabled on the corresponding pin, if the pin is
                         * configured as a digital output. */
                        | PORT_PCR_ODE(kPORT_OpenDrainEnable));
  
      SIM->SOPT5 = ((SIM->SOPT5 &
                     /* Mask bits to zero which are setting */
                     (~(SIM_SOPT5_UART0TXSRC_MASK)))
  
                    /* UART 0 transmit data source select: UART0_TX pin. */
                    | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX));
  }
  
  /* clang-format off */
  /*
   * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
  BOARD_InitPWM:
  - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
  - pin_list:
    - {pin_num: '72', peripheral: FTM0, signal: 'CH, 1', pin_signal: ADC0_SE4b/CMP1_IN0/PTC2/SPI0_PCS2/UART1_CTS_b/FTM0_CH1/FB_AD12/I2S0_TX_FS}
    - {pin_num: '76', peripheral: FTM0, signal: 'CH, 3', pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/FB_AD11/CMP1_OUT}
    - {pin_num: '93', peripheral: FTM3, signal: 'CH, 0', pin_signal: PTD0/LLWU_P12/SPI0_PCS0/UART2_RTS_b/FTM3_CH0/FB_ALE/FB_CS1_b/FB_TS_b}
    - {pin_num: '95', peripheral: FTM3, signal: 'CH, 2', pin_signal: PTD2/LLWU_P13/SPI0_SOUT/UART2_RX/FTM3_CH2/FB_AD4/I2C0_SCL}
   * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
   */
  /* clang-format on */
  
  /* FUNCTION ************************************************************************************************************
   *
   * Function Name : BOARD_InitPWM
   * Description   : Configures pin routing and optionally pin electrical features for PWM.
   *
   * END ****************************************************************************************************************/
  void BOARD_InitPWM(void)
  {
      /* Port C Clock Gate Control: Clock enabled */
      CLOCK_EnableClock(kCLOCK_PortC);
      /* Port D Clock Gate Control: Clock enabled */
      CLOCK_EnableClock(kCLOCK_PortD);
  
      /* PORTC2 (pin 72) is configured as FTM0_CH1 */
      PORT_SetPinMux(PORTC, 2U, kPORT_MuxAlt4);
  
      /* PORTC4 (pin 76) is configured as FTM0_CH3 */
      PORT_SetPinMux(PORTC, 4U, kPORT_MuxAlt4);
  
      /* PORTD0 (pin 93) is configured as FTM3_CH0 */
      PORT_SetPinMux(PORTD, 0U, kPORT_MuxAlt4);
  
      /* PORTD2 (pin 95) is configured as FTM3_CH2 */
      PORT_SetPinMux(PORTD, 2U, kPORT_MuxAlt4);
  }
  /***********************************************************************************************************************
   * EOF
   **********************************************************************************************************************/
  