text: /***********************************************************************************************************************
   * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
   * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
   **********************************************************************************************************************/
  /*
   * How to setup clock using clock driver functions:
   *
   * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
   *    and flash clock are in allowed range during clock mode switch.
   *
   * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
   *
   * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
   *    internal reference clock(MCGIRCLK). Follow the steps to setup:
   *
   *    1). Call CLOCK_BootToXxxMode to set MCG to target mode.
   *
   *    2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
   *        correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
   *        explicitly to setup MCGIRCLK.
   *
   *    3). Don't need to configure FLL explicitly, because if target mode is FLL
   *        mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
   *        if the target mode is not FLL mode, the FLL is disabled.
   *
   *    4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
   *        setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
   *        be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
   *
   * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
   */
  
  /* clang-format off */
  /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
  !!GlobalInfo
  product: Clocks v7.0
  processor: MKV42F128xxx16
  package_id: MKV42F128VLF16
  mcu_data: ksdk2_0
  processor_version: 8.0.1
   * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
  /* clang-format on */
  
  #include "core/target_specs.hpp"
  
  #ifdef __KV4X__
  
  #include "targets/KV4x/kv4x_fsl_clock_config.h"
  #include "fsl_smc.h"
  
  /*******************************************************************************
   * Definitions
   ******************************************************************************/
  #define MCG_PLL_DISABLE                                   0U  /*!< MCGPLLCLK disabled */
  #define OSC_CAP0P                                         0U  /*!< Oscillator 0pF capacitor load */
  #define OSC_ER_CLK_DISABLE                                0U  /*!< Disable external reference clock */
  #define SIM_OSC32KSEL_OSC32KCLK_CLK                       0U  /*!< OSC32KSEL select: OSC32KCLK clock */
  #define SIM_WDOG_CLK_SEL_MCGIRCLK_CLK                     1U  /*!< WDOG clock select: MCGIRCLK clock */
  
  /*******************************************************************************
   * Variables
   ******************************************************************************/
  /* System clock frequency. */
  extern uint32_t SystemCoreClock;
  
  /*******************************************************************************
   * Code
   ******************************************************************************/
  /*FUNCTION**********************************************************************
   *
   * Function Name : CLOCK_CONFIG_SetSimSafeDivs
   * Description   : This function sets the system clock dividers in SIM to safe 
   * value.
   *
   *END**************************************************************************/
  static void CLOCK_CONFIG_SetSimSafeDivs(void)
  {
      SIM->CLKDIV1 = 0x11070000U;
  }
  
  /*FUNCTION**********************************************************************
   *
   * Function Name : CLOCK_CONFIG_FllStableDelay
   * Description   : This function is used to delay for FLL stable.
   *
   *END**************************************************************************/
  static void CLOCK_CONFIG_FllStableDelay(void)
  {
      uint32_t i = 30000U;
      while (i--)
      {
          __NOP();
      }
  }
  
  /*FUNCTION**********************************************************************
   *
   * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
   * Description   : Configure FLL external reference divider (FRDIV).
   * Param frdiv   : The value to set FRDIV.
   *
   *END**************************************************************************/
  static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
  {
      MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
  }
  
  /*FUNCTION**********************************************************************
   *
   * Function Name : CLOCK_CONFIG_SetWdogClock
   * Description   : Set WDOG clock source.
   * Param src     : The value to set WDOG clock source.
   *
   *END**************************************************************************/
  static void CLOCK_CONFIG_SetWdogClock(uint8_t src)
  {
      SIM->WDOGC = ((SIM->WDOGC & ~SIM_WDOGC_WDOGCLKS_MASK) | SIM_WDOGC_WDOGCLKS(src));
  }
  
  /*******************************************************************************
   ****************** Configuration clock_config_irc_4mhz_vlpr *******************
   ******************************************************************************/
  /* clang-format off */
  /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
  !!Configuration
  name: clock_config_irc_4mhz_vlpr
  outputs:
  - {id: Bus_clock.outFreq, value: 4 MHz}
  - {id: Core_clock.outFreq, value: 4 MHz}
  - {id: Flash_clock.outFreq, value: 800 kHz}
  - {id: LPO_clock.outFreq, value: 1 kHz}
  - {id: MCGIRCLK.outFreq, value: 4 MHz}
  - {id: System_clock.outFreq, value: 4 MHz}
  - {id: WDOGCLK.outFreq, value: 4 MHz}
  settings:
  - {id: MCGMode, value: BLPI}
  - {id: powerMode, value: VLPR}
  - {id: MCG.CLKS.sel, value: MCG.IRCS}
  - {id: MCG.FCRDIV.scale, value: '1', locked: true}
  - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
  - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
  - {id: SIM.OUTDIV4.scale, value: '5'}
  - {id: SIM.WDOGCLKS.sel, value: MCG.MCGIRCLK}
  - {id: WDOGClkConfig, value: 'yes'}
   * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
  /* clang-format on */
  
  /*******************************************************************************
   * Variables for clock_config_irc_4mhz_vlpr configuration
   ******************************************************************************/
  const mcg_config_t mcgConfig_clock_config_irc_4mhz_vlpr =
      {
          .mcgMode = kMCG_ModeBLPI,                 /* BLPI - Bypassed Low Power Internal */
          .irclkEnableMode = kMCG_IrclkEnable,      /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
          .ircs = kMCG_IrcFast,                     /* Fast internal reference clock selected */
          .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
          .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 1 */
          .drs = kMCG_DrsLow,                       /* Low frequency range */
          .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
          .pll0Config =
              {
                  .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
                  .prdiv = 0x0U,                    /* PLL Reference divider: divided by 1 */
                  .vdiv = 0x0U,                     /* VCO divider: multiplied by 16 */
              },
      };
  const sim_clock_config_t simConfig_clock_config_irc_4mhz_vlpr =
      {
          .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
          .clkdiv1 = 0x40000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV4: /5 */
      };
  const osc_config_t oscConfig_clock_config_irc_4mhz_vlpr =
      {
          .freq = 0U,                               /* Oscillator frequency: 0Hz */
          .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
          .workMode = kOSC_ModeExt,                 /* Use external clock */
          .oscerConfig =
              {
                  .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
                  .erclkDiv = 0,                    /* Divider for OSCERCLK: divided by 1 */
              }
      };
  
  /*******************************************************************************
   * Code for clock_config_irc_4mhz_vlpr configuration
   ******************************************************************************/
  void clock_config_irc_4mhz_vlpr(void)
  {
      /* Set the system clock dividers in SIM to safe value. */
      CLOCK_CONFIG_SetSimSafeDivs();
      /* Set MCG to BLPI mode. */
      CLOCK_BootToBlpiMode(mcgConfig_clock_config_irc_4mhz_vlpr.fcrdiv,
                           mcgConfig_clock_config_irc_4mhz_vlpr.ircs,
                           mcgConfig_clock_config_irc_4mhz_vlpr.irclkEnableMode);
      /* Set the clock configuration in SIM module. */
      CLOCK_SetSimConfig(&simConfig_clock_config_irc_4mhz_vlpr);
      /* Set VLPR power mode. */
      SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
  #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
      SMC_SetPowerModeVlpr(SMC, false);
  #else
      SMC_SetPowerModeVlpr(SMC);
  #endif
      while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
      {
      }
      /* Set SystemCoreClock variable. */
      SystemCoreClock = CLOCK_CONFIG_IRC_4MHZ_VLPR_CORE_CLOCK;
      /* Set WDOG clock source. */
      CLOCK_CONFIG_SetWdogClock(SIM_WDOG_CLK_SEL_MCGIRCLK_CLK);
  }
  
  /*******************************************************************************
   ****************** Configuration clock_config_irc_96mhz_run *******************
   ******************************************************************************/
  /* clang-format off */
  /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
  !!Configuration
  name: clock_config_irc_96mhz_run
  called_from_default_init: true
  outputs:
  - {id: Bus_clock.outFreq, value: 95.977472 MHz}
  - {id: Core_clock.outFreq, value: 95.977472 MHz}
  - {id: Flash_clock.outFreq, value: 23.994368 MHz}
  - {id: LPO_clock.outFreq, value: 1 kHz}
  - {id: MCGIRCLK.outFreq, value: 4 MHz}
  - {id: System_clock.outFreq, value: 95.977472 MHz}
  - {id: WDOGCLK.outFreq, value: 4 MHz}
  settings:
  - {id: MCG.FCRDIV.scale, value: '1', locked: true}
  - {id: MCG.FLL_mul.scale, value: '2929', locked: true}
  - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
  - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
  - {id: MCRFFCLKAllowConfig, value: 'no'}
  - {id: SIM.OUTDIV4.scale, value: '4', locked: true}
  - {id: SIM.WDOGCLKS.sel, value: MCG.MCGIRCLK}
  - {id: WDOGClkConfig, value: 'yes'}
   * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
  /* clang-format on */
  
  /*******************************************************************************
   * Variables for clock_config_irc_96mhz_run configuration
   ******************************************************************************/
  const mcg_config_t mcgConfig_clock_config_irc_96mhz_run =
      {
          .mcgMode = kMCG_ModeFEI,                  /* FEI - FLL Engaged Internal */
          .irclkEnableMode = kMCG_IrclkEnable,      /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
          .ircs = kMCG_IrcFast,                     /* Fast internal reference clock selected */
          .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
          .frdiv = 0x0U,                            /* FLL reference clock divider: divided by 1 */
          .drs = kMCG_DrsHigh,                      /* High frequency range */
          .dmx32 = kMCG_Dmx32Fine,                  /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
          .pll0Config =
              {
                  .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
                  .prdiv = 0x0U,                    /* PLL Reference divider: divided by 1 */
                  .vdiv = 0x0U,                     /* VCO divider: multiplied by 16 */
              },
      };
  const sim_clock_config_t simConfig_clock_config_irc_96mhz_run =
      {
          .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
          .clkdiv1 = 0x30000U,                      /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV4: /4 */
      };
  const osc_config_t oscConfig_clock_config_irc_96mhz_run =
      {
          .freq = 0U,                               /* Oscillator frequency: 0Hz */
          .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
          .workMode = kOSC_ModeExt,                 /* Use external clock */
          .oscerConfig =
              {
                  .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
                  .erclkDiv = 0,                    /* Divider for OSCERCLK: divided by 1 */
              }
      };
  
  /*******************************************************************************
   * Code for clock_config_irc_96mhz_run configuration
   ******************************************************************************/
  void clock_config_irc_96mhz_run(void)
  {
      /* Set the system clock dividers in SIM to safe value. */
      CLOCK_CONFIG_SetSimSafeDivs();
      /* Set MCG to FEI mode. */
  #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
      CLOCK_BootToFeiMode(mcgConfig_clock_config_irc_96mhz_run.dmx32,
                          mcgConfig_clock_config_irc_96mhz_run.drs,
                          CLOCK_CONFIG_FllStableDelay);
  #else
      CLOCK_BootToFeiMode(mcgConfig_clock_config_irc_96mhz_run.drs,
                          CLOCK_CONFIG_FllStableDelay);
  #endif
      /* Configure the Internal Reference clock (MCGIRCLK). */
      CLOCK_SetInternalRefClkConfig(mcgConfig_clock_config_irc_96mhz_run.irclkEnableMode,
                                    mcgConfig_clock_config_irc_96mhz_run.ircs, 
                                    mcgConfig_clock_config_irc_96mhz_run.fcrdiv);
      /* Set the clock configuration in SIM module. */
      CLOCK_SetSimConfig(&simConfig_clock_config_irc_96mhz_run);
      /* Set SystemCoreClock variable. */
      SystemCoreClock = CLOCK_CONFIG_IRC_96MHZ_RUN_CORE_CLOCK;
      /* Set WDOG clock source. */
      CLOCK_CONFIG_SetWdogClock(SIM_WDOG_CLK_SEL_MCGIRCLK_CLK);
  }
  
  /*******************************************************************************
   ***************** Configuration clock_config_xtal_96mhz_run *******************
   ******************************************************************************/
  /* clang-format off */
  /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
  !!Configuration
  name: clock_config_xtal_96mhz_run
  outputs:
  - {id: Bus_clock.outFreq, value: 96 MHz}
  - {id: Core_clock.outFreq, value: 96 MHz}
  - {id: Flash_clock.outFreq, value: 24 MHz}
  - {id: LPO_clock.outFreq, value: 1 kHz}
  - {id: MCGIRCLK.outFreq, value: 4 MHz}
  - {id: System_clock.outFreq, value: 96 MHz}
  - {id: WDOGCLK.outFreq, value: 4 MHz}
  settings:
  - {id: MCGMode, value: PEE}
  - {id: MCG.FCRDIV.scale, value: '1', locked: true}
  - {id: MCG.FLL_mul.scale, value: '2929', locked: true}
  - {id: MCG.FRDIV.scale, value: '256', locked: true}
  - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
  - {id: MCG.IREFS.sel, value: MCG.FRDIV}
  - {id: MCG.PLLS.sel, value: MCG.PLL_DIV2}
  - {id: MCG.PRDIV.scale, value: '1', locked: true}
  - {id: MCG.VDIV.scale, value: '32', locked: true}
  - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
  - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscHighGain}
  - {id: MCG_C2_RANGE0_CFG, value: Very_high}
  - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
  - {id: MCRFFCLKAllowConfig, value: 'no'}
  - {id: SIM.OUTDIV1.scale, value: '2', locked: true}
  - {id: SIM.OUTDIV2.scale, value: '2'}
  - {id: SIM.OUTDIV4.scale, value: '8'}
  - {id: SIM.WDOGCLKS.sel, value: MCG.MCGIRCLK}
  - {id: WDOGClkConfig, value: 'yes'}
  sources:
  - {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
   * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
  /* clang-format on */
  
  /*******************************************************************************
   * Variables for clock_config_xtal_96mhz_run configuration
   ******************************************************************************/
  const mcg_config_t mcgConfig_clock_config_xtal_96mhz_run =
      {
          .mcgMode = kMCG_ModePEE,                  /* PEE - PLL Engaged External */
          .irclkEnableMode = kMCG_IrclkEnable,      /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
          .ircs = kMCG_IrcFast,                     /* Fast internal reference clock selected */
          .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
          .frdiv = 0x3U,                            /* FLL reference clock divider: divided by 256 */
          .drs = kMCG_DrsHigh,                      /* High frequency range */
          .dmx32 = kMCG_Dmx32Fine,                  /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
          .pll0Config =
              {
                  .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
                  .prdiv = 0x0U,                    /* PLL Reference divider: divided by 1 */
                  .vdiv = 0x10U,                    /* VCO divider: multiplied by 32 */
              },
      };
  const sim_clock_config_t simConfig_clock_config_xtal_96mhz_run =
      {
          .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
          .clkdiv1 = 0x11070000U,                   /* SIM_CLKDIV1 - OUTDIV1: /2, OUTDIV2: /2, OUTDIV4: /8 */
      };
  const osc_config_t oscConfig_clock_config_xtal_96mhz_run =
      {
          .freq = 12000000U,                        /* Oscillator frequency: 12000000Hz */
          .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
          .workMode = kOSC_ModeOscHighGain,         /* Oscillator high gain */
          .oscerConfig =
              {
                  .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
                  .erclkDiv = 0,                    /* Divider for OSCERCLK: divided by 1 */
              }
      };
  
  /*******************************************************************************
   * Code for clock_config_xtal_96mhz_run configuration
   ******************************************************************************/
  void clock_config_xtal_96mhz_run(void)
  {
      /* Set the system clock dividers in SIM to safe value. */
      CLOCK_CONFIG_SetSimSafeDivs();
      /* Initializes OSC0 according to board configuration. */
      CLOCK_InitOsc0(&oscConfig_clock_config_xtal_96mhz_run);
      CLOCK_SetXtal0Freq(oscConfig_clock_config_xtal_96mhz_run.freq);
      /* Configure FLL external reference divider (FRDIV). */
      CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_clock_config_xtal_96mhz_run.frdiv);
      /* Set MCG to PEE mode. */
      CLOCK_BootToPeeMode(kMCG_OscselOsc,
                          kMCG_PllClkSelPll0,
                          &mcgConfig_clock_config_xtal_96mhz_run.pll0Config);
      /* Configure the Internal Reference clock (MCGIRCLK). */
      CLOCK_SetInternalRefClkConfig(mcgConfig_clock_config_xtal_96mhz_run.irclkEnableMode,
                                    mcgConfig_clock_config_xtal_96mhz_run.ircs, 
                                    mcgConfig_clock_config_xtal_96mhz_run.fcrdiv);
      /* Set the clock configuration in SIM module. */
      CLOCK_SetSimConfig(&simConfig_clock_config_xtal_96mhz_run);
      /* Set SystemCoreClock variable. */
      SystemCoreClock = CLOCK_CONFIG_XTAL_96MHZ_RUN_CORE_CLOCK;
      /* Set WDOG clock source. */
      CLOCK_CONFIG_SetWdogClock(SIM_WDOG_CLK_SEL_MCGIRCLK_CLK);
  }
  
  /*******************************************************************************
   **************** Configuration clock_config_xtal_168mhz_hsrun *****************
   ******************************************************************************/
  /* clang-format off */
  /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
  !!Configuration
  name: clock_config_xtal_168mhz_hsrun
  outputs:
  - {id: Bus_clock.outFreq, value: 84 MHz}
  - {id: Core_clock.outFreq, value: 168 MHz}
  - {id: Flash_clock.outFreq, value: 21 MHz}
  - {id: LPO_clock.outFreq, value: 1 kHz}
  - {id: MCGIRCLK.outFreq, value: 4 MHz}
  - {id: System_clock.outFreq, value: 168 MHz}
  - {id: WDOGCLK.outFreq, value: 4 MHz}
  settings:
  - {id: MCGMode, value: PEE}
  - {id: powerMode, value: HSRUN}
  - {id: MCG.FCRDIV.scale, value: '1', locked: true}
  - {id: MCG.FRDIV.scale, value: '256', locked: true}
  - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
  - {id: MCG.IREFS.sel, value: MCG.FRDIV}
  - {id: MCG.PLLS.sel, value: MCG.PLL_DIV2}
  - {id: MCG.PRDIV.scale, value: '1', locked: true}
  - {id: MCG.VDIV.scale, value: '28', locked: true}
  - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
  - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscHighGain}
  - {id: MCG_C2_RANGE0_CFG, value: Very_high}
  - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
  - {id: MCRFFCLKAllowConfig, value: 'no'}
  - {id: SIM.OUTDIV1.scale, value: '1', locked: true}
  - {id: SIM.OUTDIV2.scale, value: '2'}
  - {id: SIM.OUTDIV4.scale, value: '8'}
  - {id: SIM.WDOGCLKS.sel, value: MCG.MCGIRCLK}
  - {id: WDOGClkConfig, value: 'yes'}
  sources:
  - {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
   * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
  /* clang-format on */
  
  /*******************************************************************************
   * Variables for clock_config_xtal_168mhz_hsrun configuration
   ******************************************************************************/
  const mcg_config_t mcgConfig_clock_config_xtal_168mhz_hsrun =
      {
          .mcgMode = kMCG_ModePEE,                  /* PEE - PLL Engaged External */
          .irclkEnableMode = kMCG_IrclkEnable,      /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
          .ircs = kMCG_IrcFast,                     /* Fast internal reference clock selected */
          .fcrdiv = 0x0U,                           /* Fast IRC divider: divided by 1 */
          .frdiv = 0x3U,                            /* FLL reference clock divider: divided by 256 */
          .drs = kMCG_DrsLow,                       /* Low frequency range */
          .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
          .pll0Config =
              {
                  .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
                  .prdiv = 0x0U,                    /* PLL Reference divider: divided by 1 */
                  .vdiv = 0xcU,                     /* VCO divider: multiplied by 28 */
              },
      };
  const sim_clock_config_t simConfig_clock_config_xtal_168mhz_hsrun =
      {
          .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK,  /* OSC32KSEL select: OSC32KCLK clock */
          .clkdiv1 = 0x1070000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV4: /8 */
      };
  const osc_config_t oscConfig_clock_config_xtal_168mhz_hsrun =
      {
          .freq = 12000000U,                        /* Oscillator frequency: 12000000Hz */
          .capLoad = (OSC_CAP0P),                   /* Oscillator capacity load: 0pF */
          .workMode = kOSC_ModeOscHighGain,         /* Oscillator high gain */
          .oscerConfig =
              {
                  .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
                  .erclkDiv = 0,                    /* Divider for OSCERCLK: divided by 1 */
              }
      };
  
  /*******************************************************************************
   * Code for clock_config_xtal_168mhz_hsrun configuration
   ******************************************************************************/
  void clock_config_xtal_168mhz_hsrun(void)
  {
      /* Set HSRUN power mode */
      SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
      SMC_SetPowerModeHsrun(SMC);
      while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
      {
      }
      /* Set the system clock dividers in SIM to safe value. */
      CLOCK_CONFIG_SetSimSafeDivs();
      /* Initializes OSC0 according to board configuration. */
      CLOCK_InitOsc0(&oscConfig_clock_config_xtal_168mhz_hsrun);
      CLOCK_SetXtal0Freq(oscConfig_clock_config_xtal_168mhz_hsrun.freq);
      /* Configure FLL external reference divider (FRDIV). */
      CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_clock_config_xtal_168mhz_hsrun.frdiv);
      /* Set MCG to PEE mode. */
      CLOCK_BootToPeeMode(kMCG_OscselOsc,
                          kMCG_PllClkSelPll0,
                          &mcgConfig_clock_config_xtal_168mhz_hsrun.pll0Config);
      /* Configure the Internal Reference clock (MCGIRCLK). */
      CLOCK_SetInternalRefClkConfig(mcgConfig_clock_config_xtal_168mhz_hsrun.irclkEnableMode,
                                    mcgConfig_clock_config_xtal_168mhz_hsrun.ircs, 
                                    mcgConfig_clock_config_xtal_168mhz_hsrun.fcrdiv);
      /* Set the clock configuration in SIM module. */
      CLOCK_SetSimConfig(&simConfig_clock_config_xtal_168mhz_hsrun);
      /* Set SystemCoreClock variable. */
      SystemCoreClock = CLOCK_CONFIG_XTAL_168MHZ_HSRUN_CORE_CLOCK;
      /* Set WDOG clock source. */
      CLOCK_CONFIG_SetWdogClock(SIM_WDOG_CLK_SEL_MCGIRCLK_CLK);
  }
  
  #endif // __KV4X__
  