text: #!/usr/bin/env python
  """
  
  Copyright (c) 2020 Alex Forencich
  
  Permission is hereby granted, free of charge, to any person obtaining a copy
  of this software and associated documentation files (the "Software"), to deal
  in the Software without restriction, including without limitation the rights
  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  copies of the Software, and to permit persons to whom the Software is
  furnished to do so, subject to the following conditions:
  
  The above copyright notice and this permission notice shall be included in
  all copies or substantial portions of the Software.
  
  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  THE SOFTWARE.
  
  """
  
  import itertools
  import logging
  import os
  
  import cocotb_test.simulator
  
  import cocotb
  from cocotb.clock import Clock
  from cocotb.triggers import RisingEdge
  from cocotb.regression import TestFactory
  
  from cocotbext.eth import XgmiiFrame, XgmiiSource
  from cocotbext.axi import AxiStreamBus, AxiStreamSink
  
  
  class TB:
      def __init__(self, dut):
          self.dut = dut
  
          self.log = logging.getLogger("cocotb.tb")
          self.log.setLevel(logging.DEBUG)
  
          cocotb.start_soon(Clock(dut.clk, 3.2, units="ns").start())
  
          self.source = XgmiiSource(dut.xgmii_rxd, dut.xgmii_rxc, dut.clk, dut.rst)
          self.sink = AxiStreamSink(AxiStreamBus.from_prefix(dut, "m_axis"), dut.clk, dut.rst)
  
          dut.ptp_ts.setimmediatevalue(0)
  
      async def reset(self):
          self.dut.rst.setimmediatevalue(0)
          await RisingEdge(self.dut.clk)
          await RisingEdge(self.dut.clk)
          self.dut.rst.value = 1
          await RisingEdge(self.dut.clk)
          await RisingEdge(self.dut.clk)
          self.dut.rst.value = 0
          await RisingEdge(self.dut.clk)
          await RisingEdge(self.dut.clk)
  
  
  async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
  
      tb = TB(dut)
  
      tb.source.ifg = ifg
  
      await tb.reset()
  
      test_frames = [payload_data(x) for x in payload_lengths()]
  
      for test_data in test_frames:
          test_frame = XgmiiFrame.from_payload(test_data)
          await tb.source.send(test_frame)
  
      for test_data in test_frames:
          rx_frame = await tb.sink.recv()
  
          assert rx_frame.tdata == test_data
          assert rx_frame.tuser == 0
  
      assert tb.sink.empty()
  
      await RisingEdge(dut.clk)
      await RisingEdge(dut.clk)
  
  
  def size_list():
      return list(range(60, 128)) + [512, 1514, 9214] + [60]*10
  
  
  def incrementing_payload(length):
      return bytearray(itertools.islice(itertools.cycle(range(256)), length))
  
  
  def cycle_en():
      return itertools.cycle([0, 0, 0, 1])
  
  
  if cocotb.SIM_NAME:
  
      factory = TestFactory(run_test)
      factory.add_option("payload_lengths", [size_list])
      factory.add_option("payload_data", [incrementing_payload])
      factory.add_option("ifg", [12, 0])
      factory.generate_tests()
  
  
  # cocotb-test
  
  tests_dir = os.path.abspath(os.path.dirname(__file__))
  rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
  lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
  axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
  
  
  def test_axis_xgmii_rx_32(request):
      dut = "axis_xgmii_rx_32"
      module = os.path.splitext(os.path.basename(__file__))[0]
      toplevel = dut
  
      verilog_sources = [
          os.path.join(rtl_dir, f"{dut}.v"),
          os.path.join(rtl_dir, "lfsr.v"),
      ]
  
      parameters = {}
  
      parameters['DATA_WIDTH'] = 32
      parameters['KEEP_WIDTH'] = parameters['DATA_WIDTH'] // 8
      parameters['CTRL_WIDTH'] = parameters['DATA_WIDTH'] // 8
      parameters['PTP_TS_ENABLE'] = 0
      parameters['PTP_TS_WIDTH'] = 96
      parameters['USER_WIDTH'] = (parameters['PTP_TS_WIDTH'] if parameters['PTP_TS_ENABLE'] else 0) + 1
  
      extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
  
      sim_build = os.path.join(tests_dir, "sim_build",
          request.node.name.replace('[', '-').replace(']', ''))
  
      cocotb_test.simulator.run(
          python_search=[tests_dir],
          verilog_sources=verilog_sources,
          toplevel=toplevel,
          module=module,
          parameters=parameters,
          sim_build=sim_build,
          extra_env=extra_env,
      )
  