text: //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
  //
  // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  // See https://llvm.org/LICENSE.txt for license information.
  // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  //
  //===----------------------------------------------------------------------===//
  //
  // This file contains the RISCV implementation of the TargetRegisterInfo class.
  //
  //===----------------------------------------------------------------------===//
  
  #include "RISCVRegisterInfo.h"
  #include "RISCV.h"
  #include "RISCVSubtarget.h"
  #include "llvm/CodeGen/MachineFrameInfo.h"
  #include "llvm/CodeGen/MachineFunction.h"
  #include "llvm/CodeGen/MachineInstrBuilder.h"
  #include "llvm/CodeGen/RegisterScavenging.h"
  #include "llvm/CodeGen/TargetFrameLowering.h"
  #include "llvm/CodeGen/TargetInstrInfo.h"
  #include "llvm/Support/ErrorHandling.h"
  
  #define GET_REGINFO_TARGET_DESC
  #include "RISCVGenRegisterInfo.inc"
  
  using namespace llvm;
  
  static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
  static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
  static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
  static_assert(RISCV::F31_F == RISCV::F0_F + 31,
                "Register list not consecutive");
  static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
  static_assert(RISCV::F31_D == RISCV::F0_D + 31,
                "Register list not consecutive");
  
  RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
      : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
                             /*PC*/0, HwMode) {}
  
  const MCPhysReg *
  RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
    auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
    if (MF->getFunction().hasFnAttribute("interrupt")) {
      if (Subtarget.hasStdExtD())
        return CSR_XLEN_F64_Interrupt_SaveList;
      if (Subtarget.hasStdExtF())
        return CSR_XLEN_F32_Interrupt_SaveList;
      return CSR_Interrupt_SaveList;
    }
  
    switch (Subtarget.getTargetABI()) {
    default:
      llvm_unreachable("Unrecognized ABI");
    case RISCVABI::ABI_ILP32:
    case RISCVABI::ABI_LP64:
      return CSR_ILP32_LP64_SaveList;
    case RISCVABI::ABI_ILP32F:
    case RISCVABI::ABI_LP64F:
      return CSR_ILP32F_LP64F_SaveList;
    case RISCVABI::ABI_ILP32D:
    case RISCVABI::ABI_LP64D:
      return CSR_ILP32D_LP64D_SaveList;
    }
  }
  
  BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
    const TargetFrameLowering *TFI = getFrameLowering(MF);
    BitVector Reserved(getNumRegs());
  
    // Mark any registers requested to be reserved as such
    for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
      if (MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(Reg))
        markSuperRegs(Reserved, Reg);
    }
  
    // Use markSuperRegs to ensure any register aliases are also reserved
    markSuperRegs(Reserved, RISCV::X0); // zero
    markSuperRegs(Reserved, RISCV::X2); // sp
    markSuperRegs(Reserved, RISCV::X3); // gp
    markSuperRegs(Reserved, RISCV::X4); // tp
    if (TFI->hasFP(MF))
      markSuperRegs(Reserved, RISCV::X8); // fp
    assert(checkAllSuperRegsMarked(Reserved));
    return Reserved;
  }
  
  bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
                                           unsigned PhysReg) const {
    return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
  }
  
  bool RISCVRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
    return PhysReg == RISCV::X0;
  }
  
  const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
    return CSR_NoRegs_RegMask;
  }
  
  void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
                                              int SPAdj, unsigned FIOperandNum,
                                              RegScavenger *RS) const {
    assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
  
    MachineInstr &MI = *II;
    MachineFunction &MF = *MI.getParent()->getParent();
    MachineRegisterInfo &MRI = MF.getRegInfo();
    const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
    DebugLoc DL = MI.getDebugLoc();
  
    int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
    unsigned FrameReg;
    int Offset =
        getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) +
        MI.getOperand(FIOperandNum + 1).getImm();
  
    if (!isInt<32>(Offset)) {
      report_fatal_error(
          "Frame offsets outside of the signed 32-bit range not supported");
    }
  
    MachineBasicBlock &MBB = *MI.getParent();
    bool FrameRegIsKill = false;
  
    if (!isInt<12>(Offset)) {
      assert(isInt<32>(Offset) && "Int32 expected");
      // The offset won't fit in an immediate, so use a scratch register instead
      // Modify Offset and FrameReg appropriately
      Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
      TII->movImm(MBB, II, DL, ScratchReg, Offset);
      BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
          .addReg(FrameReg)
          .addReg(ScratchReg, RegState::Kill);
      Offset = 0;
      FrameReg = ScratchReg;
      FrameRegIsKill = true;
    }
  
    MI.getOperand(FIOperandNum)
        .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
    MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
  }
  
  Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
    const TargetFrameLowering *TFI = getFrameLowering(MF);
    return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
  }
  
  const uint32_t *
  RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
                                          CallingConv::ID /*CC*/) const {
    auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
    if (MF.getFunction().hasFnAttribute("interrupt")) {
      if (Subtarget.hasStdExtD())
        return CSR_XLEN_F64_Interrupt_RegMask;
      if (Subtarget.hasStdExtF())
        return CSR_XLEN_F32_Interrupt_RegMask;
      return CSR_Interrupt_RegMask;
    }
  
    switch (Subtarget.getTargetABI()) {
    default:
      llvm_unreachable("Unrecognized ABI");
    case RISCVABI::ABI_ILP32:
    case RISCVABI::ABI_LP64:
      return CSR_ILP32_LP64_RegMask;
    case RISCVABI::ABI_ILP32F:
    case RISCVABI::ABI_LP64F:
      return CSR_ILP32F_LP64F_RegMask;
    case RISCVABI::ABI_ILP32D:
    case RISCVABI::ABI_LP64D:
      return CSR_ILP32D_LP64D_RegMask;
    }
  }
  