text: // SPDX-License-Identifier: GPL-2.0
  /**
   * core.c - DesignWare USB3 DRD Controller Core file
   *
   * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   *
   * Authors: Felipe Balbi <balbi@ti.com>,
   *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   */
  
  #include <linux/clk.h>
  #include <linux/version.h>
  #include <linux/module.h>
  #include <linux/kernel.h>
  #include <linux/slab.h>
  #include <linux/spinlock.h>
  #include <linux/platform_device.h>
  #include <linux/pm_runtime.h>
  #include <linux/interrupt.h>
  #include <linux/ioport.h>
  #include <linux/io.h>
  #include <linux/list.h>
  #include <linux/delay.h>
  #include <linux/dma-mapping.h>
  #include <linux/of.h>
  #include <linux/acpi.h>
  #include <linux/pinctrl/consumer.h>
  #include <linux/of_address.h>
  #include <linux/reset.h>
  
  #include <linux/usb/ch9.h>
  #include <linux/usb/gadget.h>
  #include <linux/usb/of.h>
  #include <linux/usb/otg.h>
  
  #include "core.h"
  #include "gadget.h"
  #include "io.h"
  
  #include "debug.h"
  
  #define DWC3_DEFAULT_AUTOSUSPEND_DELAY	5000 /* ms */
  
  /**
   * dwc3_get_dr_mode - Validates and sets dr_mode
   * @dwc: pointer to our context structure
   */
  static int dwc3_get_dr_mode(struct dwc3 *dwc)
  {
  	enum usb_dr_mode mode;
  	struct device *dev = dwc->dev;
  	unsigned int hw_mode;
  
  	if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  		dwc->dr_mode = USB_DR_MODE_OTG;
  
  	mode = dwc->dr_mode;
  	hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  
  	switch (hw_mode) {
  	case DWC3_GHWPARAMS0_MODE_GADGET:
  		if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  			dev_err(dev,
  				"Controller does not support host mode.\n");
  			return -EINVAL;
  		}
  		mode = USB_DR_MODE_PERIPHERAL;
  		break;
  	case DWC3_GHWPARAMS0_MODE_HOST:
  		if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  			dev_err(dev,
  				"Controller does not support device mode.\n");
  			return -EINVAL;
  		}
  		mode = USB_DR_MODE_HOST;
  		break;
  	default:
  		if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  			mode = USB_DR_MODE_HOST;
  		else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  			mode = USB_DR_MODE_PERIPHERAL;
  
  		/*
  		 * dwc_usb31 does not support OTG mode. If the controller
  		 * supports DRD but the dr_mode is not specified or set to OTG,
  		 * then set the mode to peripheral.
  		 */
  		if (mode == USB_DR_MODE_OTG && dwc3_is_usb31(dwc))
  			mode = USB_DR_MODE_PERIPHERAL;
  	}
  
  	if (mode != dwc->dr_mode) {
  		dev_warn(dev,
  			 "Configuration mismatch. dr_mode forced to %s\n",
  			 mode == USB_DR_MODE_HOST ? "host" : "gadget");
  
  		dwc->dr_mode = mode;
  	}
  
  	return 0;
  }
  
  void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
  {
  	u32 reg;
  
  	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  	reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  	reg |= DWC3_GCTL_PRTCAPDIR(mode);
  	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  
  	dwc->current_dr_role = mode;
  }
  
  static void __dwc3_set_mode(struct work_struct *work)
  {
  	struct dwc3 *dwc = work_to_dwc(work);
  	unsigned long flags;
  	int ret;
  
  	if (dwc->dr_mode != USB_DR_MODE_OTG)
  		return;
  
  	if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
  		dwc3_otg_update(dwc, 0);
  
  	if (!dwc->desired_dr_role)
  		return;
  
  	if (dwc->desired_dr_role == dwc->current_dr_role)
  		return;
  
  	if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
  		return;
  
  	switch (dwc->current_dr_role) {
  	case DWC3_GCTL_PRTCAP_HOST:
  		dwc3_host_exit(dwc);
  		break;
  	case DWC3_GCTL_PRTCAP_DEVICE:
  		dwc3_gadget_exit(dwc);
  		dwc3_event_buffers_cleanup(dwc);
  		break;
  	case DWC3_GCTL_PRTCAP_OTG:
  		dwc3_otg_exit(dwc);
  		spin_lock_irqsave(&dwc->lock, flags);
  		dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
  		spin_unlock_irqrestore(&dwc->lock, flags);
  		dwc3_otg_update(dwc, 1);
  		break;
  	default:
  		break;
  	}
  
  	spin_lock_irqsave(&dwc->lock, flags);
  
  	dwc3_set_prtcap(dwc, dwc->desired_dr_role);
  
  	spin_unlock_irqrestore(&dwc->lock, flags);
  
  	switch (dwc->desired_dr_role) {
  	case DWC3_GCTL_PRTCAP_HOST:
  		ret = dwc3_host_init(dwc);
  		if (ret) {
  			dev_err(dwc->dev, "failed to initialize host\n");
  		} else {
  			if (dwc->usb2_phy)
  				otg_set_vbus(dwc->usb2_phy->otg, true);
  			phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
  			phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
  			phy_calibrate(dwc->usb2_generic_phy);
  		}
  		break;
  	case DWC3_GCTL_PRTCAP_DEVICE:
  		dwc3_event_buffers_setup(dwc);
  
  		if (dwc->usb2_phy)
  			otg_set_vbus(dwc->usb2_phy->otg, false);
  		phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
  		phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
  
  		ret = dwc3_gadget_init(dwc);
  		if (ret)
  			dev_err(dwc->dev, "failed to initialize peripheral\n");
  		break;
  	case DWC3_GCTL_PRTCAP_OTG:
  		dwc3_otg_init(dwc);
  		dwc3_otg_update(dwc, 0);
  		break;
  	default:
  		break;
  	}
  
  }
  
  void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  {
  	unsigned long flags;
  
  	spin_lock_irqsave(&dwc->lock, flags);
  	dwc->desired_dr_role = mode;
  	spin_unlock_irqrestore(&dwc->lock, flags);
  
  	queue_work(system_freezable_wq, &dwc->drd_work);
  }
  
  u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
  {
  	struct dwc3		*dwc = dep->dwc;
  	u32			reg;
  
  	dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
  			DWC3_GDBGFIFOSPACE_NUM(dep->number) |
  			DWC3_GDBGFIFOSPACE_TYPE(type));
  
  	reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
  
  	return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
  }
  
  /**
   * dwc3_core_soft_reset - Issues core soft reset and PHY reset
   * @dwc: pointer to our context structure
   */
  static int dwc3_core_soft_reset(struct dwc3 *dwc)
  {
  	u32		reg;
  	int		retries = 1000;
  	int		ret;
  
  	usb_phy_init(dwc->usb2_phy);
  	usb_phy_init(dwc->usb3_phy);
  	ret = phy_init(dwc->usb2_generic_phy);
  	if (ret < 0)
  		return ret;
  
  	ret = phy_init(dwc->usb3_generic_phy);
  	if (ret < 0) {
  		phy_exit(dwc->usb2_generic_phy);
  		return ret;
  	}
  
  	/*
  	 * We're resetting only the device side because, if we're in host mode,
  	 * XHCI driver will reset the host block. If dwc3 was configured for
  	 * host-only mode, then we can return early.
  	 */
  	if (dwc->dr_mode == USB_DR_MODE_HOST || dwc->is_hibernated == true)
  		return 0;
  
  	if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
  		return 0;
  
  	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  	reg |= DWC3_DCTL_CSFTRST;
  	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  
  	do {
  		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  		if (!(reg & DWC3_DCTL_CSFTRST))
  			goto done;
  
  		udelay(1);
  	} while (--retries);
  
  	phy_exit(dwc->usb3_generic_phy);
  	phy_exit(dwc->usb2_generic_phy);
  
  	return -ETIMEDOUT;
  
  done:
  	/*
  	 * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
  	 * we must wait at least 50ms before accessing the PHY domain
  	 * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
  	 */
  	if (dwc3_is_usb31(dwc))
  		msleep(50);
  
  	return 0;
  }
  
  static const struct clk_bulk_data dwc3_core_clks[] = {
  	{ .id = "ref" },
  	{ .id = "bus_early" },
  	{ .id = "suspend" },
  };
  
  /*
   * dwc3_frame_length_adjustment - Adjusts frame length if required
   * @dwc3: Pointer to our controller context structure
   */
  static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
  {
  	u32 reg, gfladj;
  	u32 dft;
  
  	if (dwc->revision < DWC3_REVISION_250A)
  		return;
  
  	if (dwc->fladj == 0)
  		return;
  
  	/* Save the initial DWC3_GFLADJ register value */
  	reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
  	gfladj = reg;
  
  	if (dwc->refclk_fladj) {
  		if ((reg & DWC3_GFLADJ_REFCLK_FLADJ) !=
  				    (dwc->fladj & DWC3_GFLADJ_REFCLK_FLADJ)) {
  			reg &= ~DWC3_GFLADJ_REFCLK_FLADJ;
  			reg |= (dwc->fladj & DWC3_GFLADJ_REFCLK_FLADJ);
  		}
  	}
  
  	dft = reg & DWC3_GFLADJ_30MHZ_MASK;
  	if (dft != dwc->fladj) {
  		reg &= ~DWC3_GFLADJ_30MHZ_MASK;
  		reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
  	}
  
  	/* Update DWC3_GFLADJ if there is any change from initial value */
  	if (reg != gfladj)
  		dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
  }
  
  /**
   * dwc3_free_one_event_buffer - Frees one event buffer
   * @dwc: Pointer to our controller context structure
   * @evt: Pointer to event buffer to be freed
   */
  static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
  		struct dwc3_event_buffer *evt)
  {
  	dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
  }
  
  /**
   * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
   * @dwc: Pointer to our controller context structure
   * @length: size of the event buffer
   *
   * Returns a pointer to the allocated event buffer structure on success
   * otherwise ERR_PTR(errno).
   */
  static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
  		unsigned length)
  {
  	struct dwc3_event_buffer	*evt;
  
  	evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
  	if (!evt)
  		return ERR_PTR(-ENOMEM);
  
  	evt->dwc	= dwc;
  	evt->length	= length;
  	evt->cache	= devm_kzalloc(dwc->dev, length, GFP_KERNEL);
  	if (!evt->cache)
  		return ERR_PTR(-ENOMEM);
  
  	evt->buf	= dma_alloc_coherent(dwc->sysdev, length,
  			&evt->dma, GFP_KERNEL);
  	if (!evt->buf)
  		return ERR_PTR(-ENOMEM);
  
  	return evt;
  }
  
  /**
   * dwc3_free_event_buffers - frees all allocated event buffers
   * @dwc: Pointer to our controller context structure
   */
  void dwc3_free_event_buffers(struct dwc3 *dwc)
  {
  	struct dwc3_event_buffer	*evt;
  
  	evt = dwc->ev_buf;
  	if (evt)
  		dwc3_free_one_event_buffer(dwc, evt);
  }
  
  /**
   * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
   * @dwc: pointer to our controller context structure
   * @length: size of event buffer
   *
   * Returns 0 on success otherwise negative errno. In the error case, dwc
   * may contain some buffers allocated but not all which were requested.
   */
  int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
  {
  	struct dwc3_event_buffer *evt;
  
  	evt = dwc3_alloc_one_event_buffer(dwc, length);
  	if (IS_ERR(evt)) {
  		dev_err(dwc->dev, "can't allocate event buffer\n");
  		return PTR_ERR(evt);
  	}
  	dwc->ev_buf = evt;
  
  	return 0;
  }
  
  /**
   * dwc3_event_buffers_setup - setup our allocated event buffers
   * @dwc: pointer to our controller context structure
   *
   * Returns 0 on success otherwise negative errno.
   */
  int dwc3_event_buffers_setup(struct dwc3 *dwc)
  {
  	struct dwc3_event_buffer	*evt;
  
  	if (dwc->dr_mode == USB_DR_MODE_HOST)
  		return 0;
  
  	evt = dwc->ev_buf;
  	evt->lpos = 0;
  	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
  			lower_32_bits(evt->dma));
  	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
  			upper_32_bits(evt->dma));
  	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
  			DWC3_GEVNTSIZ_SIZE(evt->length));
  	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
  
  	return 0;
  }
  
  void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
  {
  	struct dwc3_event_buffer	*evt;
  
  	evt = dwc->ev_buf;
  
  	evt->lpos = 0;
  
  	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
  	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
  	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
  			| DWC3_GEVNTSIZ_SIZE(0));
  	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
  }
  
  static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
  {
  	u32 size;
  
  	if (dwc->dr_mode == USB_DR_MODE_HOST)
  		return 0;
  
  	if (!dwc->has_hibernation)
  		return 0;
  
  	if (!dwc->nr_scratch)
  		return 0;
  
  	/* Allocate only if scratchbuf is NULL */
  	if (dwc->scratchbuf)
  		return 0;
  
  	size = dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE;
  
  	dwc->scratchbuf = kzalloc(size, GFP_KERNEL);
  
  	if (!dwc->scratchbuf)
  		return -ENOMEM;
  
  	dwc->scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf, size,
  					   DMA_BIDIRECTIONAL);
  	if (dma_mapping_error(dwc->dev, dwc->scratch_addr)) {
  		dev_err(dwc->dev, "failed to map scratch buffer\n");
  		return -EFAULT;
  	}
  
  	return 0;
  }
  
  static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
  {
  	u32 param;
  	int ret;
  
  	if (dwc->dr_mode == USB_DR_MODE_HOST)
  		return 0;
  
  	if (!dwc->has_hibernation)
  		return 0;
  
  	if (!dwc->nr_scratch)
  		return 0;
  
  	 /* should never fall here */
  	if (WARN_ON(!dwc->scratchbuf))
  		return 0;
  
  	param = lower_32_bits(dwc->scratch_addr);
  
  	ret = dwc3_send_gadget_generic_command(dwc,
  			DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
  	if (ret < 0)
  		goto err1;
  
  	param = upper_32_bits(dwc->scratch_addr);
  
  	ret = dwc3_send_gadget_generic_command(dwc,
  			DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
  	if (ret < 0)
  		goto err1;
  
  	return 0;
  
  err1:
  	dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
  			DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
  
  	return ret;
  }
  
  static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
  {
  	if (!dwc->has_hibernation)
  		return;
  
  	if (!dwc->nr_scratch)
  		return;
  
  	 /* should never fall here */
  	if (WARN_ON(!dwc->scratchbuf))
  		return;
  
  	dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
  			DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
  	kfree(dwc->scratchbuf);
  }
  
  static void dwc3_core_num_eps(struct dwc3 *dwc)
  {
  	struct dwc3_hwparams	*parms = &dwc->hwparams;
  
  	dwc->num_eps = DWC3_NUM_EPS(parms);
  }
  
  static void dwc3_cache_hwparams(struct dwc3 *dwc)
  {
  	struct dwc3_hwparams	*parms = &dwc->hwparams;
  
  	parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
  	parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
  	parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
  	parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
  	parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
  	parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
  	parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
  	parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
  	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
  }
  
  static int dwc3_config_soc_bus(struct dwc3 *dwc)
  {
  	int ret;
  
  	/*
  	 * Check if CCI is enabled for USB. Returns true
  	 * if the node has property 'dma-coherent'. Otherwise
  	 * returns false.
  	 */
  	if (of_dma_is_coherent(dwc->dev->of_node)) {
  		u32 reg;
  
  		reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
  		reg |= DWC3_GSBUSCFG0_DATRDREQINFO |
  			DWC3_GSBUSCFG0_DESRDREQINFO |
  			DWC3_GSBUSCFG0_DATWRREQINFO |
  			DWC3_GSBUSCFG0_DESWRREQINFO;
  		dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
  	}
  
  	/*
  	 * This routes the usb dma traffic to go through CCI path instead
  	 * of reaching DDR directly. This traffic routing is needed to
  	 * to make SMMU and CCI work with USB dma.
  	 */
  	if (of_dma_is_coherent(dwc->dev->of_node) || dwc->dev->iommu_group) {
  		ret = dwc3_enable_hw_coherency(dwc->dev);
  		if (ret)
  			return ret;
  	}
  
  	/* Send struct dwc3 to dwc3-of-simple for configuring VBUS
  	 * during suspend/resume
  	 */
  	dwc3_set_simple_data(dwc);
  
  	return 0;
  }
  
  static int dwc3_core_ulpi_init(struct dwc3 *dwc)
  {
  	int intf;
  	int ret = 0;
  
  	intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
  
  	if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
  	    (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
  	     dwc->hsphy_interface &&
  	     !strncmp(dwc->hsphy_interface, "ulpi", 4)))
  		ret = dwc3_ulpi_init(dwc);
  
  	return ret;
  }
  
  /**
   * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
   * @dwc: Pointer to our controller context structure
   *
   * Returns 0 on success. The USB PHY interfaces are configured but not
   * initialized. The PHY interfaces and the PHYs get initialized together with
   * the core in dwc3_core_init.
   */
  static int dwc3_phy_setup(struct dwc3 *dwc)
  {
  	u32 reg;
  
  	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  
  	/*
  	 * Make sure UX_EXIT_PX is cleared as that causes issues with some
  	 * PHYs. Also, this bit is not supposed to be used in normal operation.
  	 */
  	reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
  
  	/*
  	 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
  	 * to '0' during coreConsultant configuration. So default value
  	 * will be '0' when the core is reset. Application needs to set it
  	 * to '1' after the core initialization is completed.
  	 */
  	if (dwc->revision > DWC3_REVISION_194A)
  		reg |= DWC3_GUSB3PIPECTL_SUSPHY;
  
  	if (dwc->u2ss_inp3_quirk)
  		reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
  
  	if (dwc->dis_rxdet_inp3_quirk)
  		reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
  
  	if (dwc->req_p1p2p3_quirk)
  		reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
  
  	if (dwc->del_p1p2p3_quirk)
  		reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
  
  	if (dwc->del_phy_power_chg_quirk)
  		reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
  
  	if (dwc->lfps_filter_quirk)
  		reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
  
  	if (dwc->rx_detect_poll_quirk)
  		reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
  
  	if (dwc->tx_de_emphasis_quirk)
  		reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
  
  	if (dwc->dis_u3_susphy_quirk)
  		reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
  
  	if (dwc->dis_del_phy_power_chg_quirk)
  		reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
  
  	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  
  	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  
  	/* Select the HS PHY interface */
  	switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
  	case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
  		if (dwc->hsphy_interface &&
  				!strncmp(dwc->hsphy_interface, "utmi", 4)) {
  			reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
  			break;
  		} else if (dwc->hsphy_interface &&
  				!strncmp(dwc->hsphy_interface, "ulpi", 4)) {
  			reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
  			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  		} else {
  			/* Relying on default value. */
  			if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
  				break;
  		}
  		/* FALLTHROUGH */
  	case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
  		/* FALLTHROUGH */
  	default:
  		break;
  	}
  
  	switch (dwc->hsphy_mode) {
  	case USBPHY_INTERFACE_MODE_UTMI:
  		reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
  		       DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
  		reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
  		       DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
  		break;
  	case USBPHY_INTERFACE_MODE_UTMIW:
  		reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
  		       DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
  		reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
  		       DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
  		break;
  	default:
  		break;
  	}
  
  	/*
  	 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
  	 * '0' during coreConsultant configuration. So default value will
  	 * be '0' when the core is reset. Application needs to set it to
  	 * '1' after the core initialization is completed.
  	 */
  	if (dwc->revision > DWC3_REVISION_194A)
  		reg |= DWC3_GUSB2PHYCFG_SUSPHY;
  
  	if (dwc->dis_u2_susphy_quirk)
  		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  
  	if (dwc->dis_enblslpm_quirk)
  		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
  
  	if (dwc->dis_u2_freeclk_exists_quirk)
  		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
  
  	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  
  	return 0;
  }
  
  static void dwc3_core_exit(struct dwc3 *dwc)
  {
  	usb_phy_shutdown(dwc->usb2_phy);
  	usb_phy_shutdown(dwc->usb3_phy);
  	phy_exit(dwc->usb2_generic_phy);
  	phy_exit(dwc->usb3_generic_phy);
  
  	usb_phy_set_suspend(dwc->usb2_phy, 1);
  	usb_phy_set_suspend(dwc->usb3_phy, 1);
  	phy_power_off(dwc->usb2_generic_phy);
  	phy_power_off(dwc->usb3_generic_phy);
  	clk_bulk_disable(dwc->num_clks, dwc->clks);
  	clk_bulk_unprepare(dwc->num_clks, dwc->clks);
  	reset_control_assert(dwc->reset);
  }
  
  static bool dwc3_core_is_valid(struct dwc3 *dwc)
  {
  	u32 reg;
  
  	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
  
  	/* This should read as U3 followed by revision number */
  	if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
  		/* Detected DWC_usb3 IP */
  		dwc->revision = reg;
  	} else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
  		/* Detected DWC_usb31 IP */
  		dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
  		dwc->revision |= DWC3_REVISION_IS_DWC31;
  	} else {
  		return false;
  	}
  
  	return true;
  }
  
  static void dwc3_core_setup_global_control(struct dwc3 *dwc)
  {
  	u32 hwparams4 = dwc->hwparams.hwparams4;
  	u32 reg;
  
  	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  
  	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
  	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
  		/**
  		 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
  		 * issue which would cause xHCI compliance tests to fail.
  		 *
  		 * Because of that we cannot enable clock gating on such
  		 * configurations.
  		 *
  		 * Refers to:
  		 *
  		 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
  		 * SOF/ITP Mode Used
  		 */
  		if ((dwc->dr_mode == USB_DR_MODE_HOST ||
  				dwc->dr_mode == USB_DR_MODE_OTG) &&
  				(dwc->revision >= DWC3_REVISION_210A &&
  				dwc->revision <= DWC3_REVISION_250A))
  			reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
  		else
  			reg &= ~DWC3_GCTL_DSBLCLKGTNG;
  		break;
  	case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
  		if (!device_property_read_bool(dwc->dev,
  					       "snps,enable-hibernation")) {
  			dev_dbg(dwc->dev, "Hibernation not enabled\n");
  		} else {
  			/* enable hibernation here */
  			dwc->nr_scratch =
  				DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
  			dwc->has_hibernation = 1;
  		}
  
  		/*
  		 * REVISIT Enabling this bit so that host-mode hibernation
  		 * will work. Device-mode hibernation is not yet implemented.
  		 */
  		reg |= DWC3_GCTL_GBLHIBERNATIONEN;
  		break;
  	default:
  		/* nothing */
  		break;
  	}
  
  	/* check if current dwc3 is on simulation board */
  	if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
  		dev_info(dwc->dev, "Running with FPGA optmizations\n");
  		dwc->is_fpga = true;
  	}
  
  	WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
  			"disable_scramble cannot be used on non-FPGA builds\n");
  
  	if (dwc->disable_scramble_quirk && dwc->is_fpga)
  		reg |= DWC3_GCTL_DISSCRAMBLE;
  	else
  		reg &= ~DWC3_GCTL_DISSCRAMBLE;
  
  	if (dwc->u2exit_lfps_quirk)
  		reg |= DWC3_GCTL_U2EXIT_LFPS;
  
  	/*
  	 * WORKAROUND: DWC3 revisions <1.90a have a bug
  	 * where the device can fail to connect at SuperSpeed
  	 * and falls back to high-speed mode which causes
  	 * the device to enter a Connect/Disconnect loop
  	 */
  	if (dwc->revision < DWC3_REVISION_190A)
  		reg |= DWC3_GCTL_U2RSTECN;
  
  	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  }
  
  static int dwc3_core_get_phy(struct dwc3 *dwc);
  static int dwc3_core_ulpi_init(struct dwc3 *dwc);
  
  /* set global incr burst type configuration registers */
  static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
  {
  	struct device *dev = dwc->dev;
  	/* incrx_mode : for INCR burst type. */
  	bool incrx_mode;
  	/* incrx_size : for size of INCRX burst. */
  	u32 incrx_size;
  	u32 *vals;
  	u32 cfg;
  	int ntype;
  	int ret;
  	int i;
  
  	cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
  
  	/*
  	 * Handle property "snps,incr-burst-type-adjustment".
  	 * Get the number of value from this property:
  	 * result <= 0, means this property is not supported.
  	 * result = 1, means INCRx burst mode supported.
  	 * result > 1, means undefined length burst mode supported.
  	 */
  	ntype = device_property_read_u32_array(dev,
  			"snps,incr-burst-type-adjustment", NULL, 0);
  	if (ntype <= 0)
  		return;
  
  	vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
  	if (!vals) {
  		dev_err(dev, "Error to get memory\n");
  		return;
  	}
  
  	/* Get INCR burst type, and parse it */
  	ret = device_property_read_u32_array(dev,
  			"snps,incr-burst-type-adjustment", vals, ntype);
  	if (ret) {
  		dev_err(dev, "Error to get property\n");
  		return;
  	}
  
  	incrx_size = *vals;
  
  	if (ntype > 1) {
  		/* INCRX (undefined length) burst mode */
  		incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
  		for (i = 1; i < ntype; i++) {
  			if (vals[i] > incrx_size)
  				incrx_size = vals[i];
  		}
  	} else {
  		/* INCRX burst mode */
  		incrx_mode = INCRX_BURST_MODE;
  	}
  
  	/* Enable Undefined Length INCR Burst and Enable INCRx Burst */
  	cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
  	if (incrx_mode)
  		cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
  	switch (incrx_size) {
  	case 256:
  		cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
  		break;
  	case 128:
  		cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
  		break;
  	case 64:
  		cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
  		break;
  	case 32:
  		cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
  		break;
  	case 16:
  		cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
  		break;
  	case 8:
  		cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
  		break;
  	case 4:
  		cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
  		break;
  	case 1:
  		break;
  	default:
  		dev_err(dev, "Invalid property\n");
  		break;
  	}
  
  	dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
  }
  
  /**
   * dwc3_core_init - Low-level initialization of DWC3 Core
   * @dwc: Pointer to our controller context structure
   *
   * Returns 0 on success otherwise negative errno.
   */
  int dwc3_core_init(struct dwc3 *dwc)
  {
  	u32			reg;
  	int			ret;
  
  	if (!dwc3_core_is_valid(dwc)) {
  		dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
  		ret = -ENODEV;
  		goto err0;
  	}
  
  	/*
  	 * Write Linux Version Code to our GUID register so it's easy to figure
  	 * out which kernel version a bug was found.
  	 */
  	dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
  
  	/* Handle USB2.0-only core configuration */
  	if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
  			DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
  		if (dwc->maximum_speed == USB_SPEED_SUPER)
  			dwc->maximum_speed = USB_SPEED_HIGH;
  	}
  
  	ret = dwc3_phy_setup(dwc);
  	if (ret)
  		goto err0;
  
  	if (!dwc->ulpi_ready) {
  		ret = dwc3_core_ulpi_init(dwc);
  		if (ret)
  			goto err0;
  		dwc->ulpi_ready = true;
  	}
  
  	if (!dwc->phys_ready) {
  		ret = dwc3_core_get_phy(dwc);
  		if (ret)
  			goto err0a;
  		dwc->phys_ready = true;
  	}
  
  	ret = dwc3_core_soft_reset(dwc);
  	if (ret)
  		goto err0a;
  
  	dwc3_core_setup_global_control(dwc);
  	dwc3_core_num_eps(dwc);
  
  	if (dwc->scratchbuf == NULL) {
  		ret = dwc3_alloc_scratch_buffers(dwc);
  		if (ret) {
  			dev_err(dwc->dev,
  				"Not enough memory for scratch buffers\n");
  			goto err1;
  		}
  	}
  
  	ret = dwc3_setup_scratch_buffers(dwc);
  	if (ret) {
  		dev_err(dwc->dev, "Failed to setup scratch buffers: %d\n", ret);
  		goto err1;
  	}
  
  	/* Adjust Frame Length */
  	dwc3_frame_length_adjustment(dwc);
  
  	dwc3_set_incr_burst_type(dwc);
  
  	ret = dwc3_config_soc_bus(dwc);
  	if (ret)
  		goto err1;
  
  	usb_phy_set_suspend(dwc->usb2_phy, 0);
  	usb_phy_set_suspend(dwc->usb3_phy, 0);
  	ret = phy_power_on(dwc->usb2_generic_phy);
  	if (ret < 0)
  		goto err2;
  
  	ret = phy_power_on(dwc->usb3_generic_phy);
  	if (ret < 0)
  		goto err3;
  
  	ret = dwc3_event_buffers_setup(dwc);
  	if (ret) {
  		dev_err(dwc->dev, "failed to setup event buffers\n");
  		goto err4;
  	}
  
  	switch (dwc->dr_mode) {
  	case USB_DR_MODE_PERIPHERAL:
  		dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  		break;
  	case USB_DR_MODE_HOST:
  		dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
  		break;
  	case USB_DR_MODE_OTG:
  		dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_OTG);
  		break;
  	default:
  		dev_warn(dwc->dev, "Unsupported mode %d\n", dwc->dr_mode);
  		break;
  	}
  
  	/*
  	 * ENDXFER polling is available on version 3.10a and later of
  	 * the DWC_usb3 controller. It is NOT available in the
  	 * DWC_usb31 controller.
  	 */
  	if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
  		reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
  		reg |= DWC3_GUCTL2_RST_ACTBITLATER;
  		dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
  	}
  
  	/* When configured in HOST mode, after issuing U3/L2 exit controller
  	 * fails to send proper CRC checksum in CRC5 feild. Because of this
  	 * behaviour Transaction Error is generated, resulting in reset and
  	 * re-enumeration of usb device attached. Enabling bit 10 of GUCTL1
  	 * will correct this problem
  	 */
  	if (dwc->enable_guctl1_resume_quirk) {
  		reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
  		reg |= DWC3_GUCTL1_RESUME_QUIRK;
  		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
  	}
  
  	/* SNPS controller when configureed in HOST mode maintains Inter Packet
  	 * Delay (IPD) of ~380ns which works with most of the super-speed hubs
  	 * except VIA-LAB hubs. When IPD is ~380ns HOST controller fails to
  	 * enumerate FS/LS devices when connected behind VIA-LAB hubs.
  	 * Enabling bit 9 of GUCTL1 enables the workaround in HW to reduce the
  	 * ULPI clock latency by 1 cycle, thus reducing the IPD (~360ns) and
  	 * making controller enumerate FS/LS devices connected behind VIA-LAB.
  	 */
  	if (dwc->enable_guctl1_ipd_quirk) {
  		reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
  		reg |= DWC3_GUCTL1_IPD_QUIRK;
  		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
  	}
  
  	if (dwc->revision >= DWC3_REVISION_250A) {
  		reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
  
  		/*
  		 * Enable hardware control of sending remote wakeup
  		 * in HS when the device is in the L1 state.
  		 */
  		if (dwc->revision >= DWC3_REVISION_290A)
  			reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
  
  		if (dwc->dis_tx_ipgap_linecheck_quirk)
  			reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
  
  		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
  	}
  
  	if (dwc->dr_mode == USB_DR_MODE_HOST ||
  	    dwc->dr_mode == USB_DR_MODE_OTG) {
  		reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
  
  		/*
  		 * Enable Auto retry Feature to make the controller operating in
  		 * Host mode on seeing transaction errors(CRC errors or internal
  		 * overrun scenerios) on IN transfers to reply to the device
  		 * with a non-terminating retry ACK (i.e, an ACK transcation
  		 * packet with Retry=1 & Nump != 0)
  		 */
  		reg |= DWC3_GUCTL_HSTINAUTORETRY;
  
  		dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
  	}
  
  	/*
  	 * Must config both number of packets and max burst settings to enable
  	 * RX and/or TX threshold.
  	 */
  	if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
  		u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
  		u8 rx_maxburst = dwc->rx_max_burst_prd;
  		u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
  		u8 tx_maxburst = dwc->tx_max_burst_prd;
  
  		if (rx_thr_num && rx_maxburst) {
  			reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
  			reg |= DWC31_RXTHRNUMPKTSEL_PRD;
  
  			reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
  			reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
  
  			reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
  			reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
  
  			dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
  		}
  
  		if (tx_thr_num && tx_maxburst) {
  			reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
  			reg |= DWC31_TXTHRNUMPKTSEL_PRD;
  
  			reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
  			reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
  
  			reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
  			reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
  
  			dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
  		}
  	}
  
  	return 0;
  
  err4:
  	phy_power_off(dwc->usb3_generic_phy);
  
  err3:
  	phy_power_off(dwc->usb2_generic_phy);
  
  err2:
  	usb_phy_set_suspend(dwc->usb2_phy, 1);
  	usb_phy_set_suspend(dwc->usb3_phy, 1);
  
  err1:
  	usb_phy_shutdown(dwc->usb2_phy);
  	usb_phy_shutdown(dwc->usb3_phy);
  	phy_exit(dwc->usb2_generic_phy);
  	phy_exit(dwc->usb3_generic_phy);
  
  err0a:
  	dwc3_ulpi_exit(dwc);
  
  err0:
  	return ret;
  }
  
  static int dwc3_core_get_phy(struct dwc3 *dwc)
  {
  	struct device		*dev = dwc->dev;
  	struct device_node	*node = dev->of_node;
  	int ret;
  
  	if (node) {
  		dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
  		dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
  	} else {
  		dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
  		dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
  	}
  
  	if (IS_ERR(dwc->usb2_phy)) {
  		ret = PTR_ERR(dwc->usb2_phy);
  		if (ret == -ENXIO || ret == -ENODEV) {
  			dwc->usb2_phy = NULL;
  		} else if (ret == -EPROBE_DEFER) {
  			return ret;
  		} else {
  			dev_err(dev, "no usb2 phy configured\n");
  			return ret;
  		}
  	}
  
  	if (IS_ERR(dwc->usb3_phy)) {
  		ret = PTR_ERR(dwc->usb3_phy);
  		if (ret == -ENXIO || ret == -ENODEV) {
  			dwc->usb3_phy = NULL;
  		} else if (ret == -EPROBE_DEFER) {
  			return ret;
  		} else {
  			dev_err(dev, "no usb3 phy configured\n");
  			return ret;
  		}
  	}
  
  	dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
  	if (IS_ERR(dwc->usb2_generic_phy)) {
  		ret = PTR_ERR(dwc->usb2_generic_phy);
  		if (ret == -ENOSYS || ret == -ENODEV) {
  			dwc->usb2_generic_phy = NULL;
  		} else if (ret == -EPROBE_DEFER) {
  			return ret;
  		} else {
  			dev_err(dev, "no usb2 phy configured\n");
  			return ret;
  		}
  	}
  
  	dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
  	if (IS_ERR(dwc->usb3_generic_phy)) {
  		ret = PTR_ERR(dwc->usb3_generic_phy);
  		if (ret == -ENOSYS || ret == -ENODEV) {
  			dwc->usb3_generic_phy = NULL;
  		} else if (ret == -EPROBE_DEFER) {
  			return ret;
  		} else {
  			dev_err(dev, "no usb3 phy configured\n");
  			return ret;
  		}
  	}
  
  	return 0;
  }
  
  static int dwc3_core_init_mode(struct dwc3 *dwc)
  {
  	struct device *dev = dwc->dev;
  	int ret;
  
  	switch (dwc->dr_mode) {
  	case USB_DR_MODE_PERIPHERAL:
  		dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  
  		if (dwc->usb2_phy)
  			otg_set_vbus(dwc->usb2_phy->otg, false);
  		phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
  		phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
  
  		ret = dwc3_gadget_init(dwc);
  		if (ret) {
  			if (ret != -EPROBE_DEFER)
  				dev_err(dev, "failed to initialize gadget\n");
  			return ret;
  		}
  		break;
  	case USB_DR_MODE_HOST:
  		dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
  
  		if (dwc->usb2_phy)
  			otg_set_vbus(dwc->usb2_phy->otg, true);
  		phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
  		phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
  
  		ret = dwc3_host_init(dwc);
  		if (ret) {
  			if (ret != -EPROBE_DEFER)
  				dev_err(dev, "failed to initialize host\n");
  			return ret;
  		}
  		phy_calibrate(dwc->usb2_generic_phy);
  		break;
  	case USB_DR_MODE_OTG:
  		INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
  		ret = dwc3_drd_init(dwc);
  		if (ret) {
  			if (ret != -EPROBE_DEFER)
  				dev_err(dev, "failed to initialize dual-role\n");
  			return ret;
  		}
  
  #if IS_ENABLED(CONFIG_USB_DWC3_OTG)
  		dwc->current_dr_role = 0;
  		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
  #endif
  		break;
  	default:
  		dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
  		return -EINVAL;
  	}
  
  	return 0;
  }
  
  static void dwc3_core_exit_mode(struct dwc3 *dwc)
  {
  	switch (dwc->dr_mode) {
  	case USB_DR_MODE_PERIPHERAL:
  		dwc3_gadget_exit(dwc);
  		break;
  	case USB_DR_MODE_HOST:
  		dwc3_host_exit(dwc);
  		break;
  	case USB_DR_MODE_OTG:
  		dwc3_drd_exit(dwc);
  		break;
  	default:
  		/* do nothing */
  		break;
  	}
  }
  
  static void dwc3_get_properties(struct dwc3 *dwc)
  {
  	struct device		*dev = dwc->dev;
  	u8			lpm_nyet_threshold;
  	u8			tx_de_emphasis;
  	u8			hird_threshold;
  	u8			rx_thr_num_pkt_prd;
  	u8			rx_max_burst_prd;
  	u8			tx_thr_num_pkt_prd;
  	u8			tx_max_burst_prd;
  
  	/* default to highest possible threshold */
  	lpm_nyet_threshold = 0xff;
  
  	/* default to -3.5dB de-emphasis */
  	tx_de_emphasis = 1;
  
  	/*
  	 * default to assert utmi_sleep_n and use maximum allowed HIRD
  	 * threshold value of 0b1100
  	 */
  	hird_threshold = 12;
  
  	dwc->maximum_speed = usb_get_maximum_speed(dev);
  	dwc->dr_mode = usb_get_dr_mode(dev);
  	dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
  
  	dwc->sysdev_is_parent = device_property_read_bool(dev,
  				"linux,sysdev_is_parent");
  	if (dwc->sysdev_is_parent)
  		dwc->sysdev = dwc->dev->parent;
  	else
  		dwc->sysdev = dwc->dev;
  
  	dwc->has_lpm_erratum = device_property_read_bool(dev,
  				"snps,has-lpm-erratum");
  	device_property_read_u8(dev, "snps,lpm-nyet-threshold",
  				&lpm_nyet_threshold);
  	dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
  				"snps,is-utmi-l1-suspend");
  	device_property_read_u8(dev, "snps,hird-threshold",
  				&hird_threshold);
  	dwc->usb3_lpm_capable = device_property_read_bool(dev,
  				"snps,usb3_lpm_capable");
  	device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
  				&rx_thr_num_pkt_prd);
  	device_property_read_u8(dev, "snps,rx-max-burst-prd",
  				&rx_max_burst_prd);
  	device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
  				&tx_thr_num_pkt_prd);
  	device_property_read_u8(dev, "snps,tx-max-burst-prd",
  				&tx_max_burst_prd);
  
  	dwc->disable_scramble_quirk = device_property_read_bool(dev,
  				"snps,disable_scramble_quirk");
  	dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
  				"snps,u2exit_lfps_quirk");
  	dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
  				"snps,u2ss_inp3_quirk");
  	dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
  				"snps,req_p1p2p3_quirk");
  	dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
  				"snps,del_p1p2p3_quirk");
  	dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
  				"snps,del_phy_power_chg_quirk");
  	dwc->lfps_filter_quirk = device_property_read_bool(dev,
  				"snps,lfps_filter_quirk");
  	dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
  				"snps,rx_detect_poll_quirk");
  	dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
  				"snps,dis_u3_susphy_quirk");
  	dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
  				"snps,dis_u2_susphy_quirk");
  	dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
  				"snps,dis_enblslpm_quirk");
  	dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
  				"snps,dis_rxdet_inp3_quirk");
  	dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
  				"snps,dis-u2-freeclk-exists-quirk");
  	dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
  				"snps,dis-del-phy-power-chg-quirk");
  	dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
  				"snps,dis-tx-ipgap-linecheck-quirk");
  
  	dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
  				"snps,tx_de_emphasis_quirk");
  	device_property_read_u8(dev, "snps,tx_de_emphasis",
  				&tx_de_emphasis);
  	device_property_read_string(dev, "snps,hsphy_interface",
  				    &dwc->hsphy_interface);
  	device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
  				 &dwc->fladj);
  
  	dwc->refclk_fladj = device_property_read_bool(dev,
  						      "snps,refclk_fladj");
  	dwc->enable_guctl1_resume_quirk = device_property_read_bool(dev,
  				"snps,enable_guctl1_resume_quirk");
  	dwc->enable_guctl1_ipd_quirk = device_property_read_bool(dev,
  				"snps,enable_guctl1_ipd_quirk");
  	dwc->dis_metastability_quirk = device_property_read_bool(dev,
  				"snps,dis_metastability_quirk");
  
  	dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  	dwc->tx_de_emphasis = tx_de_emphasis;
  
  	dwc->hird_threshold = hird_threshold
  		| (dwc->is_utmi_l1_suspend << 4);
  
  	/* Check if extra quirks to be added */
  	dwc3_simple_check_quirks(dwc);
  
  	dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
  	dwc->rx_max_burst_prd = rx_max_burst_prd;
  
  	dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
  	dwc->tx_max_burst_prd = tx_max_burst_prd;
  
  	dwc->imod_interval = 0;
  }
  
  /* check whether the core supports IMOD */
  bool dwc3_has_imod(struct dwc3 *dwc)
  {
  	return ((dwc3_is_usb3(dwc) &&
  		 dwc->revision >= DWC3_REVISION_300A) ||
  		(dwc3_is_usb31(dwc) &&
  		 dwc->revision >= DWC3_USB31_REVISION_120A));
  }
  
  static void dwc3_check_params(struct dwc3 *dwc)
  {
  	struct device *dev = dwc->dev;
  
  	/* Check for proper value of imod_interval */
  	if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
  		dev_warn(dwc->dev, "Interrupt moderation not supported\n");
  		dwc->imod_interval = 0;
  	}
  
  	/*
  	 * Workaround for STAR 9000961433 which affects only version
  	 * 3.00a of the DWC_usb3 core. This prevents the controller
  	 * interrupt from being masked while handling events. IMOD
  	 * allows us to work around this issue. Enable it for the
  	 * affected version.
  	 */
  	if (!dwc->imod_interval &&
  	    (dwc->revision == DWC3_REVISION_300A))
  		dwc->imod_interval = 1;
  
  	/* Check the maximum_speed parameter */
  	switch (dwc->maximum_speed) {
  	case USB_SPEED_LOW:
  	case USB_SPEED_FULL:
  	case USB_SPEED_HIGH:
  	case USB_SPEED_SUPER:
  	case USB_SPEED_SUPER_PLUS:
  		break;
  	default:
  		dev_err(dev, "invalid maximum_speed parameter %d\n",
  			dwc->maximum_speed);
  		/* fall through */
  	case USB_SPEED_UNKNOWN:
  		/* default to superspeed */
  		dwc->maximum_speed = USB_SPEED_SUPER;
  
  		/*
  		 * default to superspeed plus if we are capable.
  		 */
  		if (dwc3_is_usb31(dwc) &&
  		    (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
  		     DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
  			dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
  
  		break;
  	}
  }
  
  static int dwc3_probe(struct platform_device *pdev)
  {
  	struct device		*dev = &pdev->dev;
  	struct resource		*res, dwc_res;
  	struct dwc3		*dwc;
  	int			ret;
  	u32			mdwidth;
  	void __iomem		*regs;
  
  	dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
  	if (!dwc)
  		return -ENOMEM;
  
  	dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks),
  				 GFP_KERNEL);
  	if (!dwc->clks)
  		return -ENOMEM;
  
  	dwc->dev = dev;
  
  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  	if (!res) {
  		dev_err(dev, "missing memory resource\n");
  		return -ENODEV;
  	}
  
  	dwc->xhci_resources[0].start = res->start;
  	dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
  					DWC3_XHCI_REGS_END;
  	dwc->xhci_resources[0].flags = res->flags;
  	dwc->xhci_resources[0].name = res->name;
  
  	/*
  	 * Request memory region but exclude xHCI regs,
  	 * since it will be requested by the xhci-plat driver.
  	 */
  	dwc_res = *res;
  	dwc_res.start += DWC3_GLOBALS_REGS_START;
  
  	regs = devm_ioremap_resource(dev, &dwc_res);
  	if (IS_ERR(regs))
  		return PTR_ERR(regs);
  
  	dwc->regs	= regs;
  	dwc->regs_size	= resource_size(&dwc_res);
  
  	dwc3_get_properties(dwc);
  
  	dwc->reset = devm_reset_control_get_optional_shared(dev, NULL);
  	if (IS_ERR(dwc->reset))
  		return PTR_ERR(dwc->reset);
  
  	if (dev->of_node) {
  		dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
  
  		ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks);
  		if (ret == -EPROBE_DEFER)
  			return ret;
  		/*
  		 * Clocks are optional, but new DT platforms should support all
  		 * clocks as required by the DT-binding.
  		 */
  		if (ret)
  			dwc->num_clks = 0;
  	}
  
  	ret = reset_control_deassert(dwc->reset);
  	if (ret)
  		goto put_clks;
  
  	ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
  	if (ret)
  		goto assert_reset;
  
  	ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
  	if (ret)
  		goto unprepare_clks;
  
  	platform_set_drvdata(pdev, dwc);
  	dwc3_cache_hwparams(dwc);
  
  	spin_lock_init(&dwc->lock);
  
  	/* Set dma coherent mask to DMA BUS data width */
  	mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
  	dev_dbg(dev, "Enabling %d-bit DMA addresses.\n", mdwidth);
  	dma_set_coherent_mask(dev, DMA_BIT_MASK(mdwidth));
  
  	pm_runtime_set_active(dev);
  	pm_runtime_use_autosuspend(dev);
  	pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
  	pm_runtime_enable(dev);
  	ret = pm_runtime_get_sync(dev);
  	if (ret < 0)
  		goto err1;
  
  	pm_runtime_forbid(dev);
  
  	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
  	if (ret) {
  		dev_err(dwc->dev, "failed to allocate event buffers\n");
  		ret = -ENOMEM;
  		goto err2;
  	}
  
  	ret = dwc3_get_dr_mode(dwc);
  	if (ret)
  		goto err3;
  
  	ret = dwc3_core_init(dwc);
  	if (ret) {
  		dev_err(dev, "failed to initialize core\n");
  		goto err4;
  	}
  
  	dwc3_check_params(dwc);
  
  	ret = dwc3_core_init_mode(dwc);
  	if (ret)
  		goto err5;
  
  	dwc3_debugfs_init(dwc);
  	pm_runtime_put(dev);
  
  	return 0;
  
  err5:
  	dwc3_event_buffers_cleanup(dwc);
  
  err4:
  	dwc3_free_scratch_buffers(dwc);
  
  err3:
  	dwc3_free_event_buffers(dwc);
  
  err2:
  	pm_runtime_allow(&pdev->dev);
  
  err1:
  	pm_runtime_put_sync(&pdev->dev);
  	pm_runtime_disable(&pdev->dev);
  
  	clk_bulk_disable(dwc->num_clks, dwc->clks);
  unprepare_clks:
  	clk_bulk_unprepare(dwc->num_clks, dwc->clks);
  assert_reset:
  	reset_control_assert(dwc->reset);
  put_clks:
  	clk_bulk_put(dwc->num_clks, dwc->clks);
  
  	return ret;
  }
  
  static int dwc3_remove(struct platform_device *pdev)
  {
  	struct dwc3	*dwc = platform_get_drvdata(pdev);
  
  	pm_runtime_get_sync(&pdev->dev);
  
  	dwc3_debugfs_exit(dwc);
  	dwc3_core_exit_mode(dwc);
  
  	dwc3_event_buffers_cleanup(dwc);
  	dwc3_core_exit(dwc);
  	dwc3_ulpi_exit(dwc);
  
  	pm_runtime_put_sync(&pdev->dev);
  	pm_runtime_allow(&pdev->dev);
  	pm_runtime_disable(&pdev->dev);
  
  	dwc3_free_event_buffers(dwc);
  	dwc3_free_scratch_buffers(dwc);
  	clk_bulk_put(dwc->num_clks, dwc->clks);
  
  	return 0;
  }
  
  #ifdef CONFIG_PM
  static int dwc3_core_init_for_resume(struct dwc3 *dwc)
  {
  	int ret;
  
  	ret = reset_control_deassert(dwc->reset);
  	if (ret)
  		return ret;
  
  	ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
  	if (ret)
  		goto assert_reset;
  
  	ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
  	if (ret)
  		goto unprepare_clks;
  
  	ret = dwc3_core_init(dwc);
  	if (ret)
  		goto disable_clks;
  
  	return 0;
  
  disable_clks:
  	clk_bulk_disable(dwc->num_clks, dwc->clks);
  unprepare_clks:
  	clk_bulk_unprepare(dwc->num_clks, dwc->clks);
  assert_reset:
  	reset_control_assert(dwc->reset);
  
  	return ret;
  }
  
  static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
  {
  	unsigned long	flags;
  	u32 reg;
  
  	switch (dwc->current_dr_role) {
  	case DWC3_GCTL_PRTCAP_DEVICE:
  		spin_lock_irqsave(&dwc->lock, flags);
  		dwc3_gadget_suspend(dwc);
  		spin_unlock_irqrestore(&dwc->lock, flags);
  		dwc3_core_exit(dwc);
  		break;
  	case DWC3_GCTL_PRTCAP_HOST:
  		if (!PMSG_IS_AUTO(msg)) {
  			dwc3_core_exit(dwc);
  			break;
  		}
  
  		/* Let controller to suspend HSPHY before PHY driver suspends */
  		if (dwc->dis_u2_susphy_quirk ||
  		    dwc->dis_enblslpm_quirk) {
  			reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  			reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
  				DWC3_GUSB2PHYCFG_SUSPHY;
  			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  
  			/* Give some time for USB2 PHY to suspend */
  			usleep_range(5000, 6000);
  		}
  
  		phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
  		phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
  		break;
  	case DWC3_GCTL_PRTCAP_OTG:
  		/* do nothing during runtime_suspend */
  		if (PMSG_IS_AUTO(msg))
  			break;
  
  		if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
  			spin_lock_irqsave(&dwc->lock, flags);
  			dwc3_gadget_suspend(dwc);
  			spin_unlock_irqrestore(&dwc->lock, flags);
  		}
  
  		dwc3_otg_exit(dwc);
  		dwc3_core_exit(dwc);
  		break;
  	default:
  		/* do nothing */
  		break;
  	}
  
  	dwc3_event_buffers_cleanup(dwc);
  
  	/* Put the core into D3 state */
  	dwc3_set_usb_core_power(dwc, false);
  
  	/*
  	 * To avoid reinit of phy during resume, prevent calling the
  	 * dwc3_core_exit() when in D3 state
  	 */
  	if (!dwc->is_d3)
  		dwc3_core_exit(dwc);
  
  	return 0;
  }
  
  static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
  {
  	unsigned long	flags;
  	int		ret;
  	u32		reg;
  
  	/* Bring core to D0 state */
  	dwc3_set_usb_core_power(dwc, true);
  
  	ret = dwc3_core_init(dwc);
  	if (ret)
  		return ret;
  
  	switch (dwc->current_dr_role) {
  	case DWC3_GCTL_PRTCAP_DEVICE:
  		ret = dwc3_core_init_for_resume(dwc);
  		if (ret)
  			return ret;
  
  		dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  		spin_lock_irqsave(&dwc->lock, flags);
  		dwc3_gadget_resume(dwc);
  		spin_unlock_irqrestore(&dwc->lock, flags);
  		break;
  	case DWC3_GCTL_PRTCAP_HOST:
  		if (!PMSG_IS_AUTO(msg)) {
  			ret = dwc3_core_init_for_resume(dwc);
  			if (ret)
  				return ret;
  			dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
  			break;
  		}
  		/* Restore GUSB2PHYCFG bits that were modified in suspend */
  		reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  		if (dwc->dis_u2_susphy_quirk)
  			reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  
  		if (dwc->dis_enblslpm_quirk)
  			reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
  
  		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  
  		phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
  		phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
  		break;
  	case DWC3_GCTL_PRTCAP_OTG:
  		/* nothing to do on runtime_resume */
  		if (PMSG_IS_AUTO(msg))
  			break;
  
  		ret = dwc3_core_init(dwc);
  		if (ret)
  			return ret;
  
  		dwc3_set_prtcap(dwc, dwc->current_dr_role);
  
  		dwc3_otg_init(dwc);
  		if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
  			dwc3_otg_host_init(dwc);
  		} else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
  			spin_lock_irqsave(&dwc->lock, flags);
  			dwc3_gadget_resume(dwc);
  			spin_unlock_irqrestore(&dwc->lock, flags);
  		}
  
  		break;
  	default:
  		/* do nothing */
  		break;
  	}
  
  	return 0;
  }
  
  static int dwc3_runtime_checks(struct dwc3 *dwc)
  {
  	switch (dwc->current_dr_role) {
  	case DWC3_GCTL_PRTCAP_DEVICE:
  		if (dwc->connected)
  			return -EBUSY;
  		break;
  	case DWC3_GCTL_PRTCAP_HOST:
  	default:
  		/* do nothing */
  		break;
  	}
  
  	return 0;
  }
  
  static int dwc3_runtime_suspend(struct device *dev)
  {
  	struct dwc3     *dwc = dev_get_drvdata(dev);
  	int		ret;
  
  	if (dwc3_runtime_checks(dwc))
  		return -EBUSY;
  
  	ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
  	if (ret)
  		return ret;
  
  	device_init_wakeup(dev, true);
  
  	return 0;
  }
  
  static int dwc3_runtime_resume(struct device *dev)
  {
  	struct dwc3     *dwc = dev_get_drvdata(dev);
  	int		ret;
  
  	device_init_wakeup(dev, false);
  
  	ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
  	if (ret)
  		return ret;
  
  	switch (dwc->current_dr_role) {
  	case DWC3_GCTL_PRTCAP_DEVICE:
  		dwc3_gadget_process_pending_events(dwc);
  		break;
  	case DWC3_GCTL_PRTCAP_HOST:
  	default:
  		/* do nothing */
  		break;
  	}
  
  	pm_runtime_mark_last_busy(dev);
  
  	return 0;
  }
  
  static int dwc3_runtime_idle(struct device *dev)
  {
  	struct dwc3     *dwc = dev_get_drvdata(dev);
  
  	switch (dwc->current_dr_role) {
  	case DWC3_GCTL_PRTCAP_DEVICE:
  		if (dwc3_runtime_checks(dwc))
  			return -EBUSY;
  		break;
  	case DWC3_GCTL_PRTCAP_HOST:
  	default:
  		/* do nothing */
  		break;
  	}
  
  	pm_runtime_mark_last_busy(dev);
  	pm_runtime_autosuspend(dev);
  
  	return 0;
  }
  #endif /* CONFIG_PM */
  
  #ifdef CONFIG_PM_SLEEP
  static int dwc3_suspend(struct device *dev)
  {
  	struct dwc3	*dwc = dev_get_drvdata(dev);
  	int		ret;
  
  	ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
  	if (ret)
  		return ret;
  
  	pinctrl_pm_select_sleep_state(dev);
  
  	return 0;
  }
  
  static int dwc3_resume(struct device *dev)
  {
  	struct dwc3	*dwc = dev_get_drvdata(dev);
  	int		ret;
  
  	pinctrl_pm_select_default_state(dev);
  
  	ret = dwc3_resume_common(dwc, PMSG_RESUME);
  	if (ret)
  		return ret;
  
  	pm_runtime_disable(dev);
  	pm_runtime_set_active(dev);
  	pm_runtime_enable(dev);
  
  	return 0;
  }
  #endif /* CONFIG_PM_SLEEP */
  
  static const struct dev_pm_ops dwc3_dev_pm_ops = {
  	SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
  	SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
  			dwc3_runtime_idle)
  };
  
  #ifdef CONFIG_OF
  static const struct of_device_id of_dwc3_match[] = {
  	{
  		.compatible = "snps,dwc3"
  	},
  	{
  		.compatible = "synopsys,dwc3"
  	},
  	{ },
  };
  MODULE_DEVICE_TABLE(of, of_dwc3_match);
  #endif
  
  #ifdef CONFIG_ACPI
  
  #define ACPI_ID_INTEL_BSW	"808622B7"
  
  static const struct acpi_device_id dwc3_acpi_match[] = {
  	{ ACPI_ID_INTEL_BSW, 0 },
  	{ },
  };
  MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
  #endif
  
  static struct platform_driver dwc3_driver = {
  	.probe		= dwc3_probe,
  	.remove		= dwc3_remove,
  	.driver		= {
  		.name	= "dwc3",
  		.of_match_table	= of_match_ptr(of_dwc3_match),
  		.acpi_match_table = ACPI_PTR(dwc3_acpi_match),
  		.pm	= &dwc3_dev_pm_ops,
  	},
  };
  
  module_platform_driver(dwc3_driver);
  
  MODULE_ALIAS("platform:dwc3");
  MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  MODULE_LICENSE("GPL v2");
  MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
  