text: /*
   *         
   * 
   * 
   * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file.
   * 
   * Copyright 2007-2020 Broadcom Inc. All rights reserved.
   *         
   *     
   * DO NOT EDIT THIS FILE!
   */
  
  #ifndef _TSCO_H__H_
  #define _TSCO_H__H_
  
  #include <phymod/phymod_definitions.h>
  /*Initialize phymod module*/
  int tsco_core_identify(const phymod_core_access_t* core, uint32_t core_id, uint32_t* is_identified);
  
  /*Retrive core information*/
  int tsco_core_info_get(const phymod_core_access_t* core, phymod_core_info_t* info);
  
  /*Set\get lane mapping*/
  int tsco_core_lane_map_set(const phymod_core_access_t* core, const phymod_lane_map_t* lane_map);
  int tsco_core_lane_map_get(const phymod_core_access_t* core, phymod_lane_map_t* lane_map);
  
  /*Set\get firmware operation mode*/
  int tsco_phy_firmware_lane_config_set(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t fw_lane_config);
  int tsco_phy_firmware_lane_config_get(const phymod_phy_access_t* phy, phymod_firmware_lane_config_t* fw_lane_config);
  
  /*Set phy polarity*/
  int tsco_phy_polarity_set(const phymod_phy_access_t* phy, const phymod_polarity_t* polarity);
  int tsco_phy_polarity_get(const phymod_phy_access_t* phy, phymod_polarity_t* polarity);
  
  /*Set\Get TX Parameters*/
  int tsco_phy_tx_set(const phymod_phy_access_t* phy, const phymod_tx_t* tx);
  int tsco_phy_tx_get(const phymod_phy_access_t* phy, phymod_tx_t* tx);
  
  /*TX transmission control*/
  int tsco_phy_tx_lane_control_set(const phymod_phy_access_t* phy, phymod_phy_tx_lane_control_t tx_control);
  int tsco_phy_tx_lane_control_get(const phymod_phy_access_t* phy, phymod_phy_tx_lane_control_t* tx_control);
  
  /*Rx control*/
  int tsco_phy_rx_lane_control_set(const phymod_phy_access_t* phy, phymod_phy_rx_lane_control_t rx_control);
  int tsco_phy_rx_lane_control_get(const phymod_phy_access_t* phy, phymod_phy_rx_lane_control_t* rx_control);
  
  /*Set\Get CL72*/
  int tsco_phy_cl72_set(const phymod_phy_access_t* phy, uint32_t cl72_en);
  int tsco_phy_cl72_get(const phymod_phy_access_t* phy, uint32_t* cl72_en);
  
  /*Get CL72 status*/
  int tsco_phy_cl72_status_get(const phymod_phy_access_t* phy, phymod_cl72_status_t* status);
  
  /*Set\Get autoneg*/
  int tsco_phy_autoneg_set(const phymod_phy_access_t* phy, const phymod_autoneg_control_t* an);
  int tsco_phy_autoneg_get(const phymod_phy_access_t* phy, phymod_autoneg_control_t* an, uint32_t* an_done);
  
  /*Get Autoneg status*/
  int tsco_phy_autoneg_status_get(const phymod_phy_access_t* phy, phymod_autoneg_status_t* status);
  
  /*Core Initialization*/
  int tsco_core_init(const phymod_core_access_t* core, const phymod_core_init_config_t* init_config, const phymod_core_status_t* core_status);
  
  /*Phy Initialization*/
  int tsco_phy_init(const phymod_phy_access_t* phy, const phymod_phy_init_config_t* init_config);
  
  /*Set\get loopback mode*/
  int tsco_phy_loopback_set(const phymod_phy_access_t* phy, phymod_loopback_mode_t loopback, uint32_t enable);
  int tsco_phy_loopback_get(const phymod_phy_access_t* phy, phymod_loopback_mode_t loopback, uint32_t* enable);
  
  /*Get link up status indication*/
  int tsco_phy_link_status_get(const phymod_phy_access_t* phy, uint32_t* link_status);
  
  /*Read phymod register*/
  int tsco_phy_reg_read(const phymod_phy_access_t* phy, uint32_t reg_addr, uint32_t* val);
  
  /*Write phymod register*/
  int tsco_phy_reg_write(const phymod_phy_access_t* phy, uint32_t reg_addr, uint32_t val);
  
  /*Set/Get timesync enable*/
  int tsco_timesync_enable_set(const phymod_phy_access_t* phy, uint32_t flags, uint32_t enable);
  int tsco_timesync_enable_get(const phymod_phy_access_t* phy, uint32_t flags, uint32_t* enable);
  
  /*Set/Get timesync ts_offset*/
  int tsco_timesync_offset_set(const phymod_core_access_t* core, uint32_t ts_offset);
  
  /*Set timesync adjust*/
  int tsco_timesync_adjust_set(const phymod_phy_access_t* phy, uint32_t flags, phymod_timesync_compensation_mode_t ts_am_norm_mode);
  
  /*port enable set*/
  int tsco_port_enable_set(const phymod_phy_access_t* phy, uint32_t enable);
  int tsco_port_enable_get(const phymod_phy_access_t* phy, uint32_t* enable);
  
  /*Set the interface mode, speed and other configuration related to interface.*/
  int tsco_phy_speed_config_set(const phymod_phy_access_t* phy, const phymod_phy_speed_config_t* speed_config, const phymod_phy_pll_state_t* old_pll_state, phymod_phy_pll_state_t* new_pll_state);
  int tsco_phy_speed_config_get(const phymod_phy_access_t* phy, phymod_phy_speed_config_t* speed_config);
  
  /* get default tx taps*/
  int tsco_phy_tx_taps_default_get(const phymod_phy_access_t* phy, phymod_phy_signalling_method_t mode, phymod_tx_t* tx);
  
  /* get default tx taps*/
  int tsco_phy_lane_config_default_get(const phymod_phy_access_t* phy, phymod_phy_signalling_method_t mode, phymod_firmware_lane_config_t* lane_config);
  
  /* get PMD micro code and length*/
  int tsco_phy_firmware_load_info_get(const phymod_phy_access_t* phy, phymod_firmware_load_info_t* info);
  
  /* Set/Get autoneg advertising abilities*/
  int tsco_phy_autoneg_advert_ability_set(const phymod_phy_access_t* phy, const phymod_autoneg_advert_abilities_t* an_advert_abilities, const phymod_phy_pll_state_t* old_pll_adv_state, phymod_phy_pll_state_t* new_pll_adv_state);
  int tsco_phy_autoneg_advert_ability_get(const phymod_phy_access_t* phy, phymod_autoneg_advert_abilities_t* an_advert_abilities);
  
  /* Get remote autoneg advertising abilities*/
  int tsco_phy_autoneg_remote_advert_ability_get(const phymod_phy_access_t* phy, phymod_autoneg_advert_abilities_t* an_advert_abilities);
  
  /* enable tx pam4 precoder for extended reach channel*/
  int tsco_phy_tx_pam4_precoder_enable_set(const phymod_phy_access_t* phy, int enable);
  int tsco_phy_tx_pam4_precoder_enable_get(const phymod_phy_access_t* phy, int* enable);
  
  /* reconfig pll on a specific serdes core*/
  int tsco_phy_pll_reconfig(const phymod_phy_access_t* phy, uint8_t pll_index, uint32_t pll_div, phymod_ref_clk_t ref_clk);
  
  /* Set/Get synce clock config*/
  int tsco_phy_synce_clk_ctrl_set(const phymod_phy_access_t* phy, phymod_synce_clk_ctrl_t cfg);
  int tsco_phy_synce_clk_ctrl_get(const phymod_phy_access_t* phy, phymod_synce_clk_ctrl_t* cfg);
  
  /* Enable/Disable PCS for the port*/
  int tsco_phy_pcs_enable_set(const phymod_phy_access_t* phy, uint32_t enable);
  
  /*Serdes interrupt handler.*/
  int tsco_intr_handler(const phymod_phy_access_t* phy, phymod_interrupt_type_t type, uint32_t* is_handled);
  
  /*Get timestamp tx info*/
  int tsco_timesync_tx_info_get(const phymod_phy_access_t* phy, phymod_ts_fifo_status_t* ts_tx_info);
  
  /* pcs lane swap for RLM purpose*/
  int tsco_phy_pcs_lane_swap_adjust(const phymod_phy_access_t* phy, uint32_t active_lane_map, uint32_t original_tx_lane_map, uint32_t original_rx_lane_map);
  
  /* speed id entry load for RLM only */
  int tsco_phy_load_speed_id_entry(const phymod_phy_access_t* phy, uint32_t speed, uint32_t num_lane, phymod_fec_type_t fec_type);
  
  /*Set or get fec bypass indication. Valid for RS-FEC.*/
  int tsco_phy_fec_bypass_indication_set(const phymod_phy_access_t* phy, uint32_t enable);
  int tsco_phy_fec_bypass_indication_get(const phymod_phy_access_t* phy, uint32_t* enable);
  
  /*Set or get codec mode */
  int tsco_phy_codec_mode_set(const phymod_phy_access_t* phy, phymod_phy_codec_mode_t codec_type);
  int tsco_phy_codec_mode_get(const phymod_phy_access_t* phy, phymod_phy_codec_mode_t* codec_type);
  
  /*reload either IEEE/GSH autoneg speed id table */
  int tsco_phy_autoneg_speed_id_table_reload(const phymod_phy_access_t* phy, uint32_t gsh_header_enable);
  
  /*Get RS FEC hi_ser_LH and hi_ser_live status */
  int tsco_phy_rs_fec_rxp_get(const phymod_phy_access_t* phy, uint32_t* hi_ser_lh, uint32_t* hi_ser_live);
  
  #endif /*_TSCO_H_*/
  