text: /************************************************************************************
   * configs/px4fmu/include/board.h
   * include/arch/board/board.h
   *
   *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
   *   Author: Gregory Nutt <gnutt@nuttx.org>
   *
   * Redistribution and use in source and binary forms, with or without
   * modification, are permitted provided that the following conditions
   * are met:
   *
   * 1. Redistributions of source code must retain the above copyright
   *    notice, this list of conditions and the following disclaimer.
   * 2. Redistributions in binary form must reproduce the above copyright
   *    notice, this list of conditions and the following disclaimer in
   *    the documentation and/or other materials provided with the
   *    distribution.
   * 3. Neither the name NuttX nor the names of its contributors may be
   *    used to endorse or promote products derived from this software
   *    without specific prior written permission.
   *
   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
   * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
   * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
   * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
   * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
   * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
   * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
   * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   * POSSIBILITY OF SUCH DAMAGE.
   *
   ************************************************************************************/
  
  #ifndef __ARCH_BOARD_BOARD_H
  #define __ARCH_BOARD_BOARD_H
  
  /************************************************************************************
   * Included Files
   ************************************************************************************/
  
  #include <nuttx/config.h>
  #ifndef __ASSEMBLY__
  # include <stdint.h>
  #endif
  
  #include <stm32.h>
  
  /************************************************************************************
   * Definitions
   ************************************************************************************/
  
  /* Clocking *************************************************************************/
  /* The MINDPX uses a 8MHz crystal connected to the HSE.
   *
   * This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c:
   *   System Clock source           : PLL (HSE)
   *   SYSCLK(Hz)                    : 168000000    Determined by PLL configuration
   *   HCLK(Hz)                      : 168000000    (STM32_RCC_CFGR_HPRE)
   *   AHB Prescaler                 : 1            (STM32_RCC_CFGR_HPRE)
   *   APB1 Prescaler                : 4            (STM32_RCC_CFGR_PPRE1)
   *   APB2 Prescaler                : 2            (STM32_RCC_CFGR_PPRE2)
   *   HSE Frequency(Hz)             : 8000000     (STM32_BOARD_XTAL)
   *   PLLM                          : 8           (STM32_PLLCFG_PLLM)
   *   PLLN                          : 336          (STM32_PLLCFG_PLLN)
   *   PLLP                          : 2            (STM32_PLLCFG_PLLP)
   *   PLLQ                          : 7            (STM32_PLLCFG_PPQ)
   *   Main regulator output voltage : Scale1 mode  Needed for high speed SYSCLK
   *   Flash Latency(WS)             : 5
   *   Prefetch Buffer               : OFF
   *   Instruction cache             : ON
   *   Data cache                    : ON
   *   Require 48MHz for USB OTG FS, : Enabled
   *   SDIO and RNG clock
   */
  
  /* HSI - 16 MHz RC factory-trimmed
   * LSI - 32 KHz RC
   * HSE - On-board crystal frequency is 8MHz
   * LSE - not installed
   */
  
  #define STM32_BOARD_XTAL        8000000ul
  
  #define STM32_HSI_FREQUENCY     16000000ul
  #define STM32_LSI_FREQUENCY     32000
  #define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
  //#define STM32_LSE_FREQUENCY     32768
  
  /* Main PLL Configuration.
   *
   * PLL source is HSE
   * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
   *         = (8,000,000 / 8) * 336
   *         = 336,000,000
   * SYSCLK  = PLL_VCO / PLLP
   *         = 336,000,000 / 2 = 168,000,000
   * USB OTG FS, SDIO and RNG Clock
   *         =  PLL_VCO / PLLQ
   *         = 48,000,000
   */
  
  #define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(8)
  #define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(336)
  #define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP_2
  #define STM32_PLLCFG_PLLQ       RCC_PLLCFG_PLLQ(7)
  
  #define STM32_SYSCLK_FREQUENCY  168000000ul
  
  /* AHB clock (HCLK) is SYSCLK (168MHz) */
  
  #define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK  /* HCLK  = SYSCLK / 1 */
  #define STM32_HCLK_FREQUENCY    STM32_SYSCLK_FREQUENCY
  #define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY  /* same as above, to satisfy compiler */
  
  /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
  
  #define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd4     /* PCLK1 = HCLK / 4 */
  #define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/4)
  
  /* Timers driven from APB1 will be twice PCLK1 */
  
  #define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM5_CLKIN   (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM6_CLKIN   (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM7_CLKIN   (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM12_CLKIN  (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM13_CLKIN  (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM14_CLKIN  (2*STM32_PCLK1_FREQUENCY)
  
  /* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
  
  #define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLKd2     /* PCLK2 = HCLK / 2 */
  #define STM32_PCLK2_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
  
  /* Timers driven from APB2 will be twice PCLK2 */
  
  #define STM32_APB2_TIM1_CLKIN   (2*STM32_PCLK2_FREQUENCY)
  #define STM32_APB2_TIM8_CLKIN   (2*STM32_PCLK2_FREQUENCY)
  #define STM32_APB2_TIM9_CLKIN   (2*STM32_PCLK2_FREQUENCY)
  #define STM32_APB2_TIM10_CLKIN  (2*STM32_PCLK2_FREQUENCY)
  #define STM32_APB2_TIM11_CLKIN  (2*STM32_PCLK2_FREQUENCY)
  
  /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
   * otherwise frequency is 2xAPBx.
   * Note: TIM1,8-11 are on APB2, others on APB1
   */
  
  #define BOARD_TIM1_FREQUENCY    STM32_APB2_TIM1_CLKIN
  #define BOARD_TIM2_FREQUENCY    STM32_APB1_TIM2_CLKIN
  #define BOARD_TIM3_FREQUENCY    STM32_APB1_TIM3_CLKIN
  #define BOARD_TIM4_FREQUENCY    STM32_APB1_TIM4_CLKIN
  #define BOARD_TIM5_FREQUENCY    STM32_APB1_TIM5_CLKIN
  #define BOARD_TIM6_FREQUENCY    STM32_APB1_TIM6_CLKIN
  #define BOARD_TIM7_FREQUENCY    STM32_APB1_TIM7_CLKIN
  #define BOARD_TIM8_FREQUENCY    STM32_APB2_TIM8_CLKIN
  #define BOARD_TIM9_FREQUENCY    STM32_APB2_TIM9_CLKIN
  #define BOARD_TIM10_FREQUENCY   STM32_APB2_TIM10_CLKIN
  #define BOARD_TIM11_FREQUENCY   STM32_APB2_TIM11_CLKIN
  #define BOARD_TIM12_FREQUENCY   STM32_APB1_TIM12_CLKIN
  #define BOARD_TIM13_FREQUENCY   STM32_APB1_TIM13_CLKIN
  #define BOARD_TIM14_FREQUENCY   STM32_APB1_TIM14_CLKIN
  
  /* SDIO dividers.  Note that slower clocking is required when DMA is disabled
   * in order to avoid RX overrun/TX underrun errors due to delayed responses
   * to service FIFOs in interrupt driven mode.  These values have not been
   * tuned!!!
   *
   * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz
   */
  
  #define SDIO_INIT_CLKDIV        (118 << SDIO_CLKCR_CLKDIV_SHIFT)
  
  /* DMA ON:  SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
   * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
   */
  
  #ifdef CONFIG_SDIO_DMA
  #  define SDIO_MMCXFR_CLKDIV    (1 << SDIO_CLKCR_CLKDIV_SHIFT)
  #else
  #  define SDIO_MMCXFR_CLKDIV    (2 << SDIO_CLKCR_CLKDIV_SHIFT)
  #endif
  
  /* DMA ON:  SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
   * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
   */
  
  #ifdef CONFIG_SDIO_DMA
  #  define SDIO_SDXFR_CLKDIV     (1 << SDIO_CLKCR_CLKDIV_SHIFT)
  #else
  #  define SDIO_SDXFR_CLKDIV     (2 << SDIO_CLKCR_CLKDIV_SHIFT)
  #endif
  
  /* DMA Channl/Stream Selections *****************************************************/
  /* Stream selections are arbitrary for now but might become important in the future
   * is we set aside more DMA channels/streams.
   *
   * SDIO DMA
   *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA
   *   DMAMAP_SDIO_2 = Channel 4, Stream 6
   */
  
  #define DMAMAP_SDIO DMAMAP_SDIO_1
  
  /* Alternate function pin selections ************************************************/
  
  /*
   * UARTs.
   */
  #define GPIO_USART1_RX	GPIO_USART1_RX_2	/* RC_INPUT */
  #define GPIO_USART1_TX	GPIO_USART1_TX_2
  
  #define GPIO_USART2_RX	GPIO_USART2_RX_2
  #define GPIO_USART2_TX	GPIO_USART2_TX_2
  #define GPIO_USART2_RTS	GPIO_USART2_RTS_2
  #define GPIO_USART2_CTS	GPIO_USART2_CTS_2
  
  #define GPIO_USART3_RX	GPIO_USART3_RX_3
  #define GPIO_USART3_TX	GPIO_USART3_TX_3
  #define GPIO_USART3_RTS	GPIO_USART3_RTS_2
  #define GPIO_USART3_CTS	GPIO_USART3_CTS_2
  
  #define GPIO_UART4_RX	GPIO_UART4_RX_1
  #define GPIO_UART4_TX	GPIO_UART4_TX_1
  
  #define GPIO_USART6_RX	GPIO_USART6_RX_2
  #define GPIO_USART6_TX	GPIO_USART6_TX_2
  
  #define GPIO_UART7_RX	GPIO_UART7_RX_1
  #define GPIO_UART7_TX	GPIO_UART7_TX_1
  
  /* UART8 has no alternate pin config */
  
  /* UART RX DMA configurations */
  #define DMAMAP_USART1_RX DMAMAP_USART1_RX_2
  #define DMAMAP_USART6_RX DMAMAP_USART6_RX_2
  
  /*
   * CAN
   *
   * CAN1 is routed to the onboard transceiver.
   */
  #define GPIO_CAN1_RX	GPIO_CAN1_RX_3
  #define GPIO_CAN1_TX	GPIO_CAN1_TX_3
  
  /*
   * I2C
   *
   * The optional _GPIO configurations allow the I2C driver to manually
   * reset the bus to clear stuck slaves.  They match the pin configuration,
   * but are normally-high GPIOs.
   */
  #define GPIO_I2C1_SCL		GPIO_I2C1_SCL_2
  #define GPIO_I2C1_SDA		GPIO_I2C1_SDA_2
  #define GPIO_I2C1_SCL_GPIO	(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8)
  #define GPIO_I2C1_SDA_GPIO	(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9)
  
  #define GPIO_I2C2_SCL		GPIO_I2C2_SCL_1
  #define GPIO_I2C2_SDA		GPIO_I2C2_SDA_1
  #define GPIO_I2C2_SCL_GPIO	(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10)
  #define GPIO_I2C2_SDA_GPIO	(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11)
  
  /*
   * SPI
   *
   * There are sensors on SPI1, and SPI2 is connected to the FRAM.
   */
  #define GPIO_SPI1_MISO	(GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz)
  #define GPIO_SPI1_MOSI	(GPIO_SPI1_MOSI_2|GPIO_SPEED_50MHz)
  #define GPIO_SPI1_SCK	(GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz)
  
  #define GPIO_SPI2_MISO	(GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz)
  #define GPIO_SPI2_MOSI	(GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz)
  #define GPIO_SPI2_SCK	(GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz)
  
  #define GPIO_SPI4_MISO	(GPIO_SPI4_MISO_1|GPIO_SPEED_50MHz)
  #define GPIO_SPI4_MOSI	(GPIO_SPI4_MOSI_1|GPIO_SPEED_50MHz)
  #define GPIO_SPI4_SCK	(GPIO_SPI4_SCK_1|GPIO_SPEED_50MHz)
  
  /************************************************************************************
   * Public Data
   ************************************************************************************/
  
  #ifndef __ASSEMBLY__
  
  #undef EXTERN
  #if defined(__cplusplus)
  #define EXTERN extern "C"
  extern "C" {
  #else
  #define EXTERN extern
  #endif
  
  /************************************************************************************
   * Public Function Prototypes
   ************************************************************************************/
  /************************************************************************************
   * Name: stm32_boardinitialize
   *
   * Description:
   *   All STM32 architectures must provide the following entry point.  This entry point
   *   is called early in the intitialization -- after all memory has been configured
   *   and mapped but before any devices have been initialized.
   *
   ************************************************************************************/
  
  EXTERN void stm32_boardinitialize(void);
  
  #undef EXTERN
  #if defined(__cplusplus)
  }
  #endif
  
  #endif /* __ASSEMBLY__ */
  #endif  /* __ARCH_BOARD_BOARD_H */
  