text: // Generated register defines for snitch_cluster_peripheral
  
  // Copyright information found in source file:
  // Copyright 2020 ETH Zurich and University of Bologna.
  
  // Licensing information found in source file:
  // Licensed under Solderpad Hardware License, Version 0.51, see LICENSE for
  // details. SPDX-License-Identifier: SHL-0.51
  
  #ifndef _SNITCH_CLUSTER_PERIPHERAL_REG_DEFS_
  #define _SNITCH_CLUSTER_PERIPHERAL_REG_DEFS_
  
  #ifdef __cplusplus
  extern "C" {
  #endif
  // Number of performance counters
  #define SNITCH_CLUSTER_PERIPHERAL_PARAM_NUM_PERF_COUNTERS 16
  
  // Register width
  #define SNITCH_CLUSTER_PERIPHERAL_PARAM_REG_WIDTH 64
  
  // Enable particular performance counter and start tracking. (common
  // parameters)
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_REG_OFFSET 0x0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_CYCLE_0_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_TCDM_ACCESSED_0_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_TCDM_CONGESTED_0_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_ISSUE_FPU_0_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_ISSUE_FPU_SEQ_0_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_ISSUE_CORE_TO_FPU_0_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_RETIRED_INSTR_0_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_RETIRED_LOAD_0_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_RETIRED_I_0_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_RETIRED_ACC_0_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_AW_STALL_0_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_AR_STALL_0_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_R_STALL_0_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_W_STALL_0_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_BUF_W_STALL_0_BIT 14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_BUF_R_STALL_0_BIT 15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_AW_DONE_0_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_AW_BW_0_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_AR_DONE_0_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_AR_BW_0_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_R_DONE_0_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_R_BW_0_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_W_DONE_0_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_W_BW_0_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_B_DONE_0_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_DMA_BUSY_0_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_ICACHE_MISS_0_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_ICACHE_HIT_0_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_ICACHE_PREFETCH_0_BIT 28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_ICACHE_DOUBLE_HIT_0_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_0_ICACHE_STALL_0_BIT 30
  
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_REG_OFFSET 0x8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_CYCLE_1_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_TCDM_ACCESSED_1_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_TCDM_CONGESTED_1_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_ISSUE_FPU_1_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_ISSUE_FPU_SEQ_1_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_ISSUE_CORE_TO_FPU_1_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_RETIRED_INSTR_1_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_RETIRED_LOAD_1_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_RETIRED_I_1_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_RETIRED_ACC_1_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_AW_STALL_1_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_AR_STALL_1_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_R_STALL_1_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_W_STALL_1_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_BUF_W_STALL_1_BIT 14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_BUF_R_STALL_1_BIT 15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_AW_DONE_1_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_AW_BW_1_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_AR_DONE_1_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_AR_BW_1_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_R_DONE_1_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_R_BW_1_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_W_DONE_1_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_W_BW_1_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_B_DONE_1_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_DMA_BUSY_1_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_ICACHE_MISS_1_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_ICACHE_HIT_1_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_ICACHE_PREFETCH_1_BIT 28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_ICACHE_DOUBLE_HIT_1_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_1_ICACHE_STALL_1_BIT 30
  
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_REG_OFFSET 0x10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_CYCLE_2_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_TCDM_ACCESSED_2_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_TCDM_CONGESTED_2_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_ISSUE_FPU_2_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_ISSUE_FPU_SEQ_2_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_ISSUE_CORE_TO_FPU_2_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_RETIRED_INSTR_2_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_RETIRED_LOAD_2_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_RETIRED_I_2_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_RETIRED_ACC_2_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_AW_STALL_2_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_AR_STALL_2_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_R_STALL_2_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_W_STALL_2_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_BUF_W_STALL_2_BIT 14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_BUF_R_STALL_2_BIT 15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_AW_DONE_2_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_AW_BW_2_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_AR_DONE_2_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_AR_BW_2_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_R_DONE_2_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_R_BW_2_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_W_DONE_2_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_W_BW_2_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_B_DONE_2_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_DMA_BUSY_2_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_ICACHE_MISS_2_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_ICACHE_HIT_2_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_ICACHE_PREFETCH_2_BIT 28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_ICACHE_DOUBLE_HIT_2_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_2_ICACHE_STALL_2_BIT 30
  
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_REG_OFFSET 0x18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_CYCLE_3_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_TCDM_ACCESSED_3_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_TCDM_CONGESTED_3_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_ISSUE_FPU_3_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_ISSUE_FPU_SEQ_3_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_ISSUE_CORE_TO_FPU_3_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_RETIRED_INSTR_3_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_RETIRED_LOAD_3_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_RETIRED_I_3_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_RETIRED_ACC_3_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_AW_STALL_3_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_AR_STALL_3_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_R_STALL_3_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_W_STALL_3_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_BUF_W_STALL_3_BIT 14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_BUF_R_STALL_3_BIT 15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_AW_DONE_3_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_AW_BW_3_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_AR_DONE_3_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_AR_BW_3_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_R_DONE_3_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_R_BW_3_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_W_DONE_3_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_W_BW_3_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_B_DONE_3_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_DMA_BUSY_3_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_ICACHE_MISS_3_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_ICACHE_HIT_3_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_ICACHE_PREFETCH_3_BIT 28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_ICACHE_DOUBLE_HIT_3_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_3_ICACHE_STALL_3_BIT 30
  
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_REG_OFFSET 0x20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_CYCLE_4_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_TCDM_ACCESSED_4_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_TCDM_CONGESTED_4_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_ISSUE_FPU_4_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_ISSUE_FPU_SEQ_4_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_ISSUE_CORE_TO_FPU_4_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_RETIRED_INSTR_4_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_RETIRED_LOAD_4_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_RETIRED_I_4_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_RETIRED_ACC_4_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_AW_STALL_4_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_AR_STALL_4_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_R_STALL_4_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_W_STALL_4_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_BUF_W_STALL_4_BIT 14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_BUF_R_STALL_4_BIT 15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_AW_DONE_4_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_AW_BW_4_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_AR_DONE_4_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_AR_BW_4_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_R_DONE_4_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_R_BW_4_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_W_DONE_4_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_W_BW_4_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_B_DONE_4_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_DMA_BUSY_4_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_ICACHE_MISS_4_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_ICACHE_HIT_4_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_ICACHE_PREFETCH_4_BIT 28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_ICACHE_DOUBLE_HIT_4_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_4_ICACHE_STALL_4_BIT 30
  
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_REG_OFFSET 0x28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_CYCLE_5_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_TCDM_ACCESSED_5_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_TCDM_CONGESTED_5_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_ISSUE_FPU_5_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_ISSUE_FPU_SEQ_5_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_ISSUE_CORE_TO_FPU_5_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_RETIRED_INSTR_5_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_RETIRED_LOAD_5_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_RETIRED_I_5_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_RETIRED_ACC_5_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_AW_STALL_5_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_AR_STALL_5_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_R_STALL_5_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_W_STALL_5_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_BUF_W_STALL_5_BIT 14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_BUF_R_STALL_5_BIT 15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_AW_DONE_5_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_AW_BW_5_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_AR_DONE_5_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_AR_BW_5_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_R_DONE_5_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_R_BW_5_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_W_DONE_5_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_W_BW_5_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_B_DONE_5_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_DMA_BUSY_5_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_ICACHE_MISS_5_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_ICACHE_HIT_5_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_ICACHE_PREFETCH_5_BIT 28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_ICACHE_DOUBLE_HIT_5_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_5_ICACHE_STALL_5_BIT 30
  
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_REG_OFFSET 0x30
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_CYCLE_6_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_TCDM_ACCESSED_6_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_TCDM_CONGESTED_6_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_ISSUE_FPU_6_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_ISSUE_FPU_SEQ_6_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_ISSUE_CORE_TO_FPU_6_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_RETIRED_INSTR_6_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_RETIRED_LOAD_6_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_RETIRED_I_6_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_RETIRED_ACC_6_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_AW_STALL_6_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_AR_STALL_6_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_R_STALL_6_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_W_STALL_6_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_BUF_W_STALL_6_BIT 14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_BUF_R_STALL_6_BIT 15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_AW_DONE_6_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_AW_BW_6_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_AR_DONE_6_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_AR_BW_6_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_R_DONE_6_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_R_BW_6_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_W_DONE_6_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_W_BW_6_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_B_DONE_6_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_DMA_BUSY_6_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_ICACHE_MISS_6_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_ICACHE_HIT_6_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_ICACHE_PREFETCH_6_BIT 28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_ICACHE_DOUBLE_HIT_6_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_6_ICACHE_STALL_6_BIT 30
  
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_REG_OFFSET 0x38
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_CYCLE_7_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_TCDM_ACCESSED_7_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_TCDM_CONGESTED_7_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_ISSUE_FPU_7_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_ISSUE_FPU_SEQ_7_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_ISSUE_CORE_TO_FPU_7_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_RETIRED_INSTR_7_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_RETIRED_LOAD_7_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_RETIRED_I_7_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_RETIRED_ACC_7_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_AW_STALL_7_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_AR_STALL_7_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_R_STALL_7_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_W_STALL_7_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_BUF_W_STALL_7_BIT 14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_BUF_R_STALL_7_BIT 15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_AW_DONE_7_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_AW_BW_7_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_AR_DONE_7_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_AR_BW_7_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_R_DONE_7_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_R_BW_7_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_W_DONE_7_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_W_BW_7_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_B_DONE_7_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_DMA_BUSY_7_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_ICACHE_MISS_7_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_ICACHE_HIT_7_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_ICACHE_PREFETCH_7_BIT 28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_ICACHE_DOUBLE_HIT_7_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_7_ICACHE_STALL_7_BIT 30
  
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_REG_OFFSET 0x40
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_CYCLE_8_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_TCDM_ACCESSED_8_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_TCDM_CONGESTED_8_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_ISSUE_FPU_8_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_ISSUE_FPU_SEQ_8_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_ISSUE_CORE_TO_FPU_8_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_RETIRED_INSTR_8_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_RETIRED_LOAD_8_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_RETIRED_I_8_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_RETIRED_ACC_8_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_AW_STALL_8_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_AR_STALL_8_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_R_STALL_8_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_W_STALL_8_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_BUF_W_STALL_8_BIT 14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_BUF_R_STALL_8_BIT 15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_AW_DONE_8_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_AW_BW_8_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_AR_DONE_8_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_AR_BW_8_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_R_DONE_8_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_R_BW_8_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_W_DONE_8_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_W_BW_8_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_B_DONE_8_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_DMA_BUSY_8_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_ICACHE_MISS_8_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_ICACHE_HIT_8_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_ICACHE_PREFETCH_8_BIT 28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_ICACHE_DOUBLE_HIT_8_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_8_ICACHE_STALL_8_BIT 30
  
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_REG_OFFSET 0x48
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_CYCLE_9_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_TCDM_ACCESSED_9_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_TCDM_CONGESTED_9_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_ISSUE_FPU_9_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_ISSUE_FPU_SEQ_9_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_ISSUE_CORE_TO_FPU_9_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_RETIRED_INSTR_9_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_RETIRED_LOAD_9_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_RETIRED_I_9_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_RETIRED_ACC_9_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_AW_STALL_9_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_AR_STALL_9_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_R_STALL_9_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_W_STALL_9_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_BUF_W_STALL_9_BIT 14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_BUF_R_STALL_9_BIT 15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_AW_DONE_9_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_AW_BW_9_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_AR_DONE_9_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_AR_BW_9_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_R_DONE_9_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_R_BW_9_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_W_DONE_9_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_W_BW_9_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_B_DONE_9_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_DMA_BUSY_9_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_ICACHE_MISS_9_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_ICACHE_HIT_9_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_ICACHE_PREFETCH_9_BIT 28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_ICACHE_DOUBLE_HIT_9_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_9_ICACHE_STALL_9_BIT 30
  
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_REG_OFFSET 0x50
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_CYCLE_10_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_TCDM_ACCESSED_10_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_TCDM_CONGESTED_10_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_ISSUE_FPU_10_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_ISSUE_FPU_SEQ_10_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_ISSUE_CORE_TO_FPU_10_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_RETIRED_INSTR_10_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_RETIRED_LOAD_10_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_RETIRED_I_10_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_RETIRED_ACC_10_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_AW_STALL_10_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_AR_STALL_10_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_R_STALL_10_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_W_STALL_10_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_BUF_W_STALL_10_BIT \
      14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_BUF_R_STALL_10_BIT \
      15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_AW_DONE_10_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_AW_BW_10_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_AR_DONE_10_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_AR_BW_10_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_R_DONE_10_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_R_BW_10_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_W_DONE_10_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_W_BW_10_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_B_DONE_10_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_DMA_BUSY_10_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_ICACHE_MISS_10_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_ICACHE_HIT_10_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_ICACHE_PREFETCH_10_BIT \
      28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_ICACHE_DOUBLE_HIT_10_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_10_ICACHE_STALL_10_BIT 30
  
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_REG_OFFSET 0x58
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_CYCLE_11_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_TCDM_ACCESSED_11_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_TCDM_CONGESTED_11_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_ISSUE_FPU_11_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_ISSUE_FPU_SEQ_11_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_ISSUE_CORE_TO_FPU_11_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_RETIRED_INSTR_11_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_RETIRED_LOAD_11_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_RETIRED_I_11_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_RETIRED_ACC_11_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_AW_STALL_11_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_AR_STALL_11_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_R_STALL_11_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_W_STALL_11_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_BUF_W_STALL_11_BIT \
      14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_BUF_R_STALL_11_BIT \
      15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_AW_DONE_11_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_AW_BW_11_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_AR_DONE_11_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_AR_BW_11_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_R_DONE_11_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_R_BW_11_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_W_DONE_11_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_W_BW_11_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_B_DONE_11_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_DMA_BUSY_11_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_ICACHE_MISS_11_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_ICACHE_HIT_11_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_ICACHE_PREFETCH_11_BIT \
      28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_ICACHE_DOUBLE_HIT_11_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_11_ICACHE_STALL_11_BIT 30
  
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_REG_OFFSET 0x60
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_CYCLE_12_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_TCDM_ACCESSED_12_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_TCDM_CONGESTED_12_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_ISSUE_FPU_12_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_ISSUE_FPU_SEQ_12_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_ISSUE_CORE_TO_FPU_12_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_RETIRED_INSTR_12_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_RETIRED_LOAD_12_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_RETIRED_I_12_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_RETIRED_ACC_12_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_AW_STALL_12_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_AR_STALL_12_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_R_STALL_12_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_W_STALL_12_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_BUF_W_STALL_12_BIT \
      14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_BUF_R_STALL_12_BIT \
      15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_AW_DONE_12_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_AW_BW_12_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_AR_DONE_12_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_AR_BW_12_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_R_DONE_12_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_R_BW_12_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_W_DONE_12_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_W_BW_12_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_B_DONE_12_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_DMA_BUSY_12_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_ICACHE_MISS_12_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_ICACHE_HIT_12_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_ICACHE_PREFETCH_12_BIT \
      28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_ICACHE_DOUBLE_HIT_12_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_12_ICACHE_STALL_12_BIT 30
  
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_REG_OFFSET 0x68
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_CYCLE_13_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_TCDM_ACCESSED_13_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_TCDM_CONGESTED_13_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_ISSUE_FPU_13_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_ISSUE_FPU_SEQ_13_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_ISSUE_CORE_TO_FPU_13_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_RETIRED_INSTR_13_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_RETIRED_LOAD_13_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_RETIRED_I_13_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_RETIRED_ACC_13_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_AW_STALL_13_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_AR_STALL_13_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_R_STALL_13_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_W_STALL_13_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_BUF_W_STALL_13_BIT \
      14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_BUF_R_STALL_13_BIT \
      15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_AW_DONE_13_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_AW_BW_13_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_AR_DONE_13_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_AR_BW_13_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_R_DONE_13_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_R_BW_13_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_W_DONE_13_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_W_BW_13_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_B_DONE_13_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_DMA_BUSY_13_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_ICACHE_MISS_13_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_ICACHE_HIT_13_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_ICACHE_PREFETCH_13_BIT \
      28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_ICACHE_DOUBLE_HIT_13_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_13_ICACHE_STALL_13_BIT 30
  
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_REG_OFFSET 0x70
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_CYCLE_14_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_TCDM_ACCESSED_14_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_TCDM_CONGESTED_14_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_ISSUE_FPU_14_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_ISSUE_FPU_SEQ_14_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_ISSUE_CORE_TO_FPU_14_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_RETIRED_INSTR_14_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_RETIRED_LOAD_14_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_RETIRED_I_14_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_RETIRED_ACC_14_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_AW_STALL_14_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_AR_STALL_14_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_R_STALL_14_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_W_STALL_14_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_BUF_W_STALL_14_BIT \
      14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_BUF_R_STALL_14_BIT \
      15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_AW_DONE_14_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_AW_BW_14_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_AR_DONE_14_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_AR_BW_14_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_R_DONE_14_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_R_BW_14_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_W_DONE_14_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_W_BW_14_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_B_DONE_14_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_DMA_BUSY_14_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_ICACHE_MISS_14_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_ICACHE_HIT_14_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_ICACHE_PREFETCH_14_BIT \
      28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_ICACHE_DOUBLE_HIT_14_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_14_ICACHE_STALL_14_BIT 30
  
  // Enable particular performance counter and start tracking.
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_REG_OFFSET 0x78
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_CYCLE_15_BIT 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_TCDM_ACCESSED_15_BIT 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_TCDM_CONGESTED_15_BIT 2
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_ISSUE_FPU_15_BIT 3
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_ISSUE_FPU_SEQ_15_BIT 4
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_ISSUE_CORE_TO_FPU_15_BIT \
      5
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_RETIRED_INSTR_15_BIT 6
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_RETIRED_LOAD_15_BIT 7
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_RETIRED_I_15_BIT 8
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_RETIRED_ACC_15_BIT 9
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_AW_STALL_15_BIT 10
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_AR_STALL_15_BIT 11
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_R_STALL_15_BIT 12
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_W_STALL_15_BIT 13
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_BUF_W_STALL_15_BIT \
      14
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_BUF_R_STALL_15_BIT \
      15
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_AW_DONE_15_BIT 16
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_AW_BW_15_BIT 17
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_AR_DONE_15_BIT 18
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_AR_BW_15_BIT 19
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_R_DONE_15_BIT 20
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_R_BW_15_BIT 21
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_W_DONE_15_BIT 22
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_W_BW_15_BIT 23
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_B_DONE_15_BIT 24
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_DMA_BUSY_15_BIT 25
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_ICACHE_MISS_15_BIT 26
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_ICACHE_HIT_15_BIT 27
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_ICACHE_PREFETCH_15_BIT \
      28
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_ICACHE_DOUBLE_HIT_15_BIT \
      29
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_ENABLE_15_ICACHE_STALL_15_BIT 30
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_HART_SELECT_FIELD_WIDTH 10
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_HART_SELECT_FIELDS_PER_REG 6
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_MULTIREG_COUNT 16
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_0_REG_OFFSET 0x80
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_0_HART_SELECT_0_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_0_HART_SELECT_0_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_0_HART_SELECT_0_FIELD         \
      ((bitfield_field32_t){                                                  \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_0_HART_SELECT_0_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_0_HART_SELECT_0_OFFSET})
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_1_REG_OFFSET 0x88
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_1_HART_SELECT_1_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_1_HART_SELECT_1_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_1_HART_SELECT_1_FIELD         \
      ((bitfield_field32_t){                                                  \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_1_HART_SELECT_1_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_1_HART_SELECT_1_OFFSET})
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_2_REG_OFFSET 0x90
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_2_HART_SELECT_2_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_2_HART_SELECT_2_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_2_HART_SELECT_2_FIELD         \
      ((bitfield_field32_t){                                                  \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_2_HART_SELECT_2_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_2_HART_SELECT_2_OFFSET})
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_3_REG_OFFSET 0x98
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_3_HART_SELECT_3_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_3_HART_SELECT_3_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_3_HART_SELECT_3_FIELD         \
      ((bitfield_field32_t){                                                  \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_3_HART_SELECT_3_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_3_HART_SELECT_3_OFFSET})
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_4_REG_OFFSET 0xa0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_4_HART_SELECT_4_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_4_HART_SELECT_4_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_4_HART_SELECT_4_FIELD         \
      ((bitfield_field32_t){                                                  \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_4_HART_SELECT_4_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_4_HART_SELECT_4_OFFSET})
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_5_REG_OFFSET 0xa8
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_5_HART_SELECT_5_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_5_HART_SELECT_5_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_5_HART_SELECT_5_FIELD         \
      ((bitfield_field32_t){                                                  \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_5_HART_SELECT_5_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_5_HART_SELECT_5_OFFSET})
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_6_REG_OFFSET 0xb0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_6_HART_SELECT_6_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_6_HART_SELECT_6_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_6_HART_SELECT_6_FIELD         \
      ((bitfield_field32_t){                                                  \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_6_HART_SELECT_6_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_6_HART_SELECT_6_OFFSET})
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_7_REG_OFFSET 0xb8
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_7_HART_SELECT_7_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_7_HART_SELECT_7_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_7_HART_SELECT_7_FIELD         \
      ((bitfield_field32_t){                                                  \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_7_HART_SELECT_7_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_7_HART_SELECT_7_OFFSET})
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_8_REG_OFFSET 0xc0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_8_HART_SELECT_8_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_8_HART_SELECT_8_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_8_HART_SELECT_8_FIELD         \
      ((bitfield_field32_t){                                                  \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_8_HART_SELECT_8_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_8_HART_SELECT_8_OFFSET})
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_9_REG_OFFSET 0xc8
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_9_HART_SELECT_9_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_9_HART_SELECT_9_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_9_HART_SELECT_9_FIELD         \
      ((bitfield_field32_t){                                                  \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_9_HART_SELECT_9_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_9_HART_SELECT_9_OFFSET})
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_10_REG_OFFSET 0xd0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_10_HART_SELECT_10_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_10_HART_SELECT_10_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_10_HART_SELECT_10_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_10_HART_SELECT_10_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_10_HART_SELECT_10_OFFSET})
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_11_REG_OFFSET 0xd8
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_11_HART_SELECT_11_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_11_HART_SELECT_11_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_11_HART_SELECT_11_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_11_HART_SELECT_11_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_11_HART_SELECT_11_OFFSET})
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_12_REG_OFFSET 0xe0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_12_HART_SELECT_12_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_12_HART_SELECT_12_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_12_HART_SELECT_12_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_12_HART_SELECT_12_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_12_HART_SELECT_12_OFFSET})
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_13_REG_OFFSET 0xe8
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_13_HART_SELECT_13_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_13_HART_SELECT_13_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_13_HART_SELECT_13_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_13_HART_SELECT_13_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_13_HART_SELECT_13_OFFSET})
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_14_REG_OFFSET 0xf0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_14_HART_SELECT_14_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_14_HART_SELECT_14_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_14_HART_SELECT_14_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_14_HART_SELECT_14_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_14_HART_SELECT_14_OFFSET})
  
  // Select from which hart in the cluster, starting from `0`,
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_15_REG_OFFSET 0xf8
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_15_HART_SELECT_15_MASK 0x3ff
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_15_HART_SELECT_15_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_15_HART_SELECT_15_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_15_HART_SELECT_15_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_HART_SELECT_15_HART_SELECT_15_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_PERF_COUNTER_FIELD_WIDTH 48
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_PERF_COUNTER_FIELDS_PER_REG 1
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_MULTIREG_COUNT 16
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0_REG_OFFSET 0x100
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0_PERF_COUNTER_0_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0_PERF_COUNTER_0_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0_PERF_COUNTER_0_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0_PERF_COUNTER_0_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_0_PERF_COUNTER_0_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1_REG_OFFSET 0x108
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1_PERF_COUNTER_1_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1_PERF_COUNTER_1_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1_PERF_COUNTER_1_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1_PERF_COUNTER_1_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_1_PERF_COUNTER_1_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2_REG_OFFSET 0x110
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2_PERF_COUNTER_2_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2_PERF_COUNTER_2_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2_PERF_COUNTER_2_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2_PERF_COUNTER_2_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_2_PERF_COUNTER_2_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3_REG_OFFSET 0x118
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3_PERF_COUNTER_3_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3_PERF_COUNTER_3_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3_PERF_COUNTER_3_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3_PERF_COUNTER_3_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_3_PERF_COUNTER_3_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4_REG_OFFSET 0x120
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4_PERF_COUNTER_4_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4_PERF_COUNTER_4_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4_PERF_COUNTER_4_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4_PERF_COUNTER_4_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_4_PERF_COUNTER_4_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5_REG_OFFSET 0x128
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5_PERF_COUNTER_5_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5_PERF_COUNTER_5_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5_PERF_COUNTER_5_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5_PERF_COUNTER_5_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_5_PERF_COUNTER_5_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6_REG_OFFSET 0x130
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6_PERF_COUNTER_6_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6_PERF_COUNTER_6_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6_PERF_COUNTER_6_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6_PERF_COUNTER_6_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_6_PERF_COUNTER_6_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7_REG_OFFSET 0x138
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7_PERF_COUNTER_7_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7_PERF_COUNTER_7_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7_PERF_COUNTER_7_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7_PERF_COUNTER_7_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_7_PERF_COUNTER_7_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8_REG_OFFSET 0x140
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8_PERF_COUNTER_8_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8_PERF_COUNTER_8_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8_PERF_COUNTER_8_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8_PERF_COUNTER_8_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_8_PERF_COUNTER_8_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9_REG_OFFSET 0x148
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9_PERF_COUNTER_9_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9_PERF_COUNTER_9_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9_PERF_COUNTER_9_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9_PERF_COUNTER_9_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_9_PERF_COUNTER_9_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10_REG_OFFSET 0x150
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10_PERF_COUNTER_10_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10_PERF_COUNTER_10_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10_PERF_COUNTER_10_FIELD     \
      ((bitfield_field32_t){                                                  \
          .mask =                                                             \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10_PERF_COUNTER_10_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_10_PERF_COUNTER_10_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11_REG_OFFSET 0x158
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11_PERF_COUNTER_11_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11_PERF_COUNTER_11_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11_PERF_COUNTER_11_FIELD     \
      ((bitfield_field32_t){                                                  \
          .mask =                                                             \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11_PERF_COUNTER_11_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_11_PERF_COUNTER_11_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12_REG_OFFSET 0x160
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12_PERF_COUNTER_12_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12_PERF_COUNTER_12_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12_PERF_COUNTER_12_FIELD     \
      ((bitfield_field32_t){                                                  \
          .mask =                                                             \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12_PERF_COUNTER_12_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_12_PERF_COUNTER_12_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13_REG_OFFSET 0x168
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13_PERF_COUNTER_13_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13_PERF_COUNTER_13_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13_PERF_COUNTER_13_FIELD     \
      ((bitfield_field32_t){                                                  \
          .mask =                                                             \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13_PERF_COUNTER_13_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_13_PERF_COUNTER_13_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14_REG_OFFSET 0x170
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14_PERF_COUNTER_14_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14_PERF_COUNTER_14_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14_PERF_COUNTER_14_FIELD     \
      ((bitfield_field32_t){                                                  \
          .mask =                                                             \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14_PERF_COUNTER_14_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_14_PERF_COUNTER_14_OFFSET})
  
  // Performance counter. Set corresponding PERF_COUNTER_ENABLE bits depending
  // on what
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15_REG_OFFSET 0x178
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15_PERF_COUNTER_15_MASK \
      0xffffffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15_PERF_COUNTER_15_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15_PERF_COUNTER_15_FIELD     \
      ((bitfield_field32_t){                                                  \
          .mask =                                                             \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15_PERF_COUNTER_15_MASK, \
          .index =                                                            \
              SNITCH_CLUSTER_PERIPHERAL_PERF_COUNTER_15_PERF_COUNTER_15_OFFSET})
  
  // Set bits in the cluster-local CLINT. Writing a 1 at location i sets the
  // cluster-local interrupt
  #define SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_REG_OFFSET 0x180
  #define SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_CL_CLINT_SET_MASK 0xffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_CL_CLINT_SET_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_CL_CLINT_SET_FIELD         \
      ((bitfield_field32_t){                                                \
          .mask = SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_CL_CLINT_SET_MASK, \
          .index = SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_SET_CL_CLINT_SET_OFFSET})
  
  // Clear bits in the cluster-local CLINT. Writing a 1 at location i clears
  // the cluster-local interrupt
  #define SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_REG_OFFSET 0x188
  #define SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_CL_CLINT_CLEAR_MASK 0xffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_CL_CLINT_CLEAR_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_CL_CLINT_CLEAR_FIELD         \
      ((bitfield_field32_t){                                                    \
          .mask = SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_CL_CLINT_CLEAR_MASK, \
          .index =                                                              \
              SNITCH_CLUSTER_PERIPHERAL_CL_CLINT_CLEAR_CL_CLINT_CLEAR_OFFSET})
  
  // Hardware barrier register. Loads to this register will block until all
  // cores have
  #define SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_REG_OFFSET 0x190
  #define SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_HW_BARRIER_MASK 0xffffffff
  #define SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_HW_BARRIER_OFFSET 0
  #define SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_HW_BARRIER_FIELD         \
      ((bitfield_field32_t){                                            \
          .mask = SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_HW_BARRIER_MASK, \
          .index = SNITCH_CLUSTER_PERIPHERAL_HW_BARRIER_HW_BARRIER_OFFSET})
  
  // Controls prefetching of the instruction cache.
  #define SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_REG_OFFSET 0x198
  #define SNITCH_CLUSTER_PERIPHERAL_ICACHE_PREFETCH_ENABLE_ICACHE_PREFETCH_ENABLE_BIT \
      0
  
  #ifdef __cplusplus
  }  // extern "C"
  #endif
  #endif  // _SNITCH_CLUSTER_PERIPHERAL_REG_DEFS_
          // End generated register defines for snitch_cluster_peripheral