text: /******************************************************************************
  *
  * Copyright (C) 2016 - 2017 Xilinx, Inc.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
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  * copies of the Software, and to permit persons to whom the Software is
  * furnished to do so, subject to the following conditions:
  *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
  *
  * Use of the Software is limited solely to applications:
  * (a) running on a Xilinx device, or
  * (b) that interact with a Xilinx device through a bus or interconnect.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
  * Except as contained in this notice, the name of the Xilinx shall not be used
  * in advertising or otherwise to promote the sale, use or other dealings in
  * this Software without prior written authorization from Xilinx.
  *
  ******************************************************************************/
  
  #include <stdio.h>
  
  #include "xparameters.h"
  #include "xil_printf.h"
  
  #ifdef XPS_BOARD_ZCU102
  #ifdef XPAR_XIICPS_0_DEVICE_ID
  #include "xiicps.h"
  
  #define BUF_LEN		10U
  
  #define IOEXPANDER1_ADDR		0x20U
  
  #define IIC_SCLK_RATE_IOEXP		400000
  
  #define CMD_CFG_0_REG		0x06U
  #define CMD_OUTPUT_0_REG	0x02U
  #define DATA_OUTPUT			0x0U
  
  #define DATA_COMMON_CFG		0xE0U
  #define DATA_GT_0000_CFG	0x00U
  
  XIicPs I2c0InstancePtr;
  
  int IicPhyReset(void)
  {
  
  	u8 WriteBuffer[BUF_LEN] = {0};
  	XIicPs_Config *I2c0CfgPtr;
  	int Status = XST_SUCCESS;
  
  	/* Initialize the IIC0 driver so that it is ready to use */
  	I2c0CfgPtr = XIicPs_LookupConfig(XPAR_XIICPS_0_DEVICE_ID);
  	if (I2c0CfgPtr == NULL) {
  		Status = XST_FAILURE;
  		return Status;
  	}
  
  	Status = XIicPs_CfgInitialize(&I2c0InstancePtr, I2c0CfgPtr,
  			I2c0CfgPtr->BaseAddress);
  	if (Status != XST_SUCCESS) {
  		Status = XST_FAILURE;
  		return Status;
  	}
  
  	/* Set the IIC serial clock rate */
  	XIicPs_SetSClk(&I2c0InstancePtr, IIC_SCLK_RATE_IOEXP);
  
  	/* Configure I/O pins as Output */
  	WriteBuffer[0] = CMD_CFG_0_REG;
  	WriteBuffer[1] = DATA_OUTPUT;
  	Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
  			WriteBuffer, 2, IOEXPANDER1_ADDR);
  	if (Status != XST_SUCCESS) {
  		Status = XST_FAILURE;
  		return Status;
  	}
  
  	/* Wait until bus is idle to start another transfer */
  	while (XIicPs_BusIsBusy(&I2c0InstancePtr));
  
  	/*
  	 * Deasserting I2C_MUX_RESETB
  	 * And GEM3 Resetb
  	 * Selecting lanes based on configuration
  	 */
  	WriteBuffer[0] = CMD_OUTPUT_0_REG;
  	/* gt0000 or no GT configuration */
  	WriteBuffer[1] = DATA_COMMON_CFG | DATA_GT_0000_CFG;
  
  	/* Send the Data */
  	Status = XIicPs_MasterSendPolled(&I2c0InstancePtr,
  			WriteBuffer, 2, IOEXPANDER1_ADDR);
  	if (Status != XST_SUCCESS) {
  		Status = XST_FAILURE;
  		return Status;
  	}
  
  	/* Wait until bus is idle */
  	while (XIicPs_BusIsBusy(&I2c0InstancePtr));
  
  	xil_printf("IIC PHY reset on ZCU102 successful\n\r");
  	return Status;
  }
  #endif
  #endif
  