text: /************************************************************************************
   * configs/stm32f746g-disco/include/board.h
   *
   *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
   *   Author: Gregory Nutt <gnutt@nuttx.org>
   *
   * Redistribution and use in source and binary forms, with or without
   * modification, are permitted provided that the following conditions
   * are met:
   *
   * 1. Redistributions of source code must retain the above copyright
   *    notice, this list of conditions and the following disclaimer.
   * 2. Redistributions in binary form must reproduce the above copyright
   *    notice, this list of conditions and the following disclaimer in
   *    the documentation and/or other materials provided with the
   *    distribution.
   * 3. Neither the name NuttX nor the names of its contributors may be
   *    used to endorse or promote products derived from this software
   *    without specific prior written permission.
   *
   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
   * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
   * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
   * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
   * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
   * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
   * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
   * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   * POSSIBILITY OF SUCH DAMAGE.
   *
   ************************************************************************************/
  
  #ifndef __CONFIG_STM32F746G_DISCO_INCLUDE_BOARD_H
  #define __CONFIG_STM32F746G_DISCO_INCLUDE_BOARD_H
  
  /************************************************************************************
   * Included Files
   ************************************************************************************/
  
  #include <nuttx/config.h>
  
  #ifndef __ASSEMBLY__
  # include <stdint.h>
  #endif
  
  /************************************************************************************
   * Pre-processor Definitions
   ************************************************************************************/
  
  /* Clocking *************************************************************************/
  /* The STM32F7 Discovery board provides the following clock sources:
   *
   *   X1:  24 MHz oscillator for USB OTG HS PHY and camera module (daughter board)
   *   X2:  25 MHz oscillator for STM32F746NGH6 microcontroller and Ethernet PHY.
   *   X3:  32.768 KHz crystal for STM32F746NGH6 embedded RTC
   *
   * So we have these clock source available within the STM32
   *
   *   HSI: 16 MHz RC factory-trimmed
   *   LSI: 32 KHz RC
   *   HSE: On-board crystal frequency is 25MHz
   *   LSE: 32.768 kHz
   */
  
  #define STM32_BOARD_XTAL        25000000ul
  
  #define STM32_HSI_FREQUENCY     16000000ul
  #define STM32_LSI_FREQUENCY     32000
  #define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
  #define STM32_LSE_FREQUENCY     32768
  
  /* Main PLL Configuration.
   *
   * PLL source is HSE = 25,000,000
   *
   * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
   * Subject to:
   *
   *     2 <= PLLM <= 63
   *   192 <= PLLN <= 432
   *   192 MHz <= PLL_VCO <= 432MHz
   *
   * SYSCLK  = PLL_VCO / PLLP
   * Subject to
   *
   *   PLLP = {2, 4, 6, 8}
   *   SYSCLK <= 216 MHz
   *
   * USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
   * Subject to
   *   The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
   *   and the random number generator need a frequency lower than or equal
   *   to 48 MHz to work correctly.
   *
   * 2 <= PLLQ <= 15
   */
  
  #if defined(CONFIG_STM32F7_OTGFS)
  /* Highest SYSCLK with USB OTG FS clock = 48 MHz
   *
   * PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz
   * SYSCLK  = 384 MHz / 2 = 192 MHz
   * USB OTG FS, SDMMC and RNG Clock = 384 MHz / 8 = 48MHz
   */
  
  #define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(25)
  #define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(384)
  #define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP_2
  #define STM32_PLLCFG_PLLQ       RCC_PLLCFG_PLLQ(8)
  
  #define STM32_VCO_FREQUENCY     ((STM32_HSE_FREQUENCY / 25) * 384)
  #define STM32_SYSCLK_FREQUENCY  (STM32_VCO_FREQUENCY / 2)
  #define STM32_OTGFS_FREQUENCY   (STM32_VCO_FREQUENCY / 8)
  
  #elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_RNG)
  /* Highest SYSCLK with USB OTG FS clock <= 48MHz
   *
   * PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz
   * SYSCLK  = 432 MHz / 2 = 216 MHz
   * USB OTG FS, SDMMC and RNG Clock = 432 MHz / 10 = 43.2 MHz
   */
  
  #define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(25)
  #define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(432)
  #define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP_2
  #define STM32_PLLCFG_PLLQ       RCC_PLLCFG_PLLQ(10)
  
  #define STM32_VCO_FREQUENCY     ((STM32_HSE_FREQUENCY / 25) * 432)
  #define STM32_SYSCLK_FREQUENCY  (STM32_VCO_FREQUENCY / 2)
  #define STM32_OTGFS_FREQUENCY   (STM32_VCO_FREQUENCY / 10)
  
  #else
  /* Highest SYSCLK
   *
   * PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz
   * SYSCLK  = 432 MHz / 2 = 216 MHz
   */
  
  #define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(25)
  #define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(432)
  #define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP_2
  #define STM32_PLLCFG_PLLQ       RCC_PLLCFG_PLLQ(10)
  
  #define STM32_VCO_FREQUENCY     ((STM32_HSE_FREQUENCY / 25) * 432)
  #define STM32_SYSCLK_FREQUENCY  (STM32_VCO_FREQUENCY / 2)
  #define STM32_OTGFS_FREQUENCY   (STM32_VCO_FREQUENCY / 10)
  #endif
  
  /* Configure factors for  PLLSAI clock */
  
  #define STM32_RCC_PLLSAICFGR_PLLSAIN    RCC_PLLSAICFGR_PLLSAIN(192)
  #define STM32_RCC_PLLSAICFGR_PLLSAIP    RCC_PLLSAICFGR_PLLSAIP(2)
  #define STM32_RCC_PLLSAICFGR_PLLSAIQ    RCC_PLLSAICFGR_PLLSAIQ(2)
  #define STM32_RCC_PLLSAICFGR_PLLSAIR    RCC_PLLSAICFGR_PLLSAIR(2)
  
  /* Configure Dedicated Clock Configuration Register */
  
  #define STM32_RCC_DCKCFGR1_PLLI2SDIVQ  RCC_DCKCFGR1_PLLI2SDIVQ(1)
  #define STM32_RCC_DCKCFGR1_PLLSAIDIVQ  RCC_DCKCFGR1_PLLSAIDIVQ(1)
  #define STM32_RCC_DCKCFGR1_PLLSAIDIVR  RCC_DCKCFGR1_PLLSAIDIVR(0)
  #define STM32_RCC_DCKCFGR1_SAI1SRC     RCC_DCKCFGR1_SAI1SEL(0)
  #define STM32_RCC_DCKCFGR1_SAI2SRC     RCC_DCKCFGR1_SAI2SEL(0)
  #define STM32_RCC_DCKCFGR1_TIMPRESRC   0
  #define STM32_RCC_DCKCFGR1_DFSDM1SRC   0
  #define STM32_RCC_DCKCFGR1_ADFSDM1SRC  0
  
  
  
  /* Configure factors for  PLLI2S clock */
  
  #define STM32_RCC_PLLI2SCFGR_PLLI2SN   RCC_PLLI2SCFGR_PLLI2SN(192)
  #define STM32_RCC_PLLI2SCFGR_PLLI2SP   RCC_PLLI2SCFGR_PLLI2SP(2)
  #define STM32_RCC_PLLI2SCFGR_PLLI2SQ   RCC_PLLI2SCFGR_PLLI2SQ(2)
  #define STM32_RCC_PLLI2SCFGR_PLLI2SR   RCC_PLLI2SCFGR_PLLI2SR(2)
  
  /* Configure Dedicated Clock Configuration Register 2 */
  
  #define STM32_RCC_DCKCFGR2_USART1SRC  RCC_DCKCFGR2_USART1SEL_APB
  #define STM32_RCC_DCKCFGR2_USART2SRC  RCC_DCKCFGR2_USART2SEL_APB
  #define STM32_RCC_DCKCFGR2_UART4SRC   RCC_DCKCFGR2_UART4SEL_APB
  #define STM32_RCC_DCKCFGR2_UART5SRC   RCC_DCKCFGR2_UART5SEL_APB
  #define STM32_RCC_DCKCFGR2_USART6SRC  RCC_DCKCFGR2_USART6SEL_APB
  #define STM32_RCC_DCKCFGR2_UART7SRC   RCC_DCKCFGR2_UART7SEL_APB
  #define STM32_RCC_DCKCFGR2_UART8SRC   RCC_DCKCFGR2_UART8SEL_APB
  #define STM32_RCC_DCKCFGR2_I2C1SRC    RCC_DCKCFGR2_I2C1SEL_HSI
  #define STM32_RCC_DCKCFGR2_I2C2SRC    RCC_DCKCFGR2_I2C2SEL_HSI
  #define STM32_RCC_DCKCFGR2_I2C3SRC    RCC_DCKCFGR2_I2C3SEL_HSI
  #define STM32_RCC_DCKCFGR2_I2C4SRC    RCC_DCKCFGR2_I2C4SEL_HSI
  #define STM32_RCC_DCKCFGR2_LPTIM1SRC  RCC_DCKCFGR2_LPTIM1SEL_APB
  #define STM32_RCC_DCKCFGR2_CECSRC     RCC_DCKCFGR2_CECSEL_HSI
  #define STM32_RCC_DCKCFGR2_CK48MSRC   RCC_DCKCFGR2_CK48MSEL_PLLSAI
  #define STM32_RCC_DCKCFGR2_SDMMCSRC   RCC_DCKCFGR2_SDMMCSEL_48MHZ
  #define STM32_RCC_DCKCFGR2_SDMMC2SRC  RCC_DCKCFGR2_SDMMC2SEL_48MHZ
  
  /* Several prescalers allow the configuration of the two AHB buses, the
   * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
   * frequency of the two AHB buses is 216 MHz while the maximum frequency of
   * the high-speed APB domains is 108 MHz. The maximum allowed frequency of
   * the low-speed APB domain is 54 MHz.
   */
  
  /* AHB clock (HCLK) is SYSCLK (216 MHz) */
  
  #define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK  /* HCLK  = SYSCLK / 1 */
  #define STM32_HCLK_FREQUENCY    STM32_SYSCLK_FREQUENCY
  #define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY  /* same as above, to satisfy compiler */
  
  /* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
  
  #define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd4     /* PCLK1 = HCLK / 4 */
  #define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/4)
  
  /* Timers driven from APB1 will be twice PCLK1 */
  
  #define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM5_CLKIN   (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM6_CLKIN   (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM7_CLKIN   (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM12_CLKIN  (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM13_CLKIN  (2*STM32_PCLK1_FREQUENCY)
  #define STM32_APB1_TIM14_CLKIN  (2*STM32_PCLK1_FREQUENCY)
  
  /* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
  
  #define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLKd2     /* PCLK2 = HCLK / 2 */
  #define STM32_PCLK2_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
  
  /* Timers driven from APB2 will be twice PCLK2 */
  
  #define STM32_APB2_TIM1_CLKIN   (2*STM32_PCLK2_FREQUENCY)
  #define STM32_APB2_TIM8_CLKIN   (2*STM32_PCLK2_FREQUENCY)
  #define STM32_APB2_TIM9_CLKIN   (2*STM32_PCLK2_FREQUENCY)
  #define STM32_APB2_TIM10_CLKIN  (2*STM32_PCLK2_FREQUENCY)
  #define STM32_APB2_TIM11_CLKIN  (2*STM32_PCLK2_FREQUENCY)
  
  /* FLASH wait states
   *
   *  --------- ---------- -----------
   *  VDD       MAX SYSCLK WAIT STATES
   *  --------- ---------- -----------
   *  1.7-2.1 V   180 MHz    8
   *  2.1-2.4 V   216 MHz    9
   *  2.4-2.7 V   216 MHz    8
   *  2.7-3.6 V   216 MHz    7
   *  --------- ---------- -----------
   */
  
  #define BOARD_FLASH_WAITSTATES 7
  
  /* LED definitions ******************************************************************/
  /* The STM32F746G-DISCO board has numerous LEDs but only one, LD1 located near the
   * reset button, that can be controlled by software (LD2 is a power indicator, LD3-6
   * indicate USB status, LD7 is controlled by the ST-Link).
   *
   * LD1 is controlled by PI1 which is also the SPI2_SCK at the Arduino interface.
   * One end of LD1 is grounded so a high output on PI1 will illuminate the LED.
   *
   * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
   * The following definitions are used to access individual LEDs.
   */
  
  /* LED index values for use with board_userled() */
  
  #define BOARD_LED1        0
  #define BOARD_NLEDS       1
  
  #define BOARD_LD1         BOARD_LED1
  
  /* LED bits for use with board_userled_all() */
  
  #define BOARD_LED1_BIT    (1 << BOARD_LED1)
  
  /* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
   * include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related
   * events as follows:
   *
   *   SYMBOL              Meaning                 LD1
   *   ------------------- ----------------------- ------
   *   LED_STARTED         NuttX has been started  OFF
   *   LED_HEAPALLOCATE    Heap has been allocated OFF
   *   LED_IRQSENABLED     Interrupts enabled      OFF
   *   LED_STACKCREATED    Idle stack created      ON
   *   LED_INIRQ           In an interrupt         N/C
   *   LED_SIGNAL          In a signal handler     N/C
   *   LED_ASSERTION       An assertion failed     N/C
   *   LED_PANIC           The system has crashed  FLASH
   *
   * Thus is LD1 is statically on, NuttX has successfully  booted and is,
   * apparently, running normally.  If LD1 is flashing at approximately
   * 2Hz, then a fatal error has been detected and the system has halted.
   */
  
  #define LED_STARTED                  0 /* LD1=OFF */
  #define LED_HEAPALLOCATE             0 /* LD1=OFF */
  #define LED_IRQSENABLED              0 /* LD1=OFF */
  #define LED_STACKCREATED             1 /* LD1=ON */
  #define LED_INIRQ                    2 /* LD1=no change */
  #define LED_SIGNAL                   2 /* LD1=no change */
  #define LED_ASSERTION                2 /* LD1=no change */
  #define LED_PANIC                    3 /* LD1=flashing */
  
  /* Button definitions ***************************************************************/
  /* The STM32F7 Discovery supports one button:  Pushbutton B1, labelled "User", is
   * connected to GPIO PI11.  A high value will be sensed when the button is depressed.
   */
  
  #define BUTTON_USER        0
  #define NUM_BUTTONS        1
  #define BUTTON_USER_BIT    (1 << BUTTON_USER)
  
  /* Alternate function pin selections ************************************************/
  
  /* USART6:
   *
   * These configurations assume that you are using a standard Arduio RS-232 shield
   * with the serial interface with RX on pin D0 and TX on pin D1:
   *
   *   -------- ---------------
   *               STM32F7
   *   ARDUIONO FUNCTION  GPIO
   *   -- ----- --------- -----
   *   DO RX    USART6_RX PC7
   *   D1 TX    USART6_TX PC6
   *   -- ----- --------- -----
   */
  
  #define GPIO_USART6_RX GPIO_USART6_RX_1
  #define GPIO_USART6_TX GPIO_USART6_TX_1
  
  /* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins:
   *
   *   STM32 F7 BOARD        LAN8742A
   *   GPIO     SIGNAL       PIN NAME
   *   -------- ------------ -------------
   *   PG11     RMII_TX_EN   TXEN
   *   PG13     RMII_TXD0    TXD0
   *   PG14     RMII_TXD1    TXD1
   *   PC4      RMII_RXD0    RXD0/MODE0
   *   PC5      RMII_RXD1    RXD1/MODE1
   *   PG2      RMII_RXER    RXER/PHYAD0 -- Not used
   *   PA7      RMII_CRS_DV  CRS_DV/MODE2
   *   PC1      RMII_MDC     MDC
   *   PA2      RMII_MDIO    MDIO
   *   N/A      NRST         nRST
   *   PA1      RMII_REF_CLK nINT/REFCLK0
   *   N/A      OSC_25M      XTAL1/CLKIN
   *
   * The PHY address is either 0 or 1, depending on the state of PG2 on reset.
   * PG2 is not controlled but appears to result in a PHY address of 0.
   */
  
  #define GPIO_ETH_RMII_TX_EN   GPIO_ETH_RMII_TX_EN_2
  #define GPIO_ETH_RMII_TXD0    GPIO_ETH_RMII_TXD0_2
  #define GPIO_ETH_RMII_TXD1    GPIO_ETH_RMII_TXD1_2
  
  #endif  /* __CONFIG_STM32F746G_DISCO_INCLUDE_BOARD_H */
  