text: // Copyright 2018 The Fuchsia Authors. All rights reserved.
  // Use of this source code is governed by a BSD-style license that can be
  // found in the LICENSE file.
  
  typedef enum gxl_clk_gate_idx {
    // MPEG0
    CLK_GXL_DDR = 0,
    CLK_GXL_DOS,
    CLK_GXL_ISA,
    CLK_GXL_PL301,
    CLK_GXL_PERIPHS,
    CLK_GXL_SPICC,
    CLK_GXL_I2C,
    CLK_GXL_SANA,
    CLK_GXL_SMART_CARD,
    CLK_GXL_RNG0,
    CLK_GXL_UART0,
    CLK_GXL_SDHC,
    CLK_GXL_STREAM,
    CLK_GXL_ASYNC_FIFO,
    CLK_GXL_SDIO,
    CLK_GXL_ABUF,
    CLK_GXL_HIU_IFACE,
    CLK_GXL_BT656,
    CLK_GXL_ASSIST_MISC,
    CLK_GXL_EMMC_A,
    CLK_GXL_EMMC_B,
    CLK_GXL_EMMC_C,
    CLK_GXL_DMA,
    CLK_GXL_ACODEC,
    CLK_GXL_SPI,
  
    // MPEG1
    CLK_GXL_PCLK_TVFE,
    CLK_GXL_I2S_SPDIF,
    CLK_GXL_ETH,
    CLK_GXL_DEMUX,
    CLK_GXL_AIU_GLUE,
    CLK_GXL_IEC958,
    CLK_GXL_I2S_OUT,
    CLK_GXL_AMCLK,
    CLK_GXL_AIFIFO2,
    CLK_GXL_MIXER,
    CLK_GXL_MIXER_IFACE,
    CLK_GXL_ADC,
    CLK_GXL_BLKMV,
    CLK_GXL_AIU_TOP,
    CLK_GXL_UART1,
    CLK_GXL_G2D,
    CLK_GXL_USB0,
    CLK_GXL_USB1,
    CLK_GXL_RESET,
    CLK_GXL_NAND,
    CLK_GXL_DOS_PARSER,
    CLK_GXL_USB_GENERAL,
    CLK_GXL_VDIN1,
    CLK_GXL_AHB_ARB0,
    CLK_GXL_EFUSE,
    CLK_GXL_BOOT_ROM,
  
    // MPEG2
    CLK_GXL_AHB_DATA_BUS,
    CLK_GXL_AHB_CTRL_BUS,
    CLK_GXL_HDCP22_PCLK,
    CLK_GXL_HDMITX_PCLK,
    CLK_GXL_PDM_PCLK,
    CLK_GXL_BT656_PCLK,
    CLK_GXL_USB1_TO_DDR,
    CLK_GXL_USB0_TO_DDR,
    CLK_GXL_AIU_PCLK,
    CLK_GXL_MMC_PCLK,
    CLK_GXL_DVIN,
    CLK_GXL_UART2,
    CLK_GXL_SARADC,
    CLK_GXL_VPU_INTR,
    CLK_GXL_SEC_AHB_AHB3_BRIDGE,
    CLK_GXL_APB3_AO,
    CLK_GXL_MCLK_TVFE,
    CLK_GXL_CLK81_GIC,
  
    // Other
    CLK_GXL_VCLK2_VENCI0,
    CLK_GXL_VCLK2_VENCI1,
    CLK_GXL_VCLK2_VENCP0,
    CLK_GXL_VCLK2_VENCP1,
    CLK_GXL_VCLK2_VENCT0,
    CLK_GXL_VCLK2_VENCT1,
    CLK_GXL_VCLK2_OTHER,
    CLK_GXL_VCLK2_ENCI,
    CLK_GXL_VCLK2_ENCP,
    CLK_GXL_DAC_CLK,
    CLK_GXL_AOCLK_GATE,
    CLK_GXL_IEC958_GATE,
    CLK_GXL_ENC480P,
    CLK_GXL_RNG1,
    CLK_GXL_VCLK2_ENCT,
    CLK_GXL_VCLK2_ENCL,
    CLK_GXL_VCLK2_VENCLMMC,
    CLK_GXL_VCLK2_VENCL,
    CLK_GXL_VCLK2_OTHER1,
    CLK_GXL_EDP,
  
    // NB: This must be the last entry
    CLK_GXL_COUNT,
  } gxl_clk_gate_idx_t;
  