text: /*
  ** ###################################################################
  **     Processors:          MKV31F512VLH12
  **                          MKV31F512VLL12
  **
  **     Compilers:           Keil ARM C/C++ Compiler
  **                          Freescale C/C++ for Embedded ARM
  **                          GNU C Compiler
  **                          IAR ANSI C/C++ Compiler for ARM
  **                          MCUXpresso Compiler
  **
  **     Reference manual:    KV31P100M120SF7RM, Rev. 1, March 24, 2014
  **     Version:             rev. 1.7, 2015-02-19
  **     Build:               b171226
  **
  **     Abstract:
  **         Provides a system configuration function and a global variable that
  **         contains the system frequency. It configures the device and initializes
  **         the oscillator (PLL) that is part of the microcontroller device.
  **
  **     The Clear BSD License
  **     Copyright 2016 Freescale Semiconductor, Inc.
  **     Copyright 2016-2017 NXP
  **     All rights reserved.
  **
  **     Redistribution and use in source and binary forms, with or without
  **     modification, are permitted (subject to the limitations in the
  **     disclaimer below) provided that the following conditions are met:
  **
  **     * Redistributions of source code must retain the above copyright
  **       notice, this list of conditions and the following disclaimer.
  **
  **     * Redistributions in binary form must reproduce the above copyright
  **       notice, this list of conditions and the following disclaimer in the
  **       documentation and/or other materials provided with the distribution.
  **
  **     * Neither the name of the copyright holder nor the names of its
  **       contributors may be used to endorse or promote products derived from
  **       this software without specific prior written permission.
  **
  **     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  **     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  **     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  **     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  **     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  **     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  **     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  **     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  **     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  **     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  **     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  **     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  **
  **     http:                 www.nxp.com
  **     mail:                 support@nxp.com
  **
  **     Revisions:
  **     - rev. 1.0 (2013-11-01)
  **         Initial version.
  **     - rev. 1.1 (2013-12-20)
  **         Update according to reference manual rev. 0.6,
  **     - rev. 1.2 (2014-01-13)
  **         Update according to reference manual rev. 0.61,
  **     - rev. 1.3 (2014-02-10)
  **         The declaration of clock configurations has been moved to separate header file system_MKV31F51212.h
  **     - rev. 1.4 (2014-05-06)
  **         Update according to reference manual rev. 1.0,
  **         Update of system and startup files.
  **         Module access macro module_BASES replaced by module_BASE_PTRS.
  **     - rev. 1.5 (2014-08-28)
  **         Update of system files - default clock configuration changed.
  **         Update of startup files - possibility to override DefaultISR added.
  **     - rev. 1.6 (2014-10-14)
  **         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
  **     - rev. 1.7 (2015-02-19)
  **         Renamed interrupt vector LLW to LLWU.
  **
  ** ###################################################################
  */
  
  /*!
   * @file MKV31F51212
   * @version 1.7
   * @date 2015-02-19
   * @brief Device specific configuration file for MKV31F51212 (implementation
   *        file)
   *
   * Provides a system configuration function and a global variable that contains
   * the system frequency. It configures the device and initializes the oscillator
   * (PLL) that is part of the microcontroller device.
   */
  
  #include <stdint.h>
  #include "fsl_device_registers.h"
  
  
  
  /* ----------------------------------------------------------------------------
     -- Core clock
     ---------------------------------------------------------------------------- */
  
  uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
  
  /* ----------------------------------------------------------------------------
     -- SystemInit()
     ---------------------------------------------------------------------------- */
  
  void SystemInit (void) {
  #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
    SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
  #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
  
  #if (DISABLE_WDOG)
    /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
    WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
    /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
    WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
    /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
    WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
                   WDOG_STCTRLH_WAITEN_MASK |
                   WDOG_STCTRLH_STOPEN_MASK |
                   WDOG_STCTRLH_ALLOWUPDATE_MASK |
                   WDOG_STCTRLH_CLKSRC_MASK |
                   0x0100U;
  #endif /* (DISABLE_WDOG) */
  
    SystemInitHook();
  }
  
  /* ----------------------------------------------------------------------------
     -- SystemCoreClockUpdate()
     ---------------------------------------------------------------------------- */
  
  void SystemCoreClockUpdate (void) {
  
    uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
    uint16_t Divider;
  
    if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
      /* Output of FLL or PLL is selected */
      if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
        /* FLL is selected */
        if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
          /* External reference clock is selected */
          switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
          case 0x00U:
            MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
            break;
          case 0x02U:
          default:
            MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
            break;
          }
          if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
            switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
            case 0x38U:
              Divider = 1536U;
              break;
            case 0x30U:
              Divider = 1280U;
              break;
            default:
              Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
              break;
            }
          } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
            Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
          }
          MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
        } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
          MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
        } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
        /* Select correct multiplier to calculate the MCG output clock  */
        switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
          case 0x00U:
            MCGOUTClock *= 640U;
            break;
          case 0x20U:
            MCGOUTClock *= 1280U;
            break;
          case 0x40U:
            MCGOUTClock *= 1920U;
            break;
          case 0x60U:
            MCGOUTClock *= 2560U;
            break;
          case 0x80U:
            MCGOUTClock *= 732U;
            break;
          case 0xA0U:
            MCGOUTClock *= 1464U;
            break;
          case 0xC0U:
            MCGOUTClock *= 2197U;
            break;
          case 0xE0U:
            MCGOUTClock *= 2929U;
            break;
          default:
            break;
        }
      } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
        /* PLL is selected */
        Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
        MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
        Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
        MCGOUTClock *= Divider;          /* Calculate the MCG output clock */
      } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
    } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
      /* Internal reference clock is selected */
      if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
        MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
      } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
        Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
        MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
      } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
    } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
      /* External reference clock is selected */
      switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
      case 0x00U:
        MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
        break;
      case 0x02U:
      default:
        MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
        break;
      }
    } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
      /* Reserved value */
      return;
    } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
    SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
  }
  
  /* ----------------------------------------------------------------------------
     -- SystemInitHook()
     ---------------------------------------------------------------------------- */
  
  __attribute__ ((weak)) void SystemInitHook (void) {
    /* Void implementation of the weak function. */
  }
  