text: #include "clock_config.h"
  #include "fsl_smc.h"
  
  
  /*******************************************************************************
   * Definitions
   ******************************************************************************/
  #define MCG_PLL_DISABLE 0U             /*!< MCGPLLCLK disabled */
  #define OSC_CAP0P 0U                   /*!< Oscillator 0pF capacitor load */
  #define OSC_ER_CLK_DISABLE 0U          /*!< Disable external reference clock */
  #define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
  #define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */
  #define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
  
  #define SIM_CLKDIV1_RUN_MODE_MAX_CORE_DIV 1U    /*!< SIM CLKDIV1 maximum run mode core/system divider configurations */
  #define SIM_CLKDIV1_RUN_MODE_MAX_BUS_DIV 3U     /*!< SIM CLKDIV1 maximum run mode bus divider configurations */
  #define SIM_CLKDIV1_RUN_MODE_MAX_FLEXBUS_DIV 3U /*!< SIM CLKDIV1 maximum run mode flexbus divider configurations */
  #define SIM_CLKDIV1_RUN_MODE_MAX_FLASH_DIV 7U   /*!< SIM CLKDIV1 maximum run mode flash divider configurations */
  
  /*******************************************************************************
   * Variables
   ******************************************************************************/
  /* System clock frequency. */
  extern uint32_t SystemCoreClock;
  
  /*******************************************************************************
   * Code
   ******************************************************************************/
  /*FUNCTION**********************************************************************
   *
   * Function Name : CLOCK_CONFIG_SetFllExtRefDiv
   * Description   : Configure FLL external reference divider (FRDIV).
   * Param frdiv   : The value to set FRDIV.
   *
   *END**************************************************************************/
  static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
  {
      MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
  }
  
  /*******************************************************************************
   ********************* Configuration BOARD_BootClockHSRUN **********************
   ******************************************************************************/
  /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
  !!Configuration
  name: BOARD_BootClockHSRUN
  outputs:
  - {id: Bus_clock.outFreq, value: 75 MHz}
  - {id: Core_clock.outFreq, value: 150 MHz, locked: true, accuracy: '0.001'}
  - {id: Flash_clock.outFreq, value: 25 MHz}
  - {id: FlexBus_clock.outFreq, value: 75 MHz}
  - {id: LPO_clock.outFreq, value: 1 kHz}
  - {id: MCGFFCLK.outFreq, value: 375 kHz}
  - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
  - {id: MCGPLLCLK.outFreq, value: 150 MHz}
  - {id: MCGPLLCLK2X.outFreq, value: 300 MHz}
  - {id: OSCERCLK.outFreq, value: 12 MHz}
  - {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
  - {id: PLLFLLCLK.outFreq, value: 150 MHz}
  - {id: System_clock.outFreq, value: 150 MHz}
  settings:
  - {id: MCGMode, value: PEE}
  - {id: powerMode, value: HSRUN}
  - {id: MCG.FCRDIV.scale, value: '1'}
  - {id: MCG.FRDIV.scale, value: '32'}
  - {id: MCG.IREFS.sel, value: MCG.FRDIV}
  - {id: MCG.PLLS.sel, value: MCG.PLL_DIV2}
  - {id: MCG.VDIV.scale, value: '25'}
  - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
  - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
  - {id: MCG_C2_RANGE0_CFG, value: Very_high}
  - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
  - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
  - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
  - {id: RTC_CR_OSCE_CFG, value: Enabled}
  - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
  - {id: SIM.EMVSIMSRCSEL.sel, value: OSC.OSCERCLK}
  - {id: SIM.LPUARTSRCSEL.sel, value: OSC.OSCERCLK}
  - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
  - {id: SIM.OUTDIV2.scale, value: '2'}
  - {id: SIM.OUTDIV4.scale, value: '6'}
  - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
  - {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
  - {id: SIM.TPMSRCSEL.sel, value: OSC.OSCERCLK}
  - {id: SIM.USBFRAC.scale, value: '1', locked: true}
  - {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV}
  sources:
  - {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
   * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
  
  /*******************************************************************************
   * Variables for BOARD_BootClockHSRUN configuration
   ******************************************************************************/
  const mcg_config_t mcgConfig_BOARD_BootClockHSRUN = {
      .mcgMode         = kMCG_ModePEE,      /* PEE - PLL Engaged External */
      .irclkEnableMode = kMCG_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
      .ircs            = kMCG_IrcSlow,      /* Slow internal reference clock selected */
      .fcrdiv          = 0x0U,              /* Fast IRC divider: divided by 1 */
      .frdiv           = 0x0U,              /* FLL reference clock divider: divided by 32 */
      .drs             = kMCG_DrsLow,       /* Low frequency range */
      .dmx32           = kMCG_Dmx32Default, /* DCO has a default range of 25% */
      .oscsel          = kMCG_OscselOsc,    /* Selects System Oscillator (OSCCLK) */
      .pll0Config =
          {
              .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
              .prdiv      = 0x0U,            /* PLL Reference divider: divided by 1 */
              .vdiv       = 0x9U,            /* VCO divider: multiplied by 25 */
          },
  };
  const sim_clock_config_t simConfig_BOARD_BootClockHSRUN = {
      .pllFllSel  = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
      .pllFllDiv  = 0,                           /* PLLFLLSEL clock divider divisor: divided by 1 */
      .pllFllFrac = 0,                           /* PLLFLLSEL clock divider fraction: multiplied by 1 */
      .er32kSrc   = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
      .clkdiv1    = 0x1150000U,                  /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /6 */
  };
  const osc_config_t oscConfig_BOARD_BootClockHSRUN = {
      .freq        = 12000000U,            /* Oscillator frequency: 12000000Hz */
      .capLoad     = (OSC_CAP0P),          /* Oscillator capacity load: 0pF */
      .workMode    = kOSC_ModeOscLowPower, /* Oscillator low power */
      .oscerConfig = {
          .enableMode =
              kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
          .erclkDiv = 0,        /* Divider for OSCERCLK: divided by 1 */
      }};
  
  /*******************************************************************************
   * Code for BOARD_BootClockHSRUN configuration
   ******************************************************************************/
  void clkcfg_run_high_speed(void)
  {
      /* In HSRUN mode, the maximum allowable change in frequency of the system/bus/core/flash is
       * restricted to x2, to follow this restriction, enter HSRUN mode should follow:
       * 1.set CLKDIV1 to safe divider value.
       * 2.set the PLL or FLL output target frequency for HSRUN mode.
       * 3.switch to HSRUN mode.
       * 4.switch to HSRUN mode target requency value.
       */
  
      /* Set the system clock dividers in SIM to safe value. */
      CLOCK_SetOutDiv(SIM_CLKDIV1_RUN_MODE_MAX_CORE_DIV, SIM_CLKDIV1_RUN_MODE_MAX_BUS_DIV,
                      SIM_CLKDIV1_RUN_MODE_MAX_FLEXBUS_DIV, SIM_CLKDIV1_RUN_MODE_MAX_FLASH_DIV);
      /* Initializes OSC0 according to board configuration. */
      CLOCK_InitOsc0(&oscConfig_BOARD_BootClockHSRUN);
      CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockHSRUN.freq);
      /* Configure the Internal Reference clock (MCGIRCLK). */
      CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode, mcgConfig_BOARD_BootClockHSRUN.ircs,
                                    mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
      /* Configure FLL external reference divider (FRDIV). */
      CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv);
      /* Set MCG to PEE mode. */
      CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockHSRUN.oscsel, kMCG_PllClkSelPll0,
                          &mcgConfig_BOARD_BootClockHSRUN.pll0Config);
  
      /* Set HSRUN power mode */
      SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
      SMC_SetPowerModeHsrun(SMC);
      while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
      {
      }
  
      /* Set the clock configuration in SIM module. */
      CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
      /* Set SystemCoreClock variable. */
      SystemCoreClock = CLKCFG_CORE_CLOCK_HIGH_SPEED;
  }
  
  /*******************************************************************************
   ********************* Configuration BOARD_BootClockVLPR ***********************
   ******************************************************************************/
  /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
  !!Configuration
  name: BOARD_BootClockVLPR
  outputs:
  - {id: Bus_clock.outFreq, value: 4 MHz}
  - {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
  - {id: Flash_clock.outFreq, value: 800 kHz}
  - {id: FlexBus_clock.outFreq, value: 4 MHz}
  - {id: LPO_clock.outFreq, value: 1 kHz}
  - {id: MCGIRCLK.outFreq, value: 4 MHz}
  - {id: System_clock.outFreq, value: 4 MHz}
  settings:
  - {id: MCGMode, value: BLPI}
  - {id: powerMode, value: VLPR}
  - {id: MCG.CLKS.sel, value: MCG.IRCS}
  - {id: MCG.FCRDIV.scale, value: '1'}
  - {id: MCG.IRCS.sel, value: MCG.FCRDIV}
  - {id: MCG.PRDIV.scale, value: '1', locked: true}
  - {id: MCG.VDIV.scale, value: '16', locked: true}
  - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
  - {id: RTC_CR_OSCE_CFG, value: Enabled}
  - {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
  - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
  - {id: SIM.OUTDIV3.scale, value: '1', locked: true}
  - {id: SIM.OUTDIV4.scale, value: '5'}
  - {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
  - {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
  sources:
  - {id: OSC.OSC.outFreq, value: 12 MHz}
   * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
  
  /*******************************************************************************
   * Variables for BOARD_BootClockVLPR configuration
   ******************************************************************************/
  const mcg_config_t mcgConfig_BOARD_BootClockVLPR = {
      .mcgMode         = kMCG_ModeBLPI,     /* BLPI - Bypassed Low Power Internal */
      .irclkEnableMode = kMCG_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
      .ircs            = kMCG_IrcFast,      /* Fast internal reference clock selected */
      .fcrdiv          = 0x0U,              /* Fast IRC divider: divided by 1 */
      .frdiv           = 0x0U,              /* FLL reference clock divider: divided by 1 */
      .drs             = kMCG_DrsLow,       /* Low frequency range */
      .dmx32           = kMCG_Dmx32Default, /* DCO has a default range of 25% */
      .oscsel          = kMCG_OscselOsc,    /* Selects System Oscillator (OSCCLK) */
      .pll0Config =
          {
              .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
              .prdiv      = 0x0U,            /* PLL Reference divider: divided by 1 */
              .vdiv       = 0x0U,            /* VCO divider: multiplied by 16 */
          },
  };
  const sim_clock_config_t simConfig_BOARD_BootClockVLPR = {
      .pllFllSel  = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
      .pllFllDiv  = 0,                           /* PLLFLLSEL clock divider divisor: divided by 1 */
      .pllFllFrac = 0,                           /* PLLFLLSEL clock divider fraction: multiplied by 1 */
      .er32kSrc   = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
      .clkdiv1    = 0x40000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
  };
  const osc_config_t oscConfig_BOARD_BootClockVLPR = {
      .freq        = 0U,           /* Oscillator frequency: 0Hz */
      .capLoad     = (OSC_CAP0P),  /* Oscillator capacity load: 0pF */
      .workMode    = kOSC_ModeExt, /* Use external clock */
      .oscerConfig = {
          .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
          .erclkDiv   = 0,                  /* Divider for OSCERCLK: divided by 1 */
      }};
  
  /*******************************************************************************
   * Code for BOARD_BootClockVLPR configuration
   ******************************************************************************/
  void clkcfg_run_low_power(void)
  {
      /* Set the system clock dividers in SIM to safe value. */
      CLOCK_SetSimSafeDivs();
      /* Set MCG to BLPI mode. */
      CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv, mcgConfig_BOARD_BootClockVLPR.ircs,
                           mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
      /* Set the clock configuration in SIM module. */
      CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
      /* Set VLPR power mode. */
      SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
  #if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
      SMC_SetPowerModeVlpr(SMC, false);
  #else
      SMC_SetPowerModeVlpr(SMC);
  #endif
      while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
      {
      }
      /* Set SystemCoreClock variable. */
      SystemCoreClock = CLKCFG_CORE_CLOCK_LOW_POWER;
  }
  
  /*******************************************************************************
   ********************** Configuration BOARD_BootClockRUN ***********************
   ******************************************************************************/
  /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
  !!Configuration
  name: BOARD_BootClockRUN
  outputs:
  - {id: Bus_clock.outFreq, value: 60 MHz}
  - {id: Core_clock.outFreq, value: 120 MHz}
  - {id: Flash_clock.outFreq, value: 24 MHz}
  - {id: FlexBus_clock.outFreq, value: 60 MHz}
  - {id: LPO_clock.outFreq, value: 1 kHz}
  - {id: MCGFFCLK.outFreq, value: 375 kHz}
  - {id: MCGIRCLK.outFreq, value: 32.768 kHz}
  - {id: MCGPLLCLK.outFreq, value: 120 MHz}
  - {id: MCGPLLCLK2X.outFreq, value: 240 MHz}
  - {id: OSCERCLK.outFreq, value: 12 MHz}
  - {id: OSCERCLK_UNDIV.outFreq, value: 12 MHz}
  - {id: PLLFLLCLK.outFreq, value: 120 MHz}
  - {id: System_clock.outFreq, value: 120 MHz}
  settings:
  - {id: MCGMode, value: PEE}
  - {id: MCG.FCRDIV.scale, value: '1', locked: true}
  - {id: MCG.FRDIV.scale, value: '32'}
  - {id: MCG.IREFS.sel, value: MCG.FRDIV}
  - {id: MCG.PLLS.sel, value: MCG.PLL_DIV2}
  - {id: MCG.PRDIV.scale, value: '1', locked: true}
  - {id: MCG.VDIV.scale, value: '20', locked: true}
  - {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
  - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
  - {id: MCG_C2_RANGE0_CFG, value: Very_high}
  - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
  - {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
  - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
  - {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
  - {id: SIM.OUTDIV2.scale, value: '2'}
  - {id: SIM.OUTDIV4.scale, value: '5', locked: true}
  - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
  sources:
  - {id: OSC.OSC.outFreq, value: 12 MHz, enabled: true}
   * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
  
  /*******************************************************************************
   * Variables for BOARD_BootClockRUN configuration
   ******************************************************************************/
  const mcg_config_t mcgConfig_BOARD_BootClockRUN = {
      .mcgMode         = kMCG_ModePEE,      /* PEE - PLL Engaged External */
      .irclkEnableMode = kMCG_IrclkEnable,  /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
      .ircs            = kMCG_IrcSlow,      /* Slow internal reference clock selected */
      .fcrdiv          = 0x0U,              /* Fast IRC divider: divided by 1 */
      .frdiv           = 0x0U,              /* FLL reference clock divider: divided by 32 */
      .drs             = kMCG_DrsLow,       /* Low frequency range */
      .dmx32           = kMCG_Dmx32Default, /* DCO has a default range of 25% */
      .oscsel          = kMCG_OscselOsc,    /* Selects System Oscillator (OSCCLK) */
      .pll0Config =
          {
              .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
              .prdiv      = 0x0U,            /* PLL Reference divider: divided by 1 */
              .vdiv       = 0x4U,            /* VCO divider: multiplied by 20 */
          },
  };
  const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
      .pllFllSel  = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
      .pllFllDiv  = 0,                           /* PLLFLLSEL clock divider divisor: divided by 1 */
      .pllFllFrac = 0,                           /* PLLFLLSEL clock divider fraction: multiplied by 1 */
      .er32kSrc   = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
      .clkdiv1    = 0x1140000U,                  /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /5 */
  };
  const osc_config_t oscConfig_BOARD_BootClockRUN = {
      .freq        = 12000000U,            /* Oscillator frequency: 12000000Hz */
      .capLoad     = (OSC_CAP0P),          /* Oscillator capacity load: 0pF */
      .workMode    = kOSC_ModeOscLowPower, /* Oscillator low power */
      .oscerConfig = {
          .enableMode =
              kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
          .erclkDiv = 0,        /* Divider for OSCERCLK: divided by 1 */
      }};
  
  /*******************************************************************************
   * Code for BOARD_BootClockRUN configuration
   ******************************************************************************/
  void clkcfg_run_default(void)
  {
      /* Set the system clock dividers in SIM to safe value. */
      CLOCK_SetSimSafeDivs();
      /* Initializes OSC0 according to board configuration. */
      CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
      CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
      /* Configure the Internal Reference clock (MCGIRCLK). */
      CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode, mcgConfig_BOARD_BootClockRUN.ircs,
                                    mcgConfig_BOARD_BootClockRUN.fcrdiv);
      /* Configure FLL external reference divider (FRDIV). */
      CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
      /* Set MCG to PEE mode. */
      CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel, kMCG_PllClkSelPll0,
                          &mcgConfig_BOARD_BootClockRUN.pll0Config);
      /* Set the clock configuration in SIM module. */
      CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
      /* Set SystemCoreClock variable. */
      SystemCoreClock = CLKCFG_CORE_CLOCK_DEFAULT;
  }
  