text: /*
   * Copyright (C) 2015  Freie Universität Berlin
   *
   * This file is subject to the terms and conditions of the GNU Lesser
   * General Public License v2.1. See the file LICENSE in the top level
   * directory for more details.
   */
  
  /**
   * @defgroup    boards_nucleo-f072rb STM32 Nucleo-F072RB
   * @ingroup     boards_common_nucleo64
   * @brief       Support for the STM32 Nucleo-F072RB
   * @{
   *
   * @file
   * @brief       Peripheral MCU configuration for the nucleo-f072rb board
   *
   * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
   * @author      José Ignacio Alamos <jialamos@uc.cl>
   */
  
  #ifndef PERIPH_CONF_H
  #define PERIPH_CONF_H
  
  #include "periph_cpu.h"
  
  #ifdef __cplusplus
  extern "C" {
  #endif
  
  /**
   * @name    Clock settings
   *
   * @note    This is auto-generated from
   *          `cpu/stm32_common/dist/clk_conf/clk_conf.c`
   * @{
   */
  /* give the target core clock (HCLK) frequency [in Hz],
   * maximum: 48MHz */
   #define CLOCK_CORECLOCK      (48000000U)
   /* 0: no external high speed crystal available
    * else: actual crystal frequency [in Hz] */
   #define CLOCK_HSE            (8000000U)
   /* 0: no external low speed crystal available,
    * 1: external crystal available (always 32.768kHz) */
   #define CLOCK_LSE            (1)
   /* peripheral clock setup */
   #define CLOCK_AHB_DIV        RCC_CFGR_HPRE_DIV1
   #define CLOCK_AHB            (CLOCK_CORECLOCK / 1)
   #define CLOCK_APB1_DIV       RCC_CFGR_PPRE_DIV1      /* max 48MHz */
   #define CLOCK_APB1           (CLOCK_CORECLOCK / 1)
   #define CLOCK_APB2           (CLOCK_APB1)
  
   /* PLL factors */
   #define CLOCK_PLL_PREDIV     (1)
   #define CLOCK_PLL_MUL        (6)
   /** @} */
  
  /**
   * @name   Timer configuration
   * @{
   */
  static const timer_conf_t timer_config[] = {
      {
          .dev      = TIM1,
          .max      = 0x0000ffff,
          .rcc_mask = RCC_APB2ENR_TIM1EN,
          .bus      = APB2,
          .irqn     = TIM1_CC_IRQn
      }
  };
  
  #define TIMER_0_ISR         isr_tim1_cc
  
  #define TIMER_NUMOF         (sizeof(timer_config) / sizeof(timer_config[0]))
  /** @} */
  
  /**
   * @name   UART configuration
   * @{
   */
  static const uart_conf_t uart_config[] = {
      {
          .dev      = USART2,
          .rcc_mask = RCC_APB1ENR_USART2EN,
          .rx_pin   = GPIO_PIN(PORT_A, 3),
          .tx_pin   = GPIO_PIN(PORT_A, 2),
          .rx_af    = GPIO_AF1,
          .tx_af    = GPIO_AF1,
          .bus      = APB1,
          .irqn     = USART2_IRQn
      },
      {
          .dev      = USART1,
          .rcc_mask = RCC_APB2ENR_USART1EN,
          .rx_pin   = GPIO_PIN(PORT_A, 10),
          .tx_pin   = GPIO_PIN(PORT_A, 9),
          .rx_af    = GPIO_AF1,
          .tx_af    = GPIO_AF1,
          .bus      = APB2,
          .irqn     = USART1_IRQn
      },
      {
          .dev      = USART3,
          .rcc_mask = RCC_APB1ENR_USART3EN,
          .rx_pin   = GPIO_PIN(PORT_C, 11),
          .tx_pin   = GPIO_PIN(PORT_C, 10),
          .rx_af    = GPIO_AF1,
          .tx_af    = GPIO_AF1,
          .bus      = APB1,
          .irqn     = USART3_8_IRQn
      }
  };
  
  #define UART_0_ISR          (isr_usart2)
  #define UART_1_ISR          (isr_usart1)
  #define UART_2_ISR          (isr_usart3_8)
  
  #define UART_NUMOF          (sizeof(uart_config) / sizeof(uart_config[0]))
  /** @} */
  
  /**
   * @name    PWM configuration
   * @{
   */
  static const pwm_conf_t pwm_config[] = {
      {
          .dev      = TIM2,
          .rcc_mask = RCC_APB1ENR_TIM2EN,
          .chan     = { { .pin = GPIO_PIN(PORT_B, 3)  /* D3 */, .cc_chan = 1 },
                        { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
                        { .pin = GPIO_PIN(PORT_B, 11)         , .cc_chan = 3 },
                        { .pin = GPIO_UNDEF,                    .cc_chan = 0 } },
          .af       = GPIO_AF2,
          .bus      = APB1
      },
      {
          .dev      = TIM3,
          .rcc_mask = RCC_APB1ENR_TIM3EN,
          .chan     = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
                        { .pin = GPIO_PIN(PORT_B, 5) /* D4 */, .cc_chan = 1 },
                        { .pin = GPIO_UNDEF,                   .cc_chan = 0 },
                        { .pin = GPIO_UNDEF,                   .cc_chan = 0 } },
          .af       = GPIO_AF1,
          .bus      = APB1
      },
      {
          .dev      = TIM15,
          .rcc_mask = RCC_APB2ENR_TIM15EN,
          .chan     = { { .pin = GPIO_PIN(PORT_B, 14), .cc_chan = 0 },
                        { .pin = GPIO_PIN(PORT_B, 15), .cc_chan = 1 },
                        { .pin = GPIO_UNDEF,           .cc_chan = 0 },
                        { .pin = GPIO_UNDEF,           .cc_chan = 0 } },
          .af       = GPIO_AF1,
          .bus      = APB2
      }
  };
  
  #define PWM_NUMOF           (sizeof(pwm_config) / sizeof(pwm_config[0]))
  /** @} */
  
  /**
   * @name   SPI configuration
   *
   * @note    The spi_divtable is auto-generated from
   *          `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
   * @{
   */
  static const uint8_t spi_divtable[2][5] = {
      {       /* for APB1 @ 48000000Hz */
          7,  /* -> 187500Hz */
          6,  /* -> 375000Hz */
          5,  /* -> 750000Hz */
          2,  /* -> 6000000Hz */
          1   /* -> 12000000Hz */
      },
      {       /* for APB2 @ 48000000Hz */
          7,  /* -> 187500Hz */
          6,  /* -> 375000Hz */
          5,  /* -> 750000Hz */
          2,  /* -> 6000000Hz */
          1   /* -> 12000000Hz */
      }
  };
  
  static const spi_conf_t spi_config[] = {
      {
          .dev      = SPI1,
          .mosi_pin = GPIO_PIN(PORT_A, 7),
          .miso_pin = GPIO_PIN(PORT_A, 6),
          .sclk_pin = GPIO_PIN(PORT_A, 5),
          .cs_pin   = GPIO_PIN(PORT_A, 4),
          .af       = GPIO_AF0,
          .rccmask  = RCC_APB2ENR_SPI1EN,
          .apbbus   = APB2
      },
      {
          .dev      = SPI2,
          .mosi_pin = GPIO_PIN(PORT_B, 15),
          .miso_pin = GPIO_PIN(PORT_B, 14),
          .sclk_pin = GPIO_PIN(PORT_B, 13),
          .cs_pin   = GPIO_PIN(PORT_B, 12),
          .af       = GPIO_AF0,
          .rccmask  = RCC_APB1ENR_SPI2EN,
          .apbbus   = APB1
      },
  };
  
  #define SPI_NUMOF           (sizeof(spi_config) / sizeof(spi_config[0]))
  /** @} */
  
  /**
   * @name   ADC configuration
   * @{
   */
  #define ADC_CONFIG {            \
      { GPIO_PIN(PORT_A, 0), 0 }, \
      { GPIO_PIN(PORT_A, 1), 1 }, \
      { GPIO_PIN(PORT_A, 4), 4 }, \
      { GPIO_PIN(PORT_B, 0), 8 }, \
      { GPIO_PIN(PORT_C, 1), 11 },\
      { GPIO_PIN(PORT_C, 0), 10 } \
  }
  
  #define ADC_NUMOF           (6)
  /** @} */
  
  /**
   * @name RTC configuration
   * @{
   */
  /**
   * Nucleos with MB1136 C-02 or MB1136 C-03 -sticker on it have the required LSE
   * oscillator provided on the X2 slot.
   * See Nucleo User Manual UM1724 section 5.6.2.
   */
  #define RTC_NUMOF           (1U)
  /** @} */
  
  #ifdef __cplusplus
  }
  #endif
  
  #endif /* PERIPH_CONF_H */
  /** @} */
  