text: /*
   * Copyright (C) 2012 Marek Vasut <marex@denx.de>
   * on behalf of DENX Software Engineering GmbH
   *
   * SPDX-License-Identifier:	GPL-2.0+
   */
  
  #include <common.h>
  #include <miiphy.h>
  #include <asm/arch/cpu.h>
  #include <asm/arch/soc.h>
  #include <asm/arch/mpp.h>
  #include <asm/io.h>
  
  DECLARE_GLOBAL_DATA_PTR;
  
  #define TK71_OE_LOW			(~0)
  #define TK71_OE_HIGH			(~0)
  #define TK71_OE_VAL_LOW			(0)
  #define TK71_OE_VAL_HIGH		(0)
  
  int board_early_init_f(void)
  {
  	/*
  	 * default gpio configuration
  	 * There are maximum 64 gpios controlled through 2 sets of registers
  	 * the  below configuration configures mainly initial LED status
  	 */
  	mvebu_config_gpio(TK71_OE_VAL_LOW,
  			  TK71_OE_VAL_HIGH,
  			  TK71_OE_LOW, TK71_OE_HIGH);
  
  	/* Multi-Purpose Pins Functionality configuration */
  	static const u32 kwmpp_config[] = {
  		MPP0_NF_IO2,
  		MPP1_NF_IO3,
  		MPP2_NF_IO4,
  		MPP3_NF_IO5,
  		MPP4_NF_IO6,
  		MPP5_NF_IO7,
  		MPP6_SYSRST_OUTn,
  		MPP7_GPO,
  		MPP8_TW_SDA,
  		MPP9_TW_SCK,
  		MPP10_UART0_TXD,
  		MPP11_UART0_RXD,
  		MPP12_SD_CLK,
  		MPP13_SD_CMD,
  		MPP14_SD_D0,
  		MPP15_SD_D1,
  		MPP16_SD_D2,
  		MPP17_SD_D3,
  		MPP18_NF_IO0,
  		MPP19_NF_IO1,
  		MPP20_GE1_0,
  		MPP21_GE1_1,
  		MPP22_GE1_2,
  		MPP23_GE1_3,
  		MPP24_GE1_4,
  		MPP25_GE1_5,
  		MPP26_GE1_6,
  		MPP27_GE1_7,
  		MPP28_GPIO,
  		MPP29_GPIO,
  		MPP30_GE1_10,
  		MPP31_GE1_11,
  		MPP32_GE1_12,
  		MPP33_GE1_13,
  		MPP34_GPIO,
  		MPP35_GPIO,
  		MPP36_GPIO,
  		MPP37_GPIO,
  		MPP38_GPIO,
  		MPP39_GPIO,
  		MPP40_GPIO,
  		MPP41_GPIO,
  		MPP42_GPIO,
  		MPP43_GPIO,
  		MPP44_GPIO,
  		MPP45_GPIO,
  		MPP46_GPIO,
  		MPP47_GPIO,
  		MPP48_GPIO,
  		MPP49_GPIO,
  		0
  	};
  	kirkwood_mpp_conf(kwmpp_config, NULL);
  
  	return 0;
  }
  
  int board_init(void)
  {
  	/*
  	 * arch number of board
  	 */
  	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
  
  	/* adress of boot parameters */
  	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  
  	return 0;
  }
  
  #ifdef CONFIG_CMD_NET
  
  #define MV88E1116_MAC_CTRL2_REG		21
  #define MV88E1116_PGADR_REG		22
  #define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
  #define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
  
  static void mv_phy_88e1118_init(char *name)
  {
  	u16 reg;
  	u16 devadr;
  
  	if (miiphy_set_current_dev(name))
  		return;
  
  	/* command to read PHY dev address */
  	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
  		printf("Err..%s could not read PHY dev address\n",
  			__func__);
  		return;
  	}
  
  	/*
  	 * Enable RGMII delay on Tx and Rx for CPU port
  	 * Ref: sec 4.7.2 of chip datasheet
  	 */
  	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
  	miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
  	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
  	miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
  	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
  
  	/* reset the phy */
  	miiphy_reset(name, devadr);
  
  	printf("88E1118 Initialized on %s\n", name);
  }
  
  /* Configure and enable Switch and PHY */
  void reset_phy(void)
  {
  	/* configure and initialize PHY */
  	mv_phy_88e1118_init("egiga0");
  
  }
  #endif
  