text: // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
  // Test target codegen - host bc file has to be created first.
  // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
  // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK1
  // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
  // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK2
  // RUN: %clang_cc1 -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK3
  // expected-no-diagnostics
  #ifndef HEADER
  #define HEADER
  
  template<typename tx>
  tx ftemplate(int n) {
    int i;
  
    #pragma omp target teams distribute
    for (i = 0; i < 10; ++i)
    {
  #pragma omp parallel
      ++i;
    }
  
    return i;
  }
  
  int bar(int n){
    int a = 0;
  
    a += ftemplate<char>(n);
  
    return a;
  }
  
  #endif
  // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker
  // CHECK4-SAME: () #[[ATTR0:[0-9]+]] {
  // CHECK4-NEXT:  entry:
  // CHECK4-NEXT:    [[WORK_FN:%.*]] = alloca i8*, align 4
  // CHECK4-NEXT:    [[EXEC_STATUS:%.*]] = alloca i8, align 1
  // CHECK4-NEXT:    store i8* null, i8** [[WORK_FN]], align 4
  // CHECK4-NEXT:    store i8 0, i8* [[EXEC_STATUS]], align 1
  // CHECK4-NEXT:    br label [[DOTAWAIT_WORK:%.*]]
  // CHECK4:       .await.work:
  // CHECK4-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
  // CHECK4-NEXT:    [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]])
  // CHECK4-NEXT:    [[TMP1:%.*]] = zext i1 [[TMP0]] to i8
  // CHECK4-NEXT:    store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1
  // CHECK4-NEXT:    [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4
  // CHECK4-NEXT:    [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null
  // CHECK4-NEXT:    br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]]
  // CHECK4:       .select.workers:
  // CHECK4-NEXT:    [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1
  // CHECK4-NEXT:    [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0
  // CHECK4-NEXT:    br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]]
  // CHECK4:       .execute.parallel:
  // CHECK4-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
  // CHECK4-NEXT:    [[TMP5:%.*]] = load i8*, i8** [[WORK_FN]], align 4
  // CHECK4-NEXT:    [[WORK_MATCH:%.*]] = icmp eq i8* [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*)
  // CHECK4-NEXT:    br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.*]], label [[DOTCHECK_NEXT:%.*]]
  // CHECK4:       .execute.fn:
  // CHECK4-NEXT:    call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR3:[0-9]+]]
  // CHECK4-NEXT:    br label [[DOTTERMINATE_PARALLEL:%.*]]
  // CHECK4:       .check.next:
  // CHECK4-NEXT:    [[TMP6:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)*
  // CHECK4-NEXT:    call void [[TMP6]](i16 0, i32 [[TMP4]])
  // CHECK4-NEXT:    br label [[DOTTERMINATE_PARALLEL]]
  // CHECK4:       .terminate.parallel:
  // CHECK4-NEXT:    call void @__kmpc_kernel_end_parallel()
  // CHECK4-NEXT:    br label [[DOTBARRIER_PARALLEL]]
  // CHECK4:       .barrier.parallel:
  // CHECK4-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
  // CHECK4-NEXT:    br label [[DOTAWAIT_WORK]]
  // CHECK4:       .exit:
  // CHECK4-NEXT:    ret void
  // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19
  // CHECK4-SAME: () #[[ATTR1:[0-9]+]] {
  // CHECK4-NEXT:  entry:
  // CHECK4-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
  // CHECK4-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
  // CHECK4-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
  // CHECK4-NEXT:    [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
  // CHECK4-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
  // CHECK4-NEXT:    [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
  // CHECK4-NEXT:    [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]
  // CHECK4-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]
  // CHECK4-NEXT:    br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]]
  // CHECK4:       .worker:
  // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker() #[[ATTR3]]
  // CHECK4-NEXT:    br label [[DOTEXIT:%.*]]
  // CHECK4:       .mastercheck:
  // CHECK4-NEXT:    [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
  // CHECK4-NEXT:    [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
  // CHECK4-NEXT:    [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
  // CHECK4-NEXT:    [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1
  // CHECK4-NEXT:    [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1
  // CHECK4-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], -1
  // CHECK4-NEXT:    [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]]
  // CHECK4-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]
  // CHECK4-NEXT:    br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]
  // CHECK4:       .master:
  // CHECK4-NEXT:    [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
  // CHECK4-NEXT:    [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
  // CHECK4-NEXT:    [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]
  // CHECK4-NEXT:    call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)
  // CHECK4-NEXT:    call void @__kmpc_data_sharing_init_stack()
  // CHECK4-NEXT:    [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
  // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4
  // CHECK4-NEXT:    call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
  // CHECK4-NEXT:    br label [[DOTTERMINATION_NOTIFIER:%.*]]
  // CHECK4:       .termination.notifier:
  // CHECK4-NEXT:    call void @__kmpc_kernel_deinit(i16 1)
  // CHECK4-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
  // CHECK4-NEXT:    br label [[DOTEXIT]]
  // CHECK4:       .exit:
  // CHECK4-NEXT:    ret void
  // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__
  // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
  // CHECK4-NEXT:  entry:
  // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK4-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
  // CHECK4-NEXT:    [[TMP:%.*]] = alloca i32, align 4
  // CHECK4-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
  // CHECK4-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
  // CHECK4-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
  // CHECK4-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
  // CHECK4-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
  // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
  // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
  // CHECK4-NEXT:    [[TMP0:%.*]] = load i16, i16* @"_openmp_static_kernel$is_shared", align 2
  // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* @"_openmp_static_kernel$size", align 4
  // CHECK4-NEXT:    call void @__kmpc_get_team_static_memory(i16 0, i8* addrspacecast (i8 addrspace(3)* getelementptr inbounds (%"union._shared_openmp_static_memory_type_$_", %"union._shared_openmp_static_memory_type_$_" addrspace(3)* @"_openmp_shared_static_glob_rd_$_", i32 0, i32 0, i32 0) to i8*), i32 [[TMP1]], i16 [[TMP0]], i8** addrspacecast (i8* addrspace(3)* @"_openmp_kernel_static_glob_rd$ptr" to i8**))
  // CHECK4-NEXT:    [[TMP2:%.*]] = load i8*, i8* addrspace(3)* @"_openmp_kernel_static_glob_rd$ptr", align 4
  // CHECK4-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i32 0
  // CHECK4-NEXT:    [[TMP4:%.*]] = bitcast i8* [[TMP3]] to %struct._globalized_locals_ty*
  // CHECK4-NEXT:    [[I:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], %struct._globalized_locals_ty* [[TMP4]], i32 0, i32 0
  // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
  // CHECK4-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
  // CHECK4-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
  // CHECK4-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
  // CHECK4-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
  // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4
  // CHECK4-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
  // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 9
  // CHECK4-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
  // CHECK4:       cond.true:
  // CHECK4-NEXT:    br label [[COND_END:%.*]]
  // CHECK4:       cond.false:
  // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK4-NEXT:    br label [[COND_END]]
  // CHECK4:       cond.end:
  // CHECK4-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
  // CHECK4-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
  // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
  // CHECK4-NEXT:    store i32 [[TMP9]], i32* [[DOTOMP_IV]], align 4
  // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
  // CHECK4:       omp.inner.for.cond:
  // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK4-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
  // CHECK4-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
  // CHECK4:       omp.inner.for.body:
  // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK4-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
  // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
  // CHECK4-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
  // CHECK4-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
  // CHECK4-NEXT:    [[TMP14:%.*]] = bitcast i32* [[I]] to i8*
  // CHECK4-NEXT:    store i8* [[TMP14]], i8** [[TMP13]], align 4
  // CHECK4-NEXT:    [[TMP15:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
  // CHECK4-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP6]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP15]], i32 1)
  // CHECK4-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
  // CHECK4:       omp.body.continue:
  // CHECK4-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
  // CHECK4:       omp.inner.for.inc:
  // CHECK4-NEXT:    [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP16]], 1
  // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
  // CHECK4-NEXT:    br label [[OMP_INNER_FOR_COND]]
  // CHECK4:       omp.inner.for.end:
  // CHECK4-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
  // CHECK4:       omp.loop.exit:
  // CHECK4-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]])
  // CHECK4-NEXT:    [[TMP17:%.*]] = load i16, i16* @"_openmp_static_kernel$is_shared", align 2
  // CHECK4-NEXT:    call void @__kmpc_restore_team_static_memory(i16 0, i16 [[TMP17]])
  // CHECK4-NEXT:    ret void
  // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1
  // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] {
  // CHECK4-NEXT:  entry:
  // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK4-NEXT:    [[I_ADDR:%.*]] = alloca i32*, align 4
  // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
  // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
  // CHECK4-NEXT:    store i32* [[I]], i32** [[I_ADDR]], align 4
  // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 4
  // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
  // CHECK4-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP1]], 1
  // CHECK4-NEXT:    store i32 [[INC]], i32* [[TMP0]], align 4
  // CHECK4-NEXT:    ret void
  // CHECK4-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
  // CHECK4-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
  // CHECK4-NEXT:  entry:
  // CHECK4-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
  // CHECK4-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
  // CHECK4-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
  // CHECK4-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4
  // CHECK4-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
  // CHECK4-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
  // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
  // CHECK4-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
  // CHECK4-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4
  // CHECK4-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0
  // CHECK4-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
  // CHECK4-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4
  // CHECK4-NEXT:    call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3]]
  // CHECK4-NEXT:    ret void
  // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker
  // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
  // CHECK5-NEXT:  entry:
  // CHECK5-NEXT:    [[WORK_FN:%.*]] = alloca i8*, align 4
  // CHECK5-NEXT:    [[EXEC_STATUS:%.*]] = alloca i8, align 1
  // CHECK5-NEXT:    store i8* null, i8** [[WORK_FN]], align 4
  // CHECK5-NEXT:    store i8 0, i8* [[EXEC_STATUS]], align 1
  // CHECK5-NEXT:    br label [[DOTAWAIT_WORK:%.*]]
  // CHECK5:       .await.work:
  // CHECK5-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
  // CHECK5-NEXT:    [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]])
  // CHECK5-NEXT:    [[TMP1:%.*]] = zext i1 [[TMP0]] to i8
  // CHECK5-NEXT:    store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1
  // CHECK5-NEXT:    [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4
  // CHECK5-NEXT:    [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null
  // CHECK5-NEXT:    br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]]
  // CHECK5:       .select.workers:
  // CHECK5-NEXT:    [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1
  // CHECK5-NEXT:    [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0
  // CHECK5-NEXT:    br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]]
  // CHECK5:       .execute.parallel:
  // CHECK5-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
  // CHECK5-NEXT:    [[TMP5:%.*]] = load i8*, i8** [[WORK_FN]], align 4
  // CHECK5-NEXT:    [[WORK_MATCH:%.*]] = icmp eq i8* [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*)
  // CHECK5-NEXT:    br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.*]], label [[DOTCHECK_NEXT:%.*]]
  // CHECK5:       .execute.fn:
  // CHECK5-NEXT:    call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR3:[0-9]+]]
  // CHECK5-NEXT:    br label [[DOTTERMINATE_PARALLEL:%.*]]
  // CHECK5:       .check.next:
  // CHECK5-NEXT:    [[TMP6:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)*
  // CHECK5-NEXT:    call void [[TMP6]](i16 0, i32 [[TMP4]])
  // CHECK5-NEXT:    br label [[DOTTERMINATE_PARALLEL]]
  // CHECK5:       .terminate.parallel:
  // CHECK5-NEXT:    call void @__kmpc_kernel_end_parallel()
  // CHECK5-NEXT:    br label [[DOTBARRIER_PARALLEL]]
  // CHECK5:       .barrier.parallel:
  // CHECK5-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
  // CHECK5-NEXT:    br label [[DOTAWAIT_WORK]]
  // CHECK5:       .exit:
  // CHECK5-NEXT:    ret void
  // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19
  // CHECK5-SAME: () #[[ATTR1:[0-9]+]] {
  // CHECK5-NEXT:  entry:
  // CHECK5-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
  // CHECK5-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
  // CHECK5-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
  // CHECK5-NEXT:    [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
  // CHECK5-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
  // CHECK5-NEXT:    [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
  // CHECK5-NEXT:    [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]
  // CHECK5-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]
  // CHECK5-NEXT:    br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]]
  // CHECK5:       .worker:
  // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker() #[[ATTR3]]
  // CHECK5-NEXT:    br label [[DOTEXIT:%.*]]
  // CHECK5:       .mastercheck:
  // CHECK5-NEXT:    [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
  // CHECK5-NEXT:    [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
  // CHECK5-NEXT:    [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
  // CHECK5-NEXT:    [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1
  // CHECK5-NEXT:    [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1
  // CHECK5-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], -1
  // CHECK5-NEXT:    [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]]
  // CHECK5-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]
  // CHECK5-NEXT:    br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]
  // CHECK5:       .master:
  // CHECK5-NEXT:    [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
  // CHECK5-NEXT:    [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
  // CHECK5-NEXT:    [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]
  // CHECK5-NEXT:    call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)
  // CHECK5-NEXT:    call void @__kmpc_data_sharing_init_stack()
  // CHECK5-NEXT:    [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
  // CHECK5-NEXT:    store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4
  // CHECK5-NEXT:    call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
  // CHECK5-NEXT:    br label [[DOTTERMINATION_NOTIFIER:%.*]]
  // CHECK5:       .termination.notifier:
  // CHECK5-NEXT:    call void @__kmpc_kernel_deinit(i16 1)
  // CHECK5-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
  // CHECK5-NEXT:    br label [[DOTEXIT]]
  // CHECK5:       .exit:
  // CHECK5-NEXT:    ret void
  // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__
  // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
  // CHECK5-NEXT:  entry:
  // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
  // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
  // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
  // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
  // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
  // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
  // CHECK5-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
  // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
  // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
  // CHECK5-NEXT:    [[TMP0:%.*]] = call i8* @__kmpc_data_sharing_push_stack(i32 4, i16 1)
  // CHECK5-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to %struct._globalized_locals_ty*
  // CHECK5-NEXT:    [[I:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], %struct._globalized_locals_ty* [[TMP1]], i32 0, i32 0
  // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
  // CHECK5-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
  // CHECK5-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
  // CHECK5-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
  // CHECK5-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
  // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
  // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
  // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
  // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
  // CHECK5:       cond.true:
  // CHECK5-NEXT:    br label [[COND_END:%.*]]
  // CHECK5:       cond.false:
  // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK5-NEXT:    br label [[COND_END]]
  // CHECK5:       cond.end:
  // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
  // CHECK5-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
  // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
  // CHECK5-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
  // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
  // CHECK5:       omp.inner.for.cond:
  // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK5-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
  // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
  // CHECK5:       omp.inner.for.body:
  // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
  // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
  // CHECK5-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
  // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
  // CHECK5-NEXT:    [[TMP11:%.*]] = bitcast i32* [[I]] to i8*
  // CHECK5-NEXT:    store i8* [[TMP11]], i8** [[TMP10]], align 4
  // CHECK5-NEXT:    [[TMP12:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
  // CHECK5-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP12]], i32 1)
  // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
  // CHECK5:       omp.body.continue:
  // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
  // CHECK5:       omp.inner.for.inc:
  // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
  // CHECK5-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
  // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]]
  // CHECK5:       omp.inner.for.end:
  // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
  // CHECK5:       omp.loop.exit:
  // CHECK5-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
  // CHECK5-NEXT:    call void @__kmpc_data_sharing_pop_stack(i8* [[TMP0]])
  // CHECK5-NEXT:    ret void
  // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1
  // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] {
  // CHECK5-NEXT:  entry:
  // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK5-NEXT:    [[I_ADDR:%.*]] = alloca i32*, align 4
  // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
  // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
  // CHECK5-NEXT:    store i32* [[I]], i32** [[I_ADDR]], align 4
  // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 4
  // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
  // CHECK5-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP1]], 1
  // CHECK5-NEXT:    store i32 [[INC]], i32* [[TMP0]], align 4
  // CHECK5-NEXT:    ret void
  // CHECK5-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
  // CHECK5-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
  // CHECK5-NEXT:  entry:
  // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
  // CHECK5-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
  // CHECK5-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
  // CHECK5-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4
  // CHECK5-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
  // CHECK5-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
  // CHECK5-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
  // CHECK5-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
  // CHECK5-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4
  // CHECK5-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0
  // CHECK5-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
  // CHECK5-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4
  // CHECK5-NEXT:    call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3]]
  // CHECK5-NEXT:    ret void
  // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker
  // CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
  // CHECK6-NEXT:  entry:
  // CHECK6-NEXT:    [[WORK_FN:%.*]] = alloca i8*, align 4
  // CHECK6-NEXT:    [[EXEC_STATUS:%.*]] = alloca i8, align 1
  // CHECK6-NEXT:    store i8* null, i8** [[WORK_FN]], align 4
  // CHECK6-NEXT:    store i8 0, i8* [[EXEC_STATUS]], align 1
  // CHECK6-NEXT:    br label [[DOTAWAIT_WORK:%.*]]
  // CHECK6:       .await.work:
  // CHECK6-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
  // CHECK6-NEXT:    [[TMP0:%.*]] = call i1 @__kmpc_kernel_parallel(i8** [[WORK_FN]])
  // CHECK6-NEXT:    [[TMP1:%.*]] = zext i1 [[TMP0]] to i8
  // CHECK6-NEXT:    store i8 [[TMP1]], i8* [[EXEC_STATUS]], align 1
  // CHECK6-NEXT:    [[TMP2:%.*]] = load i8*, i8** [[WORK_FN]], align 4
  // CHECK6-NEXT:    [[SHOULD_TERMINATE:%.*]] = icmp eq i8* [[TMP2]], null
  // CHECK6-NEXT:    br i1 [[SHOULD_TERMINATE]], label [[DOTEXIT:%.*]], label [[DOTSELECT_WORKERS:%.*]]
  // CHECK6:       .select.workers:
  // CHECK6-NEXT:    [[TMP3:%.*]] = load i8, i8* [[EXEC_STATUS]], align 1
  // CHECK6-NEXT:    [[IS_ACTIVE:%.*]] = icmp ne i8 [[TMP3]], 0
  // CHECK6-NEXT:    br i1 [[IS_ACTIVE]], label [[DOTEXECUTE_PARALLEL:%.*]], label [[DOTBARRIER_PARALLEL:%.*]]
  // CHECK6:       .execute.parallel:
  // CHECK6-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]])
  // CHECK6-NEXT:    [[TMP5:%.*]] = load i8*, i8** [[WORK_FN]], align 4
  // CHECK6-NEXT:    [[WORK_MATCH:%.*]] = icmp eq i8* [[TMP5]], bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*)
  // CHECK6-NEXT:    br i1 [[WORK_MATCH]], label [[DOTEXECUTE_FN:%.*]], label [[DOTCHECK_NEXT:%.*]]
  // CHECK6:       .execute.fn:
  // CHECK6-NEXT:    call void @__omp_outlined__1_wrapper(i16 0, i32 [[TMP4]]) #[[ATTR3:[0-9]+]]
  // CHECK6-NEXT:    br label [[DOTTERMINATE_PARALLEL:%.*]]
  // CHECK6:       .check.next:
  // CHECK6-NEXT:    [[TMP6:%.*]] = bitcast i8* [[TMP2]] to void (i16, i32)*
  // CHECK6-NEXT:    call void [[TMP6]](i16 0, i32 [[TMP4]])
  // CHECK6-NEXT:    br label [[DOTTERMINATE_PARALLEL]]
  // CHECK6:       .terminate.parallel:
  // CHECK6-NEXT:    call void @__kmpc_kernel_end_parallel()
  // CHECK6-NEXT:    br label [[DOTBARRIER_PARALLEL]]
  // CHECK6:       .barrier.parallel:
  // CHECK6-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
  // CHECK6-NEXT:    br label [[DOTAWAIT_WORK]]
  // CHECK6:       .exit:
  // CHECK6-NEXT:    ret void
  // CHECK6-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19
  // CHECK6-SAME: () #[[ATTR1:[0-9]+]] {
  // CHECK6-NEXT:  entry:
  // CHECK6-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
  // CHECK6-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
  // CHECK6-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
  // CHECK6-NEXT:    [[NVPTX_TID:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
  // CHECK6-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
  // CHECK6-NEXT:    [[NVPTX_WARP_SIZE:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
  // CHECK6-NEXT:    [[THREAD_LIMIT:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS]], [[NVPTX_WARP_SIZE]]
  // CHECK6-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[NVPTX_TID]], [[THREAD_LIMIT]]
  // CHECK6-NEXT:    br i1 [[TMP0]], label [[DOTWORKER:%.*]], label [[DOTMASTERCHECK:%.*]]
  // CHECK6:       .worker:
  // CHECK6-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l19_worker() #[[ATTR3]]
  // CHECK6-NEXT:    br label [[DOTEXIT:%.*]]
  // CHECK6:       .mastercheck:
  // CHECK6-NEXT:    [[NVPTX_TID1:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
  // CHECK6-NEXT:    [[NVPTX_NUM_THREADS2:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
  // CHECK6-NEXT:    [[NVPTX_WARP_SIZE3:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
  // CHECK6-NEXT:    [[TMP1:%.*]] = sub nuw i32 [[NVPTX_WARP_SIZE3]], 1
  // CHECK6-NEXT:    [[TMP2:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS2]], 1
  // CHECK6-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP1]], -1
  // CHECK6-NEXT:    [[MASTER_TID:%.*]] = and i32 [[TMP2]], [[TMP3]]
  // CHECK6-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[NVPTX_TID1]], [[MASTER_TID]]
  // CHECK6-NEXT:    br i1 [[TMP4]], label [[DOTMASTER:%.*]], label [[DOTEXIT]]
  // CHECK6:       .master:
  // CHECK6-NEXT:    [[NVPTX_NUM_THREADS4:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
  // CHECK6-NEXT:    [[NVPTX_WARP_SIZE5:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
  // CHECK6-NEXT:    [[THREAD_LIMIT6:%.*]] = sub nuw i32 [[NVPTX_NUM_THREADS4]], [[NVPTX_WARP_SIZE5]]
  // CHECK6-NEXT:    call void @__kmpc_kernel_init(i32 [[THREAD_LIMIT6]], i16 1)
  // CHECK6-NEXT:    call void @__kmpc_data_sharing_init_stack()
  // CHECK6-NEXT:    [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]])
  // CHECK6-NEXT:    store i32 [[TMP5]], i32* [[DOTTHREADID_TEMP_]], align 4
  // CHECK6-NEXT:    call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR3]]
  // CHECK6-NEXT:    br label [[DOTTERMINATION_NOTIFIER:%.*]]
  // CHECK6:       .termination.notifier:
  // CHECK6-NEXT:    call void @__kmpc_kernel_deinit(i16 1)
  // CHECK6-NEXT:    call void @__kmpc_barrier_simple_spmd(%struct.ident_t* null, i32 0)
  // CHECK6-NEXT:    br label [[DOTEXIT]]
  // CHECK6:       .exit:
  // CHECK6-NEXT:    ret void
  // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__
  // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
  // CHECK6-NEXT:  entry:
  // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
  // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
  // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
  // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
  // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
  // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
  // CHECK6-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
  // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
  // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
  // CHECK6-NEXT:    [[TMP0:%.*]] = call i8* @__kmpc_data_sharing_push_stack(i32 4, i16 1)
  // CHECK6-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to %struct._globalized_locals_ty*
  // CHECK6-NEXT:    [[I:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], %struct._globalized_locals_ty* [[TMP1]], i32 0, i32 0
  // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
  // CHECK6-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
  // CHECK6-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
  // CHECK6-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
  // CHECK6-NEXT:    [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
  // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4
  // CHECK6-NEXT:    call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
  // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
  // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
  // CHECK6:       cond.true:
  // CHECK6-NEXT:    br label [[COND_END:%.*]]
  // CHECK6:       cond.false:
  // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK6-NEXT:    br label [[COND_END]]
  // CHECK6:       cond.end:
  // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
  // CHECK6-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
  // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
  // CHECK6-NEXT:    store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4
  // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
  // CHECK6:       omp.inner.for.cond:
  // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK6-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
  // CHECK6-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
  // CHECK6:       omp.inner.for.body:
  // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
  // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
  // CHECK6-NEXT:    store i32 [[ADD]], i32* [[I]], align 4
  // CHECK6-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
  // CHECK6-NEXT:    [[TMP11:%.*]] = bitcast i32* [[I]] to i8*
  // CHECK6-NEXT:    store i8* [[TMP11]], i8** [[TMP10]], align 4
  // CHECK6-NEXT:    [[TMP12:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
  // CHECK6-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP12]], i32 1)
  // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
  // CHECK6:       omp.body.continue:
  // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
  // CHECK6:       omp.inner.for.inc:
  // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK6-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP13]], 1
  // CHECK6-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
  // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]]
  // CHECK6:       omp.inner.for.end:
  // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
  // CHECK6:       omp.loop.exit:
  // CHECK6-NEXT:    call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]])
  // CHECK6-NEXT:    call void @__kmpc_data_sharing_pop_stack(i8* [[TMP0]])
  // CHECK6-NEXT:    ret void
  // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1
  // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] {
  // CHECK6-NEXT:  entry:
  // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK6-NEXT:    [[I_ADDR:%.*]] = alloca i32*, align 4
  // CHECK6-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
  // CHECK6-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
  // CHECK6-NEXT:    store i32* [[I]], i32** [[I_ADDR]], align 4
  // CHECK6-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 4
  // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
  // CHECK6-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP1]], 1
  // CHECK6-NEXT:    store i32 [[INC]], i32* [[TMP0]], align 4
  // CHECK6-NEXT:    ret void
  // CHECK6-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
  // CHECK6-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
  // CHECK6-NEXT:  entry:
  // CHECK6-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
  // CHECK6-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
  // CHECK6-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
  // CHECK6-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4
  // CHECK6-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
  // CHECK6-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
  // CHECK6-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
  // CHECK6-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
  // CHECK6-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4
  // CHECK6-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0
  // CHECK6-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
  // CHECK6-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4
  // CHECK6-NEXT:    call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR3]]
  // CHECK6-NEXT:    ret void
  // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l16
  // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
  // CHECK1-NEXT:  entry:
  // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
  // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
  // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)
  // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
  // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
  // CHECK1:       user_code.entry:
  // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
  // CHECK1-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
  // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
  // CHECK1-NEXT:    call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5:[0-9]+]]
  // CHECK1-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
  // CHECK1-NEXT:    ret void
  // CHECK1:       worker.exit:
  // CHECK1-NEXT:    ret void
  //
  //
  // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__
  // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
  // CHECK1-NEXT:  entry:
  // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
  // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
  // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
  // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
  // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
  // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
  // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
  // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
  // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8
  // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
  // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
  // CHECK1-NEXT:    [[I:%.*]] = call align 8 i8* @__kmpc_alloc_shared(i64 4)
  // CHECK1-NEXT:    [[I_ON_STACK:%.*]] = bitcast i8* [[I]] to i32*
  // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
  // CHECK1-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
  // CHECK1-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
  // CHECK1-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
  // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
  // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
  // CHECK1-NEXT:    call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
  // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
  // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
  // CHECK1:       cond.true:
  // CHECK1-NEXT:    br label [[COND_END:%.*]]
  // CHECK1:       cond.false:
  // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK1-NEXT:    br label [[COND_END]]
  // CHECK1:       cond.end:
  // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
  // CHECK1-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
  // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
  // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
  // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
  // CHECK1:       omp.inner.for.cond:
  // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
  // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
  // CHECK1:       omp.inner.for.body:
  // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
  // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
  // CHECK1-NEXT:    store i32 [[ADD]], i32* [[I_ON_STACK]], align 4
  // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
  // CHECK1-NEXT:    [[TMP9:%.*]] = bitcast i32* [[I_ON_STACK]] to i8*
  // CHECK1-NEXT:    store i8* [[TMP9]], i8** [[TMP8]], align 8
  // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
  // CHECK1-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP10]], i64 1)
  // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
  // CHECK1:       omp.body.continue:
  // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
  // CHECK1:       omp.inner.for.inc:
  // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
  // CHECK1-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
  // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
  // CHECK1:       omp.inner.for.end:
  // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
  // CHECK1:       omp.loop.exit:
  // CHECK1-NEXT:    call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]])
  // CHECK1-NEXT:    call void @__kmpc_free_shared(i8* [[I]], i64 4)
  // CHECK1-NEXT:    ret void
  //
  //
  // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1
  // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] {
  // CHECK1-NEXT:  entry:
  // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
  // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
  // CHECK1-NEXT:    [[I_ADDR:%.*]] = alloca i32*, align 8
  // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
  // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
  // CHECK1-NEXT:    store i32* [[I]], i32** [[I_ADDR]], align 8
  // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 8
  // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
  // CHECK1-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP1]], 1
  // CHECK1-NEXT:    store i32 [[INC]], i32* [[TMP0]], align 4
  // CHECK1-NEXT:    ret void
  //
  //
  // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
  // CHECK1-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
  // CHECK1-NEXT:  entry:
  // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
  // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
  // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
  // CHECK1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 8
  // CHECK1-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
  // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
  // CHECK1-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
  // CHECK1-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
  // CHECK1-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 8
  // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i64 0
  // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
  // CHECK1-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 8
  // CHECK1-NEXT:    call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR5]]
  // CHECK1-NEXT:    ret void
  //
  //
  // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l16
  // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
  // CHECK2-NEXT:  entry:
  // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
  // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
  // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)
  // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
  // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
  // CHECK2:       user_code.entry:
  // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
  // CHECK2-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
  // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
  // CHECK2-NEXT:    call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5:[0-9]+]]
  // CHECK2-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
  // CHECK2-NEXT:    ret void
  // CHECK2:       worker.exit:
  // CHECK2-NEXT:    ret void
  //
  //
  // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__
  // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
  // CHECK2-NEXT:  entry:
  // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
  // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
  // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
  // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
  // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
  // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
  // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
  // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
  // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
  // CHECK2-NEXT:    [[I:%.*]] = call align 8 i8* @__kmpc_alloc_shared(i32 4)
  // CHECK2-NEXT:    [[I_ON_STACK:%.*]] = bitcast i8* [[I]] to i32*
  // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
  // CHECK2-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
  // CHECK2-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
  // CHECK2-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
  // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
  // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
  // CHECK2-NEXT:    call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
  // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
  // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
  // CHECK2:       cond.true:
  // CHECK2-NEXT:    br label [[COND_END:%.*]]
  // CHECK2:       cond.false:
  // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK2-NEXT:    br label [[COND_END]]
  // CHECK2:       cond.end:
  // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
  // CHECK2-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
  // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
  // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
  // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
  // CHECK2:       omp.inner.for.cond:
  // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK2-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
  // CHECK2-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
  // CHECK2:       omp.inner.for.body:
  // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
  // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
  // CHECK2-NEXT:    store i32 [[ADD]], i32* [[I_ON_STACK]], align 4
  // CHECK2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
  // CHECK2-NEXT:    [[TMP9:%.*]] = bitcast i32* [[I_ON_STACK]] to i8*
  // CHECK2-NEXT:    store i8* [[TMP9]], i8** [[TMP8]], align 4
  // CHECK2-NEXT:    [[TMP10:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
  // CHECK2-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP10]], i32 1)
  // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
  // CHECK2:       omp.body.continue:
  // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
  // CHECK2:       omp.inner.for.inc:
  // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
  // CHECK2-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
  // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
  // CHECK2:       omp.inner.for.end:
  // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
  // CHECK2:       omp.loop.exit:
  // CHECK2-NEXT:    call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]])
  // CHECK2-NEXT:    call void @__kmpc_free_shared(i8* [[I]], i32 4)
  // CHECK2-NEXT:    ret void
  //
  //
  // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1
  // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] {
  // CHECK2-NEXT:  entry:
  // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK2-NEXT:    [[I_ADDR:%.*]] = alloca i32*, align 4
  // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
  // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
  // CHECK2-NEXT:    store i32* [[I]], i32** [[I_ADDR]], align 4
  // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 4
  // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
  // CHECK2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP1]], 1
  // CHECK2-NEXT:    store i32 [[INC]], i32* [[TMP0]], align 4
  // CHECK2-NEXT:    ret void
  //
  //
  // CHECK2-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
  // CHECK2-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
  // CHECK2-NEXT:  entry:
  // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
  // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
  // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
  // CHECK2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4
  // CHECK2-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
  // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
  // CHECK2-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
  // CHECK2-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
  // CHECK2-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4
  // CHECK2-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0
  // CHECK2-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
  // CHECK2-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4
  // CHECK2-NEXT:    call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR5]]
  // CHECK2-NEXT:    ret void
  //
  //
  // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l16
  // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
  // CHECK3-NEXT:  entry:
  // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
  // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
  // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i8 1, i1 true, i1 true)
  // CHECK3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
  // CHECK3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
  // CHECK3:       user_code.entry:
  // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
  // CHECK3-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
  // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[DOTTHREADID_TEMP_]], align 4
  // CHECK3-NEXT:    call void @__omp_outlined__(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTZERO_ADDR]]) #[[ATTR5:[0-9]+]]
  // CHECK3-NEXT:    call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB1]], i8 1, i1 true)
  // CHECK3-NEXT:    ret void
  // CHECK3:       worker.exit:
  // CHECK3-NEXT:    ret void
  //
  //
  // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__
  // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
  // CHECK3-NEXT:  entry:
  // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
  // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
  // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
  // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
  // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
  // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
  // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 4
  // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
  // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
  // CHECK3-NEXT:    [[I:%.*]] = call align 8 i8* @__kmpc_alloc_shared(i32 4)
  // CHECK3-NEXT:    [[I_ON_STACK:%.*]] = bitcast i8* [[I]] to i32*
  // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_LB]], align 4
  // CHECK3-NEXT:    store i32 9, i32* [[DOTOMP_UB]], align 4
  // CHECK3-NEXT:    store i32 1, i32* [[DOTOMP_STRIDE]], align 4
  // CHECK3-NEXT:    store i32 0, i32* [[DOTOMP_IS_LAST]], align 4
  // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
  // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
  // CHECK3-NEXT:    call void @__kmpc_distribute_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP1]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1)
  // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
  // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
  // CHECK3:       cond.true:
  // CHECK3-NEXT:    br label [[COND_END:%.*]]
  // CHECK3:       cond.false:
  // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK3-NEXT:    br label [[COND_END]]
  // CHECK3:       cond.end:
  // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
  // CHECK3-NEXT:    store i32 [[COND]], i32* [[DOTOMP_UB]], align 4
  // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4
  // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4
  // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
  // CHECK3:       omp.inner.for.cond:
  // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4
  // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
  // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
  // CHECK3:       omp.inner.for.body:
  // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
  // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
  // CHECK3-NEXT:    store i32 [[ADD]], i32* [[I_ON_STACK]], align 4
  // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
  // CHECK3-NEXT:    [[TMP9:%.*]] = bitcast i32* [[I_ON_STACK]] to i8*
  // CHECK3-NEXT:    store i8* [[TMP9]], i8** [[TMP8]], align 4
  // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**
  // CHECK3-NEXT:    call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, i32*)* @__omp_outlined__1 to i8*), i8* bitcast (void (i16, i32)* @__omp_outlined__1_wrapper to i8*), i8** [[TMP10]], i32 1)
  // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
  // CHECK3:       omp.body.continue:
  // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
  // CHECK3:       omp.inner.for.inc:
  // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4
  // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
  // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4
  // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
  // CHECK3:       omp.inner.for.end:
  // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
  // CHECK3:       omp.loop.exit:
  // CHECK3-NEXT:    call void @__kmpc_distribute_static_fini(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]])
  // CHECK3-NEXT:    call void @__kmpc_free_shared(i8* [[I]], i32 4)
  // CHECK3-NEXT:    ret void
  //
  //
  // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1
  // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR1]] {
  // CHECK3-NEXT:  entry:
  // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
  // CHECK3-NEXT:    [[I_ADDR:%.*]] = alloca i32*, align 4
  // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
  // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
  // CHECK3-NEXT:    store i32* [[I]], i32** [[I_ADDR]], align 4
  // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[I_ADDR]], align 4
  // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
  // CHECK3-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP1]], 1
  // CHECK3-NEXT:    store i32 [[INC]], i32* [[TMP0]], align 4
  // CHECK3-NEXT:    ret void
  //
  //
  // CHECK3-LABEL: define {{[^@]+}}@__omp_outlined__1_wrapper
  // CHECK3-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
  // CHECK3-NEXT:  entry:
  // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
  // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
  // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
  // CHECK3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca i8**, align 4
  // CHECK3-NEXT:    store i16 [[TMP0]], i16* [[DOTADDR]], align 2
  // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[DOTADDR1]], align 4
  // CHECK3-NEXT:    store i32 0, i32* [[DOTZERO_ADDR]], align 4
  // CHECK3-NEXT:    call void @__kmpc_get_shared_variables(i8*** [[GLOBAL_ARGS]])
  // CHECK3-NEXT:    [[TMP2:%.*]] = load i8**, i8*** [[GLOBAL_ARGS]], align 4
  // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8*, i8** [[TMP2]], i32 0
  // CHECK3-NEXT:    [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32**
  // CHECK3-NEXT:    [[TMP5:%.*]] = load i32*, i32** [[TMP4]], align 4
  // CHECK3-NEXT:    call void @__omp_outlined__1(i32* [[DOTADDR1]], i32* [[DOTZERO_ADDR]], i32* [[TMP5]]) #[[ATTR5]]
  // CHECK3-NEXT:    ret void
  //
  