text: // ==============================================================
  // File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
  // Version: 2017.4
  // Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
  // 
  // ==============================================================
  
  // psAxiLite
  // 0x00 : reserved
  // 0x04 : reserved
  // 0x08 : reserved
  // 0x0c : reserved
  // 0x10 : Data signal of rule0_V
  //        bit 31~0 - rule0_V[31:0] (Read/Write)
  // 0x14 : reserved
  // 0x18 : Data signal of rule1_V
  //        bit 31~0 - rule1_V[31:0] (Read/Write)
  // 0x1c : reserved
  // 0x20 : Data signal of rule2_V
  //        bit 31~0 - rule2_V[31:0] (Read/Write)
  // 0x24 : reserved
  // 0x28 : Data signal of rule0cnt_V
  //        bit 31~0 - rule0cnt_V[31:0] (Read)
  // 0x2c : Control signal of rule0cnt_V
  //        bit 0  - rule0cnt_V_ap_vld (Read/COR)
  //        others - reserved
  // 0x30 : Data signal of rule1cnt_V
  //        bit 31~0 - rule1cnt_V[31:0] (Read)
  // 0x34 : Control signal of rule1cnt_V
  //        bit 0  - rule1cnt_V_ap_vld (Read/COR)
  //        others - reserved
  // 0x38 : Data signal of rule2cnt_V
  //        bit 31~0 - rule2cnt_V[31:0] (Read)
  // 0x3c : Control signal of rule2cnt_V
  //        bit 0  - rule2cnt_V_ap_vld (Read/COR)
  //        others - reserved
  // (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
  
  #define XMY_IP_HLS_PSAXILITE_ADDR_RULE0_V_DATA    0x10
  #define XMY_IP_HLS_PSAXILITE_BITS_RULE0_V_DATA    32
  #define XMY_IP_HLS_PSAXILITE_ADDR_RULE1_V_DATA    0x18
  #define XMY_IP_HLS_PSAXILITE_BITS_RULE1_V_DATA    32
  #define XMY_IP_HLS_PSAXILITE_ADDR_RULE2_V_DATA    0x20
  #define XMY_IP_HLS_PSAXILITE_BITS_RULE2_V_DATA    32
  #define XMY_IP_HLS_PSAXILITE_ADDR_RULE0CNT_V_DATA 0x28
  #define XMY_IP_HLS_PSAXILITE_BITS_RULE0CNT_V_DATA 32
  #define XMY_IP_HLS_PSAXILITE_ADDR_RULE0CNT_V_CTRL 0x2c
  #define XMY_IP_HLS_PSAXILITE_ADDR_RULE1CNT_V_DATA 0x30
  #define XMY_IP_HLS_PSAXILITE_BITS_RULE1CNT_V_DATA 32
  #define XMY_IP_HLS_PSAXILITE_ADDR_RULE1CNT_V_CTRL 0x34
  #define XMY_IP_HLS_PSAXILITE_ADDR_RULE2CNT_V_DATA 0x38
  #define XMY_IP_HLS_PSAXILITE_BITS_RULE2CNT_V_DATA 32
  #define XMY_IP_HLS_PSAXILITE_ADDR_RULE2CNT_V_CTRL 0x3c
  
  