text: DECL|ADC_AVGCTRL_ADJRES_Msk|macro|ADC_AVGCTRL_ADJRES_Msk
  DECL|ADC_AVGCTRL_ADJRES_Pos|macro|ADC_AVGCTRL_ADJRES_Pos
  DECL|ADC_AVGCTRL_ADJRES|macro|ADC_AVGCTRL_ADJRES
  DECL|ADC_AVGCTRL_MASK|macro|ADC_AVGCTRL_MASK
  DECL|ADC_AVGCTRL_OFFSET|macro|ADC_AVGCTRL_OFFSET
  DECL|ADC_AVGCTRL_RESETVALUE|macro|ADC_AVGCTRL_RESETVALUE
  DECL|ADC_AVGCTRL_SAMPLENUM_1024_Val|macro|ADC_AVGCTRL_SAMPLENUM_1024_Val
  DECL|ADC_AVGCTRL_SAMPLENUM_1024|macro|ADC_AVGCTRL_SAMPLENUM_1024
  DECL|ADC_AVGCTRL_SAMPLENUM_128_Val|macro|ADC_AVGCTRL_SAMPLENUM_128_Val
  DECL|ADC_AVGCTRL_SAMPLENUM_128|macro|ADC_AVGCTRL_SAMPLENUM_128
  DECL|ADC_AVGCTRL_SAMPLENUM_16_Val|macro|ADC_AVGCTRL_SAMPLENUM_16_Val
  DECL|ADC_AVGCTRL_SAMPLENUM_16|macro|ADC_AVGCTRL_SAMPLENUM_16
  DECL|ADC_AVGCTRL_SAMPLENUM_1_Val|macro|ADC_AVGCTRL_SAMPLENUM_1_Val
  DECL|ADC_AVGCTRL_SAMPLENUM_1|macro|ADC_AVGCTRL_SAMPLENUM_1
  DECL|ADC_AVGCTRL_SAMPLENUM_256_Val|macro|ADC_AVGCTRL_SAMPLENUM_256_Val
  DECL|ADC_AVGCTRL_SAMPLENUM_256|macro|ADC_AVGCTRL_SAMPLENUM_256
  DECL|ADC_AVGCTRL_SAMPLENUM_2_Val|macro|ADC_AVGCTRL_SAMPLENUM_2_Val
  DECL|ADC_AVGCTRL_SAMPLENUM_2|macro|ADC_AVGCTRL_SAMPLENUM_2
  DECL|ADC_AVGCTRL_SAMPLENUM_32_Val|macro|ADC_AVGCTRL_SAMPLENUM_32_Val
  DECL|ADC_AVGCTRL_SAMPLENUM_32|macro|ADC_AVGCTRL_SAMPLENUM_32
  DECL|ADC_AVGCTRL_SAMPLENUM_4_Val|macro|ADC_AVGCTRL_SAMPLENUM_4_Val
  DECL|ADC_AVGCTRL_SAMPLENUM_4|macro|ADC_AVGCTRL_SAMPLENUM_4
  DECL|ADC_AVGCTRL_SAMPLENUM_512_Val|macro|ADC_AVGCTRL_SAMPLENUM_512_Val
  DECL|ADC_AVGCTRL_SAMPLENUM_512|macro|ADC_AVGCTRL_SAMPLENUM_512
  DECL|ADC_AVGCTRL_SAMPLENUM_64_Val|macro|ADC_AVGCTRL_SAMPLENUM_64_Val
  DECL|ADC_AVGCTRL_SAMPLENUM_64|macro|ADC_AVGCTRL_SAMPLENUM_64
  DECL|ADC_AVGCTRL_SAMPLENUM_8_Val|macro|ADC_AVGCTRL_SAMPLENUM_8_Val
  DECL|ADC_AVGCTRL_SAMPLENUM_8|macro|ADC_AVGCTRL_SAMPLENUM_8
  DECL|ADC_AVGCTRL_SAMPLENUM_Msk|macro|ADC_AVGCTRL_SAMPLENUM_Msk
  DECL|ADC_AVGCTRL_SAMPLENUM_Pos|macro|ADC_AVGCTRL_SAMPLENUM_Pos
  DECL|ADC_AVGCTRL_SAMPLENUM|macro|ADC_AVGCTRL_SAMPLENUM
  DECL|ADC_AVGCTRL_Type|typedef|} ADC_AVGCTRL_Type;
  DECL|ADC_CALIB_BIAS_CAL_Msk|macro|ADC_CALIB_BIAS_CAL_Msk
  DECL|ADC_CALIB_BIAS_CAL_Pos|macro|ADC_CALIB_BIAS_CAL_Pos
  DECL|ADC_CALIB_BIAS_CAL|macro|ADC_CALIB_BIAS_CAL
  DECL|ADC_CALIB_LINEARITY_CAL_Msk|macro|ADC_CALIB_LINEARITY_CAL_Msk
  DECL|ADC_CALIB_LINEARITY_CAL_Pos|macro|ADC_CALIB_LINEARITY_CAL_Pos
  DECL|ADC_CALIB_LINEARITY_CAL|macro|ADC_CALIB_LINEARITY_CAL
  DECL|ADC_CALIB_MASK|macro|ADC_CALIB_MASK
  DECL|ADC_CALIB_OFFSET|macro|ADC_CALIB_OFFSET
  DECL|ADC_CALIB_RESETVALUE|macro|ADC_CALIB_RESETVALUE
  DECL|ADC_CALIB_Type|typedef|} ADC_CALIB_Type;
  DECL|ADC_CTRLA_ENABLE_Pos|macro|ADC_CTRLA_ENABLE_Pos
  DECL|ADC_CTRLA_ENABLE|macro|ADC_CTRLA_ENABLE
  DECL|ADC_CTRLA_MASK|macro|ADC_CTRLA_MASK
  DECL|ADC_CTRLA_OFFSET|macro|ADC_CTRLA_OFFSET
  DECL|ADC_CTRLA_RESETVALUE|macro|ADC_CTRLA_RESETVALUE
  DECL|ADC_CTRLA_RUNSTDBY_Pos|macro|ADC_CTRLA_RUNSTDBY_Pos
  DECL|ADC_CTRLA_RUNSTDBY|macro|ADC_CTRLA_RUNSTDBY
  DECL|ADC_CTRLA_SWRST_Pos|macro|ADC_CTRLA_SWRST_Pos
  DECL|ADC_CTRLA_SWRST|macro|ADC_CTRLA_SWRST
  DECL|ADC_CTRLA_Type|typedef|} ADC_CTRLA_Type;
  DECL|ADC_CTRLB_CORREN_Pos|macro|ADC_CTRLB_CORREN_Pos
  DECL|ADC_CTRLB_CORREN|macro|ADC_CTRLB_CORREN
  DECL|ADC_CTRLB_DIFFMODE_Pos|macro|ADC_CTRLB_DIFFMODE_Pos
  DECL|ADC_CTRLB_DIFFMODE|macro|ADC_CTRLB_DIFFMODE
  DECL|ADC_CTRLB_FREERUN_Pos|macro|ADC_CTRLB_FREERUN_Pos
  DECL|ADC_CTRLB_FREERUN|macro|ADC_CTRLB_FREERUN
  DECL|ADC_CTRLB_LEFTADJ_Pos|macro|ADC_CTRLB_LEFTADJ_Pos
  DECL|ADC_CTRLB_LEFTADJ|macro|ADC_CTRLB_LEFTADJ
  DECL|ADC_CTRLB_MASK|macro|ADC_CTRLB_MASK
  DECL|ADC_CTRLB_OFFSET|macro|ADC_CTRLB_OFFSET
  DECL|ADC_CTRLB_PRESCALER_DIV128_Val|macro|ADC_CTRLB_PRESCALER_DIV128_Val
  DECL|ADC_CTRLB_PRESCALER_DIV128|macro|ADC_CTRLB_PRESCALER_DIV128
  DECL|ADC_CTRLB_PRESCALER_DIV16_Val|macro|ADC_CTRLB_PRESCALER_DIV16_Val
  DECL|ADC_CTRLB_PRESCALER_DIV16|macro|ADC_CTRLB_PRESCALER_DIV16
  DECL|ADC_CTRLB_PRESCALER_DIV256_Val|macro|ADC_CTRLB_PRESCALER_DIV256_Val
  DECL|ADC_CTRLB_PRESCALER_DIV256|macro|ADC_CTRLB_PRESCALER_DIV256
  DECL|ADC_CTRLB_PRESCALER_DIV32_Val|macro|ADC_CTRLB_PRESCALER_DIV32_Val
  DECL|ADC_CTRLB_PRESCALER_DIV32|macro|ADC_CTRLB_PRESCALER_DIV32
  DECL|ADC_CTRLB_PRESCALER_DIV4_Val|macro|ADC_CTRLB_PRESCALER_DIV4_Val
  DECL|ADC_CTRLB_PRESCALER_DIV4|macro|ADC_CTRLB_PRESCALER_DIV4
  DECL|ADC_CTRLB_PRESCALER_DIV512_Val|macro|ADC_CTRLB_PRESCALER_DIV512_Val
  DECL|ADC_CTRLB_PRESCALER_DIV512|macro|ADC_CTRLB_PRESCALER_DIV512
  DECL|ADC_CTRLB_PRESCALER_DIV64_Val|macro|ADC_CTRLB_PRESCALER_DIV64_Val
  DECL|ADC_CTRLB_PRESCALER_DIV64|macro|ADC_CTRLB_PRESCALER_DIV64
  DECL|ADC_CTRLB_PRESCALER_DIV8_Val|macro|ADC_CTRLB_PRESCALER_DIV8_Val
  DECL|ADC_CTRLB_PRESCALER_DIV8|macro|ADC_CTRLB_PRESCALER_DIV8
  DECL|ADC_CTRLB_PRESCALER_Msk|macro|ADC_CTRLB_PRESCALER_Msk
  DECL|ADC_CTRLB_PRESCALER_Pos|macro|ADC_CTRLB_PRESCALER_Pos
  DECL|ADC_CTRLB_PRESCALER|macro|ADC_CTRLB_PRESCALER
  DECL|ADC_CTRLB_RESETVALUE|macro|ADC_CTRLB_RESETVALUE
  DECL|ADC_CTRLB_RESSEL_10BIT_Val|macro|ADC_CTRLB_RESSEL_10BIT_Val
  DECL|ADC_CTRLB_RESSEL_10BIT|macro|ADC_CTRLB_RESSEL_10BIT
  DECL|ADC_CTRLB_RESSEL_12BIT_Val|macro|ADC_CTRLB_RESSEL_12BIT_Val
  DECL|ADC_CTRLB_RESSEL_12BIT|macro|ADC_CTRLB_RESSEL_12BIT
  DECL|ADC_CTRLB_RESSEL_16BIT_Val|macro|ADC_CTRLB_RESSEL_16BIT_Val
  DECL|ADC_CTRLB_RESSEL_16BIT|macro|ADC_CTRLB_RESSEL_16BIT
  DECL|ADC_CTRLB_RESSEL_8BIT_Val|macro|ADC_CTRLB_RESSEL_8BIT_Val
  DECL|ADC_CTRLB_RESSEL_8BIT|macro|ADC_CTRLB_RESSEL_8BIT
  DECL|ADC_CTRLB_RESSEL_Msk|macro|ADC_CTRLB_RESSEL_Msk
  DECL|ADC_CTRLB_RESSEL_Pos|macro|ADC_CTRLB_RESSEL_Pos
  DECL|ADC_CTRLB_RESSEL|macro|ADC_CTRLB_RESSEL
  DECL|ADC_CTRLB_Type|typedef|} ADC_CTRLB_Type;
  DECL|ADC_DBGCTRL_DBGRUN_Pos|macro|ADC_DBGCTRL_DBGRUN_Pos
  DECL|ADC_DBGCTRL_DBGRUN|macro|ADC_DBGCTRL_DBGRUN
  DECL|ADC_DBGCTRL_MASK|macro|ADC_DBGCTRL_MASK
  DECL|ADC_DBGCTRL_OFFSET|macro|ADC_DBGCTRL_OFFSET
  DECL|ADC_DBGCTRL_RESETVALUE|macro|ADC_DBGCTRL_RESETVALUE
  DECL|ADC_DBGCTRL_Type|typedef|} ADC_DBGCTRL_Type;
  DECL|ADC_EVCTRL_MASK|macro|ADC_EVCTRL_MASK
  DECL|ADC_EVCTRL_OFFSET|macro|ADC_EVCTRL_OFFSET
  DECL|ADC_EVCTRL_RESETVALUE|macro|ADC_EVCTRL_RESETVALUE
  DECL|ADC_EVCTRL_RESRDYEO_Pos|macro|ADC_EVCTRL_RESRDYEO_Pos
  DECL|ADC_EVCTRL_RESRDYEO|macro|ADC_EVCTRL_RESRDYEO
  DECL|ADC_EVCTRL_STARTEI_Pos|macro|ADC_EVCTRL_STARTEI_Pos
  DECL|ADC_EVCTRL_STARTEI|macro|ADC_EVCTRL_STARTEI
  DECL|ADC_EVCTRL_SYNCEI_Pos|macro|ADC_EVCTRL_SYNCEI_Pos
  DECL|ADC_EVCTRL_SYNCEI|macro|ADC_EVCTRL_SYNCEI
  DECL|ADC_EVCTRL_Type|typedef|} ADC_EVCTRL_Type;
  DECL|ADC_EVCTRL_WINMONEO_Pos|macro|ADC_EVCTRL_WINMONEO_Pos
  DECL|ADC_EVCTRL_WINMONEO|macro|ADC_EVCTRL_WINMONEO
  DECL|ADC_GAINCORR_GAINCORR_Msk|macro|ADC_GAINCORR_GAINCORR_Msk
  DECL|ADC_GAINCORR_GAINCORR_Pos|macro|ADC_GAINCORR_GAINCORR_Pos
  DECL|ADC_GAINCORR_GAINCORR|macro|ADC_GAINCORR_GAINCORR
  DECL|ADC_GAINCORR_MASK|macro|ADC_GAINCORR_MASK
  DECL|ADC_GAINCORR_OFFSET|macro|ADC_GAINCORR_OFFSET
  DECL|ADC_GAINCORR_RESETVALUE|macro|ADC_GAINCORR_RESETVALUE
  DECL|ADC_GAINCORR_Type|typedef|} ADC_GAINCORR_Type;
  DECL|ADC_INPUTCTRL_GAIN_16X_Val|macro|ADC_INPUTCTRL_GAIN_16X_Val
  DECL|ADC_INPUTCTRL_GAIN_16X|macro|ADC_INPUTCTRL_GAIN_16X
  DECL|ADC_INPUTCTRL_GAIN_1X_Val|macro|ADC_INPUTCTRL_GAIN_1X_Val
  DECL|ADC_INPUTCTRL_GAIN_1X|macro|ADC_INPUTCTRL_GAIN_1X
  DECL|ADC_INPUTCTRL_GAIN_2X_Val|macro|ADC_INPUTCTRL_GAIN_2X_Val
  DECL|ADC_INPUTCTRL_GAIN_2X|macro|ADC_INPUTCTRL_GAIN_2X
  DECL|ADC_INPUTCTRL_GAIN_4X_Val|macro|ADC_INPUTCTRL_GAIN_4X_Val
  DECL|ADC_INPUTCTRL_GAIN_4X|macro|ADC_INPUTCTRL_GAIN_4X
  DECL|ADC_INPUTCTRL_GAIN_8X_Val|macro|ADC_INPUTCTRL_GAIN_8X_Val
  DECL|ADC_INPUTCTRL_GAIN_8X|macro|ADC_INPUTCTRL_GAIN_8X
  DECL|ADC_INPUTCTRL_GAIN_DIV2_Val|macro|ADC_INPUTCTRL_GAIN_DIV2_Val
  DECL|ADC_INPUTCTRL_GAIN_DIV2|macro|ADC_INPUTCTRL_GAIN_DIV2
  DECL|ADC_INPUTCTRL_GAIN_Msk|macro|ADC_INPUTCTRL_GAIN_Msk
  DECL|ADC_INPUTCTRL_GAIN_Pos|macro|ADC_INPUTCTRL_GAIN_Pos
  DECL|ADC_INPUTCTRL_GAIN|macro|ADC_INPUTCTRL_GAIN
  DECL|ADC_INPUTCTRL_INPUTOFFSET_Msk|macro|ADC_INPUTCTRL_INPUTOFFSET_Msk
  DECL|ADC_INPUTCTRL_INPUTOFFSET_Pos|macro|ADC_INPUTCTRL_INPUTOFFSET_Pos
  DECL|ADC_INPUTCTRL_INPUTOFFSET|macro|ADC_INPUTCTRL_INPUTOFFSET
  DECL|ADC_INPUTCTRL_INPUTSCAN_Msk|macro|ADC_INPUTCTRL_INPUTSCAN_Msk
  DECL|ADC_INPUTCTRL_INPUTSCAN_Pos|macro|ADC_INPUTCTRL_INPUTSCAN_Pos
  DECL|ADC_INPUTCTRL_INPUTSCAN|macro|ADC_INPUTCTRL_INPUTSCAN
  DECL|ADC_INPUTCTRL_MASK|macro|ADC_INPUTCTRL_MASK
  DECL|ADC_INPUTCTRL_MUXNEG_GND_Val|macro|ADC_INPUTCTRL_MUXNEG_GND_Val
  DECL|ADC_INPUTCTRL_MUXNEG_GND|macro|ADC_INPUTCTRL_MUXNEG_GND
  DECL|ADC_INPUTCTRL_MUXNEG_IOGND_Val|macro|ADC_INPUTCTRL_MUXNEG_IOGND_Val
  DECL|ADC_INPUTCTRL_MUXNEG_IOGND|macro|ADC_INPUTCTRL_MUXNEG_IOGND
  DECL|ADC_INPUTCTRL_MUXNEG_Msk|macro|ADC_INPUTCTRL_MUXNEG_Msk
  DECL|ADC_INPUTCTRL_MUXNEG_PIN0_Val|macro|ADC_INPUTCTRL_MUXNEG_PIN0_Val
  DECL|ADC_INPUTCTRL_MUXNEG_PIN0|macro|ADC_INPUTCTRL_MUXNEG_PIN0
  DECL|ADC_INPUTCTRL_MUXNEG_PIN1_Val|macro|ADC_INPUTCTRL_MUXNEG_PIN1_Val
  DECL|ADC_INPUTCTRL_MUXNEG_PIN1|macro|ADC_INPUTCTRL_MUXNEG_PIN1
  DECL|ADC_INPUTCTRL_MUXNEG_PIN2_Val|macro|ADC_INPUTCTRL_MUXNEG_PIN2_Val
  DECL|ADC_INPUTCTRL_MUXNEG_PIN2|macro|ADC_INPUTCTRL_MUXNEG_PIN2
  DECL|ADC_INPUTCTRL_MUXNEG_PIN3_Val|macro|ADC_INPUTCTRL_MUXNEG_PIN3_Val
  DECL|ADC_INPUTCTRL_MUXNEG_PIN3|macro|ADC_INPUTCTRL_MUXNEG_PIN3
  DECL|ADC_INPUTCTRL_MUXNEG_PIN4_Val|macro|ADC_INPUTCTRL_MUXNEG_PIN4_Val
  DECL|ADC_INPUTCTRL_MUXNEG_PIN4|macro|ADC_INPUTCTRL_MUXNEG_PIN4
  DECL|ADC_INPUTCTRL_MUXNEG_PIN5_Val|macro|ADC_INPUTCTRL_MUXNEG_PIN5_Val
  DECL|ADC_INPUTCTRL_MUXNEG_PIN5|macro|ADC_INPUTCTRL_MUXNEG_PIN5
  DECL|ADC_INPUTCTRL_MUXNEG_PIN6_Val|macro|ADC_INPUTCTRL_MUXNEG_PIN6_Val
  DECL|ADC_INPUTCTRL_MUXNEG_PIN6|macro|ADC_INPUTCTRL_MUXNEG_PIN6
  DECL|ADC_INPUTCTRL_MUXNEG_PIN7_Val|macro|ADC_INPUTCTRL_MUXNEG_PIN7_Val
  DECL|ADC_INPUTCTRL_MUXNEG_PIN7|macro|ADC_INPUTCTRL_MUXNEG_PIN7
  DECL|ADC_INPUTCTRL_MUXNEG_Pos|macro|ADC_INPUTCTRL_MUXNEG_Pos
  DECL|ADC_INPUTCTRL_MUXNEG|macro|ADC_INPUTCTRL_MUXNEG
  DECL|ADC_INPUTCTRL_MUXPOS_BANDGAP_Val|macro|ADC_INPUTCTRL_MUXPOS_BANDGAP_Val
  DECL|ADC_INPUTCTRL_MUXPOS_BANDGAP|macro|ADC_INPUTCTRL_MUXPOS_BANDGAP
  DECL|ADC_INPUTCTRL_MUXPOS_DAC_Val|macro|ADC_INPUTCTRL_MUXPOS_DAC_Val
  DECL|ADC_INPUTCTRL_MUXPOS_DAC|macro|ADC_INPUTCTRL_MUXPOS_DAC
  DECL|ADC_INPUTCTRL_MUXPOS_Msk|macro|ADC_INPUTCTRL_MUXPOS_Msk
  DECL|ADC_INPUTCTRL_MUXPOS_PIN0_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN0_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN0|macro|ADC_INPUTCTRL_MUXPOS_PIN0
  DECL|ADC_INPUTCTRL_MUXPOS_PIN10_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN10_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN10|macro|ADC_INPUTCTRL_MUXPOS_PIN10
  DECL|ADC_INPUTCTRL_MUXPOS_PIN11_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN11_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN11|macro|ADC_INPUTCTRL_MUXPOS_PIN11
  DECL|ADC_INPUTCTRL_MUXPOS_PIN12_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN12_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN12|macro|ADC_INPUTCTRL_MUXPOS_PIN12
  DECL|ADC_INPUTCTRL_MUXPOS_PIN13_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN13_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN13|macro|ADC_INPUTCTRL_MUXPOS_PIN13
  DECL|ADC_INPUTCTRL_MUXPOS_PIN14_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN14_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN14|macro|ADC_INPUTCTRL_MUXPOS_PIN14
  DECL|ADC_INPUTCTRL_MUXPOS_PIN15_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN15_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN15|macro|ADC_INPUTCTRL_MUXPOS_PIN15
  DECL|ADC_INPUTCTRL_MUXPOS_PIN16_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN16_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN16|macro|ADC_INPUTCTRL_MUXPOS_PIN16
  DECL|ADC_INPUTCTRL_MUXPOS_PIN17_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN17_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN17|macro|ADC_INPUTCTRL_MUXPOS_PIN17
  DECL|ADC_INPUTCTRL_MUXPOS_PIN18_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN18_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN18|macro|ADC_INPUTCTRL_MUXPOS_PIN18
  DECL|ADC_INPUTCTRL_MUXPOS_PIN19_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN19_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN19|macro|ADC_INPUTCTRL_MUXPOS_PIN19
  DECL|ADC_INPUTCTRL_MUXPOS_PIN1_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN1_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN1|macro|ADC_INPUTCTRL_MUXPOS_PIN1
  DECL|ADC_INPUTCTRL_MUXPOS_PIN2_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN2_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN2|macro|ADC_INPUTCTRL_MUXPOS_PIN2
  DECL|ADC_INPUTCTRL_MUXPOS_PIN3_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN3_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN3|macro|ADC_INPUTCTRL_MUXPOS_PIN3
  DECL|ADC_INPUTCTRL_MUXPOS_PIN4_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN4_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN4|macro|ADC_INPUTCTRL_MUXPOS_PIN4
  DECL|ADC_INPUTCTRL_MUXPOS_PIN5_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN5_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN5|macro|ADC_INPUTCTRL_MUXPOS_PIN5
  DECL|ADC_INPUTCTRL_MUXPOS_PIN6_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN6_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN6|macro|ADC_INPUTCTRL_MUXPOS_PIN6
  DECL|ADC_INPUTCTRL_MUXPOS_PIN7_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN7_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN7|macro|ADC_INPUTCTRL_MUXPOS_PIN7
  DECL|ADC_INPUTCTRL_MUXPOS_PIN8_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN8_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN8|macro|ADC_INPUTCTRL_MUXPOS_PIN8
  DECL|ADC_INPUTCTRL_MUXPOS_PIN9_Val|macro|ADC_INPUTCTRL_MUXPOS_PIN9_Val
  DECL|ADC_INPUTCTRL_MUXPOS_PIN9|macro|ADC_INPUTCTRL_MUXPOS_PIN9
  DECL|ADC_INPUTCTRL_MUXPOS_Pos|macro|ADC_INPUTCTRL_MUXPOS_Pos
  DECL|ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val|macro|ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val
  DECL|ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC|macro|ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC
  DECL|ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val|macro|ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val
  DECL|ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC|macro|ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC
  DECL|ADC_INPUTCTRL_MUXPOS_TEMP_Val|macro|ADC_INPUTCTRL_MUXPOS_TEMP_Val
  DECL|ADC_INPUTCTRL_MUXPOS_TEMP|macro|ADC_INPUTCTRL_MUXPOS_TEMP
  DECL|ADC_INPUTCTRL_MUXPOS|macro|ADC_INPUTCTRL_MUXPOS
  DECL|ADC_INPUTCTRL_OFFSET|macro|ADC_INPUTCTRL_OFFSET
  DECL|ADC_INPUTCTRL_RESETVALUE|macro|ADC_INPUTCTRL_RESETVALUE
  DECL|ADC_INPUTCTRL_Type|typedef|} ADC_INPUTCTRL_Type;
  DECL|ADC_INTENCLR_MASK|macro|ADC_INTENCLR_MASK
  DECL|ADC_INTENCLR_OFFSET|macro|ADC_INTENCLR_OFFSET
  DECL|ADC_INTENCLR_OVERRUN_Pos|macro|ADC_INTENCLR_OVERRUN_Pos
  DECL|ADC_INTENCLR_OVERRUN|macro|ADC_INTENCLR_OVERRUN
  DECL|ADC_INTENCLR_RESETVALUE|macro|ADC_INTENCLR_RESETVALUE
  DECL|ADC_INTENCLR_RESRDY_Pos|macro|ADC_INTENCLR_RESRDY_Pos
  DECL|ADC_INTENCLR_RESRDY|macro|ADC_INTENCLR_RESRDY
  DECL|ADC_INTENCLR_SYNCRDY_Pos|macro|ADC_INTENCLR_SYNCRDY_Pos
  DECL|ADC_INTENCLR_SYNCRDY|macro|ADC_INTENCLR_SYNCRDY
  DECL|ADC_INTENCLR_Type|typedef|} ADC_INTENCLR_Type;
  DECL|ADC_INTENCLR_WINMON_Pos|macro|ADC_INTENCLR_WINMON_Pos
  DECL|ADC_INTENCLR_WINMON|macro|ADC_INTENCLR_WINMON
  DECL|ADC_INTENSET_MASK|macro|ADC_INTENSET_MASK
  DECL|ADC_INTENSET_OFFSET|macro|ADC_INTENSET_OFFSET
  DECL|ADC_INTENSET_OVERRUN_Pos|macro|ADC_INTENSET_OVERRUN_Pos
  DECL|ADC_INTENSET_OVERRUN|macro|ADC_INTENSET_OVERRUN
  DECL|ADC_INTENSET_RESETVALUE|macro|ADC_INTENSET_RESETVALUE
  DECL|ADC_INTENSET_RESRDY_Pos|macro|ADC_INTENSET_RESRDY_Pos
  DECL|ADC_INTENSET_RESRDY|macro|ADC_INTENSET_RESRDY
  DECL|ADC_INTENSET_SYNCRDY_Pos|macro|ADC_INTENSET_SYNCRDY_Pos
  DECL|ADC_INTENSET_SYNCRDY|macro|ADC_INTENSET_SYNCRDY
  DECL|ADC_INTENSET_Type|typedef|} ADC_INTENSET_Type;
  DECL|ADC_INTENSET_WINMON_Pos|macro|ADC_INTENSET_WINMON_Pos
  DECL|ADC_INTENSET_WINMON|macro|ADC_INTENSET_WINMON
  DECL|ADC_INTFLAG_MASK|macro|ADC_INTFLAG_MASK
  DECL|ADC_INTFLAG_OFFSET|macro|ADC_INTFLAG_OFFSET
  DECL|ADC_INTFLAG_OVERRUN_Pos|macro|ADC_INTFLAG_OVERRUN_Pos
  DECL|ADC_INTFLAG_OVERRUN|macro|ADC_INTFLAG_OVERRUN
  DECL|ADC_INTFLAG_RESETVALUE|macro|ADC_INTFLAG_RESETVALUE
  DECL|ADC_INTFLAG_RESRDY_Pos|macro|ADC_INTFLAG_RESRDY_Pos
  DECL|ADC_INTFLAG_RESRDY|macro|ADC_INTFLAG_RESRDY
  DECL|ADC_INTFLAG_SYNCRDY_Pos|macro|ADC_INTFLAG_SYNCRDY_Pos
  DECL|ADC_INTFLAG_SYNCRDY|macro|ADC_INTFLAG_SYNCRDY
  DECL|ADC_INTFLAG_Type|typedef|} ADC_INTFLAG_Type;
  DECL|ADC_INTFLAG_WINMON_Pos|macro|ADC_INTFLAG_WINMON_Pos
  DECL|ADC_INTFLAG_WINMON|macro|ADC_INTFLAG_WINMON
  DECL|ADC_OFFSETCORR_MASK|macro|ADC_OFFSETCORR_MASK
  DECL|ADC_OFFSETCORR_OFFSETCORR_Msk|macro|ADC_OFFSETCORR_OFFSETCORR_Msk
  DECL|ADC_OFFSETCORR_OFFSETCORR_Pos|macro|ADC_OFFSETCORR_OFFSETCORR_Pos
  DECL|ADC_OFFSETCORR_OFFSETCORR|macro|ADC_OFFSETCORR_OFFSETCORR
  DECL|ADC_OFFSETCORR_OFFSET|macro|ADC_OFFSETCORR_OFFSET
  DECL|ADC_OFFSETCORR_RESETVALUE|macro|ADC_OFFSETCORR_RESETVALUE
  DECL|ADC_OFFSETCORR_Type|typedef|} ADC_OFFSETCORR_Type;
  DECL|ADC_REFCTRL_MASK|macro|ADC_REFCTRL_MASK
  DECL|ADC_REFCTRL_OFFSET|macro|ADC_REFCTRL_OFFSET
  DECL|ADC_REFCTRL_REFCOMP_Pos|macro|ADC_REFCTRL_REFCOMP_Pos
  DECL|ADC_REFCTRL_REFCOMP|macro|ADC_REFCTRL_REFCOMP
  DECL|ADC_REFCTRL_REFSEL_AREFA_Val|macro|ADC_REFCTRL_REFSEL_AREFA_Val
  DECL|ADC_REFCTRL_REFSEL_AREFA|macro|ADC_REFCTRL_REFSEL_AREFA
  DECL|ADC_REFCTRL_REFSEL_AREFB_Val|macro|ADC_REFCTRL_REFSEL_AREFB_Val
  DECL|ADC_REFCTRL_REFSEL_AREFB|macro|ADC_REFCTRL_REFSEL_AREFB
  DECL|ADC_REFCTRL_REFSEL_INT1V_Val|macro|ADC_REFCTRL_REFSEL_INT1V_Val
  DECL|ADC_REFCTRL_REFSEL_INT1V|macro|ADC_REFCTRL_REFSEL_INT1V
  DECL|ADC_REFCTRL_REFSEL_INTVCC0_Val|macro|ADC_REFCTRL_REFSEL_INTVCC0_Val
  DECL|ADC_REFCTRL_REFSEL_INTVCC0|macro|ADC_REFCTRL_REFSEL_INTVCC0
  DECL|ADC_REFCTRL_REFSEL_INTVCC1_Val|macro|ADC_REFCTRL_REFSEL_INTVCC1_Val
  DECL|ADC_REFCTRL_REFSEL_INTVCC1|macro|ADC_REFCTRL_REFSEL_INTVCC1
  DECL|ADC_REFCTRL_REFSEL_Msk|macro|ADC_REFCTRL_REFSEL_Msk
  DECL|ADC_REFCTRL_REFSEL_Pos|macro|ADC_REFCTRL_REFSEL_Pos
  DECL|ADC_REFCTRL_REFSEL|macro|ADC_REFCTRL_REFSEL
  DECL|ADC_REFCTRL_RESETVALUE|macro|ADC_REFCTRL_RESETVALUE
  DECL|ADC_REFCTRL_Type|typedef|} ADC_REFCTRL_Type;
  DECL|ADC_RESULT_MASK|macro|ADC_RESULT_MASK
  DECL|ADC_RESULT_OFFSET|macro|ADC_RESULT_OFFSET
  DECL|ADC_RESULT_RESETVALUE|macro|ADC_RESULT_RESETVALUE
  DECL|ADC_RESULT_RESULT_Msk|macro|ADC_RESULT_RESULT_Msk
  DECL|ADC_RESULT_RESULT_Pos|macro|ADC_RESULT_RESULT_Pos
  DECL|ADC_RESULT_RESULT|macro|ADC_RESULT_RESULT
  DECL|ADC_RESULT_Type|typedef|} ADC_RESULT_Type;
  DECL|ADC_SAMPCTRL_MASK|macro|ADC_SAMPCTRL_MASK
  DECL|ADC_SAMPCTRL_OFFSET|macro|ADC_SAMPCTRL_OFFSET
  DECL|ADC_SAMPCTRL_RESETVALUE|macro|ADC_SAMPCTRL_RESETVALUE
  DECL|ADC_SAMPCTRL_SAMPLEN_Msk|macro|ADC_SAMPCTRL_SAMPLEN_Msk
  DECL|ADC_SAMPCTRL_SAMPLEN_Pos|macro|ADC_SAMPCTRL_SAMPLEN_Pos
  DECL|ADC_SAMPCTRL_SAMPLEN|macro|ADC_SAMPCTRL_SAMPLEN
  DECL|ADC_SAMPCTRL_Type|typedef|} ADC_SAMPCTRL_Type;
  DECL|ADC_STATUS_MASK|macro|ADC_STATUS_MASK
  DECL|ADC_STATUS_OFFSET|macro|ADC_STATUS_OFFSET
  DECL|ADC_STATUS_RESETVALUE|macro|ADC_STATUS_RESETVALUE
  DECL|ADC_STATUS_SYNCBUSY_Pos|macro|ADC_STATUS_SYNCBUSY_Pos
  DECL|ADC_STATUS_SYNCBUSY|macro|ADC_STATUS_SYNCBUSY
  DECL|ADC_STATUS_Type|typedef|} ADC_STATUS_Type;
  DECL|ADC_SWTRIG_FLUSH_Pos|macro|ADC_SWTRIG_FLUSH_Pos
  DECL|ADC_SWTRIG_FLUSH|macro|ADC_SWTRIG_FLUSH
  DECL|ADC_SWTRIG_MASK|macro|ADC_SWTRIG_MASK
  DECL|ADC_SWTRIG_OFFSET|macro|ADC_SWTRIG_OFFSET
  DECL|ADC_SWTRIG_RESETVALUE|macro|ADC_SWTRIG_RESETVALUE
  DECL|ADC_SWTRIG_START_Pos|macro|ADC_SWTRIG_START_Pos
  DECL|ADC_SWTRIG_START|macro|ADC_SWTRIG_START
  DECL|ADC_SWTRIG_Type|typedef|} ADC_SWTRIG_Type;
  DECL|ADC_U2204|macro|ADC_U2204
  DECL|ADC_WINCTRL_MASK|macro|ADC_WINCTRL_MASK
  DECL|ADC_WINCTRL_OFFSET|macro|ADC_WINCTRL_OFFSET
  DECL|ADC_WINCTRL_RESETVALUE|macro|ADC_WINCTRL_RESETVALUE
  DECL|ADC_WINCTRL_Type|typedef|} ADC_WINCTRL_Type;
  DECL|ADC_WINCTRL_WINMODE_DISABLE_Val|macro|ADC_WINCTRL_WINMODE_DISABLE_Val
  DECL|ADC_WINCTRL_WINMODE_DISABLE|macro|ADC_WINCTRL_WINMODE_DISABLE
  DECL|ADC_WINCTRL_WINMODE_MODE1_Val|macro|ADC_WINCTRL_WINMODE_MODE1_Val
  DECL|ADC_WINCTRL_WINMODE_MODE1|macro|ADC_WINCTRL_WINMODE_MODE1
  DECL|ADC_WINCTRL_WINMODE_MODE2_Val|macro|ADC_WINCTRL_WINMODE_MODE2_Val
  DECL|ADC_WINCTRL_WINMODE_MODE2|macro|ADC_WINCTRL_WINMODE_MODE2
  DECL|ADC_WINCTRL_WINMODE_MODE3_Val|macro|ADC_WINCTRL_WINMODE_MODE3_Val
  DECL|ADC_WINCTRL_WINMODE_MODE3|macro|ADC_WINCTRL_WINMODE_MODE3
  DECL|ADC_WINCTRL_WINMODE_MODE4_Val|macro|ADC_WINCTRL_WINMODE_MODE4_Val
  DECL|ADC_WINCTRL_WINMODE_MODE4|macro|ADC_WINCTRL_WINMODE_MODE4
  DECL|ADC_WINCTRL_WINMODE_Msk|macro|ADC_WINCTRL_WINMODE_Msk
  DECL|ADC_WINCTRL_WINMODE_Pos|macro|ADC_WINCTRL_WINMODE_Pos
  DECL|ADC_WINCTRL_WINMODE|macro|ADC_WINCTRL_WINMODE
  DECL|ADC_WINLT_MASK|macro|ADC_WINLT_MASK
  DECL|ADC_WINLT_OFFSET|macro|ADC_WINLT_OFFSET
  DECL|ADC_WINLT_RESETVALUE|macro|ADC_WINLT_RESETVALUE
  DECL|ADC_WINLT_Type|typedef|} ADC_WINLT_Type;
  DECL|ADC_WINLT_WINLT_Msk|macro|ADC_WINLT_WINLT_Msk
  DECL|ADC_WINLT_WINLT_Pos|macro|ADC_WINLT_WINLT_Pos
  DECL|ADC_WINLT_WINLT|macro|ADC_WINLT_WINLT
  DECL|ADC_WINUT_MASK|macro|ADC_WINUT_MASK
  DECL|ADC_WINUT_OFFSET|macro|ADC_WINUT_OFFSET
  DECL|ADC_WINUT_RESETVALUE|macro|ADC_WINUT_RESETVALUE
  DECL|ADC_WINUT_Type|typedef|} ADC_WINUT_Type;
  DECL|ADC_WINUT_WINUT_Msk|macro|ADC_WINUT_WINUT_Msk
  DECL|ADC_WINUT_WINUT_Pos|macro|ADC_WINUT_WINUT_Pos
  DECL|ADC_WINUT_WINUT|macro|ADC_WINUT_WINUT
  DECL|ADJRES|member|uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
  DECL|AVGCTRL|member|__IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
  DECL|Adc|typedef|} Adc;
  DECL|BIAS_CAL|member|uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
  DECL|CALIB|member|__IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
  DECL|CORREN|member|uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
  DECL|CTRLA|member|__IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
  DECL|CTRLB|member|__IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
  DECL|DBGCTRL|member|__IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
  DECL|DBGRUN|member|uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
  DECL|DIFFMODE|member|uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
  DECL|ENABLE|member|uint8_t ENABLE:1; /*!< bit: 1 Enable */
  DECL|EVCTRL|member|__IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
  DECL|FLUSH|member|uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
  DECL|FREERUN|member|uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
  DECL|GAINCORR|member|__IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
  DECL|GAINCORR|member|uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
  DECL|GAIN|member|uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
  DECL|INPUTCTRL|member|__IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Inputs Control */
  DECL|INPUTOFFSET|member|uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive MUX Setting Offset */
  DECL|INPUTSCAN|member|uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
  DECL|INTENCLR|member|__IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
  DECL|INTENSET|member|__IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
  DECL|INTFLAG|member|__IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
  DECL|LEFTADJ|member|uint16_t LEFTADJ:1; /*!< bit: 1 Left Adjusted Result */
  DECL|LINEARITY_CAL|member|uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
  DECL|MUXNEG|member|uint32_t MUXNEG:5; /*!< bit: 8..12 Negative MUX Input Selection */
  DECL|MUXPOS|member|uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive MUX Input Selection */
  DECL|OFFSETCORR|member|__IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
  DECL|OFFSETCORR|member|uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
  DECL|OVERRUN|member|__I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
  DECL|OVERRUN|member|uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
  DECL|OVERRUN|member|uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
  DECL|PRESCALER|member|uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
  DECL|REFCOMP|member|uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
  DECL|REFCTRL|member|__IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
  DECL|REFSEL|member|uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
  DECL|RESRDYEO|member|uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
  DECL|RESRDY|member|__I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
  DECL|RESRDY|member|uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
  DECL|RESRDY|member|uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
  DECL|RESSEL|member|uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
  DECL|RESULT|member|__I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
  DECL|RESULT|member|uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
  DECL|REV_ADC|macro|REV_ADC
  DECL|RUNSTDBY|member|uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
  DECL|Reserved1|member|RoReg8 Reserved1[0x2];
  DECL|Reserved2|member|RoReg8 Reserved2[0x3];
  DECL|Reserved3|member|RoReg8 Reserved3[0x3];
  DECL|Reserved4|member|RoReg8 Reserved4[0x1];
  DECL|Reserved5|member|RoReg8 Reserved5[0x2];
  DECL|Reserved6|member|RoReg8 Reserved6[0x2];
  DECL|SAMPCTRL|member|__IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
  DECL|SAMPLENUM|member|uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
  DECL|SAMPLEN|member|uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
  DECL|STARTEI|member|uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
  DECL|START|member|uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
  DECL|STATUS|member|__I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
  DECL|SWRST|member|uint8_t SWRST:1; /*!< bit: 0 Software Reset */
  DECL|SWTRIG|member|__IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
  DECL|SYNCBUSY|member|uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
  DECL|SYNCEI|member|uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
  DECL|SYNCRDY|member|__I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
  DECL|SYNCRDY|member|uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
  DECL|SYNCRDY|member|uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
  DECL|WINCTRL|member|__IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
  DECL|WINLT|member|__IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
  DECL|WINLT|member|uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
  DECL|WINMODE|member|uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
  DECL|WINMONEO|member|uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
  DECL|WINMON|member|__I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
  DECL|WINMON|member|uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
  DECL|WINMON|member|uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
  DECL|WINUT|member|__IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
  DECL|WINUT|member|uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
  DECL|_SAMD20_ADC_COMPONENT_|macro|_SAMD20_ADC_COMPONENT_
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|bit|member|} bit; /*!< Structure used for bit access */
  DECL|reg|member|uint16_t reg; /*!< Type used for register access */
  DECL|reg|member|uint16_t reg; /*!< Type used for register access */
  DECL|reg|member|uint16_t reg; /*!< Type used for register access */
  DECL|reg|member|uint16_t reg; /*!< Type used for register access */
  DECL|reg|member|uint16_t reg; /*!< Type used for register access */
  DECL|reg|member|uint16_t reg; /*!< Type used for register access */
  DECL|reg|member|uint16_t reg; /*!< Type used for register access */
  DECL|reg|member|uint32_t reg; /*!< Type used for register access */
  DECL|reg|member|uint8_t reg; /*!< Type used for register access */
  DECL|reg|member|uint8_t reg; /*!< Type used for register access */
  DECL|reg|member|uint8_t reg; /*!< Type used for register access */
  DECL|reg|member|uint8_t reg; /*!< Type used for register access */
  DECL|reg|member|uint8_t reg; /*!< Type used for register access */
  DECL|reg|member|uint8_t reg; /*!< Type used for register access */
  DECL|reg|member|uint8_t reg; /*!< Type used for register access */
  DECL|reg|member|uint8_t reg; /*!< Type used for register access */
  DECL|reg|member|uint8_t reg; /*!< Type used for register access */
  DECL|reg|member|uint8_t reg; /*!< Type used for register access */
  DECL|reg|member|uint8_t reg; /*!< Type used for register access */
  DECL|reg|member|uint8_t reg; /*!< Type used for register access */
  DECL|uint16_t|member|uint16_t :2; /*!< bit: 6.. 7 Reserved */
  DECL|uint16_t|member|uint16_t :4; /*!< bit: 12..15 Reserved */
  DECL|uint16_t|member|uint16_t :4; /*!< bit: 12..15 Reserved */
  DECL|uint16_t|member|uint16_t :5; /*!< bit: 11..15 Reserved */
  DECL|uint16_t|member|uint16_t :5; /*!< bit: 11..15 Reserved */
  DECL|uint32_t|member|uint32_t :3; /*!< bit: 13..15 Reserved */
  DECL|uint32_t|member|uint32_t :3; /*!< bit: 5.. 7 Reserved */
  DECL|uint32_t|member|uint32_t :4; /*!< bit: 28..31 Reserved */
  DECL|uint8_t|member|__I uint8_t :4; /*!< bit: 4.. 7 Reserved */
  DECL|uint8_t|member|uint8_t :1; /*!< bit: 7 Reserved */
  DECL|uint8_t|member|uint8_t :2; /*!< bit: 2.. 3 Reserved */
  DECL|uint8_t|member|uint8_t :2; /*!< bit: 6.. 7 Reserved */
  DECL|uint8_t|member|uint8_t :2; /*!< bit: 6.. 7 Reserved */
  DECL|uint8_t|member|uint8_t :3; /*!< bit: 4.. 6 Reserved */
  DECL|uint8_t|member|uint8_t :4; /*!< bit: 4.. 7 Reserved */
  DECL|uint8_t|member|uint8_t :4; /*!< bit: 4.. 7 Reserved */
  DECL|uint8_t|member|uint8_t :5; /*!< bit: 3.. 7 Reserved */
  DECL|uint8_t|member|uint8_t :5; /*!< bit: 3.. 7 Reserved */
  DECL|uint8_t|member|uint8_t :6; /*!< bit: 2.. 7 Reserved */
  DECL|uint8_t|member|uint8_t :7; /*!< bit: 0.. 6 Reserved */
  DECL|uint8_t|member|uint8_t :7; /*!< bit: 1.. 7 Reserved */
  