text: /*
  ** ###################################################################
  **     Processors:          MKV31F128VLH10
  **                          MKV31F128VLL10
  **
  **     Compilers:           Keil ARM C/C++ Compiler
  **                          Freescale C/C++ for Embedded ARM
  **                          GNU C Compiler
  **                          IAR ANSI C/C++ Compiler for ARM
  **                          MCUXpresso Compiler
  **
  **     Reference manual:    KV31P100M100SF9RM, Rev. 1, April 25, 2014
  **     Version:             rev. 1.6, 2015-02-19
  **     Build:               b180801
  **
  **     Abstract:
  **         CMSIS Peripheral Access Layer for MKV31F12810
  **
  **     Copyright 1997-2016 Freescale Semiconductor, Inc.
  **     Copyright 2016-2018 NXP
  **
  **     SPDX-License-Identifier: BSD-3-Clause
  **
  **     http:                 www.nxp.com
  **     mail:                 support@nxp.com
  **
  **     Revisions:
  **     - rev. 1.0 (2013-11-01)
  **         Initial version.
  **     - rev. 1.1 (2013-12-20)
  **         Update according to reference manual rev. 0.1,
  **     - rev. 1.2 (2014-02-10)
  **         The declaration of clock configurations has been moved to separate header file system_MKV21F12810.h
  **     - rev. 1.3 (2014-05-06)
  **         Update according to reference manual rev. 1.0,
  **         Update of system and startup files.
  **         Module access macro module_BASES replaced by module_BASE_PTRS.
  **     - rev. 1.4 (2014-08-28)
  **         Update of system files - default clock configuration changed.
  **         Update of startup files - possibility to override DefaultISR added.
  **     - rev. 1.5 (2014-10-14)
  **         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
  **     - rev. 1.6 (2015-02-19)
  **         Renamed interrupt vector LLW to LLWU.
  **
  ** ###################################################################
  */
  
  /*!
   * @file MKV31F12810.h
   * @version 1.6
   * @date 2015-02-19
   * @brief CMSIS Peripheral Access Layer for MKV31F12810
   *
   * CMSIS Peripheral Access Layer for MKV31F12810
   */
  
  #ifndef _MKV31F12810_H_
  #define _MKV31F12810_H_                          /**< Symbol preventing repeated inclusion */
  
  /** Memory map major version (memory maps with equal major version number are
   * compatible) */
  #define MCU_MEM_MAP_VERSION 0x0100U
  /** Memory map minor version */
  #define MCU_MEM_MAP_VERSION_MINOR 0x0006U
  
  /**
   * @brief Macro to calculate address of an aliased word in the peripheral
   *        bitband area for a peripheral register and bit (bit band region 0x40000000 to
   *        0x400FFFFF).
   * @param Reg Register to access.
   * @param Bit Bit number to access.
   * @return  Address of the aliased word in the peripheral bitband area.
   */
  #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
  /**
   * @brief Macro to access a single bit of a peripheral register (bit band region
   *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
   *        be used for peripherals with 32bit access allowed.
   * @param Reg Register to access.
   * @param Bit Bit number to access.
   * @return Value of the targeted bit in the bit band region.
   */
  #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
  #define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
  /**
   * @brief Macro to access a single bit of a peripheral register (bit band region
   *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
   *        be used for peripherals with 16bit access allowed.
   * @param Reg Register to access.
   * @param Bit Bit number to access.
   * @return Value of the targeted bit in the bit band region.
   */
  #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
  /**
   * @brief Macro to access a single bit of a peripheral register (bit band region
   *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
   *        be used for peripherals with 8bit access allowed.
   * @param Reg Register to access.
   * @param Bit Bit number to access.
   * @return Value of the targeted bit in the bit band region.
   */
  #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
  
  /* ----------------------------------------------------------------------------
     -- Interrupt vector numbers
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
   * @{
   */
  
  /** Interrupt Number Definitions */
  #define NUMBER_OF_INT_VECTORS 102                /**< Number of interrupts in the Vector table */
  
  typedef enum IRQn {
    /* Auxiliary constants */
    NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
  
    /* Core interrupts */
    NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
    HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
    MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
    BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
    UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
    SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
    DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
    PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
    SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
  
    /* Device specific interrupts */
    DMA0_IRQn                    = 0,                /**< DMA Channel 0 Transfer Complete */
    DMA1_IRQn                    = 1,                /**< DMA Channel 1 Transfer Complete */
    DMA2_IRQn                    = 2,                /**< DMA Channel 2 Transfer Complete */
    DMA3_IRQn                    = 3,                /**< DMA Channel 3 Transfer Complete */
    Reserved20_IRQn              = 4,                /**< Reserved interrupt 20 */
    Reserved21_IRQn              = 5,                /**< Reserved interrupt 21 */
    Reserved22_IRQn              = 6,                /**< Reserved interrupt 22 */
    Reserved23_IRQn              = 7,                /**< Reserved interrupt 23 */
    Reserved24_IRQn              = 8,                /**< Reserved interrupt 24 */
    Reserved25_IRQn              = 9,                /**< Reserved interrupt 25 */
    Reserved26_IRQn              = 10,               /**< Reserved interrupt 26 */
    Reserved27_IRQn              = 11,               /**< Reserved interrupt 27 */
    Reserved28_IRQn              = 12,               /**< Reserved interrupt 28 */
    Reserved29_IRQn              = 13,               /**< Reserved interrupt 29 */
    Reserved30_IRQn              = 14,               /**< Reserved interrupt 30 */
    Reserved31_IRQn              = 15,               /**< Reserved interrupt 31 */
    DMA_Error_IRQn               = 16,               /**< DMA Error Interrupt */
    MCM_IRQn                     = 17,               /**< Normal Interrupt */
    FTF_IRQn                     = 18,               /**< FTFA Command complete interrupt */
    Read_Collision_IRQn          = 19,               /**< Read Collision Interrupt */
    LVD_LVW_IRQn                 = 20,               /**< Low Voltage Detect, Low Voltage Warning */
    LLWU_IRQn                    = 21,               /**< Low Leakage Wakeup Unit */
    WDOG_EWM_IRQn                = 22,               /**< WDOG Interrupt */
    Reserved39_IRQn              = 23,               /**< Reserved Interrupt 39 */
    I2C0_IRQn                    = 24,               /**< I2C0 interrupt */
    I2C1_IRQn                    = 25,               /**< I2C1 interrupt */
    SPI0_IRQn                    = 26,               /**< SPI0 Interrupt */
    SPI1_IRQn                    = 27,               /**< SPI1 Interrupt */
    Reserved44_IRQn              = 28,               /**< Reserved Interrupt 44 */
    Reserved45_IRQn              = 29,               /**< Reserved interrupt 45 */
    LPUART0_IRQn                 = 30,               /**< LPUART0 status/error interrupt */
    UART0_RX_TX_IRQn             = 31,               /**< UART0 Receive/Transmit interrupt */
    UART0_ERR_IRQn               = 32,               /**< UART0 Error interrupt */
    UART1_RX_TX_IRQn             = 33,               /**< UART1 Receive/Transmit interrupt */
    UART1_ERR_IRQn               = 34,               /**< UART1 Error interrupt */
    UART2_RX_TX_IRQn             = 35,               /**< UART2 Receive/Transmit interrupt */
    UART2_ERR_IRQn               = 36,               /**< UART2 Error interrupt */
    Reserved53_IRQn              = 37,               /**< Reserved interrupt 53 */
    Reserved54_IRQn              = 38,               /**< Reserved interrupt 54 */
    ADC0_IRQn                    = 39,               /**< ADC0 interrupt */
    CMP0_IRQn                    = 40,               /**< CMP0 interrupt */
    CMP1_IRQn                    = 41,               /**< CMP1 interrupt */
    FTM0_IRQn                    = 42,               /**< FTM0 fault, overflow and channels interrupt */
    FTM1_IRQn                    = 43,               /**< FTM1 fault, overflow and channels interrupt */
    FTM2_IRQn                    = 44,               /**< FTM2 fault, overflow and channels interrupt */
    Reserved61_IRQn              = 45,               /**< Reserved interrupt 61 */
    Reserved62_IRQn              = 46,               /**< Reserved interrupt 62 */
    Reserved63_IRQn              = 47,               /**< Reserved interrupt 63 */
    PIT0_IRQn                    = 48,               /**< PIT timer channel 0 interrupt */
    PIT1_IRQn                    = 49,               /**< PIT timer channel 1 interrupt */
    PIT2_IRQn                    = 50,               /**< PIT timer channel 2 interrupt */
    PIT3_IRQn                    = 51,               /**< PIT timer channel 3 interrupt */
    PDB0_IRQn                    = 52,               /**< PDB0 Interrupt */
    Reserved69_IRQn              = 53,               /**< Reserved interrupt 69 */
    Reserved70_IRQn              = 54,               /**< Reserved interrupt 70 */
    Reserved71_IRQn              = 55,               /**< Reserved interrupt 71 */
    DAC0_IRQn                    = 56,               /**< DAC0 interrupt */
    MCG_IRQn                     = 57,               /**< MCG Interrupt */
    LPTMR0_IRQn                  = 58,               /**< LPTimer interrupt */
    PORTA_IRQn                   = 59,               /**< Port A interrupt */
    PORTB_IRQn                   = 60,               /**< Port B interrupt */
    PORTC_IRQn                   = 61,               /**< Port C interrupt */
    PORTD_IRQn                   = 62,               /**< Port D interrupt */
    PORTE_IRQn                   = 63,               /**< Port E interrupt */
    SWI_IRQn                     = 64,               /**< Software interrupt */
    Reserved81_IRQn              = 65,               /**< Reserved interrupt 81 */
    Reserved82_IRQn              = 66,               /**< Reserved interrupt 82 */
    Reserved83_IRQn              = 67,               /**< Reserved interrupt 83 */
    Reserved84_IRQn              = 68,               /**< Reserved interrupt 84 */
    Reserved85_IRQn              = 69,               /**< Reserved interrupt 85 */
    Reserved86_IRQn              = 70,               /**< Reserved interrupt 86 */
    Reserved87_IRQn              = 71,               /**< Reserved interrupt 87 */
    Reserved88_IRQn              = 72,               /**< Reserved interrupt 88 */
    ADC1_IRQn                    = 73,               /**< ADC1 interrupt */
    Reserved90_IRQn              = 74,               /**< Reserved Interrupt 90 */
    Reserved91_IRQn              = 75,               /**< Reserved Interrupt 91 */
    Reserved92_IRQn              = 76,               /**< Reserved Interrupt 92 */
    Reserved93_IRQn              = 77,               /**< Reserved Interrupt 93 */
    Reserved94_IRQn              = 78,               /**< Reserved Interrupt 94 */
    Reserved95_IRQn              = 79,               /**< Reserved Interrupt 95 */
    Reserved96_IRQn              = 80,               /**< Reserved Interrupt 96 */
    Reserved97_IRQn              = 81,               /**< Reserved Interrupt 97 */
    Reserved98_IRQn              = 82,               /**< Reserved Interrupt 98 */
    Reserved99_IRQn              = 83,               /**< Reserved Interrupt 99 */
    Reserved100_IRQn             = 84,               /**< Reserved Interrupt 100 */
    Reserved101_IRQn             = 85                /**< Reserved Interrupt 101 */
  } IRQn_Type;
  
  /*!
   * @}
   */ /* end of group Interrupt_vector_numbers */
  
  
  /* ----------------------------------------------------------------------------
     -- Cortex M4 Core Configuration
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
   * @{
   */
  
  #define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
  #define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
  #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
  #define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
  
  #include "core_cm4.h"                  /* Core Peripheral Access Layer */
  #include "system_MKV31F12810.h"        /* Device specific configuration file */
  
  /*!
   * @}
   */ /* end of group Cortex_Core_Configuration */
  
  
  /* ----------------------------------------------------------------------------
     -- Mapping Information
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup Mapping_Information Mapping Information
   * @{
   */
  
  /** Mapping Information */
  /*!
   * @addtogroup edma_request
   * @{
   */
  
  /*******************************************************************************
   * Definitions
   ******************************************************************************/
  
  /*!
   * @brief Structure for the DMA hardware request
   *
   * Defines the structure for the DMA hardware request collections. The user can configure the
   * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
   * of the hardware request varies according  to the to SoC.
   */
  typedef enum _dma_request_source
  {
      kDmaRequestMux0Disable          = 0|0x100U,    /**< DMAMUX TriggerDisabled. */
      kDmaRequestMux0Reserved1        = 1|0x100U,    /**< Reserved1 */
      kDmaRequestMux0UART0Rx          = 2|0x100U,    /**< UART0 Receive. */
      kDmaRequestMux0UART0Tx          = 3|0x100U,    /**< UART0 Transmit. */
      kDmaRequestMux0UART1Rx          = 4|0x100U,    /**< UART1 Receive. */
      kDmaRequestMux0UART1Tx          = 5|0x100U,    /**< UART1 Transmit. */
      kDmaRequestMux0UART2Rx          = 6|0x100U,    /**< UART2 Receive. */
      kDmaRequestMux0UART2Tx          = 7|0x100U,    /**< UART2 Transmit. */
      kDmaRequestMux0Reserved8        = 8|0x100U,    /**< Reserved8 */
      kDmaRequestMux0Reserved9        = 9|0x100U,    /**< Reserved9 */
      kDmaRequestMux0Reserved10       = 10|0x100U,   /**< Reserved10 */
      kDmaRequestMux0Reserved11       = 11|0x100U,   /**< Reserved11 */
      kDmaRequestMux0Reserved12       = 12|0x100U,   /**< Reserved12 */
      kDmaRequestMux0Reserved13       = 13|0x100U,   /**< Reserved13 */
      kDmaRequestMux0SPI0Rx           = 14|0x100U,   /**< SPI0 Receive. */
      kDmaRequestMux0SPI0Tx           = 15|0x100U,   /**< SPI0 Transmit. */
      kDmaRequestMux0SPI1             = 16|0x100U,   /**< SPI1 Transmit or Receive. */
      kDmaRequestMux0Reserved17       = 17|0x100U,   /**< Reserved17 */
      kDmaRequestMux0I2C0             = 18|0x100U,   /**< I2C0. */
      kDmaRequestMux0I2C1             = 19|0x100U,   /**< I2C1. */
      kDmaRequestMux0FTM0Channel0     = 20|0x100U,   /**< FTM0 C0V. */
      kDmaRequestMux0FTM0Channel1     = 21|0x100U,   /**< FTM0 C1V. */
      kDmaRequestMux0FTM0Channel2     = 22|0x100U,   /**< FTM0 C2V. */
      kDmaRequestMux0FTM0Channel3     = 23|0x100U,   /**< FTM0 C3V. */
      kDmaRequestMux0FTM0Channel4     = 24|0x100U,   /**< FTM0 C4V. */
      kDmaRequestMux0FTM0Channel5     = 25|0x100U,   /**< FTM0 C5V. */
      kDmaRequestMux0FTM0Channel6     = 26|0x100U,   /**< FTM0 C6V. */
      kDmaRequestMux0FTM0Channel7     = 27|0x100U,   /**< FTM0 C7V. */
      kDmaRequestMux0FTM1Channel0     = 28|0x100U,   /**< FTM1 C0V. */
      kDmaRequestMux0FTM1Channel1     = 29|0x100U,   /**< FTM1 C1V. */
      kDmaRequestMux0FTM2Channel0     = 30|0x100U,   /**< FTM2 C0V. */
      kDmaRequestMux0FTM2Channel1     = 31|0x100U,   /**< FTM2 C1V. */
      kDmaRequestMux0Reserved32       = 32|0x100U,   /**< Reserved32 */
      kDmaRequestMux0Reserved33       = 33|0x100U,   /**< Reserved33 */
      kDmaRequestMux0Reserved34       = 34|0x100U,   /**< Reserved34 */
      kDmaRequestMux0Reserved35       = 35|0x100U,   /**< Reserved35 */
      kDmaRequestMux0Reserved36       = 36|0x100U,   /**< Reserved36 */
      kDmaRequestMux0Reserved37       = 37|0x100U,   /**< Reserved37 */
      kDmaRequestMux0Reserved38       = 38|0x100U,   /**< Reserved38 */
      kDmaRequestMux0Reserved39       = 39|0x100U,   /**< Reserved39 */
      kDmaRequestMux0ADC0             = 40|0x100U,   /**< ADC0. */
      kDmaRequestMux0ADC1             = 41|0x100U,   /**< ADC1. */
      kDmaRequestMux0CMP0             = 42|0x100U,   /**< CMP0. */
      kDmaRequestMux0CMP1             = 43|0x100U,   /**< CMP1. */
      kDmaRequestMux0Reserved44       = 44|0x100U,   /**< Reserved44 */
      kDmaRequestMux0DAC0             = 45|0x100U,   /**< DAC0. */
      kDmaRequestMux0Reserved46       = 46|0x100U,   /**< Reserved46 */
      kDmaRequestMux0Reserved47       = 47|0x100U,   /**< Reserved47 */
      kDmaRequestMux0PDB              = 48|0x100U,   /**< PDB0. */
      kDmaRequestMux0PortA            = 49|0x100U,   /**< PTA. */
      kDmaRequestMux0PortB            = 50|0x100U,   /**< PTB. */
      kDmaRequestMux0PortC            = 51|0x100U,   /**< PTC. */
      kDmaRequestMux0PortD            = 52|0x100U,   /**< PTD. */
      kDmaRequestMux0PortE            = 53|0x100U,   /**< PTE. */
      kDmaRequestMux0Reserved54       = 54|0x100U,   /**< Reserved54 */
      kDmaRequestMux0Reserved55       = 55|0x100U,   /**< Reserved55 */
      kDmaRequestMux0Reserved56       = 56|0x100U,   /**< Reserved56 */
      kDmaRequestMux0Reserved57       = 57|0x100U,   /**< Reserved57 */
      kDmaRequestMux0LPUART0Rx        = 58|0x100U,   /**< LPUART0 Receive. */
      kDmaRequestMux0LPUART0Tx        = 59|0x100U,   /**< LPUART0 Transmit. */
      kDmaRequestMux0AlwaysOn60       = 60|0x100U,   /**< DMAMUX Always Enabled slot. */
      kDmaRequestMux0AlwaysOn61       = 61|0x100U,   /**< DMAMUX Always Enabled slot. */
      kDmaRequestMux0AlwaysOn62       = 62|0x100U,   /**< DMAMUX Always Enabled slot. */
      kDmaRequestMux0AlwaysOn63       = 63|0x100U,   /**< DMAMUX Always Enabled slot. */
  } dma_request_source_t;
  
  /* @} */
  
  
  /*!
   * @}
   */ /* end of group Mapping_Information */
  
  
  /* ----------------------------------------------------------------------------
     -- Device Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
   * @{
   */
  
  
  /*
  ** Start of section using anonymous unions
  */
  
  #if defined(__ARMCC_VERSION)
    #if (__ARMCC_VERSION >= 6010050)
      #pragma clang diagnostic push
    #else
      #pragma push
      #pragma anon_unions
    #endif
  #elif defined(__CWCC__)
    #pragma push
    #pragma cpp_extensions on
  #elif defined(__GNUC__)
    /* anonymous unions are enabled by default */
  #elif defined(__IAR_SYSTEMS_ICC__)
    #pragma language=extended
  #else
    #error Not supported compiler type
  #endif
  
  /* ----------------------------------------------------------------------------
     -- ADC Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
   * @{
   */
  
  /** ADC - Register Layout Typedef */
  typedef struct {
    __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
    __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
    __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
    __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
    __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
    __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
    __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
    __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
    __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
    __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
    __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
    __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
    __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
    __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
    __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
    __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
    __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
    __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
         uint8_t RESERVED_0[4];
    __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
    __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
    __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
    __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
    __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
    __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
    __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
  } ADC_Type;
  
  /* ----------------------------------------------------------------------------
     -- ADC Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup ADC_Register_Masks ADC Register Masks
   * @{
   */
  
  /*! @name SC1 - ADC Status and Control Registers 1 */
  /*! @{ */
  #define ADC_SC1_ADCH_MASK                        (0x1FU)
  #define ADC_SC1_ADCH_SHIFT                       (0U)
  /*! ADCH - Input channel select
   *  0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
   *  0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
   *  0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
   *  0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
   *  0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
   *  0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
   *  0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
   *  0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
   *  0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
   *  0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
   *  0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
   *  0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
   *  0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
   *  0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
   *  0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
   *  0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
   *  0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
   *  0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
   *  0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
   *  0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
   *  0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
   *  0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
   *  0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
   *  0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
   *  0b11000..Reserved.
   *  0b11001..Reserved.
   *  0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
   *  0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
   *  0b11100..Reserved.
   *  0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
   *  0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
   *  0b11111..Module is disabled.
   */
  #define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
  #define ADC_SC1_DIFF_MASK                        (0x20U)
  #define ADC_SC1_DIFF_SHIFT                       (5U)
  /*! DIFF - Differential Mode Enable
   *  0b0..Single-ended conversions and input channels are selected.
   *  0b1..Differential conversions and input channels are selected.
   */
  #define ADC_SC1_DIFF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
  #define ADC_SC1_AIEN_MASK                        (0x40U)
  #define ADC_SC1_AIEN_SHIFT                       (6U)
  /*! AIEN - Interrupt Enable
   *  0b0..Conversion complete interrupt is disabled.
   *  0b1..Conversion complete interrupt is enabled.
   */
  #define ADC_SC1_AIEN(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
  #define ADC_SC1_COCO_MASK                        (0x80U)
  #define ADC_SC1_COCO_SHIFT                       (7U)
  /*! COCO - Conversion Complete Flag
   *  0b0..Conversion is not completed.
   *  0b1..Conversion is completed.
   */
  #define ADC_SC1_COCO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
  /*! @} */
  
  /* The count of ADC_SC1 */
  #define ADC_SC1_COUNT                            (2U)
  
  /*! @name CFG1 - ADC Configuration Register 1 */
  /*! @{ */
  #define ADC_CFG1_ADICLK_MASK                     (0x3U)
  #define ADC_CFG1_ADICLK_SHIFT                    (0U)
  /*! ADICLK - Input Clock Select
   *  0b00..Bus clock
   *  0b01..Alternate clock 2 (ALTCLK2)
   *  0b10..Alternate clock (ALTCLK)
   *  0b11..Asynchronous clock (ADACK)
   */
  #define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
  #define ADC_CFG1_MODE_MASK                       (0xCU)
  #define ADC_CFG1_MODE_SHIFT                      (2U)
  /*! MODE - Conversion mode selection
   *  0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
   *  0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
   *  0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output
   *  0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output
   */
  #define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
  #define ADC_CFG1_ADLSMP_MASK                     (0x10U)
  #define ADC_CFG1_ADLSMP_SHIFT                    (4U)
  /*! ADLSMP - Sample Time Configuration
   *  0b0..Short sample time.
   *  0b1..Long sample time.
   */
  #define ADC_CFG1_ADLSMP(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
  #define ADC_CFG1_ADIV_MASK                       (0x60U)
  #define ADC_CFG1_ADIV_SHIFT                      (5U)
  /*! ADIV - Clock Divide Select
   *  0b00..The divide ratio is 1 and the clock rate is input clock.
   *  0b01..The divide ratio is 2 and the clock rate is (input clock)/2.
   *  0b10..The divide ratio is 4 and the clock rate is (input clock)/4.
   *  0b11..The divide ratio is 8 and the clock rate is (input clock)/8.
   */
  #define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
  #define ADC_CFG1_ADLPC_MASK                      (0x80U)
  #define ADC_CFG1_ADLPC_SHIFT                     (7U)
  /*! ADLPC - Low-Power Configuration
   *  0b0..Normal power configuration.
   *  0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.
   */
  #define ADC_CFG1_ADLPC(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
  /*! @} */
  
  /*! @name CFG2 - ADC Configuration Register 2 */
  /*! @{ */
  #define ADC_CFG2_ADLSTS_MASK                     (0x3U)
  #define ADC_CFG2_ADLSTS_SHIFT                    (0U)
  /*! ADLSTS - Long Sample Time Select
   *  0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
   *  0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time.
   *  0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time.
   *  0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.
   */
  #define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
  #define ADC_CFG2_ADHSC_MASK                      (0x4U)
  #define ADC_CFG2_ADHSC_SHIFT                     (2U)
  /*! ADHSC - High-Speed Configuration
   *  0b0..Normal conversion sequence selected.
   *  0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
   */
  #define ADC_CFG2_ADHSC(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
  #define ADC_CFG2_ADACKEN_MASK                    (0x8U)
  #define ADC_CFG2_ADACKEN_SHIFT                   (3U)
  /*! ADACKEN - Asynchronous Clock Output Enable
   *  0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
   *  0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.
   */
  #define ADC_CFG2_ADACKEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
  #define ADC_CFG2_MUXSEL_MASK                     (0x10U)
  #define ADC_CFG2_MUXSEL_SHIFT                    (4U)
  /*! MUXSEL - ADC Mux Select
   *  0b0..ADxxa channels are selected.
   *  0b1..ADxxb channels are selected.
   */
  #define ADC_CFG2_MUXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
  /*! @} */
  
  /*! @name R - ADC Data Result Register */
  /*! @{ */
  #define ADC_R_D_MASK                             (0xFFFFU)
  #define ADC_R_D_SHIFT                            (0U)
  #define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
  /*! @} */
  
  /* The count of ADC_R */
  #define ADC_R_COUNT                              (2U)
  
  /*! @name CV1 - Compare Value Registers */
  /*! @{ */
  #define ADC_CV1_CV_MASK                          (0xFFFFU)
  #define ADC_CV1_CV_SHIFT                         (0U)
  #define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
  /*! @} */
  
  /*! @name CV2 - Compare Value Registers */
  /*! @{ */
  #define ADC_CV2_CV_MASK                          (0xFFFFU)
  #define ADC_CV2_CV_SHIFT                         (0U)
  #define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
  /*! @} */
  
  /*! @name SC2 - Status and Control Register 2 */
  /*! @{ */
  #define ADC_SC2_REFSEL_MASK                      (0x3U)
  #define ADC_SC2_REFSEL_SHIFT                     (0U)
  /*! REFSEL - Voltage Reference Selection
   *  0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL
   *  0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
   *  0b10..Reserved
   *  0b11..Reserved
   */
  #define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
  #define ADC_SC2_DMAEN_MASK                       (0x4U)
  #define ADC_SC2_DMAEN_SHIFT                      (2U)
  /*! DMAEN - DMA Enable
   *  0b0..DMA is disabled.
   *  0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
   */
  #define ADC_SC2_DMAEN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
  #define ADC_SC2_ACREN_MASK                       (0x8U)
  #define ADC_SC2_ACREN_SHIFT                      (3U)
  /*! ACREN - Compare Function Range Enable
   *  0b0..Range function disabled. Only CV1 is compared.
   *  0b1..Range function enabled. Both CV1 and CV2 are compared.
   */
  #define ADC_SC2_ACREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
  #define ADC_SC2_ACFGT_MASK                       (0x10U)
  #define ADC_SC2_ACFGT_SHIFT                      (4U)
  /*! ACFGT - Compare Function Greater Than Enable
   *  0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
   *  0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
   */
  #define ADC_SC2_ACFGT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
  #define ADC_SC2_ACFE_MASK                        (0x20U)
  #define ADC_SC2_ACFE_SHIFT                       (5U)
  /*! ACFE - Compare Function Enable
   *  0b0..Compare function disabled.
   *  0b1..Compare function enabled.
   */
  #define ADC_SC2_ACFE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
  #define ADC_SC2_ADTRG_MASK                       (0x40U)
  #define ADC_SC2_ADTRG_SHIFT                      (6U)
  /*! ADTRG - Conversion Trigger Select
   *  0b0..Software trigger selected.
   *  0b1..Hardware trigger selected.
   */
  #define ADC_SC2_ADTRG(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
  #define ADC_SC2_ADACT_MASK                       (0x80U)
  #define ADC_SC2_ADACT_SHIFT                      (7U)
  /*! ADACT - Conversion Active
   *  0b0..Conversion not in progress.
   *  0b1..Conversion in progress.
   */
  #define ADC_SC2_ADACT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
  /*! @} */
  
  /*! @name SC3 - Status and Control Register 3 */
  /*! @{ */
  #define ADC_SC3_AVGS_MASK                        (0x3U)
  #define ADC_SC3_AVGS_SHIFT                       (0U)
  /*! AVGS - Hardware Average Select
   *  0b00..4 samples averaged.
   *  0b01..8 samples averaged.
   *  0b10..16 samples averaged.
   *  0b11..32 samples averaged.
   */
  #define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
  #define ADC_SC3_AVGE_MASK                        (0x4U)
  #define ADC_SC3_AVGE_SHIFT                       (2U)
  /*! AVGE - Hardware Average Enable
   *  0b0..Hardware average function disabled.
   *  0b1..Hardware average function enabled.
   */
  #define ADC_SC3_AVGE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
  #define ADC_SC3_ADCO_MASK                        (0x8U)
  #define ADC_SC3_ADCO_SHIFT                       (3U)
  /*! ADCO - Continuous Conversion Enable
   *  0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
   *  0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
   */
  #define ADC_SC3_ADCO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
  #define ADC_SC3_CALF_MASK                        (0x40U)
  #define ADC_SC3_CALF_SHIFT                       (6U)
  /*! CALF - Calibration Failed Flag
   *  0b0..Calibration completed normally.
   *  0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
   */
  #define ADC_SC3_CALF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
  #define ADC_SC3_CAL_MASK                         (0x80U)
  #define ADC_SC3_CAL_SHIFT                        (7U)
  #define ADC_SC3_CAL(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
  /*! @} */
  
  /*! @name OFS - ADC Offset Correction Register */
  /*! @{ */
  #define ADC_OFS_OFS_MASK                         (0xFFFFU)
  #define ADC_OFS_OFS_SHIFT                        (0U)
  #define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
  /*! @} */
  
  /*! @name PG - ADC Plus-Side Gain Register */
  /*! @{ */
  #define ADC_PG_PG_MASK                           (0xFFFFU)
  #define ADC_PG_PG_SHIFT                          (0U)
  #define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
  /*! @} */
  
  /*! @name MG - ADC Minus-Side Gain Register */
  /*! @{ */
  #define ADC_MG_MG_MASK                           (0xFFFFU)
  #define ADC_MG_MG_SHIFT                          (0U)
  #define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
  /*! @} */
  
  /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
  /*! @{ */
  #define ADC_CLPD_CLPD_MASK                       (0x3FU)
  #define ADC_CLPD_CLPD_SHIFT                      (0U)
  #define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
  /*! @} */
  
  /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
  /*! @{ */
  #define ADC_CLPS_CLPS_MASK                       (0x3FU)
  #define ADC_CLPS_CLPS_SHIFT                      (0U)
  #define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
  /*! @} */
  
  /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
  /*! @{ */
  #define ADC_CLP4_CLP4_MASK                       (0x3FFU)
  #define ADC_CLP4_CLP4_SHIFT                      (0U)
  #define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
  /*! @} */
  
  /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
  /*! @{ */
  #define ADC_CLP3_CLP3_MASK                       (0x1FFU)
  #define ADC_CLP3_CLP3_SHIFT                      (0U)
  #define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
  /*! @} */
  
  /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
  /*! @{ */
  #define ADC_CLP2_CLP2_MASK                       (0xFFU)
  #define ADC_CLP2_CLP2_SHIFT                      (0U)
  #define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
  /*! @} */
  
  /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
  /*! @{ */
  #define ADC_CLP1_CLP1_MASK                       (0x7FU)
  #define ADC_CLP1_CLP1_SHIFT                      (0U)
  #define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
  /*! @} */
  
  /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
  /*! @{ */
  #define ADC_CLP0_CLP0_MASK                       (0x3FU)
  #define ADC_CLP0_CLP0_SHIFT                      (0U)
  #define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
  /*! @} */
  
  /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
  /*! @{ */
  #define ADC_CLMD_CLMD_MASK                       (0x3FU)
  #define ADC_CLMD_CLMD_SHIFT                      (0U)
  #define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
  /*! @} */
  
  /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
  /*! @{ */
  #define ADC_CLMS_CLMS_MASK                       (0x3FU)
  #define ADC_CLMS_CLMS_SHIFT                      (0U)
  #define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
  /*! @} */
  
  /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
  /*! @{ */
  #define ADC_CLM4_CLM4_MASK                       (0x3FFU)
  #define ADC_CLM4_CLM4_SHIFT                      (0U)
  #define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
  /*! @} */
  
  /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
  /*! @{ */
  #define ADC_CLM3_CLM3_MASK                       (0x1FFU)
  #define ADC_CLM3_CLM3_SHIFT                      (0U)
  #define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
  /*! @} */
  
  /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
  /*! @{ */
  #define ADC_CLM2_CLM2_MASK                       (0xFFU)
  #define ADC_CLM2_CLM2_SHIFT                      (0U)
  #define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
  /*! @} */
  
  /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
  /*! @{ */
  #define ADC_CLM1_CLM1_MASK                       (0x7FU)
  #define ADC_CLM1_CLM1_SHIFT                      (0U)
  #define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
  /*! @} */
  
  /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
  /*! @{ */
  #define ADC_CLM0_CLM0_MASK                       (0x3FU)
  #define ADC_CLM0_CLM0_SHIFT                      (0U)
  #define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group ADC_Register_Masks */
  
  
  /* ADC - Peripheral instance base addresses */
  /** Peripheral ADC0 base address */
  #define ADC0_BASE                                (0x4003B000u)
  /** Peripheral ADC0 base pointer */
  #define ADC0                                     ((ADC_Type *)ADC0_BASE)
  /** Peripheral ADC1 base address */
  #define ADC1_BASE                                (0x40027000u)
  /** Peripheral ADC1 base pointer */
  #define ADC1                                     ((ADC_Type *)ADC1_BASE)
  /** Array initializer of ADC peripheral base addresses */
  #define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
  /** Array initializer of ADC peripheral base pointers */
  #define ADC_BASE_PTRS                            { ADC0, ADC1 }
  /** Interrupt vectors for the ADC peripheral type */
  #define ADC_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
  
  /*!
   * @}
   */ /* end of group ADC_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- CMP Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
   * @{
   */
  
  /** CMP - Register Layout Typedef */
  typedef struct {
    __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
    __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
    __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
    __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
    __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
    __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
  } CMP_Type;
  
  /* ----------------------------------------------------------------------------
     -- CMP Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CMP_Register_Masks CMP Register Masks
   * @{
   */
  
  /*! @name CR0 - CMP Control Register 0 */
  /*! @{ */
  #define CMP_CR0_HYSTCTR_MASK                     (0x3U)
  #define CMP_CR0_HYSTCTR_SHIFT                    (0U)
  /*! HYSTCTR - Comparator hard block hysteresis control
   *  0b00..Level 0
   *  0b01..Level 1
   *  0b10..Level 2
   *  0b11..Level 3
   */
  #define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
  #define CMP_CR0_FILTER_CNT_MASK                  (0x70U)
  #define CMP_CR0_FILTER_CNT_SHIFT                 (4U)
  /*! FILTER_CNT - Filter Sample Count
   *  0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
   *  0b001..One sample must agree. The comparator output is simply sampled.
   *  0b010..2 consecutive samples must agree.
   *  0b011..3 consecutive samples must agree.
   *  0b100..4 consecutive samples must agree.
   *  0b101..5 consecutive samples must agree.
   *  0b110..6 consecutive samples must agree.
   *  0b111..7 consecutive samples must agree.
   */
  #define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
  /*! @} */
  
  /*! @name CR1 - CMP Control Register 1 */
  /*! @{ */
  #define CMP_CR1_EN_MASK                          (0x1U)
  #define CMP_CR1_EN_SHIFT                         (0U)
  /*! EN - Comparator Module Enable
   *  0b0..Analog Comparator is disabled.
   *  0b1..Analog Comparator is enabled.
   */
  #define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
  #define CMP_CR1_OPE_MASK                         (0x2U)
  #define CMP_CR1_OPE_SHIFT                        (1U)
  /*! OPE - Comparator Output Pin Enable
   *  0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
   *  0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
   */
  #define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
  #define CMP_CR1_COS_MASK                         (0x4U)
  #define CMP_CR1_COS_SHIFT                        (2U)
  /*! COS - Comparator Output Select
   *  0b0..Set the filtered comparator output (CMPO) to equal COUT.
   *  0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
   */
  #define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
  #define CMP_CR1_INV_MASK                         (0x8U)
  #define CMP_CR1_INV_SHIFT                        (3U)
  /*! INV - Comparator INVERT
   *  0b0..Does not invert the comparator output.
   *  0b1..Inverts the comparator output.
   */
  #define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
  #define CMP_CR1_PMODE_MASK                       (0x10U)
  #define CMP_CR1_PMODE_SHIFT                      (4U)
  /*! PMODE - Power Mode Select
   *  0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
   *  0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
   */
  #define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
  #define CMP_CR1_TRIGM_MASK                       (0x20U)
  #define CMP_CR1_TRIGM_SHIFT                      (5U)
  /*! TRIGM - Trigger Mode Enable
   *  0b0..Trigger mode is disabled.
   *  0b1..Trigger mode is enabled.
   */
  #define CMP_CR1_TRIGM(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
  #define CMP_CR1_WE_MASK                          (0x40U)
  #define CMP_CR1_WE_SHIFT                         (6U)
  /*! WE - Windowing Enable
   *  0b0..Windowing mode is not selected.
   *  0b1..Windowing mode is selected.
   */
  #define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
  #define CMP_CR1_SE_MASK                          (0x80U)
  #define CMP_CR1_SE_SHIFT                         (7U)
  /*! SE - Sample Enable
   *  0b0..Sampling mode is not selected.
   *  0b1..Sampling mode is selected.
   */
  #define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
  /*! @} */
  
  /*! @name FPR - CMP Filter Period Register */
  /*! @{ */
  #define CMP_FPR_FILT_PER_MASK                    (0xFFU)
  #define CMP_FPR_FILT_PER_SHIFT                   (0U)
  #define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
  /*! @} */
  
  /*! @name SCR - CMP Status and Control Register */
  /*! @{ */
  #define CMP_SCR_COUT_MASK                        (0x1U)
  #define CMP_SCR_COUT_SHIFT                       (0U)
  #define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
  #define CMP_SCR_CFF_MASK                         (0x2U)
  #define CMP_SCR_CFF_SHIFT                        (1U)
  /*! CFF - Analog Comparator Flag Falling
   *  0b0..Falling-edge on COUT has not been detected.
   *  0b1..Falling-edge on COUT has occurred.
   */
  #define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
  #define CMP_SCR_CFR_MASK                         (0x4U)
  #define CMP_SCR_CFR_SHIFT                        (2U)
  /*! CFR - Analog Comparator Flag Rising
   *  0b0..Rising-edge on COUT has not been detected.
   *  0b1..Rising-edge on COUT has occurred.
   */
  #define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
  #define CMP_SCR_IEF_MASK                         (0x8U)
  #define CMP_SCR_IEF_SHIFT                        (3U)
  /*! IEF - Comparator Interrupt Enable Falling
   *  0b0..Interrupt is disabled.
   *  0b1..Interrupt is enabled.
   */
  #define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
  #define CMP_SCR_IER_MASK                         (0x10U)
  #define CMP_SCR_IER_SHIFT                        (4U)
  /*! IER - Comparator Interrupt Enable Rising
   *  0b0..Interrupt is disabled.
   *  0b1..Interrupt is enabled.
   */
  #define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
  #define CMP_SCR_DMAEN_MASK                       (0x40U)
  #define CMP_SCR_DMAEN_SHIFT                      (6U)
  /*! DMAEN - DMA Enable Control
   *  0b0..DMA is disabled.
   *  0b1..DMA is enabled.
   */
  #define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
  /*! @} */
  
  /*! @name DACCR - DAC Control Register */
  /*! @{ */
  #define CMP_DACCR_VOSEL_MASK                     (0x3FU)
  #define CMP_DACCR_VOSEL_SHIFT                    (0U)
  #define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
  #define CMP_DACCR_VRSEL_MASK                     (0x40U)
  #define CMP_DACCR_VRSEL_SHIFT                    (6U)
  /*! VRSEL - Supply Voltage Reference Source Select
   *  0b0..Vin1 is selected as resistor ladder network supply reference.
   *  0b1..Vin2 is selected as resistor ladder network supply reference.
   */
  #define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
  #define CMP_DACCR_DACEN_MASK                     (0x80U)
  #define CMP_DACCR_DACEN_SHIFT                    (7U)
  /*! DACEN - DAC Enable
   *  0b0..DAC is disabled.
   *  0b1..DAC is enabled.
   */
  #define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
  /*! @} */
  
  /*! @name MUXCR - MUX Control Register */
  /*! @{ */
  #define CMP_MUXCR_MSEL_MASK                      (0x7U)
  #define CMP_MUXCR_MSEL_SHIFT                     (0U)
  /*! MSEL - Minus Input Mux Control
   *  0b000..IN0
   *  0b001..IN1
   *  0b010..IN2
   *  0b011..IN3
   *  0b100..IN4
   *  0b101..IN5
   *  0b110..IN6
   *  0b111..IN7
   */
  #define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
  #define CMP_MUXCR_PSEL_MASK                      (0x38U)
  #define CMP_MUXCR_PSEL_SHIFT                     (3U)
  /*! PSEL - Plus Input Mux Control
   *  0b000..IN0
   *  0b001..IN1
   *  0b010..IN2
   *  0b011..IN3
   *  0b100..IN4
   *  0b101..IN5
   *  0b110..IN6
   *  0b111..IN7
   */
  #define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group CMP_Register_Masks */
  
  
  /* CMP - Peripheral instance base addresses */
  /** Peripheral CMP0 base address */
  #define CMP0_BASE                                (0x40073000u)
  /** Peripheral CMP0 base pointer */
  #define CMP0                                     ((CMP_Type *)CMP0_BASE)
  /** Peripheral CMP1 base address */
  #define CMP1_BASE                                (0x40073008u)
  /** Peripheral CMP1 base pointer */
  #define CMP1                                     ((CMP_Type *)CMP1_BASE)
  /** Array initializer of CMP peripheral base addresses */
  #define CMP_BASE_ADDRS                           { CMP0_BASE, CMP1_BASE }
  /** Array initializer of CMP peripheral base pointers */
  #define CMP_BASE_PTRS                            { CMP0, CMP1 }
  /** Interrupt vectors for the CMP peripheral type */
  #define CMP_IRQS                                 { CMP0_IRQn, CMP1_IRQn }
  
  /*!
   * @}
   */ /* end of group CMP_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- CRC Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
   * @{
   */
  
  /** CRC - Register Layout Typedef */
  typedef struct {
    union {                                          /* offset: 0x0 */
      struct {                                         /* offset: 0x0 */
        __IO uint16_t DATAL;                             /**< CRC_DATAL register., offset: 0x0 */
        __IO uint16_t DATAH;                             /**< CRC_DATAH register., offset: 0x2 */
      } ACCESS16BIT;
      __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
      struct {                                         /* offset: 0x0 */
        __IO uint8_t DATALL;                             /**< CRC_DATALL register., offset: 0x0 */
        __IO uint8_t DATALU;                             /**< CRC_DATALU register., offset: 0x1 */
        __IO uint8_t DATAHL;                             /**< CRC_DATAHL register., offset: 0x2 */
        __IO uint8_t DATAHU;                             /**< CRC_DATAHU register., offset: 0x3 */
      } ACCESS8BIT;
    };
    union {                                          /* offset: 0x4 */
      struct {                                         /* offset: 0x4 */
        __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register., offset: 0x4 */
        __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register., offset: 0x6 */
      } GPOLY_ACCESS16BIT;
      __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
      struct {                                         /* offset: 0x4 */
        __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register., offset: 0x4 */
        __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register., offset: 0x5 */
        __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register., offset: 0x6 */
        __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register., offset: 0x7 */
      } GPOLY_ACCESS8BIT;
    };
    union {                                          /* offset: 0x8 */
      __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
      struct {                                         /* offset: 0x8 */
             uint8_t RESERVED_0[3];
        __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
      } CTRL_ACCESS8BIT;
    };
  } CRC_Type;
  
  /* ----------------------------------------------------------------------------
     -- CRC Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup CRC_Register_Masks CRC Register Masks
   * @{
   */
  
  /*! @name DATAL - CRC_DATAL register. */
  /*! @{ */
  #define CRC_DATAL_DATAL_MASK                     (0xFFFFU)
  #define CRC_DATAL_DATAL_SHIFT                    (0U)
  #define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
  /*! @} */
  
  /*! @name DATAH - CRC_DATAH register. */
  /*! @{ */
  #define CRC_DATAH_DATAH_MASK                     (0xFFFFU)
  #define CRC_DATAH_DATAH_SHIFT                    (0U)
  #define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
  /*! @} */
  
  /*! @name DATA - CRC Data register */
  /*! @{ */
  #define CRC_DATA_LL_MASK                         (0xFFU)
  #define CRC_DATA_LL_SHIFT                        (0U)
  #define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
  #define CRC_DATA_LU_MASK                         (0xFF00U)
  #define CRC_DATA_LU_SHIFT                        (8U)
  #define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
  #define CRC_DATA_HL_MASK                         (0xFF0000U)
  #define CRC_DATA_HL_SHIFT                        (16U)
  #define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
  #define CRC_DATA_HU_MASK                         (0xFF000000U)
  #define CRC_DATA_HU_SHIFT                        (24U)
  #define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
  /*! @} */
  
  /*! @name DATALL - CRC_DATALL register. */
  /*! @{ */
  #define CRC_DATALL_DATALL_MASK                   (0xFFU)
  #define CRC_DATALL_DATALL_SHIFT                  (0U)
  #define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
  /*! @} */
  
  /*! @name DATALU - CRC_DATALU register. */
  /*! @{ */
  #define CRC_DATALU_DATALU_MASK                   (0xFFU)
  #define CRC_DATALU_DATALU_SHIFT                  (0U)
  #define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
  /*! @} */
  
  /*! @name DATAHL - CRC_DATAHL register. */
  /*! @{ */
  #define CRC_DATAHL_DATAHL_MASK                   (0xFFU)
  #define CRC_DATAHL_DATAHL_SHIFT                  (0U)
  #define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
  /*! @} */
  
  /*! @name DATAHU - CRC_DATAHU register. */
  /*! @{ */
  #define CRC_DATAHU_DATAHU_MASK                   (0xFFU)
  #define CRC_DATAHU_DATAHU_SHIFT                  (0U)
  #define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
  /*! @} */
  
  /*! @name GPOLYL - CRC_GPOLYL register. */
  /*! @{ */
  #define CRC_GPOLYL_GPOLYL_MASK                   (0xFFFFU)
  #define CRC_GPOLYL_GPOLYL_SHIFT                  (0U)
  #define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
  /*! @} */
  
  /*! @name GPOLYH - CRC_GPOLYH register. */
  /*! @{ */
  #define CRC_GPOLYH_GPOLYH_MASK                   (0xFFFFU)
  #define CRC_GPOLYH_GPOLYH_SHIFT                  (0U)
  #define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
  /*! @} */
  
  /*! @name GPOLY - CRC Polynomial register */
  /*! @{ */
  #define CRC_GPOLY_LOW_MASK                       (0xFFFFU)
  #define CRC_GPOLY_LOW_SHIFT                      (0U)
  #define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
  #define CRC_GPOLY_HIGH_MASK                      (0xFFFF0000U)
  #define CRC_GPOLY_HIGH_SHIFT                     (16U)
  #define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
  /*! @} */
  
  /*! @name GPOLYLL - CRC_GPOLYLL register. */
  /*! @{ */
  #define CRC_GPOLYLL_GPOLYLL_MASK                 (0xFFU)
  #define CRC_GPOLYLL_GPOLYLL_SHIFT                (0U)
  #define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
  /*! @} */
  
  /*! @name GPOLYLU - CRC_GPOLYLU register. */
  /*! @{ */
  #define CRC_GPOLYLU_GPOLYLU_MASK                 (0xFFU)
  #define CRC_GPOLYLU_GPOLYLU_SHIFT                (0U)
  #define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
  /*! @} */
  
  /*! @name GPOLYHL - CRC_GPOLYHL register. */
  /*! @{ */
  #define CRC_GPOLYHL_GPOLYHL_MASK                 (0xFFU)
  #define CRC_GPOLYHL_GPOLYHL_SHIFT                (0U)
  #define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
  /*! @} */
  
  /*! @name GPOLYHU - CRC_GPOLYHU register. */
  /*! @{ */
  #define CRC_GPOLYHU_GPOLYHU_MASK                 (0xFFU)
  #define CRC_GPOLYHU_GPOLYHU_SHIFT                (0U)
  #define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
  /*! @} */
  
  /*! @name CTRL - CRC Control register */
  /*! @{ */
  #define CRC_CTRL_TCRC_MASK                       (0x1000000U)
  #define CRC_CTRL_TCRC_SHIFT                      (24U)
  /*! TCRC
   *  0b0..16-bit CRC protocol.
   *  0b1..32-bit CRC protocol.
   */
  #define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
  #define CRC_CTRL_WAS_MASK                        (0x2000000U)
  #define CRC_CTRL_WAS_SHIFT                       (25U)
  /*! WAS - Write CRC Data Register As Seed
   *  0b0..Writes to the CRC data register are data values.
   *  0b1..Writes to the CRC data register are seed values.
   */
  #define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
  #define CRC_CTRL_FXOR_MASK                       (0x4000000U)
  #define CRC_CTRL_FXOR_SHIFT                      (26U)
  /*! FXOR - Complement Read Of CRC Data Register
   *  0b0..No XOR on reading.
   *  0b1..Invert or complement the read value of the CRC Data register.
   */
  #define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
  #define CRC_CTRL_TOTR_MASK                       (0x30000000U)
  #define CRC_CTRL_TOTR_SHIFT                      (28U)
  /*! TOTR - Type Of Transpose For Read
   *  0b00..No transposition.
   *  0b01..Bits in bytes are transposed; bytes are not transposed.
   *  0b10..Both bits in bytes and bytes are transposed.
   *  0b11..Only bytes are transposed; no bits in a byte are transposed.
   */
  #define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
  #define CRC_CTRL_TOT_MASK                        (0xC0000000U)
  #define CRC_CTRL_TOT_SHIFT                       (30U)
  /*! TOT - Type Of Transpose For Writes
   *  0b00..No transposition.
   *  0b01..Bits in bytes are transposed; bytes are not transposed.
   *  0b10..Both bits in bytes and bytes are transposed.
   *  0b11..Only bytes are transposed; no bits in a byte are transposed.
   */
  #define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
  /*! @} */
  
  /*! @name CTRLHU - CRC_CTRLHU register. */
  /*! @{ */
  #define CRC_CTRLHU_TCRC_MASK                     (0x1U)
  #define CRC_CTRLHU_TCRC_SHIFT                    (0U)
  /*! TCRC
   *  0b0..16-bit CRC protocol.
   *  0b1..32-bit CRC protocol.
   */
  #define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
  #define CRC_CTRLHU_WAS_MASK                      (0x2U)
  #define CRC_CTRLHU_WAS_SHIFT                     (1U)
  /*! WAS
   *  0b0..Writes to CRC data register are data values.
   *  0b1..Writes to CRC data reguster are seed values.
   */
  #define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
  #define CRC_CTRLHU_FXOR_MASK                     (0x4U)
  #define CRC_CTRLHU_FXOR_SHIFT                    (2U)
  /*! FXOR
   *  0b0..No XOR on reading.
   *  0b1..Invert or complement the read value of CRC data register.
   */
  #define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
  #define CRC_CTRLHU_TOTR_MASK                     (0x30U)
  #define CRC_CTRLHU_TOTR_SHIFT                    (4U)
  /*! TOTR
   *  0b00..No Transposition.
   *  0b01..Bits in bytes are transposed, bytes are not transposed.
   *  0b10..Both bits in bytes and bytes are transposed.
   *  0b11..Only bytes are transposed; no bits in a byte are transposed.
   */
  #define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
  #define CRC_CTRLHU_TOT_MASK                      (0xC0U)
  #define CRC_CTRLHU_TOT_SHIFT                     (6U)
  /*! TOT
   *  0b00..No Transposition.
   *  0b01..Bits in bytes are transposed, bytes are not transposed.
   *  0b10..Both bits in bytes and bytes are transposed.
   *  0b11..Only bytes are transposed; no bits in a byte are transposed.
   */
  #define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group CRC_Register_Masks */
  
  
  /* CRC - Peripheral instance base addresses */
  /** Peripheral CRC base address */
  #define CRC_BASE                                 (0x40032000u)
  /** Peripheral CRC base pointer */
  #define CRC0                                     ((CRC_Type *)CRC_BASE)
  /** Array initializer of CRC peripheral base addresses */
  #define CRC_BASE_ADDRS                           { CRC_BASE }
  /** Array initializer of CRC peripheral base pointers */
  #define CRC_BASE_PTRS                            { CRC0 }
  
  /*!
   * @}
   */ /* end of group CRC_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- DAC Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
   * @{
   */
  
  /** DAC - Register Layout Typedef */
  typedef struct {
    struct {                                         /* offset: 0x0, array step: 0x2 */
      __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
      __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
    } DAT[16];
    __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
    __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
    __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
    __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
  } DAC_Type;
  
  /* ----------------------------------------------------------------------------
     -- DAC Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DAC_Register_Masks DAC Register Masks
   * @{
   */
  
  /*! @name DATL - DAC Data Low Register */
  /*! @{ */
  #define DAC_DATL_DATA0_MASK                      (0xFFU)
  #define DAC_DATL_DATA0_SHIFT                     (0U)
  #define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
  /*! @} */
  
  /* The count of DAC_DATL */
  #define DAC_DATL_COUNT                           (16U)
  
  /*! @name DATH - DAC Data High Register */
  /*! @{ */
  #define DAC_DATH_DATA1_MASK                      (0xFU)
  #define DAC_DATH_DATA1_SHIFT                     (0U)
  #define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
  /*! @} */
  
  /* The count of DAC_DATH */
  #define DAC_DATH_COUNT                           (16U)
  
  /*! @name SR - DAC Status Register */
  /*! @{ */
  #define DAC_SR_DACBFRPBF_MASK                    (0x1U)
  #define DAC_SR_DACBFRPBF_SHIFT                   (0U)
  /*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag
   *  0b0..The DAC buffer read pointer is not equal to C2[DACBFUP].
   *  0b1..The DAC buffer read pointer is equal to C2[DACBFUP].
   */
  #define DAC_SR_DACBFRPBF(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
  #define DAC_SR_DACBFRPTF_MASK                    (0x2U)
  #define DAC_SR_DACBFRPTF_SHIFT                   (1U)
  /*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag
   *  0b0..The DAC buffer read pointer is not zero.
   *  0b1..The DAC buffer read pointer is zero.
   */
  #define DAC_SR_DACBFRPTF(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
  #define DAC_SR_DACBFWMF_MASK                     (0x4U)
  #define DAC_SR_DACBFWMF_SHIFT                    (2U)
  /*! DACBFWMF - DAC Buffer Watermark Flag
   *  0b0..The DAC buffer read pointer has not reached the watermark level.
   *  0b1..The DAC buffer read pointer has reached the watermark level.
   */
  #define DAC_SR_DACBFWMF(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
  /*! @} */
  
  /*! @name C0 - DAC Control Register */
  /*! @{ */
  #define DAC_C0_DACBBIEN_MASK                     (0x1U)
  #define DAC_C0_DACBBIEN_SHIFT                    (0U)
  /*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable
   *  0b0..The DAC buffer read pointer bottom flag interrupt is disabled.
   *  0b1..The DAC buffer read pointer bottom flag interrupt is enabled.
   */
  #define DAC_C0_DACBBIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
  #define DAC_C0_DACBTIEN_MASK                     (0x2U)
  #define DAC_C0_DACBTIEN_SHIFT                    (1U)
  /*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable
   *  0b0..The DAC buffer read pointer top flag interrupt is disabled.
   *  0b1..The DAC buffer read pointer top flag interrupt is enabled.
   */
  #define DAC_C0_DACBTIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
  #define DAC_C0_DACBWIEN_MASK                     (0x4U)
  #define DAC_C0_DACBWIEN_SHIFT                    (2U)
  /*! DACBWIEN - DAC Buffer Watermark Interrupt Enable
   *  0b0..The DAC buffer watermark interrupt is disabled.
   *  0b1..The DAC buffer watermark interrupt is enabled.
   */
  #define DAC_C0_DACBWIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
  #define DAC_C0_LPEN_MASK                         (0x8U)
  #define DAC_C0_LPEN_SHIFT                        (3U)
  /*! LPEN - DAC Low Power Control
   *  0b0..High-Power mode
   *  0b1..Low-Power mode
   */
  #define DAC_C0_LPEN(x)                           (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
  #define DAC_C0_DACSWTRG_MASK                     (0x10U)
  #define DAC_C0_DACSWTRG_SHIFT                    (4U)
  /*! DACSWTRG - DAC Software Trigger
   *  0b0..The DAC soft trigger is not valid.
   *  0b1..The DAC soft trigger is valid.
   */
  #define DAC_C0_DACSWTRG(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
  #define DAC_C0_DACTRGSEL_MASK                    (0x20U)
  #define DAC_C0_DACTRGSEL_SHIFT                   (5U)
  /*! DACTRGSEL - DAC Trigger Select
   *  0b0..The DAC hardware trigger is selected.
   *  0b1..The DAC software trigger is selected.
   */
  #define DAC_C0_DACTRGSEL(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
  #define DAC_C0_DACRFS_MASK                       (0x40U)
  #define DAC_C0_DACRFS_SHIFT                      (6U)
  /*! DACRFS - DAC Reference Select
   *  0b0..The DAC selects DACREF_1 as the reference voltage.
   *  0b1..The DAC selects DACREF_2 as the reference voltage.
   */
  #define DAC_C0_DACRFS(x)                         (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
  #define DAC_C0_DACEN_MASK                        (0x80U)
  #define DAC_C0_DACEN_SHIFT                       (7U)
  /*! DACEN - DAC Enable
   *  0b0..The DAC system is disabled.
   *  0b1..The DAC system is enabled.
   */
  #define DAC_C0_DACEN(x)                          (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
  /*! @} */
  
  /*! @name C1 - DAC Control Register 1 */
  /*! @{ */
  #define DAC_C1_DACBFEN_MASK                      (0x1U)
  #define DAC_C1_DACBFEN_SHIFT                     (0U)
  /*! DACBFEN - DAC Buffer Enable
   *  0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer.
   *  0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.
   */
  #define DAC_C1_DACBFEN(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
  #define DAC_C1_DACBFMD_MASK                      (0x6U)
  #define DAC_C1_DACBFMD_SHIFT                     (1U)
  /*! DACBFMD - DAC Buffer Work Mode Select
   *  0b00..Normal mode
   *  0b01..Swing mode
   *  0b10..One-Time Scan mode
   *  0b11..FIFO mode
   */
  #define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
  #define DAC_C1_DACBFWM_MASK                      (0x18U)
  #define DAC_C1_DACBFWM_SHIFT                     (3U)
  /*! DACBFWM - DAC Buffer Watermark Select
   *  0b00..In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining in FIFO will set watermark status bit.
   *  0b01..In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data remaining in FIFO will set watermark status bit.
   *  0b10..In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data remaining in FIFO will set watermark status bit.
   *  0b11..In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data remaining in FIFO will set watermark status bit.
   */
  #define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
  #define DAC_C1_DMAEN_MASK                        (0x80U)
  #define DAC_C1_DMAEN_SHIFT                       (7U)
  /*! DMAEN - DMA Enable Select
   *  0b0..DMA is disabled.
   *  0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
   */
  #define DAC_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
  /*! @} */
  
  /*! @name C2 - DAC Control Register 2 */
  /*! @{ */
  #define DAC_C2_DACBFUP_MASK                      (0xFU)
  #define DAC_C2_DACBFUP_SHIFT                     (0U)
  #define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
  #define DAC_C2_DACBFRP_MASK                      (0xF0U)
  #define DAC_C2_DACBFRP_SHIFT                     (4U)
  #define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group DAC_Register_Masks */
  
  
  /* DAC - Peripheral instance base addresses */
  /** Peripheral DAC0 base address */
  #define DAC0_BASE                                (0x4003F000u)
  /** Peripheral DAC0 base pointer */
  #define DAC0                                     ((DAC_Type *)DAC0_BASE)
  /** Array initializer of DAC peripheral base addresses */
  #define DAC_BASE_ADDRS                           { DAC0_BASE }
  /** Array initializer of DAC peripheral base pointers */
  #define DAC_BASE_PTRS                            { DAC0 }
  /** Interrupt vectors for the DAC peripheral type */
  #define DAC_IRQS                                 { DAC0_IRQn }
  
  /*!
   * @}
   */ /* end of group DAC_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- DMA Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
   * @{
   */
  
  /** DMA - Register Layout Typedef */
  typedef struct {
    __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
    __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
         uint8_t RESERVED_0[4];
    __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
         uint8_t RESERVED_1[4];
    __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
    __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
    __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
    __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
    __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
    __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
    __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
    __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
    __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
         uint8_t RESERVED_2[4];
    __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
         uint8_t RESERVED_3[4];
    __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
         uint8_t RESERVED_4[4];
    __I  uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
         uint8_t RESERVED_5[12];
    __IO uint32_t EARS;                              /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
         uint8_t RESERVED_6[184];
    __IO uint8_t DCHPRI3;                            /**< Channel n Priority Register, offset: 0x100 */
    __IO uint8_t DCHPRI2;                            /**< Channel n Priority Register, offset: 0x101 */
    __IO uint8_t DCHPRI1;                            /**< Channel n Priority Register, offset: 0x102 */
    __IO uint8_t DCHPRI0;                            /**< Channel n Priority Register, offset: 0x103 */
         uint8_t RESERVED_7[3836];
    struct {                                         /* offset: 0x1000, array step: 0x20 */
      __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
      __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
      __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
      union {                                          /* offset: 0x1008, array step: 0x20 */
        __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
        __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
        __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
      };
      __IO int32_t SLAST;                              /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
      __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
      __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
      union {                                          /* offset: 0x1016, array step: 0x20 */
        __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
        __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
      };
      __IO int32_t DLAST_SGA;                          /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
      __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
      union {                                          /* offset: 0x101E, array step: 0x20 */
        __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
        __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
      };
    } TCD[4];
  } DMA_Type;
  
  /* ----------------------------------------------------------------------------
     -- DMA Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DMA_Register_Masks DMA Register Masks
   * @{
   */
  
  /*! @name CR - Control Register */
  /*! @{ */
  #define DMA_CR_EDBG_MASK                         (0x2U)
  #define DMA_CR_EDBG_SHIFT                        (1U)
  /*! EDBG - Enable Debug
   *  0b0..When in debug mode, the DMA continues to operate.
   *  0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
   */
  #define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
  #define DMA_CR_ERCA_MASK                         (0x4U)
  #define DMA_CR_ERCA_SHIFT                        (2U)
  /*! ERCA - Enable Round Robin Channel Arbitration
   *  0b0..Fixed priority arbitration is used for channel selection .
   *  0b1..Round robin arbitration is used for channel selection .
   */
  #define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
  #define DMA_CR_HOE_MASK                          (0x10U)
  #define DMA_CR_HOE_SHIFT                         (4U)
  /*! HOE - Halt On Error
   *  0b0..Normal operation
   *  0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
   */
  #define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
  #define DMA_CR_HALT_MASK                         (0x20U)
  #define DMA_CR_HALT_SHIFT                        (5U)
  /*! HALT - Halt DMA Operations
   *  0b0..Normal operation
   *  0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
   */
  #define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
  #define DMA_CR_CLM_MASK                          (0x40U)
  #define DMA_CR_CLM_SHIFT                         (6U)
  /*! CLM - Continuous Link Mode
   *  0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
   *  0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.
   */
  #define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
  #define DMA_CR_EMLM_MASK                         (0x80U)
  #define DMA_CR_EMLM_SHIFT                        (7U)
  /*! EMLM - Enable Minor Loop Mapping
   *  0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
   *  0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.
   */
  #define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
  #define DMA_CR_ECX_MASK                          (0x10000U)
  #define DMA_CR_ECX_SHIFT                         (16U)
  /*! ECX - Error Cancel Transfer
   *  0b0..Normal operation
   *  0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
   */
  #define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
  #define DMA_CR_CX_MASK                           (0x20000U)
  #define DMA_CR_CX_SHIFT                          (17U)
  /*! CX - Cancel Transfer
   *  0b0..Normal operation
   *  0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
   */
  #define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
  #define DMA_CR_ACTIVE_MASK                       (0x80000000U)
  #define DMA_CR_ACTIVE_SHIFT                      (31U)
  /*! ACTIVE - DMA Active Status
   *  0b0..eDMA is idle.
   *  0b1..eDMA is executing a channel.
   */
  #define DMA_CR_ACTIVE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
  /*! @} */
  
  /*! @name ES - Error Status Register */
  /*! @{ */
  #define DMA_ES_DBE_MASK                          (0x1U)
  #define DMA_ES_DBE_SHIFT                         (0U)
  /*! DBE - Destination Bus Error
   *  0b0..No destination bus error
   *  0b1..The last recorded error was a bus error on a destination write
   */
  #define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
  #define DMA_ES_SBE_MASK                          (0x2U)
  #define DMA_ES_SBE_SHIFT                         (1U)
  /*! SBE - Source Bus Error
   *  0b0..No source bus error
   *  0b1..The last recorded error was a bus error on a source read
   */
  #define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
  #define DMA_ES_SGE_MASK                          (0x4U)
  #define DMA_ES_SGE_SHIFT                         (2U)
  /*! SGE - Scatter/Gather Configuration Error
   *  0b0..No scatter/gather configuration error
   *  0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
   */
  #define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
  #define DMA_ES_NCE_MASK                          (0x8U)
  #define DMA_ES_NCE_SHIFT                         (3U)
  /*! NCE - NBYTES/CITER Configuration Error
   *  0b0..No NBYTES/CITER configuration error
   *  0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
   */
  #define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
  #define DMA_ES_DOE_MASK                          (0x10U)
  #define DMA_ES_DOE_SHIFT                         (4U)
  /*! DOE - Destination Offset Error
   *  0b0..No destination offset configuration error
   *  0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
   */
  #define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
  #define DMA_ES_DAE_MASK                          (0x20U)
  #define DMA_ES_DAE_SHIFT                         (5U)
  /*! DAE - Destination Address Error
   *  0b0..No destination address configuration error
   *  0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
   */
  #define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
  #define DMA_ES_SOE_MASK                          (0x40U)
  #define DMA_ES_SOE_SHIFT                         (6U)
  /*! SOE - Source Offset Error
   *  0b0..No source offset configuration error
   *  0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
   */
  #define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
  #define DMA_ES_SAE_MASK                          (0x80U)
  #define DMA_ES_SAE_SHIFT                         (7U)
  /*! SAE - Source Address Error
   *  0b0..No source address configuration error.
   *  0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
   */
  #define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
  #define DMA_ES_ERRCHN_MASK                       (0x300U)
  #define DMA_ES_ERRCHN_SHIFT                      (8U)
  #define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
  #define DMA_ES_CPE_MASK                          (0x4000U)
  #define DMA_ES_CPE_SHIFT                         (14U)
  /*! CPE - Channel Priority Error
   *  0b0..No channel priority error
   *  0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique.
   */
  #define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
  #define DMA_ES_ECX_MASK                          (0x10000U)
  #define DMA_ES_ECX_SHIFT                         (16U)
  /*! ECX - Transfer Canceled
   *  0b0..No canceled transfers
   *  0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
   */
  #define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
  #define DMA_ES_VLD_MASK                          (0x80000000U)
  #define DMA_ES_VLD_SHIFT                         (31U)
  /*! VLD
   *  0b0..No ERR bits are set
   *  0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared
   */
  #define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
  /*! @} */
  
  /*! @name ERQ - Enable Request Register */
  /*! @{ */
  #define DMA_ERQ_ERQ0_MASK                        (0x1U)
  #define DMA_ERQ_ERQ0_SHIFT                       (0U)
  /*! ERQ0 - Enable DMA Request 0
   *  0b0..The DMA request signal for the corresponding channel is disabled
   *  0b1..The DMA request signal for the corresponding channel is enabled
   */
  #define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
  #define DMA_ERQ_ERQ1_MASK                        (0x2U)
  #define DMA_ERQ_ERQ1_SHIFT                       (1U)
  /*! ERQ1 - Enable DMA Request 1
   *  0b0..The DMA request signal for the corresponding channel is disabled
   *  0b1..The DMA request signal for the corresponding channel is enabled
   */
  #define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
  #define DMA_ERQ_ERQ2_MASK                        (0x4U)
  #define DMA_ERQ_ERQ2_SHIFT                       (2U)
  /*! ERQ2 - Enable DMA Request 2
   *  0b0..The DMA request signal for the corresponding channel is disabled
   *  0b1..The DMA request signal for the corresponding channel is enabled
   */
  #define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
  #define DMA_ERQ_ERQ3_MASK                        (0x8U)
  #define DMA_ERQ_ERQ3_SHIFT                       (3U)
  /*! ERQ3 - Enable DMA Request 3
   *  0b0..The DMA request signal for the corresponding channel is disabled
   *  0b1..The DMA request signal for the corresponding channel is enabled
   */
  #define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
  /*! @} */
  
  /*! @name EEI - Enable Error Interrupt Register */
  /*! @{ */
  #define DMA_EEI_EEI0_MASK                        (0x1U)
  #define DMA_EEI_EEI0_SHIFT                       (0U)
  /*! EEI0 - Enable Error Interrupt 0
   *  0b0..The error signal for corresponding channel does not generate an error interrupt
   *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
   */
  #define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
  #define DMA_EEI_EEI1_MASK                        (0x2U)
  #define DMA_EEI_EEI1_SHIFT                       (1U)
  /*! EEI1 - Enable Error Interrupt 1
   *  0b0..The error signal for corresponding channel does not generate an error interrupt
   *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
   */
  #define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
  #define DMA_EEI_EEI2_MASK                        (0x4U)
  #define DMA_EEI_EEI2_SHIFT                       (2U)
  /*! EEI2 - Enable Error Interrupt 2
   *  0b0..The error signal for corresponding channel does not generate an error interrupt
   *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
   */
  #define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
  #define DMA_EEI_EEI3_MASK                        (0x8U)
  #define DMA_EEI_EEI3_SHIFT                       (3U)
  /*! EEI3 - Enable Error Interrupt 3
   *  0b0..The error signal for corresponding channel does not generate an error interrupt
   *  0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
   */
  #define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
  /*! @} */
  
  /*! @name CEEI - Clear Enable Error Interrupt Register */
  /*! @{ */
  #define DMA_CEEI_CEEI_MASK                       (0x3U)
  #define DMA_CEEI_CEEI_SHIFT                      (0U)
  #define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
  #define DMA_CEEI_CAEE_MASK                       (0x40U)
  #define DMA_CEEI_CAEE_SHIFT                      (6U)
  /*! CAEE - Clear All Enable Error Interrupts
   *  0b0..Clear only the EEI bit specified in the CEEI field
   *  0b1..Clear all bits in EEI
   */
  #define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
  #define DMA_CEEI_NOP_MASK                        (0x80U)
  #define DMA_CEEI_NOP_SHIFT                       (7U)
  /*! NOP - No Op enable
   *  0b0..Normal operation
   *  0b1..No operation, ignore the other bits in this register
   */
  #define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
  /*! @} */
  
  /*! @name SEEI - Set Enable Error Interrupt Register */
  /*! @{ */
  #define DMA_SEEI_SEEI_MASK                       (0x3U)
  #define DMA_SEEI_SEEI_SHIFT                      (0U)
  #define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
  #define DMA_SEEI_SAEE_MASK                       (0x40U)
  #define DMA_SEEI_SAEE_SHIFT                      (6U)
  /*! SAEE - Sets All Enable Error Interrupts
   *  0b0..Set only the EEI bit specified in the SEEI field.
   *  0b1..Sets all bits in EEI
   */
  #define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
  #define DMA_SEEI_NOP_MASK                        (0x80U)
  #define DMA_SEEI_NOP_SHIFT                       (7U)
  /*! NOP - No Op enable
   *  0b0..Normal operation
   *  0b1..No operation, ignore the other bits in this register
   */
  #define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
  /*! @} */
  
  /*! @name CERQ - Clear Enable Request Register */
  /*! @{ */
  #define DMA_CERQ_CERQ_MASK                       (0x3U)
  #define DMA_CERQ_CERQ_SHIFT                      (0U)
  #define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
  #define DMA_CERQ_CAER_MASK                       (0x40U)
  #define DMA_CERQ_CAER_SHIFT                      (6U)
  /*! CAER - Clear All Enable Requests
   *  0b0..Clear only the ERQ bit specified in the CERQ field
   *  0b1..Clear all bits in ERQ
   */
  #define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
  #define DMA_CERQ_NOP_MASK                        (0x80U)
  #define DMA_CERQ_NOP_SHIFT                       (7U)
  /*! NOP - No Op enable
   *  0b0..Normal operation
   *  0b1..No operation, ignore the other bits in this register
   */
  #define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
  /*! @} */
  
  /*! @name SERQ - Set Enable Request Register */
  /*! @{ */
  #define DMA_SERQ_SERQ_MASK                       (0x3U)
  #define DMA_SERQ_SERQ_SHIFT                      (0U)
  #define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
  #define DMA_SERQ_SAER_MASK                       (0x40U)
  #define DMA_SERQ_SAER_SHIFT                      (6U)
  /*! SAER - Set All Enable Requests
   *  0b0..Set only the ERQ bit specified in the SERQ field
   *  0b1..Set all bits in ERQ
   */
  #define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
  #define DMA_SERQ_NOP_MASK                        (0x80U)
  #define DMA_SERQ_NOP_SHIFT                       (7U)
  /*! NOP - No Op enable
   *  0b0..Normal operation
   *  0b1..No operation, ignore the other bits in this register
   */
  #define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
  /*! @} */
  
  /*! @name CDNE - Clear DONE Status Bit Register */
  /*! @{ */
  #define DMA_CDNE_CDNE_MASK                       (0x3U)
  #define DMA_CDNE_CDNE_SHIFT                      (0U)
  #define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
  #define DMA_CDNE_CADN_MASK                       (0x40U)
  #define DMA_CDNE_CADN_SHIFT                      (6U)
  /*! CADN - Clears All DONE Bits
   *  0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
   *  0b1..Clears all bits in TCDn_CSR[DONE]
   */
  #define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
  #define DMA_CDNE_NOP_MASK                        (0x80U)
  #define DMA_CDNE_NOP_SHIFT                       (7U)
  /*! NOP - No Op enable
   *  0b0..Normal operation
   *  0b1..No operation, ignore the other bits in this register
   */
  #define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
  /*! @} */
  
  /*! @name SSRT - Set START Bit Register */
  /*! @{ */
  #define DMA_SSRT_SSRT_MASK                       (0x3U)
  #define DMA_SSRT_SSRT_SHIFT                      (0U)
  #define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
  #define DMA_SSRT_SAST_MASK                       (0x40U)
  #define DMA_SSRT_SAST_SHIFT                      (6U)
  /*! SAST - Set All START Bits (activates all channels)
   *  0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
   *  0b1..Set all bits in TCDn_CSR[START]
   */
  #define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
  #define DMA_SSRT_NOP_MASK                        (0x80U)
  #define DMA_SSRT_NOP_SHIFT                       (7U)
  /*! NOP - No Op enable
   *  0b0..Normal operation
   *  0b1..No operation, ignore the other bits in this register
   */
  #define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
  /*! @} */
  
  /*! @name CERR - Clear Error Register */
  /*! @{ */
  #define DMA_CERR_CERR_MASK                       (0x3U)
  #define DMA_CERR_CERR_SHIFT                      (0U)
  #define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
  #define DMA_CERR_CAEI_MASK                       (0x40U)
  #define DMA_CERR_CAEI_SHIFT                      (6U)
  /*! CAEI - Clear All Error Indicators
   *  0b0..Clear only the ERR bit specified in the CERR field
   *  0b1..Clear all bits in ERR
   */
  #define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
  #define DMA_CERR_NOP_MASK                        (0x80U)
  #define DMA_CERR_NOP_SHIFT                       (7U)
  /*! NOP - No Op enable
   *  0b0..Normal operation
   *  0b1..No operation, ignore the other bits in this register
   */
  #define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
  /*! @} */
  
  /*! @name CINT - Clear Interrupt Request Register */
  /*! @{ */
  #define DMA_CINT_CINT_MASK                       (0x3U)
  #define DMA_CINT_CINT_SHIFT                      (0U)
  #define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
  #define DMA_CINT_CAIR_MASK                       (0x40U)
  #define DMA_CINT_CAIR_SHIFT                      (6U)
  /*! CAIR - Clear All Interrupt Requests
   *  0b0..Clear only the INT bit specified in the CINT field
   *  0b1..Clear all bits in INT
   */
  #define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
  #define DMA_CINT_NOP_MASK                        (0x80U)
  #define DMA_CINT_NOP_SHIFT                       (7U)
  /*! NOP - No Op enable
   *  0b0..Normal operation
   *  0b1..No operation, ignore the other bits in this register
   */
  #define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
  /*! @} */
  
  /*! @name INT - Interrupt Request Register */
  /*! @{ */
  #define DMA_INT_INT0_MASK                        (0x1U)
  #define DMA_INT_INT0_SHIFT                       (0U)
  /*! INT0 - Interrupt Request 0
   *  0b0..The interrupt request for corresponding channel is cleared
   *  0b1..The interrupt request for corresponding channel is active
   */
  #define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
  #define DMA_INT_INT1_MASK                        (0x2U)
  #define DMA_INT_INT1_SHIFT                       (1U)
  /*! INT1 - Interrupt Request 1
   *  0b0..The interrupt request for corresponding channel is cleared
   *  0b1..The interrupt request for corresponding channel is active
   */
  #define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
  #define DMA_INT_INT2_MASK                        (0x4U)
  #define DMA_INT_INT2_SHIFT                       (2U)
  /*! INT2 - Interrupt Request 2
   *  0b0..The interrupt request for corresponding channel is cleared
   *  0b1..The interrupt request for corresponding channel is active
   */
  #define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
  #define DMA_INT_INT3_MASK                        (0x8U)
  #define DMA_INT_INT3_SHIFT                       (3U)
  /*! INT3 - Interrupt Request 3
   *  0b0..The interrupt request for corresponding channel is cleared
   *  0b1..The interrupt request for corresponding channel is active
   */
  #define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
  /*! @} */
  
  /*! @name ERR - Error Register */
  /*! @{ */
  #define DMA_ERR_ERR0_MASK                        (0x1U)
  #define DMA_ERR_ERR0_SHIFT                       (0U)
  /*! ERR0 - Error In Channel 0
   *  0b0..An error in the corresponding channel has not occurred
   *  0b1..An error in the corresponding channel has occurred
   */
  #define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
  #define DMA_ERR_ERR1_MASK                        (0x2U)
  #define DMA_ERR_ERR1_SHIFT                       (1U)
  /*! ERR1 - Error In Channel 1
   *  0b0..An error in the corresponding channel has not occurred
   *  0b1..An error in the corresponding channel has occurred
   */
  #define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
  #define DMA_ERR_ERR2_MASK                        (0x4U)
  #define DMA_ERR_ERR2_SHIFT                       (2U)
  /*! ERR2 - Error In Channel 2
   *  0b0..An error in the corresponding channel has not occurred
   *  0b1..An error in the corresponding channel has occurred
   */
  #define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
  #define DMA_ERR_ERR3_MASK                        (0x8U)
  #define DMA_ERR_ERR3_SHIFT                       (3U)
  /*! ERR3 - Error In Channel 3
   *  0b0..An error in the corresponding channel has not occurred
   *  0b1..An error in the corresponding channel has occurred
   */
  #define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
  /*! @} */
  
  /*! @name HRS - Hardware Request Status Register */
  /*! @{ */
  #define DMA_HRS_HRS0_MASK                        (0x1U)
  #define DMA_HRS_HRS0_SHIFT                       (0U)
  /*! HRS0 - Hardware Request Status Channel 0
   *  0b0..A hardware service request for channel 0 is not present
   *  0b1..A hardware service request for channel 0 is present
   */
  #define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
  #define DMA_HRS_HRS1_MASK                        (0x2U)
  #define DMA_HRS_HRS1_SHIFT                       (1U)
  /*! HRS1 - Hardware Request Status Channel 1
   *  0b0..A hardware service request for channel 1 is not present
   *  0b1..A hardware service request for channel 1 is present
   */
  #define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
  #define DMA_HRS_HRS2_MASK                        (0x4U)
  #define DMA_HRS_HRS2_SHIFT                       (2U)
  /*! HRS2 - Hardware Request Status Channel 2
   *  0b0..A hardware service request for channel 2 is not present
   *  0b1..A hardware service request for channel 2 is present
   */
  #define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
  #define DMA_HRS_HRS3_MASK                        (0x8U)
  #define DMA_HRS_HRS3_SHIFT                       (3U)
  /*! HRS3 - Hardware Request Status Channel 3
   *  0b0..A hardware service request for channel 3 is not present
   *  0b1..A hardware service request for channel 3 is present
   */
  #define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
  /*! @} */
  
  /*! @name EARS - Enable Asynchronous Request in Stop Register */
  /*! @{ */
  #define DMA_EARS_EDREQ_0_MASK                    (0x1U)
  #define DMA_EARS_EDREQ_0_SHIFT                   (0U)
  /*! EDREQ_0 - Enable asynchronous DMA request in stop for channel 0.
   *  0b0..Disable asynchronous DMA request for channel 0.
   *  0b1..Enable asynchronous DMA request for channel 0.
   */
  #define DMA_EARS_EDREQ_0(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
  #define DMA_EARS_EDREQ_1_MASK                    (0x2U)
  #define DMA_EARS_EDREQ_1_SHIFT                   (1U)
  /*! EDREQ_1 - Enable asynchronous DMA request in stop for channel 1.
   *  0b0..Disable asynchronous DMA request for channel 1
   *  0b1..Enable asynchronous DMA request for channel 1.
   */
  #define DMA_EARS_EDREQ_1(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
  #define DMA_EARS_EDREQ_2_MASK                    (0x4U)
  #define DMA_EARS_EDREQ_2_SHIFT                   (2U)
  /*! EDREQ_2 - Enable asynchronous DMA request in stop for channel 2.
   *  0b0..Disable asynchronous DMA request for channel 2.
   *  0b1..Enable asynchronous DMA request for channel 2.
   */
  #define DMA_EARS_EDREQ_2(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
  #define DMA_EARS_EDREQ_3_MASK                    (0x8U)
  #define DMA_EARS_EDREQ_3_SHIFT                   (3U)
  /*! EDREQ_3 - Enable asynchronous DMA request in stop for channel 3.
   *  0b0..Disable asynchronous DMA request for channel 3.
   *  0b1..Enable asynchronous DMA request for channel 3.
   */
  #define DMA_EARS_EDREQ_3(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
  /*! @} */
  
  /*! @name DCHPRI3 - Channel n Priority Register */
  /*! @{ */
  #define DMA_DCHPRI3_CHPRI_MASK                   (0x3U)
  #define DMA_DCHPRI3_CHPRI_SHIFT                  (0U)
  #define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
  #define DMA_DCHPRI3_DPA_MASK                     (0x40U)
  #define DMA_DCHPRI3_DPA_SHIFT                    (6U)
  /*! DPA - Disable Preempt Ability
   *  0b0..Channel n can suspend a lower priority channel
   *  0b1..Channel n cannot suspend any channel, regardless of channel priority
   */
  #define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
  #define DMA_DCHPRI3_ECP_MASK                     (0x80U)
  #define DMA_DCHPRI3_ECP_SHIFT                    (7U)
  /*! ECP - Enable Channel Preemption
   *  0b0..Channel n cannot be suspended by a higher priority channel's service request
   *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
   */
  #define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
  /*! @} */
  
  /*! @name DCHPRI2 - Channel n Priority Register */
  /*! @{ */
  #define DMA_DCHPRI2_CHPRI_MASK                   (0x3U)
  #define DMA_DCHPRI2_CHPRI_SHIFT                  (0U)
  #define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
  #define DMA_DCHPRI2_DPA_MASK                     (0x40U)
  #define DMA_DCHPRI2_DPA_SHIFT                    (6U)
  /*! DPA - Disable Preempt Ability
   *  0b0..Channel n can suspend a lower priority channel
   *  0b1..Channel n cannot suspend any channel, regardless of channel priority
   */
  #define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
  #define DMA_DCHPRI2_ECP_MASK                     (0x80U)
  #define DMA_DCHPRI2_ECP_SHIFT                    (7U)
  /*! ECP - Enable Channel Preemption
   *  0b0..Channel n cannot be suspended by a higher priority channel's service request
   *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
   */
  #define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
  /*! @} */
  
  /*! @name DCHPRI1 - Channel n Priority Register */
  /*! @{ */
  #define DMA_DCHPRI1_CHPRI_MASK                   (0x3U)
  #define DMA_DCHPRI1_CHPRI_SHIFT                  (0U)
  #define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
  #define DMA_DCHPRI1_DPA_MASK                     (0x40U)
  #define DMA_DCHPRI1_DPA_SHIFT                    (6U)
  /*! DPA - Disable Preempt Ability
   *  0b0..Channel n can suspend a lower priority channel
   *  0b1..Channel n cannot suspend any channel, regardless of channel priority
   */
  #define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
  #define DMA_DCHPRI1_ECP_MASK                     (0x80U)
  #define DMA_DCHPRI1_ECP_SHIFT                    (7U)
  /*! ECP - Enable Channel Preemption
   *  0b0..Channel n cannot be suspended by a higher priority channel's service request
   *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
   */
  #define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
  /*! @} */
  
  /*! @name DCHPRI0 - Channel n Priority Register */
  /*! @{ */
  #define DMA_DCHPRI0_CHPRI_MASK                   (0x3U)
  #define DMA_DCHPRI0_CHPRI_SHIFT                  (0U)
  #define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
  #define DMA_DCHPRI0_DPA_MASK                     (0x40U)
  #define DMA_DCHPRI0_DPA_SHIFT                    (6U)
  /*! DPA - Disable Preempt Ability
   *  0b0..Channel n can suspend a lower priority channel
   *  0b1..Channel n cannot suspend any channel, regardless of channel priority
   */
  #define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
  #define DMA_DCHPRI0_ECP_MASK                     (0x80U)
  #define DMA_DCHPRI0_ECP_SHIFT                    (7U)
  /*! ECP - Enable Channel Preemption
   *  0b0..Channel n cannot be suspended by a higher priority channel's service request
   *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
   */
  #define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
  /*! @} */
  
  /*! @name SADDR - TCD Source Address */
  /*! @{ */
  #define DMA_SADDR_SADDR_MASK                     (0xFFFFFFFFU)
  #define DMA_SADDR_SADDR_SHIFT                    (0U)
  #define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
  /*! @} */
  
  /* The count of DMA_SADDR */
  #define DMA_SADDR_COUNT                          (4U)
  
  /*! @name SOFF - TCD Signed Source Address Offset */
  /*! @{ */
  #define DMA_SOFF_SOFF_MASK                       (0xFFFFU)
  #define DMA_SOFF_SOFF_SHIFT                      (0U)
  #define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
  /*! @} */
  
  /* The count of DMA_SOFF */
  #define DMA_SOFF_COUNT                           (4U)
  
  /*! @name ATTR - TCD Transfer Attributes */
  /*! @{ */
  #define DMA_ATTR_DSIZE_MASK                      (0x7U)
  #define DMA_ATTR_DSIZE_SHIFT                     (0U)
  #define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
  #define DMA_ATTR_DMOD_MASK                       (0xF8U)
  #define DMA_ATTR_DMOD_SHIFT                      (3U)
  #define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
  #define DMA_ATTR_SSIZE_MASK                      (0x700U)
  #define DMA_ATTR_SSIZE_SHIFT                     (8U)
  /*! SSIZE - Source data transfer size
   *  0b000..8-bit
   *  0b001..16-bit
   *  0b010..32-bit
   *  0b011..Reserved
   *  0b100..16-byte
   *  0b101..32-byte
   *  0b110..Reserved
   *  0b111..Reserved
   */
  #define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
  #define DMA_ATTR_SMOD_MASK                       (0xF800U)
  #define DMA_ATTR_SMOD_SHIFT                      (11U)
  /*! SMOD - Source Address Modulo.
   *  0b00000..Source address modulo feature is disabled
   */
  #define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
  /*! @} */
  
  /* The count of DMA_ATTR */
  #define DMA_ATTR_COUNT                           (4U)
  
  /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */
  /*! @{ */
  #define DMA_NBYTES_MLNO_NBYTES_MASK              (0xFFFFFFFFU)
  #define DMA_NBYTES_MLNO_NBYTES_SHIFT             (0U)
  #define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
  /*! @} */
  
  /* The count of DMA_NBYTES_MLNO */
  #define DMA_NBYTES_MLNO_COUNT                    (4U)
  
  /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
  /*! @{ */
  #define DMA_NBYTES_MLOFFNO_NBYTES_MASK           (0x3FFFFFFFU)
  #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          (0U)
  #define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
  #define DMA_NBYTES_MLOFFNO_DMLOE_MASK            (0x40000000U)
  #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           (30U)
  /*! DMLOE - Destination Minor Loop Offset enable
   *  0b0..The minor loop offset is not applied to the DADDR
   *  0b1..The minor loop offset is applied to the DADDR
   */
  #define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
  #define DMA_NBYTES_MLOFFNO_SMLOE_MASK            (0x80000000U)
  #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           (31U)
  /*! SMLOE - Source Minor Loop Offset Enable
   *  0b0..The minor loop offset is not applied to the SADDR
   *  0b1..The minor loop offset is applied to the SADDR
   */
  #define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
  /*! @} */
  
  /* The count of DMA_NBYTES_MLOFFNO */
  #define DMA_NBYTES_MLOFFNO_COUNT                 (4U)
  
  /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
  /*! @{ */
  #define DMA_NBYTES_MLOFFYES_NBYTES_MASK          (0x3FFU)
  #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         (0U)
  #define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
  #define DMA_NBYTES_MLOFFYES_MLOFF_MASK           (0x3FFFFC00U)
  #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          (10U)
  #define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
  #define DMA_NBYTES_MLOFFYES_DMLOE_MASK           (0x40000000U)
  #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          (30U)
  /*! DMLOE - Destination Minor Loop Offset enable
   *  0b0..The minor loop offset is not applied to the DADDR
   *  0b1..The minor loop offset is applied to the DADDR
   */
  #define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
  #define DMA_NBYTES_MLOFFYES_SMLOE_MASK           (0x80000000U)
  #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          (31U)
  /*! SMLOE - Source Minor Loop Offset Enable
   *  0b0..The minor loop offset is not applied to the SADDR
   *  0b1..The minor loop offset is applied to the SADDR
   */
  #define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
  /*! @} */
  
  /* The count of DMA_NBYTES_MLOFFYES */
  #define DMA_NBYTES_MLOFFYES_COUNT                (4U)
  
  /*! @name SLAST - TCD Last Source Address Adjustment */
  /*! @{ */
  #define DMA_SLAST_SLAST_MASK                     (0xFFFFFFFFU)
  #define DMA_SLAST_SLAST_SHIFT                    (0U)
  #define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
  /*! @} */
  
  /* The count of DMA_SLAST */
  #define DMA_SLAST_COUNT                          (4U)
  
  /*! @name DADDR - TCD Destination Address */
  /*! @{ */
  #define DMA_DADDR_DADDR_MASK                     (0xFFFFFFFFU)
  #define DMA_DADDR_DADDR_SHIFT                    (0U)
  #define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
  /*! @} */
  
  /* The count of DMA_DADDR */
  #define DMA_DADDR_COUNT                          (4U)
  
  /*! @name DOFF - TCD Signed Destination Address Offset */
  /*! @{ */
  #define DMA_DOFF_DOFF_MASK                       (0xFFFFU)
  #define DMA_DOFF_DOFF_SHIFT                      (0U)
  #define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
  /*! @} */
  
  /* The count of DMA_DOFF */
  #define DMA_DOFF_COUNT                           (4U)
  
  /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
  /*! @{ */
  #define DMA_CITER_ELINKNO_CITER_MASK             (0x7FFFU)
  #define DMA_CITER_ELINKNO_CITER_SHIFT            (0U)
  #define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
  #define DMA_CITER_ELINKNO_ELINK_MASK             (0x8000U)
  #define DMA_CITER_ELINKNO_ELINK_SHIFT            (15U)
  /*! ELINK - Enable channel-to-channel linking on minor-loop complete
   *  0b0..The channel-to-channel linking is disabled
   *  0b1..The channel-to-channel linking is enabled
   */
  #define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
  /*! @} */
  
  /* The count of DMA_CITER_ELINKNO */
  #define DMA_CITER_ELINKNO_COUNT                  (4U)
  
  /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
  /*! @{ */
  #define DMA_CITER_ELINKYES_CITER_MASK            (0x1FFU)
  #define DMA_CITER_ELINKYES_CITER_SHIFT           (0U)
  #define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
  #define DMA_CITER_ELINKYES_LINKCH_MASK           (0x600U)
  #define DMA_CITER_ELINKYES_LINKCH_SHIFT          (9U)
  #define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
  #define DMA_CITER_ELINKYES_ELINK_MASK            (0x8000U)
  #define DMA_CITER_ELINKYES_ELINK_SHIFT           (15U)
  /*! ELINK - Enable channel-to-channel linking on minor-loop complete
   *  0b0..The channel-to-channel linking is disabled
   *  0b1..The channel-to-channel linking is enabled
   */
  #define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
  /*! @} */
  
  /* The count of DMA_CITER_ELINKYES */
  #define DMA_CITER_ELINKYES_COUNT                 (4U)
  
  /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
  /*! @{ */
  #define DMA_DLAST_SGA_DLASTSGA_MASK              (0xFFFFFFFFU)
  #define DMA_DLAST_SGA_DLASTSGA_SHIFT             (0U)
  #define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
  /*! @} */
  
  /* The count of DMA_DLAST_SGA */
  #define DMA_DLAST_SGA_COUNT                      (4U)
  
  /*! @name CSR - TCD Control and Status */
  /*! @{ */
  #define DMA_CSR_START_MASK                       (0x1U)
  #define DMA_CSR_START_SHIFT                      (0U)
  /*! START - Channel Start
   *  0b0..The channel is not explicitly started
   *  0b1..The channel is explicitly started via a software initiated service request
   */
  #define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
  #define DMA_CSR_INTMAJOR_MASK                    (0x2U)
  #define DMA_CSR_INTMAJOR_SHIFT                   (1U)
  /*! INTMAJOR - Enable an interrupt when major iteration count completes
   *  0b0..The end-of-major loop interrupt is disabled
   *  0b1..The end-of-major loop interrupt is enabled
   */
  #define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
  #define DMA_CSR_INTHALF_MASK                     (0x4U)
  #define DMA_CSR_INTHALF_SHIFT                    (2U)
  /*! INTHALF - Enable an interrupt when major counter is half complete.
   *  0b0..The half-point interrupt is disabled
   *  0b1..The half-point interrupt is enabled
   */
  #define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
  #define DMA_CSR_DREQ_MASK                        (0x8U)
  #define DMA_CSR_DREQ_SHIFT                       (3U)
  /*! DREQ - Disable Request
   *  0b0..The channel's ERQ bit is not affected
   *  0b1..The channel's ERQ bit is cleared when the major loop is complete
   */
  #define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
  #define DMA_CSR_ESG_MASK                         (0x10U)
  #define DMA_CSR_ESG_SHIFT                        (4U)
  /*! ESG - Enable Scatter/Gather Processing
   *  0b0..The current channel's TCD is normal format.
   *  0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
   */
  #define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
  #define DMA_CSR_MAJORELINK_MASK                  (0x20U)
  #define DMA_CSR_MAJORELINK_SHIFT                 (5U)
  /*! MAJORELINK - Enable channel-to-channel linking on major loop complete
   *  0b0..The channel-to-channel linking is disabled
   *  0b1..The channel-to-channel linking is enabled
   */
  #define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
  #define DMA_CSR_ACTIVE_MASK                      (0x40U)
  #define DMA_CSR_ACTIVE_SHIFT                     (6U)
  #define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
  #define DMA_CSR_DONE_MASK                        (0x80U)
  #define DMA_CSR_DONE_SHIFT                       (7U)
  #define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
  #define DMA_CSR_MAJORLINKCH_MASK                 (0x300U)
  #define DMA_CSR_MAJORLINKCH_SHIFT                (8U)
  #define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
  #define DMA_CSR_BWC_MASK                         (0xC000U)
  #define DMA_CSR_BWC_SHIFT                        (14U)
  /*! BWC - Bandwidth Control
   *  0b00..No eDMA engine stalls
   *  0b01..Reserved
   *  0b10..eDMA engine stalls for 4 cycles after each r/w
   *  0b11..eDMA engine stalls for 8 cycles after each r/w
   */
  #define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
  /*! @} */
  
  /* The count of DMA_CSR */
  #define DMA_CSR_COUNT                            (4U)
  
  /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
  /*! @{ */
  #define DMA_BITER_ELINKNO_BITER_MASK             (0x7FFFU)
  #define DMA_BITER_ELINKNO_BITER_SHIFT            (0U)
  #define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
  #define DMA_BITER_ELINKNO_ELINK_MASK             (0x8000U)
  #define DMA_BITER_ELINKNO_ELINK_SHIFT            (15U)
  /*! ELINK - Enables channel-to-channel linking on minor loop complete
   *  0b0..The channel-to-channel linking is disabled
   *  0b1..The channel-to-channel linking is enabled
   */
  #define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
  /*! @} */
  
  /* The count of DMA_BITER_ELINKNO */
  #define DMA_BITER_ELINKNO_COUNT                  (4U)
  
  /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
  /*! @{ */
  #define DMA_BITER_ELINKYES_BITER_MASK            (0x1FFU)
  #define DMA_BITER_ELINKYES_BITER_SHIFT           (0U)
  #define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
  #define DMA_BITER_ELINKYES_LINKCH_MASK           (0x600U)
  #define DMA_BITER_ELINKYES_LINKCH_SHIFT          (9U)
  #define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
  #define DMA_BITER_ELINKYES_ELINK_MASK            (0x8000U)
  #define DMA_BITER_ELINKYES_ELINK_SHIFT           (15U)
  /*! ELINK - Enables channel-to-channel linking on minor loop complete
   *  0b0..The channel-to-channel linking is disabled
   *  0b1..The channel-to-channel linking is enabled
   */
  #define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
  /*! @} */
  
  /* The count of DMA_BITER_ELINKYES */
  #define DMA_BITER_ELINKYES_COUNT                 (4U)
  
  
  /*!
   * @}
   */ /* end of group DMA_Register_Masks */
  
  
  /* DMA - Peripheral instance base addresses */
  /** Peripheral DMA base address */
  #define DMA_BASE                                 (0x40008000u)
  /** Peripheral DMA base pointer */
  #define DMA0                                     ((DMA_Type *)DMA_BASE)
  /** Array initializer of DMA peripheral base addresses */
  #define DMA_BASE_ADDRS                           { DMA_BASE }
  /** Array initializer of DMA peripheral base pointers */
  #define DMA_BASE_PTRS                            { DMA0 }
  /** Interrupt vectors for the DMA peripheral type */
  #define DMA_CHN_IRQS                             { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
  #define DMA_ERROR_IRQS                           { DMA_Error_IRQn }
  
  /*!
   * @}
   */ /* end of group DMA_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- DMAMUX Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
   * @{
   */
  
  /** DMAMUX - Register Layout Typedef */
  typedef struct {
    __IO uint8_t CHCFG[4];                           /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
  } DMAMUX_Type;
  
  /* ----------------------------------------------------------------------------
     -- DMAMUX Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
   * @{
   */
  
  /*! @name CHCFG - Channel Configuration register */
  /*! @{ */
  #define DMAMUX_CHCFG_SOURCE_MASK                 (0x3FU)
  #define DMAMUX_CHCFG_SOURCE_SHIFT                (0U)
  /*! SOURCE - DMA Channel Source (Slot)
   *  0b000000..Disable_Signal
   *  0b000010..UART0_Rx_Signal
   *  0b000011..UART0_Tx_Signal
   *  0b000100..UART1_Rx_Signal
   *  0b000101..UART1_Tx_Signal
   *  0b000110..UART2_Rx_Signal
   *  0b000111..UART2_Tx_Signal
   *  0b001110..SPI0_Rx_Signal
   *  0b001111..SPI0_Tx_Signal
   *  0b010000..SPI1_Signal
   *  0b010010..I2C0_Signal
   *  0b010011..I2C1_Signal
   *  0b010100..FTM0_Channel0_Signal
   *  0b010101..FTM0_Channel1_Signal
   *  0b010110..FTM0_Channel2_Signal
   *  0b010111..FTM0_Channel3_Signal
   *  0b011000..FTM0_Channel4_Signal
   *  0b011001..FTM0_Channel5_Signal
   *  0b011010..FTM0_Channel6_Signal
   *  0b011011..FTM0_Channel7_Signal
   *  0b011100..FTM1_Channel0_Signal
   *  0b011101..FTM1_Channel1_Signal
   *  0b011110..FTM2_Channel0_Signal
   *  0b011111..FTM2_Channel1_Signal
   *  0b101000..ADC0_Signal
   *  0b101001..ADC1_Signal
   *  0b101010..CMP0_Signal
   *  0b101011..CMP1_Signal
   *  0b101101..DAC0_Signal
   *  0b110000..PDB_Signal
   *  0b110001..PortA_Signal
   *  0b110010..PortB_Signal
   *  0b110011..PortC_Signal
   *  0b110100..PortD_Signal
   *  0b110101..PortE_Signal
   *  0b111010..LPUART0_Rx_Signal
   *  0b111011..LPUART0_Tx_Signal
   *  0b111100..AlwaysOn60_Signal
   *  0b111101..AlwaysOn61_Signal
   *  0b111110..AlwaysOn62_Signal
   *  0b111111..AlwaysOn63_Signal
   */
  #define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
  #define DMAMUX_CHCFG_TRIG_MASK                   (0x40U)
  #define DMAMUX_CHCFG_TRIG_SHIFT                  (6U)
  /*! TRIG - DMA Channel Trigger Enable
   *  0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
   *  0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
   */
  #define DMAMUX_CHCFG_TRIG(x)                     (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
  #define DMAMUX_CHCFG_ENBL_MASK                   (0x80U)
  #define DMAMUX_CHCFG_ENBL_SHIFT                  (7U)
  /*! ENBL - DMA Channel Enable
   *  0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
   *  0b1..DMA channel is enabled
   */
  #define DMAMUX_CHCFG_ENBL(x)                     (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
  /*! @} */
  
  /* The count of DMAMUX_CHCFG */
  #define DMAMUX_CHCFG_COUNT                       (4U)
  
  
  /*!
   * @}
   */ /* end of group DMAMUX_Register_Masks */
  
  
  /* DMAMUX - Peripheral instance base addresses */
  /** Peripheral DMAMUX base address */
  #define DMAMUX_BASE                              (0x40021000u)
  /** Peripheral DMAMUX base pointer */
  #define DMAMUX                                   ((DMAMUX_Type *)DMAMUX_BASE)
  /** Array initializer of DMAMUX peripheral base addresses */
  #define DMAMUX_BASE_ADDRS                        { DMAMUX_BASE }
  /** Array initializer of DMAMUX peripheral base pointers */
  #define DMAMUX_BASE_PTRS                         { DMAMUX }
  
  /*!
   * @}
   */ /* end of group DMAMUX_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- EWM Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
   * @{
   */
  
  /** EWM - Register Layout Typedef */
  typedef struct {
    __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
    __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
    __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
    __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
         uint8_t RESERVED_0[1];
    __IO uint8_t CLKPRESCALER;                       /**< Clock Prescaler Register, offset: 0x5 */
  } EWM_Type;
  
  /* ----------------------------------------------------------------------------
     -- EWM Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup EWM_Register_Masks EWM Register Masks
   * @{
   */
  
  /*! @name CTRL - Control Register */
  /*! @{ */
  #define EWM_CTRL_EWMEN_MASK                      (0x1U)
  #define EWM_CTRL_EWMEN_SHIFT                     (0U)
  #define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
  #define EWM_CTRL_ASSIN_MASK                      (0x2U)
  #define EWM_CTRL_ASSIN_SHIFT                     (1U)
  #define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
  #define EWM_CTRL_INEN_MASK                       (0x4U)
  #define EWM_CTRL_INEN_SHIFT                      (2U)
  #define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
  #define EWM_CTRL_INTEN_MASK                      (0x8U)
  #define EWM_CTRL_INTEN_SHIFT                     (3U)
  #define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
  /*! @} */
  
  /*! @name SERV - Service Register */
  /*! @{ */
  #define EWM_SERV_SERVICE_MASK                    (0xFFU)
  #define EWM_SERV_SERVICE_SHIFT                   (0U)
  #define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
  /*! @} */
  
  /*! @name CMPL - Compare Low Register */
  /*! @{ */
  #define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
  #define EWM_CMPL_COMPAREL_SHIFT                  (0U)
  #define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
  /*! @} */
  
  /*! @name CMPH - Compare High Register */
  /*! @{ */
  #define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
  #define EWM_CMPH_COMPAREH_SHIFT                  (0U)
  #define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
  /*! @} */
  
  /*! @name CLKPRESCALER - Clock Prescaler Register */
  /*! @{ */
  #define EWM_CLKPRESCALER_CLK_DIV_MASK            (0xFFU)
  #define EWM_CLKPRESCALER_CLK_DIV_SHIFT           (0U)
  #define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group EWM_Register_Masks */
  
  
  /* EWM - Peripheral instance base addresses */
  /** Peripheral EWM base address */
  #define EWM_BASE                                 (0x40061000u)
  /** Peripheral EWM base pointer */
  #define EWM                                      ((EWM_Type *)EWM_BASE)
  /** Array initializer of EWM peripheral base addresses */
  #define EWM_BASE_ADDRS                           { EWM_BASE }
  /** Array initializer of EWM peripheral base pointers */
  #define EWM_BASE_PTRS                            { EWM }
  /** Interrupt vectors for the EWM peripheral type */
  #define EWM_IRQS                                 { WDOG_EWM_IRQn }
  
  /*!
   * @}
   */ /* end of group EWM_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- FMC Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
   * @{
   */
  
  /** FMC - Register Layout Typedef */
  typedef struct {
    __IO uint32_t PFAPR;                             /**< Flash Access Protection Register, offset: 0x0 */
    __IO uint32_t PFB0CR;                            /**< Flash Bank 0 Control Register, offset: 0x4 */
    __IO uint32_t PFB1CR;                            /**< Flash Bank 1 Control Register, offset: 0x8 */
         uint8_t RESERVED_0[244];
    __IO uint32_t TAGVDW0S[8];                       /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
    __IO uint32_t TAGVDW1S[8];                       /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
    __IO uint32_t TAGVDW2S[8];                       /**< Cache Tag Storage, array offset: 0x140, array step: 0x4 */
    __IO uint32_t TAGVDW3S[8];                       /**< Cache Tag Storage, array offset: 0x160, array step: 0x4 */
         uint8_t RESERVED_1[128];
    struct {                                         /* offset: 0x200, array step: index*0x40, index2*0x8 */
      __IO uint32_t DATA_U;                            /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
      __IO uint32_t DATA_L;                            /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
    } SET[4][8];
  } FMC_Type;
  
  /* ----------------------------------------------------------------------------
     -- FMC Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FMC_Register_Masks FMC Register Masks
   * @{
   */
  
  /*! @name PFAPR - Flash Access Protection Register */
  /*! @{ */
  #define FMC_PFAPR_M0AP_MASK                      (0x3U)
  #define FMC_PFAPR_M0AP_SHIFT                     (0U)
  /*! M0AP - Master 0 Access Protection
   *  0b00..No access may be performed by this master
   *  0b01..Only read accesses may be performed by this master
   *  0b10..Only write accesses may be performed by this master
   *  0b11..Both read and write accesses may be performed by this master
   */
  #define FMC_PFAPR_M0AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
  #define FMC_PFAPR_M1AP_MASK                      (0xCU)
  #define FMC_PFAPR_M1AP_SHIFT                     (2U)
  /*! M1AP - Master 1 Access Protection
   *  0b00..No access may be performed by this master
   *  0b01..Only read accesses may be performed by this master
   *  0b10..Only write accesses may be performed by this master
   *  0b11..Both read and write accesses may be performed by this master
   */
  #define FMC_PFAPR_M1AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
  #define FMC_PFAPR_M2AP_MASK                      (0x30U)
  #define FMC_PFAPR_M2AP_SHIFT                     (4U)
  /*! M2AP - Master 2 Access Protection
   *  0b00..No access may be performed by this master
   *  0b01..Only read accesses may be performed by this master
   *  0b10..Only write accesses may be performed by this master
   *  0b11..Both read and write accesses may be performed by this master
   */
  #define FMC_PFAPR_M2AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
  #define FMC_PFAPR_M3AP_MASK                      (0xC0U)
  #define FMC_PFAPR_M3AP_SHIFT                     (6U)
  /*! M3AP - Master 3 Access Protection
   *  0b00..No access may be performed by this master
   *  0b01..Only read accesses may be performed by this master
   *  0b10..Only write accesses may be performed by this master
   *  0b11..Both read and write accesses may be performed by this master
   */
  #define FMC_PFAPR_M3AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
  #define FMC_PFAPR_M4AP_MASK                      (0x300U)
  #define FMC_PFAPR_M4AP_SHIFT                     (8U)
  /*! M4AP - Master 4 Access Protection
   *  0b00..No access may be performed by this master
   *  0b01..Only read accesses may be performed by this master
   *  0b10..Only write accesses may be performed by this master
   *  0b11..Both read and write accesses may be performed by this master
   */
  #define FMC_PFAPR_M4AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
  #define FMC_PFAPR_M5AP_MASK                      (0xC00U)
  #define FMC_PFAPR_M5AP_SHIFT                     (10U)
  /*! M5AP - Master 5 Access Protection
   *  0b00..No access may be performed by this master
   *  0b01..Only read accesses may be performed by this master
   *  0b10..Only write accesses may be performed by this master
   *  0b11..Both read and write accesses may be performed by this master
   */
  #define FMC_PFAPR_M5AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
  #define FMC_PFAPR_M6AP_MASK                      (0x3000U)
  #define FMC_PFAPR_M6AP_SHIFT                     (12U)
  /*! M6AP - Master 6 Access Protection
   *  0b00..No access may be performed by this master
   *  0b01..Only read accesses may be performed by this master
   *  0b10..Only write accesses may be performed by this master
   *  0b11..Both read and write accesses may be performed by this master
   */
  #define FMC_PFAPR_M6AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
  #define FMC_PFAPR_M7AP_MASK                      (0xC000U)
  #define FMC_PFAPR_M7AP_SHIFT                     (14U)
  /*! M7AP - Master 7 Access Protection
   *  0b00..No access may be performed by this master.
   *  0b01..Only read accesses may be performed by this master.
   *  0b10..Only write accesses may be performed by this master.
   *  0b11..Both read and write accesses may be performed by this master.
   */
  #define FMC_PFAPR_M7AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
  #define FMC_PFAPR_M0PFD_MASK                     (0x10000U)
  #define FMC_PFAPR_M0PFD_SHIFT                    (16U)
  /*! M0PFD - Master 0 Prefetch Disable
   *  0b0..Prefetching for this master is enabled.
   *  0b1..Prefetching for this master is disabled.
   */
  #define FMC_PFAPR_M0PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
  #define FMC_PFAPR_M1PFD_MASK                     (0x20000U)
  #define FMC_PFAPR_M1PFD_SHIFT                    (17U)
  /*! M1PFD - Master 1 Prefetch Disable
   *  0b0..Prefetching for this master is enabled.
   *  0b1..Prefetching for this master is disabled.
   */
  #define FMC_PFAPR_M1PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
  #define FMC_PFAPR_M2PFD_MASK                     (0x40000U)
  #define FMC_PFAPR_M2PFD_SHIFT                    (18U)
  /*! M2PFD - Master 2 Prefetch Disable
   *  0b0..Prefetching for this master is enabled.
   *  0b1..Prefetching for this master is disabled.
   */
  #define FMC_PFAPR_M2PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
  #define FMC_PFAPR_M3PFD_MASK                     (0x80000U)
  #define FMC_PFAPR_M3PFD_SHIFT                    (19U)
  /*! M3PFD - Master 3 Prefetch Disable
   *  0b0..Prefetching for this master is enabled.
   *  0b1..Prefetching for this master is disabled.
   */
  #define FMC_PFAPR_M3PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
  #define FMC_PFAPR_M4PFD_MASK                     (0x100000U)
  #define FMC_PFAPR_M4PFD_SHIFT                    (20U)
  /*! M4PFD - Master 4 Prefetch Disable
   *  0b0..Prefetching for this master is enabled.
   *  0b1..Prefetching for this master is disabled.
   */
  #define FMC_PFAPR_M4PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
  #define FMC_PFAPR_M5PFD_MASK                     (0x200000U)
  #define FMC_PFAPR_M5PFD_SHIFT                    (21U)
  /*! M5PFD - Master 5 Prefetch Disable
   *  0b0..Prefetching for this master is enabled.
   *  0b1..Prefetching for this master is disabled.
   */
  #define FMC_PFAPR_M5PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
  #define FMC_PFAPR_M6PFD_MASK                     (0x400000U)
  #define FMC_PFAPR_M6PFD_SHIFT                    (22U)
  /*! M6PFD - Master 6 Prefetch Disable
   *  0b0..Prefetching for this master is enabled.
   *  0b1..Prefetching for this master is disabled.
   */
  #define FMC_PFAPR_M6PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
  #define FMC_PFAPR_M7PFD_MASK                     (0x800000U)
  #define FMC_PFAPR_M7PFD_SHIFT                    (23U)
  /*! M7PFD - Master 7 Prefetch Disable
   *  0b0..Prefetching for this master is enabled.
   *  0b1..Prefetching for this master is disabled.
   */
  #define FMC_PFAPR_M7PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
  /*! @} */
  
  /*! @name PFB0CR - Flash Bank 0 Control Register */
  /*! @{ */
  #define FMC_PFB0CR_B0SEBE_MASK                   (0x1U)
  #define FMC_PFB0CR_B0SEBE_SHIFT                  (0U)
  /*! B0SEBE - Bank 0 Single Entry Buffer Enable
   *  0b0..Single entry buffer is disabled.
   *  0b1..Single entry buffer is enabled.
   */
  #define FMC_PFB0CR_B0SEBE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
  #define FMC_PFB0CR_B0IPE_MASK                    (0x2U)
  #define FMC_PFB0CR_B0IPE_SHIFT                   (1U)
  /*! B0IPE - Bank 0 Instruction Prefetch Enable
   *  0b0..Do not prefetch in response to instruction fetches.
   *  0b1..Enable prefetches in response to instruction fetches.
   */
  #define FMC_PFB0CR_B0IPE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
  #define FMC_PFB0CR_B0DPE_MASK                    (0x4U)
  #define FMC_PFB0CR_B0DPE_SHIFT                   (2U)
  /*! B0DPE - Bank 0 Data Prefetch Enable
   *  0b0..Do not prefetch in response to data references.
   *  0b1..Enable prefetches in response to data references.
   */
  #define FMC_PFB0CR_B0DPE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
  #define FMC_PFB0CR_B0ICE_MASK                    (0x8U)
  #define FMC_PFB0CR_B0ICE_SHIFT                   (3U)
  /*! B0ICE - Bank 0 Instruction Cache Enable
   *  0b0..Do not cache instruction fetches.
   *  0b1..Cache instruction fetches.
   */
  #define FMC_PFB0CR_B0ICE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
  #define FMC_PFB0CR_B0DCE_MASK                    (0x10U)
  #define FMC_PFB0CR_B0DCE_SHIFT                   (4U)
  /*! B0DCE - Bank 0 Data Cache Enable
   *  0b0..Do not cache data references.
   *  0b1..Cache data references.
   */
  #define FMC_PFB0CR_B0DCE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
  #define FMC_PFB0CR_CRC_MASK                      (0xE0U)
  #define FMC_PFB0CR_CRC_SHIFT                     (5U)
  /*! CRC - Cache Replacement Control
   *  0b000..LRU replacement algorithm per set across all four ways
   *  0b001..Reserved
   *  0b010..Independent LRU with ways [0-1] for ifetches, [2-3] for data
   *  0b011..Independent LRU with ways [0-2] for ifetches, [3] for data
   *  0b1xx..Reserved
   */
  #define FMC_PFB0CR_CRC(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
  #define FMC_PFB0CR_B0MW_MASK                     (0x60000U)
  #define FMC_PFB0CR_B0MW_SHIFT                    (17U)
  /*! B0MW - Bank 0 Memory Width
   *  0b00..32 bits
   *  0b01..64 bits
   *  0b10..Reserved
   *  0b11..Reserved
   */
  #define FMC_PFB0CR_B0MW(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
  #define FMC_PFB0CR_S_B_INV_MASK                  (0x80000U)
  #define FMC_PFB0CR_S_B_INV_SHIFT                 (19U)
  /*! S_B_INV - Invalidate Prefetch Speculation Buffer
   *  0b0..Speculation buffer and single entry buffer are not affected.
   *  0b1..Invalidate (clear) speculation buffer and single entry buffer.
   */
  #define FMC_PFB0CR_S_B_INV(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
  #define FMC_PFB0CR_CINV_WAY_MASK                 (0xF00000U)
  #define FMC_PFB0CR_CINV_WAY_SHIFT                (20U)
  /*! CINV_WAY - Cache Invalidate Way x
   *  0b0000..No cache way invalidation for the corresponding cache
   *  0b0001..Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected
   */
  #define FMC_PFB0CR_CINV_WAY(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
  #define FMC_PFB0CR_CLCK_WAY_MASK                 (0xF000000U)
  #define FMC_PFB0CR_CLCK_WAY_SHIFT                (24U)
  /*! CLCK_WAY - Cache Lock Way x
   *  0b0000..Cache way is unlocked and may be displaced
   *  0b0001..Cache way is locked and its contents are not displaced
   */
  #define FMC_PFB0CR_CLCK_WAY(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
  #define FMC_PFB0CR_B0RWSC_MASK                   (0xF0000000U)
  #define FMC_PFB0CR_B0RWSC_SHIFT                  (28U)
  #define FMC_PFB0CR_B0RWSC(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
  /*! @} */
  
  /*! @name PFB1CR - Flash Bank 1 Control Register */
  /*! @{ */
  #define FMC_PFB1CR_B1SEBE_MASK                   (0x1U)
  #define FMC_PFB1CR_B1SEBE_SHIFT                  (0U)
  /*! B1SEBE - Bank 1 Single Entry Buffer Enable
   *  0b0..Single entry buffer is disabled.
   *  0b1..Single entry buffer is enabled.
   */
  #define FMC_PFB1CR_B1SEBE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
  #define FMC_PFB1CR_B1IPE_MASK                    (0x2U)
  #define FMC_PFB1CR_B1IPE_SHIFT                   (1U)
  /*! B1IPE - Bank 1 Instruction Prefetch Enable
   *  0b0..Do not prefetch in response to instruction fetches.
   *  0b1..Enable prefetches in response to instruction fetches.
   */
  #define FMC_PFB1CR_B1IPE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
  #define FMC_PFB1CR_B1DPE_MASK                    (0x4U)
  #define FMC_PFB1CR_B1DPE_SHIFT                   (2U)
  /*! B1DPE - Bank 1 Data Prefetch Enable
   *  0b0..Do not prefetch in response to data references.
   *  0b1..Enable prefetches in response to data references.
   */
  #define FMC_PFB1CR_B1DPE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
  #define FMC_PFB1CR_B1ICE_MASK                    (0x8U)
  #define FMC_PFB1CR_B1ICE_SHIFT                   (3U)
  /*! B1ICE - Bank 1 Instruction Cache Enable
   *  0b0..Do not cache instruction fetches.
   *  0b1..Cache instruction fetches.
   */
  #define FMC_PFB1CR_B1ICE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
  #define FMC_PFB1CR_B1DCE_MASK                    (0x10U)
  #define FMC_PFB1CR_B1DCE_SHIFT                   (4U)
  /*! B1DCE - Bank 1 Data Cache Enable
   *  0b0..Do not cache data references.
   *  0b1..Cache data references.
   */
  #define FMC_PFB1CR_B1DCE(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
  #define FMC_PFB1CR_B1MW_MASK                     (0x60000U)
  #define FMC_PFB1CR_B1MW_SHIFT                    (17U)
  /*! B1MW - Bank 1 Memory Width
   *  0b00..32 bits
   *  0b01..64 bits
   *  0b10..Reserved
   *  0b11..Reserved
   */
  #define FMC_PFB1CR_B1MW(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
  #define FMC_PFB1CR_B1RWSC_MASK                   (0xF0000000U)
  #define FMC_PFB1CR_B1RWSC_SHIFT                  (28U)
  #define FMC_PFB1CR_B1RWSC(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
  /*! @} */
  
  /*! @name TAGVDW0S - Cache Tag Storage */
  /*! @{ */
  #define FMC_TAGVDW0S_valid_MASK                  (0x1U)
  #define FMC_TAGVDW0S_valid_SHIFT                 (0U)
  #define FMC_TAGVDW0S_valid(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
  #define FMC_TAGVDW0S_tag_MASK                    (0x7FFE0U)
  #define FMC_TAGVDW0S_tag_SHIFT                   (5U)
  #define FMC_TAGVDW0S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
  /*! @} */
  
  /* The count of FMC_TAGVDW0S */
  #define FMC_TAGVDW0S_COUNT                       (8U)
  
  /*! @name TAGVDW1S - Cache Tag Storage */
  /*! @{ */
  #define FMC_TAGVDW1S_valid_MASK                  (0x1U)
  #define FMC_TAGVDW1S_valid_SHIFT                 (0U)
  #define FMC_TAGVDW1S_valid(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
  #define FMC_TAGVDW1S_tag_MASK                    (0x7FFE0U)
  #define FMC_TAGVDW1S_tag_SHIFT                   (5U)
  #define FMC_TAGVDW1S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
  /*! @} */
  
  /* The count of FMC_TAGVDW1S */
  #define FMC_TAGVDW1S_COUNT                       (8U)
  
  /*! @name TAGVDW2S - Cache Tag Storage */
  /*! @{ */
  #define FMC_TAGVDW2S_valid_MASK                  (0x1U)
  #define FMC_TAGVDW2S_valid_SHIFT                 (0U)
  #define FMC_TAGVDW2S_valid(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
  #define FMC_TAGVDW2S_tag_MASK                    (0x7FFE0U)
  #define FMC_TAGVDW2S_tag_SHIFT                   (5U)
  #define FMC_TAGVDW2S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
  /*! @} */
  
  /* The count of FMC_TAGVDW2S */
  #define FMC_TAGVDW2S_COUNT                       (8U)
  
  /*! @name TAGVDW3S - Cache Tag Storage */
  /*! @{ */
  #define FMC_TAGVDW3S_valid_MASK                  (0x1U)
  #define FMC_TAGVDW3S_valid_SHIFT                 (0U)
  #define FMC_TAGVDW3S_valid(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
  #define FMC_TAGVDW3S_tag_MASK                    (0x7FFE0U)
  #define FMC_TAGVDW3S_tag_SHIFT                   (5U)
  #define FMC_TAGVDW3S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
  /*! @} */
  
  /* The count of FMC_TAGVDW3S */
  #define FMC_TAGVDW3S_COUNT                       (8U)
  
  /*! @name DATA_U - Cache Data Storage (upper word) */
  /*! @{ */
  #define FMC_DATA_U_data_MASK                     (0xFFFFFFFFU)
  #define FMC_DATA_U_data_SHIFT                    (0U)
  #define FMC_DATA_U_data(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK)
  /*! @} */
  
  /* The count of FMC_DATA_U */
  #define FMC_DATA_U_COUNT                         (4U)
  
  /* The count of FMC_DATA_U */
  #define FMC_DATA_U_COUNT2                        (8U)
  
  /*! @name DATA_L - Cache Data Storage (lower word) */
  /*! @{ */
  #define FMC_DATA_L_data_MASK                     (0xFFFFFFFFU)
  #define FMC_DATA_L_data_SHIFT                    (0U)
  #define FMC_DATA_L_data(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK)
  /*! @} */
  
  /* The count of FMC_DATA_L */
  #define FMC_DATA_L_COUNT                         (4U)
  
  /* The count of FMC_DATA_L */
  #define FMC_DATA_L_COUNT2                        (8U)
  
  
  /*!
   * @}
   */ /* end of group FMC_Register_Masks */
  
  
  /* FMC - Peripheral instance base addresses */
  /** Peripheral FMC base address */
  #define FMC_BASE                                 (0x4001F000u)
  /** Peripheral FMC base pointer */
  #define FMC                                      ((FMC_Type *)FMC_BASE)
  /** Array initializer of FMC peripheral base addresses */
  #define FMC_BASE_ADDRS                           { FMC_BASE }
  /** Array initializer of FMC peripheral base pointers */
  #define FMC_BASE_PTRS                            { FMC }
  
  /*!
   * @}
   */ /* end of group FMC_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- FTFA Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
   * @{
   */
  
  /** FTFA - Register Layout Typedef */
  typedef struct {
    __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
    __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
    __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
    __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
    __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
    __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
    __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
    __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
    __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
    __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
    __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
    __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
    __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
    __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
    __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
    __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
    __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
    __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
    __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
    __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
         uint8_t RESERVED_0[4];
    __I  uint8_t XACCH3;                             /**< Execute-only Access Registers, offset: 0x18 */
    __I  uint8_t XACCH2;                             /**< Execute-only Access Registers, offset: 0x19 */
    __I  uint8_t XACCH1;                             /**< Execute-only Access Registers, offset: 0x1A */
    __I  uint8_t XACCH0;                             /**< Execute-only Access Registers, offset: 0x1B */
    __I  uint8_t XACCL3;                             /**< Execute-only Access Registers, offset: 0x1C */
    __I  uint8_t XACCL2;                             /**< Execute-only Access Registers, offset: 0x1D */
    __I  uint8_t XACCL1;                             /**< Execute-only Access Registers, offset: 0x1E */
    __I  uint8_t XACCL0;                             /**< Execute-only Access Registers, offset: 0x1F */
    __I  uint8_t SACCH3;                             /**< Supervisor-only Access Registers, offset: 0x20 */
    __I  uint8_t SACCH2;                             /**< Supervisor-only Access Registers, offset: 0x21 */
    __I  uint8_t SACCH1;                             /**< Supervisor-only Access Registers, offset: 0x22 */
    __I  uint8_t SACCH0;                             /**< Supervisor-only Access Registers, offset: 0x23 */
    __I  uint8_t SACCL3;                             /**< Supervisor-only Access Registers, offset: 0x24 */
    __I  uint8_t SACCL2;                             /**< Supervisor-only Access Registers, offset: 0x25 */
    __I  uint8_t SACCL1;                             /**< Supervisor-only Access Registers, offset: 0x26 */
    __I  uint8_t SACCL0;                             /**< Supervisor-only Access Registers, offset: 0x27 */
    __I  uint8_t FACSS;                              /**< Flash Access Segment Size Register, offset: 0x28 */
         uint8_t RESERVED_1[2];
    __I  uint8_t FACSN;                              /**< Flash Access Segment Number Register, offset: 0x2B */
  } FTFA_Type;
  
  /* ----------------------------------------------------------------------------
     -- FTFA Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FTFA_Register_Masks FTFA Register Masks
   * @{
   */
  
  /*! @name FSTAT - Flash Status Register */
  /*! @{ */
  #define FTFA_FSTAT_MGSTAT0_MASK                  (0x1U)
  #define FTFA_FSTAT_MGSTAT0_SHIFT                 (0U)
  #define FTFA_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
  #define FTFA_FSTAT_FPVIOL_MASK                   (0x10U)
  #define FTFA_FSTAT_FPVIOL_SHIFT                  (4U)
  /*! FPVIOL - Flash Protection Violation Flag
   *  0b0..No protection violation detected
   *  0b1..Protection violation detected
   */
  #define FTFA_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
  #define FTFA_FSTAT_ACCERR_MASK                   (0x20U)
  #define FTFA_FSTAT_ACCERR_SHIFT                  (5U)
  /*! ACCERR - Flash Access Error Flag
   *  0b0..No access error detected
   *  0b1..Access error detected
   */
  #define FTFA_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
  #define FTFA_FSTAT_RDCOLERR_MASK                 (0x40U)
  #define FTFA_FSTAT_RDCOLERR_SHIFT                (6U)
  /*! RDCOLERR - Flash Read Collision Error Flag
   *  0b0..No collision error detected
   *  0b1..Collision error detected
   */
  #define FTFA_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
  #define FTFA_FSTAT_CCIF_MASK                     (0x80U)
  #define FTFA_FSTAT_CCIF_SHIFT                    (7U)
  /*! CCIF - Command Complete Interrupt Flag
   *  0b0..Flash command in progress
   *  0b1..Flash command has completed
   */
  #define FTFA_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
  /*! @} */
  
  /*! @name FCNFG - Flash Configuration Register */
  /*! @{ */
  #define FTFA_FCNFG_ERSSUSP_MASK                  (0x10U)
  #define FTFA_FCNFG_ERSSUSP_SHIFT                 (4U)
  /*! ERSSUSP - Erase Suspend
   *  0b0..No suspend requested
   *  0b1..Suspend the current Erase Flash Sector command execution.
   */
  #define FTFA_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
  #define FTFA_FCNFG_ERSAREQ_MASK                  (0x20U)
  #define FTFA_FCNFG_ERSAREQ_SHIFT                 (5U)
  /*! ERSAREQ - Erase All Request
   *  0b0..No request or request complete
   *  0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.
   */
  #define FTFA_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
  #define FTFA_FCNFG_RDCOLLIE_MASK                 (0x40U)
  #define FTFA_FCNFG_RDCOLLIE_SHIFT                (6U)
  /*! RDCOLLIE - Read Collision Error Interrupt Enable
   *  0b0..Read collision error interrupt disabled
   *  0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]).
   */
  #define FTFA_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
  #define FTFA_FCNFG_CCIE_MASK                     (0x80U)
  #define FTFA_FCNFG_CCIE_SHIFT                    (7U)
  /*! CCIE - Command Complete Interrupt Enable
   *  0b0..Command complete interrupt disabled
   *  0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
   */
  #define FTFA_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
  /*! @} */
  
  /*! @name FSEC - Flash Security Register */
  /*! @{ */
  #define FTFA_FSEC_SEC_MASK                       (0x3U)
  #define FTFA_FSEC_SEC_SHIFT                      (0U)
  /*! SEC - Flash Security
   *  0b00..MCU security status is secure.
   *  0b01..MCU security status is secure.
   *  0b10..MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
   *  0b11..MCU security status is secure.
   */
  #define FTFA_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
  #define FTFA_FSEC_FSLACC_MASK                    (0xCU)
  #define FTFA_FSEC_FSLACC_SHIFT                   (2U)
  /*! FSLACC - Freescale Failure Analysis Access Code
   *  0b00..Freescale factory access granted
   *  0b01..Freescale factory access denied
   *  0b10..Freescale factory access denied
   *  0b11..Freescale factory access granted
   */
  #define FTFA_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
  #define FTFA_FSEC_MEEN_MASK                      (0x30U)
  #define FTFA_FSEC_MEEN_SHIFT                     (4U)
  /*! MEEN - Mass Erase Enable Bits
   *  0b00..Mass erase is enabled
   *  0b01..Mass erase is enabled
   *  0b10..Mass erase is disabled
   *  0b11..Mass erase is enabled
   */
  #define FTFA_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
  #define FTFA_FSEC_KEYEN_MASK                     (0xC0U)
  #define FTFA_FSEC_KEYEN_SHIFT                    (6U)
  /*! KEYEN - Backdoor Key Security Enable
   *  0b00..Backdoor key access disabled
   *  0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
   *  0b10..Backdoor key access enabled
   *  0b11..Backdoor key access disabled
   */
  #define FTFA_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
  /*! @} */
  
  /*! @name FOPT - Flash Option Register */
  /*! @{ */
  #define FTFA_FOPT_OPT_MASK                       (0xFFU)
  #define FTFA_FOPT_OPT_SHIFT                      (0U)
  #define FTFA_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
  /*! @} */
  
  /*! @name FCCOB3 - Flash Common Command Object Registers */
  /*! @{ */
  #define FTFA_FCCOB3_CCOBn_MASK                   (0xFFU)
  #define FTFA_FCCOB3_CCOBn_SHIFT                  (0U)
  #define FTFA_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
  /*! @} */
  
  /*! @name FCCOB2 - Flash Common Command Object Registers */
  /*! @{ */
  #define FTFA_FCCOB2_CCOBn_MASK                   (0xFFU)
  #define FTFA_FCCOB2_CCOBn_SHIFT                  (0U)
  #define FTFA_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
  /*! @} */
  
  /*! @name FCCOB1 - Flash Common Command Object Registers */
  /*! @{ */
  #define FTFA_FCCOB1_CCOBn_MASK                   (0xFFU)
  #define FTFA_FCCOB1_CCOBn_SHIFT                  (0U)
  #define FTFA_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
  /*! @} */
  
  /*! @name FCCOB0 - Flash Common Command Object Registers */
  /*! @{ */
  #define FTFA_FCCOB0_CCOBn_MASK                   (0xFFU)
  #define FTFA_FCCOB0_CCOBn_SHIFT                  (0U)
  #define FTFA_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
  /*! @} */
  
  /*! @name FCCOB7 - Flash Common Command Object Registers */
  /*! @{ */
  #define FTFA_FCCOB7_CCOBn_MASK                   (0xFFU)
  #define FTFA_FCCOB7_CCOBn_SHIFT                  (0U)
  #define FTFA_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
  /*! @} */
  
  /*! @name FCCOB6 - Flash Common Command Object Registers */
  /*! @{ */
  #define FTFA_FCCOB6_CCOBn_MASK                   (0xFFU)
  #define FTFA_FCCOB6_CCOBn_SHIFT                  (0U)
  #define FTFA_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
  /*! @} */
  
  /*! @name FCCOB5 - Flash Common Command Object Registers */
  /*! @{ */
  #define FTFA_FCCOB5_CCOBn_MASK                   (0xFFU)
  #define FTFA_FCCOB5_CCOBn_SHIFT                  (0U)
  #define FTFA_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
  /*! @} */
  
  /*! @name FCCOB4 - Flash Common Command Object Registers */
  /*! @{ */
  #define FTFA_FCCOB4_CCOBn_MASK                   (0xFFU)
  #define FTFA_FCCOB4_CCOBn_SHIFT                  (0U)
  #define FTFA_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
  /*! @} */
  
  /*! @name FCCOBB - Flash Common Command Object Registers */
  /*! @{ */
  #define FTFA_FCCOBB_CCOBn_MASK                   (0xFFU)
  #define FTFA_FCCOBB_CCOBn_SHIFT                  (0U)
  #define FTFA_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
  /*! @} */
  
  /*! @name FCCOBA - Flash Common Command Object Registers */
  /*! @{ */
  #define FTFA_FCCOBA_CCOBn_MASK                   (0xFFU)
  #define FTFA_FCCOBA_CCOBn_SHIFT                  (0U)
  #define FTFA_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
  /*! @} */
  
  /*! @name FCCOB9 - Flash Common Command Object Registers */
  /*! @{ */
  #define FTFA_FCCOB9_CCOBn_MASK                   (0xFFU)
  #define FTFA_FCCOB9_CCOBn_SHIFT                  (0U)
  #define FTFA_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
  /*! @} */
  
  /*! @name FCCOB8 - Flash Common Command Object Registers */
  /*! @{ */
  #define FTFA_FCCOB8_CCOBn_MASK                   (0xFFU)
  #define FTFA_FCCOB8_CCOBn_SHIFT                  (0U)
  #define FTFA_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
  /*! @} */
  
  /*! @name FPROT3 - Program Flash Protection Registers */
  /*! @{ */
  #define FTFA_FPROT3_PROT_MASK                    (0xFFU)
  #define FTFA_FPROT3_PROT_SHIFT                   (0U)
  /*! PROT - Program Flash Region Protect
   *  0b00000000..Program flash region is protected.
   *  0b00000001..Program flash region is not protected
   */
  #define FTFA_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
  /*! @} */
  
  /*! @name FPROT2 - Program Flash Protection Registers */
  /*! @{ */
  #define FTFA_FPROT2_PROT_MASK                    (0xFFU)
  #define FTFA_FPROT2_PROT_SHIFT                   (0U)
  /*! PROT - Program Flash Region Protect
   *  0b00000000..Program flash region is protected.
   *  0b00000001..Program flash region is not protected
   */
  #define FTFA_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
  /*! @} */
  
  /*! @name FPROT1 - Program Flash Protection Registers */
  /*! @{ */
  #define FTFA_FPROT1_PROT_MASK                    (0xFFU)
  #define FTFA_FPROT1_PROT_SHIFT                   (0U)
  /*! PROT - Program Flash Region Protect
   *  0b00000000..Program flash region is protected.
   *  0b00000001..Program flash region is not protected
   */
  #define FTFA_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
  /*! @} */
  
  /*! @name FPROT0 - Program Flash Protection Registers */
  /*! @{ */
  #define FTFA_FPROT0_PROT_MASK                    (0xFFU)
  #define FTFA_FPROT0_PROT_SHIFT                   (0U)
  /*! PROT - Program Flash Region Protect
   *  0b00000000..Program flash region is protected.
   *  0b00000001..Program flash region is not protected
   */
  #define FTFA_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
  /*! @} */
  
  /*! @name XACCH3 - Execute-only Access Registers */
  /*! @{ */
  #define FTFA_XACCH3_XA_MASK                      (0xFFU)
  #define FTFA_XACCH3_XA_SHIFT                     (0U)
  /*! XA - Execute-only access control
   *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
   *  0b00000001..Associated segment is accessible as data or in execute mode
   */
  #define FTFA_XACCH3_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK)
  /*! @} */
  
  /*! @name XACCH2 - Execute-only Access Registers */
  /*! @{ */
  #define FTFA_XACCH2_XA_MASK                      (0xFFU)
  #define FTFA_XACCH2_XA_SHIFT                     (0U)
  /*! XA - Execute-only access control
   *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
   *  0b00000001..Associated segment is accessible as data or in execute mode
   */
  #define FTFA_XACCH2_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK)
  /*! @} */
  
  /*! @name XACCH1 - Execute-only Access Registers */
  /*! @{ */
  #define FTFA_XACCH1_XA_MASK                      (0xFFU)
  #define FTFA_XACCH1_XA_SHIFT                     (0U)
  /*! XA - Execute-only access control
   *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
   *  0b00000001..Associated segment is accessible as data or in execute mode
   */
  #define FTFA_XACCH1_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK)
  /*! @} */
  
  /*! @name XACCH0 - Execute-only Access Registers */
  /*! @{ */
  #define FTFA_XACCH0_XA_MASK                      (0xFFU)
  #define FTFA_XACCH0_XA_SHIFT                     (0U)
  /*! XA - Execute-only access control
   *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
   *  0b00000001..Associated segment is accessible as data or in execute mode
   */
  #define FTFA_XACCH0_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK)
  /*! @} */
  
  /*! @name XACCL3 - Execute-only Access Registers */
  /*! @{ */
  #define FTFA_XACCL3_XA_MASK                      (0xFFU)
  #define FTFA_XACCL3_XA_SHIFT                     (0U)
  /*! XA - Execute-only access control
   *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
   *  0b00000001..Associated segment is accessible as data or in execute mode
   */
  #define FTFA_XACCL3_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK)
  /*! @} */
  
  /*! @name XACCL2 - Execute-only Access Registers */
  /*! @{ */
  #define FTFA_XACCL2_XA_MASK                      (0xFFU)
  #define FTFA_XACCL2_XA_SHIFT                     (0U)
  /*! XA - Execute-only access control
   *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
   *  0b00000001..Associated segment is accessible as data or in execute mode
   */
  #define FTFA_XACCL2_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK)
  /*! @} */
  
  /*! @name XACCL1 - Execute-only Access Registers */
  /*! @{ */
  #define FTFA_XACCL1_XA_MASK                      (0xFFU)
  #define FTFA_XACCL1_XA_SHIFT                     (0U)
  /*! XA - Execute-only access control
   *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
   *  0b00000001..Associated segment is accessible as data or in execute mode
   */
  #define FTFA_XACCL1_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK)
  /*! @} */
  
  /*! @name XACCL0 - Execute-only Access Registers */
  /*! @{ */
  #define FTFA_XACCL0_XA_MASK                      (0xFFU)
  #define FTFA_XACCL0_XA_SHIFT                     (0U)
  /*! XA - Execute-only access control
   *  0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
   *  0b00000001..Associated segment is accessible as data or in execute mode
   */
  #define FTFA_XACCL0_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK)
  /*! @} */
  
  /*! @name SACCH3 - Supervisor-only Access Registers */
  /*! @{ */
  #define FTFA_SACCH3_SA_MASK                      (0xFFU)
  #define FTFA_SACCH3_SA_SHIFT                     (0U)
  /*! SA - Supervisor-only access control
   *  0b00000000..Associated segment is accessible in supervisor mode only
   *  0b00000001..Associated segment is accessible in user or supervisor mode
   */
  #define FTFA_SACCH3_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK)
  /*! @} */
  
  /*! @name SACCH2 - Supervisor-only Access Registers */
  /*! @{ */
  #define FTFA_SACCH2_SA_MASK                      (0xFFU)
  #define FTFA_SACCH2_SA_SHIFT                     (0U)
  /*! SA - Supervisor-only access control
   *  0b00000000..Associated segment is accessible in supervisor mode only
   *  0b00000001..Associated segment is accessible in user or supervisor mode
   */
  #define FTFA_SACCH2_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK)
  /*! @} */
  
  /*! @name SACCH1 - Supervisor-only Access Registers */
  /*! @{ */
  #define FTFA_SACCH1_SA_MASK                      (0xFFU)
  #define FTFA_SACCH1_SA_SHIFT                     (0U)
  /*! SA - Supervisor-only access control
   *  0b00000000..Associated segment is accessible in supervisor mode only
   *  0b00000001..Associated segment is accessible in user or supervisor mode
   */
  #define FTFA_SACCH1_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK)
  /*! @} */
  
  /*! @name SACCH0 - Supervisor-only Access Registers */
  /*! @{ */
  #define FTFA_SACCH0_SA_MASK                      (0xFFU)
  #define FTFA_SACCH0_SA_SHIFT                     (0U)
  /*! SA - Supervisor-only access control
   *  0b00000000..Associated segment is accessible in supervisor mode only
   *  0b00000001..Associated segment is accessible in user or supervisor mode
   */
  #define FTFA_SACCH0_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK)
  /*! @} */
  
  /*! @name SACCL3 - Supervisor-only Access Registers */
  /*! @{ */
  #define FTFA_SACCL3_SA_MASK                      (0xFFU)
  #define FTFA_SACCL3_SA_SHIFT                     (0U)
  /*! SA - Supervisor-only access control
   *  0b00000000..Associated segment is accessible in supervisor mode only
   *  0b00000001..Associated segment is accessible in user or supervisor mode
   */
  #define FTFA_SACCL3_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK)
  /*! @} */
  
  /*! @name SACCL2 - Supervisor-only Access Registers */
  /*! @{ */
  #define FTFA_SACCL2_SA_MASK                      (0xFFU)
  #define FTFA_SACCL2_SA_SHIFT                     (0U)
  /*! SA - Supervisor-only access control
   *  0b00000000..Associated segment is accessible in supervisor mode only
   *  0b00000001..Associated segment is accessible in user or supervisor mode
   */
  #define FTFA_SACCL2_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK)
  /*! @} */
  
  /*! @name SACCL1 - Supervisor-only Access Registers */
  /*! @{ */
  #define FTFA_SACCL1_SA_MASK                      (0xFFU)
  #define FTFA_SACCL1_SA_SHIFT                     (0U)
  /*! SA - Supervisor-only access control
   *  0b00000000..Associated segment is accessible in supervisor mode only
   *  0b00000001..Associated segment is accessible in user or supervisor mode
   */
  #define FTFA_SACCL1_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK)
  /*! @} */
  
  /*! @name SACCL0 - Supervisor-only Access Registers */
  /*! @{ */
  #define FTFA_SACCL0_SA_MASK                      (0xFFU)
  #define FTFA_SACCL0_SA_SHIFT                     (0U)
  /*! SA - Supervisor-only access control
   *  0b00000000..Associated segment is accessible in supervisor mode only
   *  0b00000001..Associated segment is accessible in user or supervisor mode
   */
  #define FTFA_SACCL0_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK)
  /*! @} */
  
  /*! @name FACSS - Flash Access Segment Size Register */
  /*! @{ */
  #define FTFA_FACSS_SGSIZE_MASK                   (0xFFU)
  #define FTFA_FACSS_SGSIZE_SHIFT                  (0U)
  #define FTFA_FACSS_SGSIZE(x)                     (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK)
  /*! @} */
  
  /*! @name FACSN - Flash Access Segment Number Register */
  /*! @{ */
  #define FTFA_FACSN_NUMSG_MASK                    (0xFFU)
  #define FTFA_FACSN_NUMSG_SHIFT                   (0U)
  /*! NUMSG - Number of Segments Indicator
   *  0b00100000..Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes)
   *  0b00101000..Program flash memory is divided into 40 segments (160 Kbytes)
   *  0b01000000..Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes)
   */
  #define FTFA_FACSN_NUMSG(x)                      (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group FTFA_Register_Masks */
  
  
  /* FTFA - Peripheral instance base addresses */
  /** Peripheral FTFA base address */
  #define FTFA_BASE                                (0x40020000u)
  /** Peripheral FTFA base pointer */
  #define FTFA                                     ((FTFA_Type *)FTFA_BASE)
  /** Array initializer of FTFA peripheral base addresses */
  #define FTFA_BASE_ADDRS                          { FTFA_BASE }
  /** Array initializer of FTFA peripheral base pointers */
  #define FTFA_BASE_PTRS                           { FTFA }
  /** Interrupt vectors for the FTFA peripheral type */
  #define FTFA_COMMAND_COMPLETE_IRQS               { FTF_IRQn }
  #define FTFA_READ_COLLISION_IRQS                 { Read_Collision_IRQn }
  
  /*!
   * @}
   */ /* end of group FTFA_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- FTM Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
   * @{
   */
  
  /** FTM - Register Layout Typedef */
  typedef struct {
    __IO uint32_t SC;                                /**< Status And Control, offset: 0x0 */
    __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
    __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
    struct {                                         /* offset: 0xC, array step: 0x8 */
      __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
      __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
    } CONTROLS[8];
    __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
    __IO uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
    __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
    __IO uint32_t SYNC;                              /**< Synchronization, offset: 0x58 */
    __IO uint32_t OUTINIT;                           /**< Initial State For Channels Output, offset: 0x5C */
    __IO uint32_t OUTMASK;                           /**< Output Mask, offset: 0x60 */
    __IO uint32_t COMBINE;                           /**< Function For Linked Channels, offset: 0x64 */
    __IO uint32_t DEADTIME;                          /**< Deadtime Insertion Control, offset: 0x68 */
    __IO uint32_t EXTTRIG;                           /**< FTM External Trigger, offset: 0x6C */
    __IO uint32_t POL;                               /**< Channels Polarity, offset: 0x70 */
    __IO uint32_t FMS;                               /**< Fault Mode Status, offset: 0x74 */
    __IO uint32_t FILTER;                            /**< Input Capture Filter Control, offset: 0x78 */
    __IO uint32_t FLTCTRL;                           /**< Fault Control, offset: 0x7C */
    __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control And Status, offset: 0x80 */
    __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
    __IO uint32_t FLTPOL;                            /**< FTM Fault Input Polarity, offset: 0x88 */
    __IO uint32_t SYNCONF;                           /**< Synchronization Configuration, offset: 0x8C */
    __IO uint32_t INVCTRL;                           /**< FTM Inverting Control, offset: 0x90 */
    __IO uint32_t SWOCTRL;                           /**< FTM Software Output Control, offset: 0x94 */
    __IO uint32_t PWMLOAD;                           /**< FTM PWM Load, offset: 0x98 */
  } FTM_Type;
  
  /* ----------------------------------------------------------------------------
     -- FTM Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup FTM_Register_Masks FTM Register Masks
   * @{
   */
  
  /*! @name SC - Status And Control */
  /*! @{ */
  #define FTM_SC_PS_MASK                           (0x7U)
  #define FTM_SC_PS_SHIFT                          (0U)
  /*! PS - Prescale Factor Selection
   *  0b000..Divide by 1
   *  0b001..Divide by 2
   *  0b010..Divide by 4
   *  0b011..Divide by 8
   *  0b100..Divide by 16
   *  0b101..Divide by 32
   *  0b110..Divide by 64
   *  0b111..Divide by 128
   */
  #define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
  #define FTM_SC_CLKS_MASK                         (0x18U)
  #define FTM_SC_CLKS_SHIFT                        (3U)
  /*! CLKS - Clock Source Selection
   *  0b00..No clock selected. This in effect disables the FTM counter.
   *  0b01..System clock
   *  0b10..Fixed frequency clock
   *  0b11..External clock
   */
  #define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
  #define FTM_SC_CPWMS_MASK                        (0x20U)
  #define FTM_SC_CPWMS_SHIFT                       (5U)
  /*! CPWMS - Center-Aligned PWM Select
   *  0b0..FTM counter operates in Up Counting mode.
   *  0b1..FTM counter operates in Up-Down Counting mode.
   */
  #define FTM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
  #define FTM_SC_TOIE_MASK                         (0x40U)
  #define FTM_SC_TOIE_SHIFT                        (6U)
  /*! TOIE - Timer Overflow Interrupt Enable
   *  0b0..Disable TOF interrupts. Use software polling.
   *  0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
   */
  #define FTM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
  #define FTM_SC_TOF_MASK                          (0x80U)
  #define FTM_SC_TOF_SHIFT                         (7U)
  /*! TOF - Timer Overflow Flag
   *  0b0..FTM counter has not overflowed.
   *  0b1..FTM counter has overflowed.
   */
  #define FTM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
  /*! @} */
  
  /*! @name CNT - Counter */
  /*! @{ */
  #define FTM_CNT_COUNT_MASK                       (0xFFFFU)
  #define FTM_CNT_COUNT_SHIFT                      (0U)
  #define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
  /*! @} */
  
  /*! @name MOD - Modulo */
  /*! @{ */
  #define FTM_MOD_MOD_MASK                         (0xFFFFU)
  #define FTM_MOD_MOD_SHIFT                        (0U)
  #define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
  /*! @} */
  
  /*! @name CnSC - Channel (n) Status And Control */
  /*! @{ */
  #define FTM_CnSC_DMA_MASK                        (0x1U)
  #define FTM_CnSC_DMA_SHIFT                       (0U)
  /*! DMA - DMA Enable
   *  0b0..Disable DMA transfers.
   *  0b1..Enable DMA transfers.
   */
  #define FTM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
  #define FTM_CnSC_ICRST_MASK                      (0x2U)
  #define FTM_CnSC_ICRST_SHIFT                     (1U)
  /*! ICRST - FTM counter reset by the selected input capture event.
   *  0b0..FTM counter is not reset when the selected channel (n) input event is detected.
   *  0b1..FTM counter is reset when the selected channel (n) input event is detected.
   */
  #define FTM_CnSC_ICRST(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK)
  #define FTM_CnSC_ELSA_MASK                       (0x4U)
  #define FTM_CnSC_ELSA_SHIFT                      (2U)
  #define FTM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
  #define FTM_CnSC_ELSB_MASK                       (0x8U)
  #define FTM_CnSC_ELSB_SHIFT                      (3U)
  #define FTM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
  #define FTM_CnSC_MSA_MASK                        (0x10U)
  #define FTM_CnSC_MSA_SHIFT                       (4U)
  #define FTM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
  #define FTM_CnSC_MSB_MASK                        (0x20U)
  #define FTM_CnSC_MSB_SHIFT                       (5U)
  #define FTM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
  #define FTM_CnSC_CHIE_MASK                       (0x40U)
  #define FTM_CnSC_CHIE_SHIFT                      (6U)
  /*! CHIE - Channel Interrupt Enable
   *  0b0..Disable channel interrupts. Use software polling.
   *  0b1..Enable channel interrupts.
   */
  #define FTM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
  #define FTM_CnSC_CHF_MASK                        (0x80U)
  #define FTM_CnSC_CHF_SHIFT                       (7U)
  /*! CHF - Channel Flag
   *  0b0..No channel event has occurred.
   *  0b1..A channel event has occurred.
   */
  #define FTM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
  /*! @} */
  
  /* The count of FTM_CnSC */
  #define FTM_CnSC_COUNT                           (8U)
  
  /*! @name CnV - Channel (n) Value */
  /*! @{ */
  #define FTM_CnV_VAL_MASK                         (0xFFFFU)
  #define FTM_CnV_VAL_SHIFT                        (0U)
  #define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
  /*! @} */
  
  /* The count of FTM_CnV */
  #define FTM_CnV_COUNT                            (8U)
  
  /*! @name CNTIN - Counter Initial Value */
  /*! @{ */
  #define FTM_CNTIN_INIT_MASK                      (0xFFFFU)
  #define FTM_CNTIN_INIT_SHIFT                     (0U)
  #define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
  /*! @} */
  
  /*! @name STATUS - Capture And Compare Status */
  /*! @{ */
  #define FTM_STATUS_CH0F_MASK                     (0x1U)
  #define FTM_STATUS_CH0F_SHIFT                    (0U)
  /*! CH0F - Channel 0 Flag
   *  0b0..No channel event has occurred.
   *  0b1..A channel event has occurred.
   */
  #define FTM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
  #define FTM_STATUS_CH1F_MASK                     (0x2U)
  #define FTM_STATUS_CH1F_SHIFT                    (1U)
  /*! CH1F - Channel 1 Flag
   *  0b0..No channel event has occurred.
   *  0b1..A channel event has occurred.
   */
  #define FTM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
  #define FTM_STATUS_CH2F_MASK                     (0x4U)
  #define FTM_STATUS_CH2F_SHIFT                    (2U)
  /*! CH2F - Channel 2 Flag
   *  0b0..No channel event has occurred.
   *  0b1..A channel event has occurred.
   */
  #define FTM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
  #define FTM_STATUS_CH3F_MASK                     (0x8U)
  #define FTM_STATUS_CH3F_SHIFT                    (3U)
  /*! CH3F - Channel 3 Flag
   *  0b0..No channel event has occurred.
   *  0b1..A channel event has occurred.
   */
  #define FTM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
  #define FTM_STATUS_CH4F_MASK                     (0x10U)
  #define FTM_STATUS_CH4F_SHIFT                    (4U)
  /*! CH4F - Channel 4 Flag
   *  0b0..No channel event has occurred.
   *  0b1..A channel event has occurred.
   */
  #define FTM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
  #define FTM_STATUS_CH5F_MASK                     (0x20U)
  #define FTM_STATUS_CH5F_SHIFT                    (5U)
  /*! CH5F - Channel 5 Flag
   *  0b0..No channel event has occurred.
   *  0b1..A channel event has occurred.
   */
  #define FTM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
  #define FTM_STATUS_CH6F_MASK                     (0x40U)
  #define FTM_STATUS_CH6F_SHIFT                    (6U)
  /*! CH6F - Channel 6 Flag
   *  0b0..No channel event has occurred.
   *  0b1..A channel event has occurred.
   */
  #define FTM_STATUS_CH6F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
  #define FTM_STATUS_CH7F_MASK                     (0x80U)
  #define FTM_STATUS_CH7F_SHIFT                    (7U)
  /*! CH7F - Channel 7 Flag
   *  0b0..No channel event has occurred.
   *  0b1..A channel event has occurred.
   */
  #define FTM_STATUS_CH7F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
  /*! @} */
  
  /*! @name MODE - Features Mode Selection */
  /*! @{ */
  #define FTM_MODE_FTMEN_MASK                      (0x1U)
  #define FTM_MODE_FTMEN_SHIFT                     (0U)
  /*! FTMEN - FTM Enable
   *  0b0..TPM compatibility. Free running counter and synchronization compatible with TPM.
   *  0b1..Free running counter and synchronization are different from TPM behavior.
   */
  #define FTM_MODE_FTMEN(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
  #define FTM_MODE_INIT_MASK                       (0x2U)
  #define FTM_MODE_INIT_SHIFT                      (1U)
  #define FTM_MODE_INIT(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
  #define FTM_MODE_WPDIS_MASK                      (0x4U)
  #define FTM_MODE_WPDIS_SHIFT                     (2U)
  /*! WPDIS - Write Protection Disable
   *  0b0..Write protection is enabled.
   *  0b1..Write protection is disabled.
   */
  #define FTM_MODE_WPDIS(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
  #define FTM_MODE_PWMSYNC_MASK                    (0x8U)
  #define FTM_MODE_PWMSYNC_SHIFT                   (3U)
  /*! PWMSYNC - PWM Synchronization Mode
   *  0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
   *  0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
   */
  #define FTM_MODE_PWMSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
  #define FTM_MODE_CAPTEST_MASK                    (0x10U)
  #define FTM_MODE_CAPTEST_SHIFT                   (4U)
  /*! CAPTEST - Capture Test Mode Enable
   *  0b0..Capture test mode is disabled.
   *  0b1..Capture test mode is enabled.
   */
  #define FTM_MODE_CAPTEST(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
  #define FTM_MODE_FAULTM_MASK                     (0x60U)
  #define FTM_MODE_FAULTM_SHIFT                    (5U)
  /*! FAULTM - Fault Control Mode
   *  0b00..Fault control is disabled for all channels.
   *  0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
   *  0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
   *  0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
   */
  #define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
  #define FTM_MODE_FAULTIE_MASK                    (0x80U)
  #define FTM_MODE_FAULTIE_SHIFT                   (7U)
  /*! FAULTIE - Fault Interrupt Enable
   *  0b0..Fault control interrupt is disabled.
   *  0b1..Fault control interrupt is enabled.
   */
  #define FTM_MODE_FAULTIE(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
  /*! @} */
  
  /*! @name SYNC - Synchronization */
  /*! @{ */
  #define FTM_SYNC_CNTMIN_MASK                     (0x1U)
  #define FTM_SYNC_CNTMIN_SHIFT                    (0U)
  /*! CNTMIN - Minimum Loading Point Enable
   *  0b0..The minimum loading point is disabled.
   *  0b1..The minimum loading point is enabled.
   */
  #define FTM_SYNC_CNTMIN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
  #define FTM_SYNC_CNTMAX_MASK                     (0x2U)
  #define FTM_SYNC_CNTMAX_SHIFT                    (1U)
  /*! CNTMAX - Maximum Loading Point Enable
   *  0b0..The maximum loading point is disabled.
   *  0b1..The maximum loading point is enabled.
   */
  #define FTM_SYNC_CNTMAX(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
  #define FTM_SYNC_REINIT_MASK                     (0x4U)
  #define FTM_SYNC_REINIT_SHIFT                    (2U)
  /*! REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
   *  0b0..FTM counter continues to count normally.
   *  0b1..FTM counter is updated with its initial value when the selected trigger is detected.
   */
  #define FTM_SYNC_REINIT(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
  #define FTM_SYNC_SYNCHOM_MASK                    (0x8U)
  #define FTM_SYNC_SYNCHOM_SHIFT                   (3U)
  /*! SYNCHOM - Output Mask Synchronization
   *  0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
   *  0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
   */
  #define FTM_SYNC_SYNCHOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
  #define FTM_SYNC_TRIG0_MASK                      (0x10U)
  #define FTM_SYNC_TRIG0_SHIFT                     (4U)
  /*! TRIG0 - PWM Synchronization Hardware Trigger 0
   *  0b0..Trigger is disabled.
   *  0b1..Trigger is enabled.
   */
  #define FTM_SYNC_TRIG0(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
  #define FTM_SYNC_TRIG1_MASK                      (0x20U)
  #define FTM_SYNC_TRIG1_SHIFT                     (5U)
  /*! TRIG1 - PWM Synchronization Hardware Trigger 1
   *  0b0..Trigger is disabled.
   *  0b1..Trigger is enabled.
   */
  #define FTM_SYNC_TRIG1(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
  #define FTM_SYNC_TRIG2_MASK                      (0x40U)
  #define FTM_SYNC_TRIG2_SHIFT                     (6U)
  /*! TRIG2 - PWM Synchronization Hardware Trigger 2
   *  0b0..Trigger is disabled.
   *  0b1..Trigger is enabled.
   */
  #define FTM_SYNC_TRIG2(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
  #define FTM_SYNC_SWSYNC_MASK                     (0x80U)
  #define FTM_SYNC_SWSYNC_SHIFT                    (7U)
  /*! SWSYNC - PWM Synchronization Software Trigger
   *  0b0..Software trigger is not selected.
   *  0b1..Software trigger is selected.
   */
  #define FTM_SYNC_SWSYNC(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
  /*! @} */
  
  /*! @name OUTINIT - Initial State For Channels Output */
  /*! @{ */
  #define FTM_OUTINIT_CH0OI_MASK                   (0x1U)
  #define FTM_OUTINIT_CH0OI_SHIFT                  (0U)
  /*! CH0OI - Channel 0 Output Initialization Value
   *  0b0..The initialization value is 0.
   *  0b1..The initialization value is 1.
   */
  #define FTM_OUTINIT_CH0OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
  #define FTM_OUTINIT_CH1OI_MASK                   (0x2U)
  #define FTM_OUTINIT_CH1OI_SHIFT                  (1U)
  /*! CH1OI - Channel 1 Output Initialization Value
   *  0b0..The initialization value is 0.
   *  0b1..The initialization value is 1.
   */
  #define FTM_OUTINIT_CH1OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
  #define FTM_OUTINIT_CH2OI_MASK                   (0x4U)
  #define FTM_OUTINIT_CH2OI_SHIFT                  (2U)
  /*! CH2OI - Channel 2 Output Initialization Value
   *  0b0..The initialization value is 0.
   *  0b1..The initialization value is 1.
   */
  #define FTM_OUTINIT_CH2OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
  #define FTM_OUTINIT_CH3OI_MASK                   (0x8U)
  #define FTM_OUTINIT_CH3OI_SHIFT                  (3U)
  /*! CH3OI - Channel 3 Output Initialization Value
   *  0b0..The initialization value is 0.
   *  0b1..The initialization value is 1.
   */
  #define FTM_OUTINIT_CH3OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
  #define FTM_OUTINIT_CH4OI_MASK                   (0x10U)
  #define FTM_OUTINIT_CH4OI_SHIFT                  (4U)
  /*! CH4OI - Channel 4 Output Initialization Value
   *  0b0..The initialization value is 0.
   *  0b1..The initialization value is 1.
   */
  #define FTM_OUTINIT_CH4OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
  #define FTM_OUTINIT_CH5OI_MASK                   (0x20U)
  #define FTM_OUTINIT_CH5OI_SHIFT                  (5U)
  /*! CH5OI - Channel 5 Output Initialization Value
   *  0b0..The initialization value is 0.
   *  0b1..The initialization value is 1.
   */
  #define FTM_OUTINIT_CH5OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
  #define FTM_OUTINIT_CH6OI_MASK                   (0x40U)
  #define FTM_OUTINIT_CH6OI_SHIFT                  (6U)
  /*! CH6OI - Channel 6 Output Initialization Value
   *  0b0..The initialization value is 0.
   *  0b1..The initialization value is 1.
   */
  #define FTM_OUTINIT_CH6OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
  #define FTM_OUTINIT_CH7OI_MASK                   (0x80U)
  #define FTM_OUTINIT_CH7OI_SHIFT                  (7U)
  /*! CH7OI - Channel 7 Output Initialization Value
   *  0b0..The initialization value is 0.
   *  0b1..The initialization value is 1.
   */
  #define FTM_OUTINIT_CH7OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
  /*! @} */
  
  /*! @name OUTMASK - Output Mask */
  /*! @{ */
  #define FTM_OUTMASK_CH0OM_MASK                   (0x1U)
  #define FTM_OUTMASK_CH0OM_SHIFT                  (0U)
  /*! CH0OM - Channel 0 Output Mask
   *  0b0..Channel output is not masked. It continues to operate normally.
   *  0b1..Channel output is masked. It is forced to its inactive state.
   */
  #define FTM_OUTMASK_CH0OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
  #define FTM_OUTMASK_CH1OM_MASK                   (0x2U)
  #define FTM_OUTMASK_CH1OM_SHIFT                  (1U)
  /*! CH1OM - Channel 1 Output Mask
   *  0b0..Channel output is not masked. It continues to operate normally.
   *  0b1..Channel output is masked. It is forced to its inactive state.
   */
  #define FTM_OUTMASK_CH1OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
  #define FTM_OUTMASK_CH2OM_MASK                   (0x4U)
  #define FTM_OUTMASK_CH2OM_SHIFT                  (2U)
  /*! CH2OM - Channel 2 Output Mask
   *  0b0..Channel output is not masked. It continues to operate normally.
   *  0b1..Channel output is masked. It is forced to its inactive state.
   */
  #define FTM_OUTMASK_CH2OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
  #define FTM_OUTMASK_CH3OM_MASK                   (0x8U)
  #define FTM_OUTMASK_CH3OM_SHIFT                  (3U)
  /*! CH3OM - Channel 3 Output Mask
   *  0b0..Channel output is not masked. It continues to operate normally.
   *  0b1..Channel output is masked. It is forced to its inactive state.
   */
  #define FTM_OUTMASK_CH3OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
  #define FTM_OUTMASK_CH4OM_MASK                   (0x10U)
  #define FTM_OUTMASK_CH4OM_SHIFT                  (4U)
  /*! CH4OM - Channel 4 Output Mask
   *  0b0..Channel output is not masked. It continues to operate normally.
   *  0b1..Channel output is masked. It is forced to its inactive state.
   */
  #define FTM_OUTMASK_CH4OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
  #define FTM_OUTMASK_CH5OM_MASK                   (0x20U)
  #define FTM_OUTMASK_CH5OM_SHIFT                  (5U)
  /*! CH5OM - Channel 5 Output Mask
   *  0b0..Channel output is not masked. It continues to operate normally.
   *  0b1..Channel output is masked. It is forced to its inactive state.
   */
  #define FTM_OUTMASK_CH5OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
  #define FTM_OUTMASK_CH6OM_MASK                   (0x40U)
  #define FTM_OUTMASK_CH6OM_SHIFT                  (6U)
  /*! CH6OM - Channel 6 Output Mask
   *  0b0..Channel output is not masked. It continues to operate normally.
   *  0b1..Channel output is masked. It is forced to its inactive state.
   */
  #define FTM_OUTMASK_CH6OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
  #define FTM_OUTMASK_CH7OM_MASK                   (0x80U)
  #define FTM_OUTMASK_CH7OM_SHIFT                  (7U)
  /*! CH7OM - Channel 7 Output Mask
   *  0b0..Channel output is not masked. It continues to operate normally.
   *  0b1..Channel output is masked. It is forced to its inactive state.
   */
  #define FTM_OUTMASK_CH7OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
  /*! @} */
  
  /*! @name COMBINE - Function For Linked Channels */
  /*! @{ */
  #define FTM_COMBINE_COMBINE0_MASK                (0x1U)
  #define FTM_COMBINE_COMBINE0_SHIFT               (0U)
  /*! COMBINE0 - Combine Channels For n = 0
   *  0b0..Channels (n) and (n+1) are independent.
   *  0b1..Channels (n) and (n+1) are combined.
   */
  #define FTM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
  #define FTM_COMBINE_COMP0_MASK                   (0x2U)
  #define FTM_COMBINE_COMP0_SHIFT                  (1U)
  /*! COMP0 - Complement Of Channel (n) For n = 0
   *  0b0..The channel (n+1) output is the same as the channel (n) output.
   *  0b1..The channel (n+1) output is the complement of the channel (n) output.
   */
  #define FTM_COMBINE_COMP0(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
  #define FTM_COMBINE_DECAPEN0_MASK                (0x4U)
  #define FTM_COMBINE_DECAPEN0_SHIFT               (2U)
  /*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0
   *  0b0..The Dual Edge Capture mode in this pair of channels is disabled.
   *  0b1..The Dual Edge Capture mode in this pair of channels is enabled.
   */
  #define FTM_COMBINE_DECAPEN0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
  #define FTM_COMBINE_DECAP0_MASK                  (0x8U)
  #define FTM_COMBINE_DECAP0_SHIFT                 (3U)
  /*! DECAP0 - Dual Edge Capture Mode Captures For n = 0
   *  0b0..The dual edge captures are inactive.
   *  0b1..The dual edge captures are active.
   */
  #define FTM_COMBINE_DECAP0(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
  #define FTM_COMBINE_DTEN0_MASK                   (0x10U)
  #define FTM_COMBINE_DTEN0_SHIFT                  (4U)
  /*! DTEN0 - Deadtime Enable For n = 0
   *  0b0..The deadtime insertion in this pair of channels is disabled.
   *  0b1..The deadtime insertion in this pair of channels is enabled.
   */
  #define FTM_COMBINE_DTEN0(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
  #define FTM_COMBINE_SYNCEN0_MASK                 (0x20U)
  #define FTM_COMBINE_SYNCEN0_SHIFT                (5U)
  /*! SYNCEN0 - Synchronization Enable For n = 0
   *  0b0..The PWM synchronization in this pair of channels is disabled.
   *  0b1..The PWM synchronization in this pair of channels is enabled.
   */
  #define FTM_COMBINE_SYNCEN0(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
  #define FTM_COMBINE_FAULTEN0_MASK                (0x40U)
  #define FTM_COMBINE_FAULTEN0_SHIFT               (6U)
  /*! FAULTEN0 - Fault Control Enable For n = 0
   *  0b0..The fault control in this pair of channels is disabled.
   *  0b1..The fault control in this pair of channels is enabled.
   */
  #define FTM_COMBINE_FAULTEN0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
  #define FTM_COMBINE_COMBINE1_MASK                (0x100U)
  #define FTM_COMBINE_COMBINE1_SHIFT               (8U)
  /*! COMBINE1 - Combine Channels For n = 2
   *  0b0..Channels (n) and (n+1) are independent.
   *  0b1..Channels (n) and (n+1) are combined.
   */
  #define FTM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
  #define FTM_COMBINE_COMP1_MASK                   (0x200U)
  #define FTM_COMBINE_COMP1_SHIFT                  (9U)
  /*! COMP1 - Complement Of Channel (n) For n = 2
   *  0b0..The channel (n+1) output is the same as the channel (n) output.
   *  0b1..The channel (n+1) output is the complement of the channel (n) output.
   */
  #define FTM_COMBINE_COMP1(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
  #define FTM_COMBINE_DECAPEN1_MASK                (0x400U)
  #define FTM_COMBINE_DECAPEN1_SHIFT               (10U)
  /*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2
   *  0b0..The Dual Edge Capture mode in this pair of channels is disabled.
   *  0b1..The Dual Edge Capture mode in this pair of channels is enabled.
   */
  #define FTM_COMBINE_DECAPEN1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
  #define FTM_COMBINE_DECAP1_MASK                  (0x800U)
  #define FTM_COMBINE_DECAP1_SHIFT                 (11U)
  /*! DECAP1 - Dual Edge Capture Mode Captures For n = 2
   *  0b0..The dual edge captures are inactive.
   *  0b1..The dual edge captures are active.
   */
  #define FTM_COMBINE_DECAP1(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
  #define FTM_COMBINE_DTEN1_MASK                   (0x1000U)
  #define FTM_COMBINE_DTEN1_SHIFT                  (12U)
  /*! DTEN1 - Deadtime Enable For n = 2
   *  0b0..The deadtime insertion in this pair of channels is disabled.
   *  0b1..The deadtime insertion in this pair of channels is enabled.
   */
  #define FTM_COMBINE_DTEN1(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
  #define FTM_COMBINE_SYNCEN1_MASK                 (0x2000U)
  #define FTM_COMBINE_SYNCEN1_SHIFT                (13U)
  /*! SYNCEN1 - Synchronization Enable For n = 2
   *  0b0..The PWM synchronization in this pair of channels is disabled.
   *  0b1..The PWM synchronization in this pair of channels is enabled.
   */
  #define FTM_COMBINE_SYNCEN1(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
  #define FTM_COMBINE_FAULTEN1_MASK                (0x4000U)
  #define FTM_COMBINE_FAULTEN1_SHIFT               (14U)
  /*! FAULTEN1 - Fault Control Enable For n = 2
   *  0b0..The fault control in this pair of channels is disabled.
   *  0b1..The fault control in this pair of channels is enabled.
   */
  #define FTM_COMBINE_FAULTEN1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
  #define FTM_COMBINE_COMBINE2_MASK                (0x10000U)
  #define FTM_COMBINE_COMBINE2_SHIFT               (16U)
  /*! COMBINE2 - Combine Channels For n = 4
   *  0b0..Channels (n) and (n+1) are independent.
   *  0b1..Channels (n) and (n+1) are combined.
   */
  #define FTM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
  #define FTM_COMBINE_COMP2_MASK                   (0x20000U)
  #define FTM_COMBINE_COMP2_SHIFT                  (17U)
  /*! COMP2 - Complement Of Channel (n) For n = 4
   *  0b0..The channel (n+1) output is the same as the channel (n) output.
   *  0b1..The channel (n+1) output is the complement of the channel (n) output.
   */
  #define FTM_COMBINE_COMP2(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
  #define FTM_COMBINE_DECAPEN2_MASK                (0x40000U)
  #define FTM_COMBINE_DECAPEN2_SHIFT               (18U)
  /*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4
   *  0b0..The Dual Edge Capture mode in this pair of channels is disabled.
   *  0b1..The Dual Edge Capture mode in this pair of channels is enabled.
   */
  #define FTM_COMBINE_DECAPEN2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
  #define FTM_COMBINE_DECAP2_MASK                  (0x80000U)
  #define FTM_COMBINE_DECAP2_SHIFT                 (19U)
  /*! DECAP2 - Dual Edge Capture Mode Captures For n = 4
   *  0b0..The dual edge captures are inactive.
   *  0b1..The dual edge captures are active.
   */
  #define FTM_COMBINE_DECAP2(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
  #define FTM_COMBINE_DTEN2_MASK                   (0x100000U)
  #define FTM_COMBINE_DTEN2_SHIFT                  (20U)
  /*! DTEN2 - Deadtime Enable For n = 4
   *  0b0..The deadtime insertion in this pair of channels is disabled.
   *  0b1..The deadtime insertion in this pair of channels is enabled.
   */
  #define FTM_COMBINE_DTEN2(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
  #define FTM_COMBINE_SYNCEN2_MASK                 (0x200000U)
  #define FTM_COMBINE_SYNCEN2_SHIFT                (21U)
  /*! SYNCEN2 - Synchronization Enable For n = 4
   *  0b0..The PWM synchronization in this pair of channels is disabled.
   *  0b1..The PWM synchronization in this pair of channels is enabled.
   */
  #define FTM_COMBINE_SYNCEN2(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
  #define FTM_COMBINE_FAULTEN2_MASK                (0x400000U)
  #define FTM_COMBINE_FAULTEN2_SHIFT               (22U)
  /*! FAULTEN2 - Fault Control Enable For n = 4
   *  0b0..The fault control in this pair of channels is disabled.
   *  0b1..The fault control in this pair of channels is enabled.
   */
  #define FTM_COMBINE_FAULTEN2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
  #define FTM_COMBINE_COMBINE3_MASK                (0x1000000U)
  #define FTM_COMBINE_COMBINE3_SHIFT               (24U)
  /*! COMBINE3 - Combine Channels For n = 6
   *  0b0..Channels (n) and (n+1) are independent.
   *  0b1..Channels (n) and (n+1) are combined.
   */
  #define FTM_COMBINE_COMBINE3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
  #define FTM_COMBINE_COMP3_MASK                   (0x2000000U)
  #define FTM_COMBINE_COMP3_SHIFT                  (25U)
  /*! COMP3 - Complement Of Channel (n) for n = 6
   *  0b0..The channel (n+1) output is the same as the channel (n) output.
   *  0b1..The channel (n+1) output is the complement of the channel (n) output.
   */
  #define FTM_COMBINE_COMP3(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
  #define FTM_COMBINE_DECAPEN3_MASK                (0x4000000U)
  #define FTM_COMBINE_DECAPEN3_SHIFT               (26U)
  /*! DECAPEN3 - Dual Edge Capture Mode Enable For n = 6
   *  0b0..The Dual Edge Capture mode in this pair of channels is disabled.
   *  0b1..The Dual Edge Capture mode in this pair of channels is enabled.
   */
  #define FTM_COMBINE_DECAPEN3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
  #define FTM_COMBINE_DECAP3_MASK                  (0x8000000U)
  #define FTM_COMBINE_DECAP3_SHIFT                 (27U)
  /*! DECAP3 - Dual Edge Capture Mode Captures For n = 6
   *  0b0..The dual edge captures are inactive.
   *  0b1..The dual edge captures are active.
   */
  #define FTM_COMBINE_DECAP3(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
  #define FTM_COMBINE_DTEN3_MASK                   (0x10000000U)
  #define FTM_COMBINE_DTEN3_SHIFT                  (28U)
  /*! DTEN3 - Deadtime Enable For n = 6
   *  0b0..The deadtime insertion in this pair of channels is disabled.
   *  0b1..The deadtime insertion in this pair of channels is enabled.
   */
  #define FTM_COMBINE_DTEN3(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
  #define FTM_COMBINE_SYNCEN3_MASK                 (0x20000000U)
  #define FTM_COMBINE_SYNCEN3_SHIFT                (29U)
  /*! SYNCEN3 - Synchronization Enable For n = 6
   *  0b0..The PWM synchronization in this pair of channels is disabled.
   *  0b1..The PWM synchronization in this pair of channels is enabled.
   */
  #define FTM_COMBINE_SYNCEN3(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
  #define FTM_COMBINE_FAULTEN3_MASK                (0x40000000U)
  #define FTM_COMBINE_FAULTEN3_SHIFT               (30U)
  /*! FAULTEN3 - Fault Control Enable For n = 6
   *  0b0..The fault control in this pair of channels is disabled.
   *  0b1..The fault control in this pair of channels is enabled.
   */
  #define FTM_COMBINE_FAULTEN3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
  /*! @} */
  
  /*! @name DEADTIME - Deadtime Insertion Control */
  /*! @{ */
  #define FTM_DEADTIME_DTVAL_MASK                  (0x3FU)
  #define FTM_DEADTIME_DTVAL_SHIFT                 (0U)
  #define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
  #define FTM_DEADTIME_DTPS_MASK                   (0xC0U)
  #define FTM_DEADTIME_DTPS_SHIFT                  (6U)
  /*! DTPS - Deadtime Prescaler Value
   *  0b0x..Divide the system clock by 1.
   *  0b10..Divide the system clock by 4.
   *  0b11..Divide the system clock by 16.
   */
  #define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
  /*! @} */
  
  /*! @name EXTTRIG - FTM External Trigger */
  /*! @{ */
  #define FTM_EXTTRIG_CH2TRIG_MASK                 (0x1U)
  #define FTM_EXTTRIG_CH2TRIG_SHIFT                (0U)
  /*! CH2TRIG - Channel 2 Trigger Enable
   *  0b0..The generation of the channel trigger is disabled.
   *  0b1..The generation of the channel trigger is enabled.
   */
  #define FTM_EXTTRIG_CH2TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
  #define FTM_EXTTRIG_CH3TRIG_MASK                 (0x2U)
  #define FTM_EXTTRIG_CH3TRIG_SHIFT                (1U)
  /*! CH3TRIG - Channel 3 Trigger Enable
   *  0b0..The generation of the channel trigger is disabled.
   *  0b1..The generation of the channel trigger is enabled.
   */
  #define FTM_EXTTRIG_CH3TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
  #define FTM_EXTTRIG_CH4TRIG_MASK                 (0x4U)
  #define FTM_EXTTRIG_CH4TRIG_SHIFT                (2U)
  /*! CH4TRIG - Channel 4 Trigger Enable
   *  0b0..The generation of the channel trigger is disabled.
   *  0b1..The generation of the channel trigger is enabled.
   */
  #define FTM_EXTTRIG_CH4TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
  #define FTM_EXTTRIG_CH5TRIG_MASK                 (0x8U)
  #define FTM_EXTTRIG_CH5TRIG_SHIFT                (3U)
  /*! CH5TRIG - Channel 5 Trigger Enable
   *  0b0..The generation of the channel trigger is disabled.
   *  0b1..The generation of the channel trigger is enabled.
   */
  #define FTM_EXTTRIG_CH5TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
  #define FTM_EXTTRIG_CH0TRIG_MASK                 (0x10U)
  #define FTM_EXTTRIG_CH0TRIG_SHIFT                (4U)
  /*! CH0TRIG - Channel 0 Trigger Enable
   *  0b0..The generation of the channel trigger is disabled.
   *  0b1..The generation of the channel trigger is enabled.
   */
  #define FTM_EXTTRIG_CH0TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
  #define FTM_EXTTRIG_CH1TRIG_MASK                 (0x20U)
  #define FTM_EXTTRIG_CH1TRIG_SHIFT                (5U)
  /*! CH1TRIG - Channel 1 Trigger Enable
   *  0b0..The generation of the channel trigger is disabled.
   *  0b1..The generation of the channel trigger is enabled.
   */
  #define FTM_EXTTRIG_CH1TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
  #define FTM_EXTTRIG_INITTRIGEN_MASK              (0x40U)
  #define FTM_EXTTRIG_INITTRIGEN_SHIFT             (6U)
  /*! INITTRIGEN - Initialization Trigger Enable
   *  0b0..The generation of initialization trigger is disabled.
   *  0b1..The generation of initialization trigger is enabled.
   */
  #define FTM_EXTTRIG_INITTRIGEN(x)                (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
  #define FTM_EXTTRIG_TRIGF_MASK                   (0x80U)
  #define FTM_EXTTRIG_TRIGF_SHIFT                  (7U)
  /*! TRIGF - Channel Trigger Flag
   *  0b0..No channel trigger was generated.
   *  0b1..A channel trigger was generated.
   */
  #define FTM_EXTTRIG_TRIGF(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
  /*! @} */
  
  /*! @name POL - Channels Polarity */
  /*! @{ */
  #define FTM_POL_POL0_MASK                        (0x1U)
  #define FTM_POL_POL0_SHIFT                       (0U)
  /*! POL0 - Channel 0 Polarity
   *  0b0..The channel polarity is active high.
   *  0b1..The channel polarity is active low.
   */
  #define FTM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
  #define FTM_POL_POL1_MASK                        (0x2U)
  #define FTM_POL_POL1_SHIFT                       (1U)
  /*! POL1 - Channel 1 Polarity
   *  0b0..The channel polarity is active high.
   *  0b1..The channel polarity is active low.
   */
  #define FTM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
  #define FTM_POL_POL2_MASK                        (0x4U)
  #define FTM_POL_POL2_SHIFT                       (2U)
  /*! POL2 - Channel 2 Polarity
   *  0b0..The channel polarity is active high.
   *  0b1..The channel polarity is active low.
   */
  #define FTM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
  #define FTM_POL_POL3_MASK                        (0x8U)
  #define FTM_POL_POL3_SHIFT                       (3U)
  /*! POL3 - Channel 3 Polarity
   *  0b0..The channel polarity is active high.
   *  0b1..The channel polarity is active low.
   */
  #define FTM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
  #define FTM_POL_POL4_MASK                        (0x10U)
  #define FTM_POL_POL4_SHIFT                       (4U)
  /*! POL4 - Channel 4 Polarity
   *  0b0..The channel polarity is active high.
   *  0b1..The channel polarity is active low.
   */
  #define FTM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
  #define FTM_POL_POL5_MASK                        (0x20U)
  #define FTM_POL_POL5_SHIFT                       (5U)
  /*! POL5 - Channel 5 Polarity
   *  0b0..The channel polarity is active high.
   *  0b1..The channel polarity is active low.
   */
  #define FTM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
  #define FTM_POL_POL6_MASK                        (0x40U)
  #define FTM_POL_POL6_SHIFT                       (6U)
  /*! POL6 - Channel 6 Polarity
   *  0b0..The channel polarity is active high.
   *  0b1..The channel polarity is active low.
   */
  #define FTM_POL_POL6(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
  #define FTM_POL_POL7_MASK                        (0x80U)
  #define FTM_POL_POL7_SHIFT                       (7U)
  /*! POL7 - Channel 7 Polarity
   *  0b0..The channel polarity is active high.
   *  0b1..The channel polarity is active low.
   */
  #define FTM_POL_POL7(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
  /*! @} */
  
  /*! @name FMS - Fault Mode Status */
  /*! @{ */
  #define FTM_FMS_FAULTF0_MASK                     (0x1U)
  #define FTM_FMS_FAULTF0_SHIFT                    (0U)
  /*! FAULTF0 - Fault Detection Flag 0
   *  0b0..No fault condition was detected at the fault input.
   *  0b1..A fault condition was detected at the fault input.
   */
  #define FTM_FMS_FAULTF0(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
  #define FTM_FMS_FAULTF1_MASK                     (0x2U)
  #define FTM_FMS_FAULTF1_SHIFT                    (1U)
  /*! FAULTF1 - Fault Detection Flag 1
   *  0b0..No fault condition was detected at the fault input.
   *  0b1..A fault condition was detected at the fault input.
   */
  #define FTM_FMS_FAULTF1(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
  #define FTM_FMS_FAULTF2_MASK                     (0x4U)
  #define FTM_FMS_FAULTF2_SHIFT                    (2U)
  /*! FAULTF2 - Fault Detection Flag 2
   *  0b0..No fault condition was detected at the fault input.
   *  0b1..A fault condition was detected at the fault input.
   */
  #define FTM_FMS_FAULTF2(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
  #define FTM_FMS_FAULTF3_MASK                     (0x8U)
  #define FTM_FMS_FAULTF3_SHIFT                    (3U)
  /*! FAULTF3 - Fault Detection Flag 3
   *  0b0..No fault condition was detected at the fault input.
   *  0b1..A fault condition was detected at the fault input.
   */
  #define FTM_FMS_FAULTF3(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
  #define FTM_FMS_FAULTIN_MASK                     (0x20U)
  #define FTM_FMS_FAULTIN_SHIFT                    (5U)
  /*! FAULTIN - Fault Inputs
   *  0b0..The logic OR of the enabled fault inputs is 0.
   *  0b1..The logic OR of the enabled fault inputs is 1.
   */
  #define FTM_FMS_FAULTIN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
  #define FTM_FMS_WPEN_MASK                        (0x40U)
  #define FTM_FMS_WPEN_SHIFT                       (6U)
  /*! WPEN - Write Protection Enable
   *  0b0..Write protection is disabled. Write protected bits can be written.
   *  0b1..Write protection is enabled. Write protected bits cannot be written.
   */
  #define FTM_FMS_WPEN(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
  #define FTM_FMS_FAULTF_MASK                      (0x80U)
  #define FTM_FMS_FAULTF_SHIFT                     (7U)
  /*! FAULTF - Fault Detection Flag
   *  0b0..No fault condition was detected.
   *  0b1..A fault condition was detected.
   */
  #define FTM_FMS_FAULTF(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
  /*! @} */
  
  /*! @name FILTER - Input Capture Filter Control */
  /*! @{ */
  #define FTM_FILTER_CH0FVAL_MASK                  (0xFU)
  #define FTM_FILTER_CH0FVAL_SHIFT                 (0U)
  #define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
  #define FTM_FILTER_CH1FVAL_MASK                  (0xF0U)
  #define FTM_FILTER_CH1FVAL_SHIFT                 (4U)
  #define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
  #define FTM_FILTER_CH2FVAL_MASK                  (0xF00U)
  #define FTM_FILTER_CH2FVAL_SHIFT                 (8U)
  #define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
  #define FTM_FILTER_CH3FVAL_MASK                  (0xF000U)
  #define FTM_FILTER_CH3FVAL_SHIFT                 (12U)
  #define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
  /*! @} */
  
  /*! @name FLTCTRL - Fault Control */
  /*! @{ */
  #define FTM_FLTCTRL_FAULT0EN_MASK                (0x1U)
  #define FTM_FLTCTRL_FAULT0EN_SHIFT               (0U)
  /*! FAULT0EN - Fault Input 0 Enable
   *  0b0..Fault input is disabled.
   *  0b1..Fault input is enabled.
   */
  #define FTM_FLTCTRL_FAULT0EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
  #define FTM_FLTCTRL_FAULT1EN_MASK                (0x2U)
  #define FTM_FLTCTRL_FAULT1EN_SHIFT               (1U)
  /*! FAULT1EN - Fault Input 1 Enable
   *  0b0..Fault input is disabled.
   *  0b1..Fault input is enabled.
   */
  #define FTM_FLTCTRL_FAULT1EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
  #define FTM_FLTCTRL_FAULT2EN_MASK                (0x4U)
  #define FTM_FLTCTRL_FAULT2EN_SHIFT               (2U)
  /*! FAULT2EN - Fault Input 2 Enable
   *  0b0..Fault input is disabled.
   *  0b1..Fault input is enabled.
   */
  #define FTM_FLTCTRL_FAULT2EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
  #define FTM_FLTCTRL_FAULT3EN_MASK                (0x8U)
  #define FTM_FLTCTRL_FAULT3EN_SHIFT               (3U)
  /*! FAULT3EN - Fault Input 3 Enable
   *  0b0..Fault input is disabled.
   *  0b1..Fault input is enabled.
   */
  #define FTM_FLTCTRL_FAULT3EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
  #define FTM_FLTCTRL_FFLTR0EN_MASK                (0x10U)
  #define FTM_FLTCTRL_FFLTR0EN_SHIFT               (4U)
  /*! FFLTR0EN - Fault Input 0 Filter Enable
   *  0b0..Fault input filter is disabled.
   *  0b1..Fault input filter is enabled.
   */
  #define FTM_FLTCTRL_FFLTR0EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
  #define FTM_FLTCTRL_FFLTR1EN_MASK                (0x20U)
  #define FTM_FLTCTRL_FFLTR1EN_SHIFT               (5U)
  /*! FFLTR1EN - Fault Input 1 Filter Enable
   *  0b0..Fault input filter is disabled.
   *  0b1..Fault input filter is enabled.
   */
  #define FTM_FLTCTRL_FFLTR1EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
  #define FTM_FLTCTRL_FFLTR2EN_MASK                (0x40U)
  #define FTM_FLTCTRL_FFLTR2EN_SHIFT               (6U)
  /*! FFLTR2EN - Fault Input 2 Filter Enable
   *  0b0..Fault input filter is disabled.
   *  0b1..Fault input filter is enabled.
   */
  #define FTM_FLTCTRL_FFLTR2EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
  #define FTM_FLTCTRL_FFLTR3EN_MASK                (0x80U)
  #define FTM_FLTCTRL_FFLTR3EN_SHIFT               (7U)
  /*! FFLTR3EN - Fault Input 3 Filter Enable
   *  0b0..Fault input filter is disabled.
   *  0b1..Fault input filter is enabled.
   */
  #define FTM_FLTCTRL_FFLTR3EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
  #define FTM_FLTCTRL_FFVAL_MASK                   (0xF00U)
  #define FTM_FLTCTRL_FFVAL_SHIFT                  (8U)
  #define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
  /*! @} */
  
  /*! @name QDCTRL - Quadrature Decoder Control And Status */
  /*! @{ */
  #define FTM_QDCTRL_QUADEN_MASK                   (0x1U)
  #define FTM_QDCTRL_QUADEN_SHIFT                  (0U)
  /*! QUADEN - Quadrature Decoder Mode Enable
   *  0b0..Quadrature Decoder mode is disabled.
   *  0b1..Quadrature Decoder mode is enabled.
   */
  #define FTM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
  #define FTM_QDCTRL_TOFDIR_MASK                   (0x2U)
  #define FTM_QDCTRL_TOFDIR_SHIFT                  (1U)
  /*! TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode
   *  0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).
   *  0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).
   */
  #define FTM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
  #define FTM_QDCTRL_QUADIR_MASK                   (0x4U)
  #define FTM_QDCTRL_QUADIR_SHIFT                  (2U)
  /*! QUADIR - FTM Counter Direction In Quadrature Decoder Mode
   *  0b0..Counting direction is decreasing (FTM counter decrement).
   *  0b1..Counting direction is increasing (FTM counter increment).
   */
  #define FTM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
  #define FTM_QDCTRL_QUADMODE_MASK                 (0x8U)
  #define FTM_QDCTRL_QUADMODE_SHIFT                (3U)
  /*! QUADMODE - Quadrature Decoder Mode
   *  0b0..Phase A and phase B encoding mode.
   *  0b1..Count and direction encoding mode.
   */
  #define FTM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
  #define FTM_QDCTRL_PHBPOL_MASK                   (0x10U)
  #define FTM_QDCTRL_PHBPOL_SHIFT                  (4U)
  /*! PHBPOL - Phase B Input Polarity
   *  0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
   *  0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
   */
  #define FTM_QDCTRL_PHBPOL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
  #define FTM_QDCTRL_PHAPOL_MASK                   (0x20U)
  #define FTM_QDCTRL_PHAPOL_SHIFT                  (5U)
  /*! PHAPOL - Phase A Input Polarity
   *  0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
   *  0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
   */
  #define FTM_QDCTRL_PHAPOL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
  #define FTM_QDCTRL_PHBFLTREN_MASK                (0x40U)
  #define FTM_QDCTRL_PHBFLTREN_SHIFT               (6U)
  /*! PHBFLTREN - Phase B Input Filter Enable
   *  0b0..Phase B input filter is disabled.
   *  0b1..Phase B input filter is enabled.
   */
  #define FTM_QDCTRL_PHBFLTREN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
  #define FTM_QDCTRL_PHAFLTREN_MASK                (0x80U)
  #define FTM_QDCTRL_PHAFLTREN_SHIFT               (7U)
  /*! PHAFLTREN - Phase A Input Filter Enable
   *  0b0..Phase A input filter is disabled.
   *  0b1..Phase A input filter is enabled.
   */
  #define FTM_QDCTRL_PHAFLTREN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
  /*! @} */
  
  /*! @name CONF - Configuration */
  /*! @{ */
  #define FTM_CONF_NUMTOF_MASK                     (0x1FU)
  #define FTM_CONF_NUMTOF_SHIFT                    (0U)
  #define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
  #define FTM_CONF_BDMMODE_MASK                    (0xC0U)
  #define FTM_CONF_BDMMODE_SHIFT                   (6U)
  #define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
  #define FTM_CONF_GTBEEN_MASK                     (0x200U)
  #define FTM_CONF_GTBEEN_SHIFT                    (9U)
  /*! GTBEEN - Global Time Base Enable
   *  0b0..Use of an external global time base is disabled.
   *  0b1..Use of an external global time base is enabled.
   */
  #define FTM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
  #define FTM_CONF_GTBEOUT_MASK                    (0x400U)
  #define FTM_CONF_GTBEOUT_SHIFT                   (10U)
  /*! GTBEOUT - Global Time Base Output
   *  0b0..A global time base signal generation is disabled.
   *  0b1..A global time base signal generation is enabled.
   */
  #define FTM_CONF_GTBEOUT(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
  /*! @} */
  
  /*! @name FLTPOL - FTM Fault Input Polarity */
  /*! @{ */
  #define FTM_FLTPOL_FLT0POL_MASK                  (0x1U)
  #define FTM_FLTPOL_FLT0POL_SHIFT                 (0U)
  /*! FLT0POL - Fault Input 0 Polarity
   *  0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
   *  0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
   */
  #define FTM_FLTPOL_FLT0POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
  #define FTM_FLTPOL_FLT1POL_MASK                  (0x2U)
  #define FTM_FLTPOL_FLT1POL_SHIFT                 (1U)
  /*! FLT1POL - Fault Input 1 Polarity
   *  0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
   *  0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
   */
  #define FTM_FLTPOL_FLT1POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
  #define FTM_FLTPOL_FLT2POL_MASK                  (0x4U)
  #define FTM_FLTPOL_FLT2POL_SHIFT                 (2U)
  /*! FLT2POL - Fault Input 2 Polarity
   *  0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
   *  0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
   */
  #define FTM_FLTPOL_FLT2POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
  #define FTM_FLTPOL_FLT3POL_MASK                  (0x8U)
  #define FTM_FLTPOL_FLT3POL_SHIFT                 (3U)
  /*! FLT3POL - Fault Input 3 Polarity
   *  0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
   *  0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
   */
  #define FTM_FLTPOL_FLT3POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
  /*! @} */
  
  /*! @name SYNCONF - Synchronization Configuration */
  /*! @{ */
  #define FTM_SYNCONF_HWTRIGMODE_MASK              (0x1U)
  #define FTM_SYNCONF_HWTRIGMODE_SHIFT             (0U)
  /*! HWTRIGMODE - Hardware Trigger Mode
   *  0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
   *  0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
   */
  #define FTM_SYNCONF_HWTRIGMODE(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
  #define FTM_SYNCONF_CNTINC_MASK                  (0x4U)
  #define FTM_SYNCONF_CNTINC_SHIFT                 (2U)
  /*! CNTINC - CNTIN Register Synchronization
   *  0b0..CNTIN register is updated with its buffer value at all rising edges of system clock.
   *  0b1..CNTIN register is updated with its buffer value by the PWM synchronization.
   */
  #define FTM_SYNCONF_CNTINC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
  #define FTM_SYNCONF_INVC_MASK                    (0x10U)
  #define FTM_SYNCONF_INVC_SHIFT                   (4U)
  /*! INVC - INVCTRL Register Synchronization
   *  0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock.
   *  0b1..INVCTRL register is updated with its buffer value by the PWM synchronization.
   */
  #define FTM_SYNCONF_INVC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
  #define FTM_SYNCONF_SWOC_MASK                    (0x20U)
  #define FTM_SYNCONF_SWOC_SHIFT                   (5U)
  /*! SWOC - SWOCTRL Register Synchronization
   *  0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock.
   *  0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization.
   */
  #define FTM_SYNCONF_SWOC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
  #define FTM_SYNCONF_SYNCMODE_MASK                (0x80U)
  #define FTM_SYNCONF_SYNCMODE_SHIFT               (7U)
  /*! SYNCMODE - Synchronization Mode
   *  0b0..Legacy PWM synchronization is selected.
   *  0b1..Enhanced PWM synchronization is selected.
   */
  #define FTM_SYNCONF_SYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
  #define FTM_SYNCONF_SWRSTCNT_MASK                (0x100U)
  #define FTM_SYNCONF_SWRSTCNT_SHIFT               (8U)
  /*! SWRSTCNT
   *  0b0..The software trigger does not activate the FTM counter synchronization.
   *  0b1..The software trigger activates the FTM counter synchronization.
   */
  #define FTM_SYNCONF_SWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
  #define FTM_SYNCONF_SWWRBUF_MASK                 (0x200U)
  #define FTM_SYNCONF_SWWRBUF_SHIFT                (9U)
  /*! SWWRBUF
   *  0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
   *  0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization.
   */
  #define FTM_SYNCONF_SWWRBUF(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
  #define FTM_SYNCONF_SWOM_MASK                    (0x400U)
  #define FTM_SYNCONF_SWOM_SHIFT                   (10U)
  /*! SWOM
   *  0b0..The software trigger does not activate the OUTMASK register synchronization.
   *  0b1..The software trigger activates the OUTMASK register synchronization.
   */
  #define FTM_SYNCONF_SWOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
  #define FTM_SYNCONF_SWINVC_MASK                  (0x800U)
  #define FTM_SYNCONF_SWINVC_SHIFT                 (11U)
  /*! SWINVC
   *  0b0..The software trigger does not activate the INVCTRL register synchronization.
   *  0b1..The software trigger activates the INVCTRL register synchronization.
   */
  #define FTM_SYNCONF_SWINVC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
  #define FTM_SYNCONF_SWSOC_MASK                   (0x1000U)
  #define FTM_SYNCONF_SWSOC_SHIFT                  (12U)
  /*! SWSOC
   *  0b0..The software trigger does not activate the SWOCTRL register synchronization.
   *  0b1..The software trigger activates the SWOCTRL register synchronization.
   */
  #define FTM_SYNCONF_SWSOC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
  #define FTM_SYNCONF_HWRSTCNT_MASK                (0x10000U)
  #define FTM_SYNCONF_HWRSTCNT_SHIFT               (16U)
  /*! HWRSTCNT
   *  0b0..A hardware trigger does not activate the FTM counter synchronization.
   *  0b1..A hardware trigger activates the FTM counter synchronization.
   */
  #define FTM_SYNCONF_HWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
  #define FTM_SYNCONF_HWWRBUF_MASK                 (0x20000U)
  #define FTM_SYNCONF_HWWRBUF_SHIFT                (17U)
  /*! HWWRBUF
   *  0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
   *  0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
   */
  #define FTM_SYNCONF_HWWRBUF(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
  #define FTM_SYNCONF_HWOM_MASK                    (0x40000U)
  #define FTM_SYNCONF_HWOM_SHIFT                   (18U)
  /*! HWOM
   *  0b0..A hardware trigger does not activate the OUTMASK register synchronization.
   *  0b1..A hardware trigger activates the OUTMASK register synchronization.
   */
  #define FTM_SYNCONF_HWOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
  #define FTM_SYNCONF_HWINVC_MASK                  (0x80000U)
  #define FTM_SYNCONF_HWINVC_SHIFT                 (19U)
  /*! HWINVC
   *  0b0..A hardware trigger does not activate the INVCTRL register synchronization.
   *  0b1..A hardware trigger activates the INVCTRL register synchronization.
   */
  #define FTM_SYNCONF_HWINVC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
  #define FTM_SYNCONF_HWSOC_MASK                   (0x100000U)
  #define FTM_SYNCONF_HWSOC_SHIFT                  (20U)
  /*! HWSOC
   *  0b0..A hardware trigger does not activate the SWOCTRL register synchronization.
   *  0b1..A hardware trigger activates the SWOCTRL register synchronization.
   */
  #define FTM_SYNCONF_HWSOC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
  /*! @} */
  
  /*! @name INVCTRL - FTM Inverting Control */
  /*! @{ */
  #define FTM_INVCTRL_INV0EN_MASK                  (0x1U)
  #define FTM_INVCTRL_INV0EN_SHIFT                 (0U)
  /*! INV0EN - Pair Channels 0 Inverting Enable
   *  0b0..Inverting is disabled.
   *  0b1..Inverting is enabled.
   */
  #define FTM_INVCTRL_INV0EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
  #define FTM_INVCTRL_INV1EN_MASK                  (0x2U)
  #define FTM_INVCTRL_INV1EN_SHIFT                 (1U)
  /*! INV1EN - Pair Channels 1 Inverting Enable
   *  0b0..Inverting is disabled.
   *  0b1..Inverting is enabled.
   */
  #define FTM_INVCTRL_INV1EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
  #define FTM_INVCTRL_INV2EN_MASK                  (0x4U)
  #define FTM_INVCTRL_INV2EN_SHIFT                 (2U)
  /*! INV2EN - Pair Channels 2 Inverting Enable
   *  0b0..Inverting is disabled.
   *  0b1..Inverting is enabled.
   */
  #define FTM_INVCTRL_INV2EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
  #define FTM_INVCTRL_INV3EN_MASK                  (0x8U)
  #define FTM_INVCTRL_INV3EN_SHIFT                 (3U)
  /*! INV3EN - Pair Channels 3 Inverting Enable
   *  0b0..Inverting is disabled.
   *  0b1..Inverting is enabled.
   */
  #define FTM_INVCTRL_INV3EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
  /*! @} */
  
  /*! @name SWOCTRL - FTM Software Output Control */
  /*! @{ */
  #define FTM_SWOCTRL_CH0OC_MASK                   (0x1U)
  #define FTM_SWOCTRL_CH0OC_SHIFT                  (0U)
  /*! CH0OC - Channel 0 Software Output Control Enable
   *  0b0..The channel output is not affected by software output control.
   *  0b1..The channel output is affected by software output control.
   */
  #define FTM_SWOCTRL_CH0OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
  #define FTM_SWOCTRL_CH1OC_MASK                   (0x2U)
  #define FTM_SWOCTRL_CH1OC_SHIFT                  (1U)
  /*! CH1OC - Channel 1 Software Output Control Enable
   *  0b0..The channel output is not affected by software output control.
   *  0b1..The channel output is affected by software output control.
   */
  #define FTM_SWOCTRL_CH1OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
  #define FTM_SWOCTRL_CH2OC_MASK                   (0x4U)
  #define FTM_SWOCTRL_CH2OC_SHIFT                  (2U)
  /*! CH2OC - Channel 2 Software Output Control Enable
   *  0b0..The channel output is not affected by software output control.
   *  0b1..The channel output is affected by software output control.
   */
  #define FTM_SWOCTRL_CH2OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
  #define FTM_SWOCTRL_CH3OC_MASK                   (0x8U)
  #define FTM_SWOCTRL_CH3OC_SHIFT                  (3U)
  /*! CH3OC - Channel 3 Software Output Control Enable
   *  0b0..The channel output is not affected by software output control.
   *  0b1..The channel output is affected by software output control.
   */
  #define FTM_SWOCTRL_CH3OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
  #define FTM_SWOCTRL_CH4OC_MASK                   (0x10U)
  #define FTM_SWOCTRL_CH4OC_SHIFT                  (4U)
  /*! CH4OC - Channel 4 Software Output Control Enable
   *  0b0..The channel output is not affected by software output control.
   *  0b1..The channel output is affected by software output control.
   */
  #define FTM_SWOCTRL_CH4OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
  #define FTM_SWOCTRL_CH5OC_MASK                   (0x20U)
  #define FTM_SWOCTRL_CH5OC_SHIFT                  (5U)
  /*! CH5OC - Channel 5 Software Output Control Enable
   *  0b0..The channel output is not affected by software output control.
   *  0b1..The channel output is affected by software output control.
   */
  #define FTM_SWOCTRL_CH5OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
  #define FTM_SWOCTRL_CH6OC_MASK                   (0x40U)
  #define FTM_SWOCTRL_CH6OC_SHIFT                  (6U)
  /*! CH6OC - Channel 6 Software Output Control Enable
   *  0b0..The channel output is not affected by software output control.
   *  0b1..The channel output is affected by software output control.
   */
  #define FTM_SWOCTRL_CH6OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
  #define FTM_SWOCTRL_CH7OC_MASK                   (0x80U)
  #define FTM_SWOCTRL_CH7OC_SHIFT                  (7U)
  /*! CH7OC - Channel 7 Software Output Control Enable
   *  0b0..The channel output is not affected by software output control.
   *  0b1..The channel output is affected by software output control.
   */
  #define FTM_SWOCTRL_CH7OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
  #define FTM_SWOCTRL_CH0OCV_MASK                  (0x100U)
  #define FTM_SWOCTRL_CH0OCV_SHIFT                 (8U)
  /*! CH0OCV - Channel 0 Software Output Control Value
   *  0b0..The software output control forces 0 to the channel output.
   *  0b1..The software output control forces 1 to the channel output.
   */
  #define FTM_SWOCTRL_CH0OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
  #define FTM_SWOCTRL_CH1OCV_MASK                  (0x200U)
  #define FTM_SWOCTRL_CH1OCV_SHIFT                 (9U)
  /*! CH1OCV - Channel 1 Software Output Control Value
   *  0b0..The software output control forces 0 to the channel output.
   *  0b1..The software output control forces 1 to the channel output.
   */
  #define FTM_SWOCTRL_CH1OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
  #define FTM_SWOCTRL_CH2OCV_MASK                  (0x400U)
  #define FTM_SWOCTRL_CH2OCV_SHIFT                 (10U)
  /*! CH2OCV - Channel 2 Software Output Control Value
   *  0b0..The software output control forces 0 to the channel output.
   *  0b1..The software output control forces 1 to the channel output.
   */
  #define FTM_SWOCTRL_CH2OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
  #define FTM_SWOCTRL_CH3OCV_MASK                  (0x800U)
  #define FTM_SWOCTRL_CH3OCV_SHIFT                 (11U)
  /*! CH3OCV - Channel 3 Software Output Control Value
   *  0b0..The software output control forces 0 to the channel output.
   *  0b1..The software output control forces 1 to the channel output.
   */
  #define FTM_SWOCTRL_CH3OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
  #define FTM_SWOCTRL_CH4OCV_MASK                  (0x1000U)
  #define FTM_SWOCTRL_CH4OCV_SHIFT                 (12U)
  /*! CH4OCV - Channel 4 Software Output Control Value
   *  0b0..The software output control forces 0 to the channel output.
   *  0b1..The software output control forces 1 to the channel output.
   */
  #define FTM_SWOCTRL_CH4OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
  #define FTM_SWOCTRL_CH5OCV_MASK                  (0x2000U)
  #define FTM_SWOCTRL_CH5OCV_SHIFT                 (13U)
  /*! CH5OCV - Channel 5 Software Output Control Value
   *  0b0..The software output control forces 0 to the channel output.
   *  0b1..The software output control forces 1 to the channel output.
   */
  #define FTM_SWOCTRL_CH5OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
  #define FTM_SWOCTRL_CH6OCV_MASK                  (0x4000U)
  #define FTM_SWOCTRL_CH6OCV_SHIFT                 (14U)
  /*! CH6OCV - Channel 6 Software Output Control Value
   *  0b0..The software output control forces 0 to the channel output.
   *  0b1..The software output control forces 1 to the channel output.
   */
  #define FTM_SWOCTRL_CH6OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
  #define FTM_SWOCTRL_CH7OCV_MASK                  (0x8000U)
  #define FTM_SWOCTRL_CH7OCV_SHIFT                 (15U)
  /*! CH7OCV - Channel 7 Software Output Control Value
   *  0b0..The software output control forces 0 to the channel output.
   *  0b1..The software output control forces 1 to the channel output.
   */
  #define FTM_SWOCTRL_CH7OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
  /*! @} */
  
  /*! @name PWMLOAD - FTM PWM Load */
  /*! @{ */
  #define FTM_PWMLOAD_CH0SEL_MASK                  (0x1U)
  #define FTM_PWMLOAD_CH0SEL_SHIFT                 (0U)
  /*! CH0SEL - Channel 0 Select
   *  0b0..Do not include the channel in the matching process.
   *  0b1..Include the channel in the matching process.
   */
  #define FTM_PWMLOAD_CH0SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
  #define FTM_PWMLOAD_CH1SEL_MASK                  (0x2U)
  #define FTM_PWMLOAD_CH1SEL_SHIFT                 (1U)
  /*! CH1SEL - Channel 1 Select
   *  0b0..Do not include the channel in the matching process.
   *  0b1..Include the channel in the matching process.
   */
  #define FTM_PWMLOAD_CH1SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
  #define FTM_PWMLOAD_CH2SEL_MASK                  (0x4U)
  #define FTM_PWMLOAD_CH2SEL_SHIFT                 (2U)
  /*! CH2SEL - Channel 2 Select
   *  0b0..Do not include the channel in the matching process.
   *  0b1..Include the channel in the matching process.
   */
  #define FTM_PWMLOAD_CH2SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
  #define FTM_PWMLOAD_CH3SEL_MASK                  (0x8U)
  #define FTM_PWMLOAD_CH3SEL_SHIFT                 (3U)
  /*! CH3SEL - Channel 3 Select
   *  0b0..Do not include the channel in the matching process.
   *  0b1..Include the channel in the matching process.
   */
  #define FTM_PWMLOAD_CH3SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
  #define FTM_PWMLOAD_CH4SEL_MASK                  (0x10U)
  #define FTM_PWMLOAD_CH4SEL_SHIFT                 (4U)
  /*! CH4SEL - Channel 4 Select
   *  0b0..Do not include the channel in the matching process.
   *  0b1..Include the channel in the matching process.
   */
  #define FTM_PWMLOAD_CH4SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
  #define FTM_PWMLOAD_CH5SEL_MASK                  (0x20U)
  #define FTM_PWMLOAD_CH5SEL_SHIFT                 (5U)
  /*! CH5SEL - Channel 5 Select
   *  0b0..Do not include the channel in the matching process.
   *  0b1..Include the channel in the matching process.
   */
  #define FTM_PWMLOAD_CH5SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
  #define FTM_PWMLOAD_CH6SEL_MASK                  (0x40U)
  #define FTM_PWMLOAD_CH6SEL_SHIFT                 (6U)
  /*! CH6SEL - Channel 6 Select
   *  0b0..Do not include the channel in the matching process.
   *  0b1..Include the channel in the matching process.
   */
  #define FTM_PWMLOAD_CH6SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
  #define FTM_PWMLOAD_CH7SEL_MASK                  (0x80U)
  #define FTM_PWMLOAD_CH7SEL_SHIFT                 (7U)
  /*! CH7SEL - Channel 7 Select
   *  0b0..Do not include the channel in the matching process.
   *  0b1..Include the channel in the matching process.
   */
  #define FTM_PWMLOAD_CH7SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
  #define FTM_PWMLOAD_LDOK_MASK                    (0x200U)
  #define FTM_PWMLOAD_LDOK_SHIFT                   (9U)
  /*! LDOK - Load Enable
   *  0b0..Loading updated values is disabled.
   *  0b1..Loading updated values is enabled.
   */
  #define FTM_PWMLOAD_LDOK(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group FTM_Register_Masks */
  
  
  /* FTM - Peripheral instance base addresses */
  /** Peripheral FTM0 base address */
  #define FTM0_BASE                                (0x40038000u)
  /** Peripheral FTM0 base pointer */
  #define FTM0                                     ((FTM_Type *)FTM0_BASE)
  /** Peripheral FTM1 base address */
  #define FTM1_BASE                                (0x40039000u)
  /** Peripheral FTM1 base pointer */
  #define FTM1                                     ((FTM_Type *)FTM1_BASE)
  /** Peripheral FTM2 base address */
  #define FTM2_BASE                                (0x4003A000u)
  /** Peripheral FTM2 base pointer */
  #define FTM2                                     ((FTM_Type *)FTM2_BASE)
  /** Array initializer of FTM peripheral base addresses */
  #define FTM_BASE_ADDRS                           { FTM0_BASE, FTM1_BASE, FTM2_BASE }
  /** Array initializer of FTM peripheral base pointers */
  #define FTM_BASE_PTRS                            { FTM0, FTM1, FTM2 }
  /** Interrupt vectors for the FTM peripheral type */
  #define FTM_IRQS                                 { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn }
  
  /*!
   * @}
   */ /* end of group FTM_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- GPIO Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
   * @{
   */
  
  /** GPIO - Register Layout Typedef */
  typedef struct {
    __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
    __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
    __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
    __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
    __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
    __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
  } GPIO_Type;
  
  /* ----------------------------------------------------------------------------
     -- GPIO Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup GPIO_Register_Masks GPIO Register Masks
   * @{
   */
  
  /*! @name PDOR - Port Data Output Register */
  /*! @{ */
  #define GPIO_PDOR_PDO_MASK                       (0xFFFFFFFFU)
  #define GPIO_PDOR_PDO_SHIFT                      (0U)
  /*! PDO - Port Data Output
   *  0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
   *  0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
   */
  #define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
  /*! @} */
  
  /*! @name PSOR - Port Set Output Register */
  /*! @{ */
  #define GPIO_PSOR_PTSO_MASK                      (0xFFFFFFFFU)
  #define GPIO_PSOR_PTSO_SHIFT                     (0U)
  /*! PTSO - Port Set Output
   *  0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
   *  0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1.
   */
  #define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
  /*! @} */
  
  /*! @name PCOR - Port Clear Output Register */
  /*! @{ */
  #define GPIO_PCOR_PTCO_MASK                      (0xFFFFFFFFU)
  #define GPIO_PCOR_PTCO_SHIFT                     (0U)
  /*! PTCO - Port Clear Output
   *  0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
   *  0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0.
   */
  #define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
  /*! @} */
  
  /*! @name PTOR - Port Toggle Output Register */
  /*! @{ */
  #define GPIO_PTOR_PTTO_MASK                      (0xFFFFFFFFU)
  #define GPIO_PTOR_PTTO_SHIFT                     (0U)
  /*! PTTO - Port Toggle Output
   *  0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
   *  0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state.
   */
  #define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
  /*! @} */
  
  /*! @name PDIR - Port Data Input Register */
  /*! @{ */
  #define GPIO_PDIR_PDI_MASK                       (0xFFFFFFFFU)
  #define GPIO_PDIR_PDI_SHIFT                      (0U)
  /*! PDI - Port Data Input
   *  0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function.
   *  0b00000000000000000000000000000001..Pin logic level is logic 1.
   */
  #define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
  /*! @} */
  
  /*! @name PDDR - Port Data Direction Register */
  /*! @{ */
  #define GPIO_PDDR_PDD_MASK                       (0xFFFFFFFFU)
  #define GPIO_PDDR_PDD_SHIFT                      (0U)
  /*! PDD - Port Data Direction
   *  0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function.
   *  0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function.
   */
  #define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group GPIO_Register_Masks */
  
  
  /* GPIO - Peripheral instance base addresses */
  /** Peripheral GPIOA base address */
  #define GPIOA_BASE                               (0x400FF000u)
  /** Peripheral GPIOA base pointer */
  #define GPIOA                                    ((GPIO_Type *)GPIOA_BASE)
  /** Peripheral GPIOB base address */
  #define GPIOB_BASE                               (0x400FF040u)
  /** Peripheral GPIOB base pointer */
  #define GPIOB                                    ((GPIO_Type *)GPIOB_BASE)
  /** Peripheral GPIOC base address */
  #define GPIOC_BASE                               (0x400FF080u)
  /** Peripheral GPIOC base pointer */
  #define GPIOC                                    ((GPIO_Type *)GPIOC_BASE)
  /** Peripheral GPIOD base address */
  #define GPIOD_BASE                               (0x400FF0C0u)
  /** Peripheral GPIOD base pointer */
  #define GPIOD                                    ((GPIO_Type *)GPIOD_BASE)
  /** Peripheral GPIOE base address */
  #define GPIOE_BASE                               (0x400FF100u)
  /** Peripheral GPIOE base pointer */
  #define GPIOE                                    ((GPIO_Type *)GPIOE_BASE)
  /** Array initializer of GPIO peripheral base addresses */
  #define GPIO_BASE_ADDRS                          { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
  /** Array initializer of GPIO peripheral base pointers */
  #define GPIO_BASE_PTRS                           { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
  
  /*!
   * @}
   */ /* end of group GPIO_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- I2C Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
   * @{
   */
  
  /** I2C - Register Layout Typedef */
  typedef struct {
    __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
    __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
    __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
    __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
    __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
    __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
    __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
    __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
    __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
    __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
    __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
    __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
  } I2C_Type;
  
  /* ----------------------------------------------------------------------------
     -- I2C Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup I2C_Register_Masks I2C Register Masks
   * @{
   */
  
  /*! @name A1 - I2C Address Register 1 */
  /*! @{ */
  #define I2C_A1_AD_MASK                           (0xFEU)
  #define I2C_A1_AD_SHIFT                          (1U)
  #define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
  /*! @} */
  
  /*! @name F - I2C Frequency Divider register */
  /*! @{ */
  #define I2C_F_ICR_MASK                           (0x3FU)
  #define I2C_F_ICR_SHIFT                          (0U)
  #define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
  #define I2C_F_MULT_MASK                          (0xC0U)
  #define I2C_F_MULT_SHIFT                         (6U)
  /*! MULT - Multiplier Factor
   *  0b00..mul = 1
   *  0b01..mul = 2
   *  0b10..mul = 4
   *  0b11..Reserved
   */
  #define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
  /*! @} */
  
  /*! @name C1 - I2C Control Register 1 */
  /*! @{ */
  #define I2C_C1_DMAEN_MASK                        (0x1U)
  #define I2C_C1_DMAEN_SHIFT                       (0U)
  /*! DMAEN - DMA Enable
   *  0b0..All DMA signalling disabled.
   *  0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
   */
  #define I2C_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
  #define I2C_C1_WUEN_MASK                         (0x2U)
  #define I2C_C1_WUEN_SHIFT                        (1U)
  /*! WUEN - Wakeup Enable
   *  0b0..Normal operation. No interrupt generated when address matching in low power mode.
   *  0b1..Enables the wakeup function in low power mode.
   */
  #define I2C_C1_WUEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
  #define I2C_C1_RSTA_MASK                         (0x4U)
  #define I2C_C1_RSTA_SHIFT                        (2U)
  #define I2C_C1_RSTA(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
  #define I2C_C1_TXAK_MASK                         (0x8U)
  #define I2C_C1_TXAK_SHIFT                        (3U)
  /*! TXAK - Transmit Acknowledge Enable
   *  0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
   *  0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
   */
  #define I2C_C1_TXAK(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
  #define I2C_C1_TX_MASK                           (0x10U)
  #define I2C_C1_TX_SHIFT                          (4U)
  /*! TX - Transmit Mode Select
   *  0b0..Receive
   *  0b1..Transmit
   */
  #define I2C_C1_TX(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
  #define I2C_C1_MST_MASK                          (0x20U)
  #define I2C_C1_MST_SHIFT                         (5U)
  /*! MST - Master Mode Select
   *  0b0..Slave mode
   *  0b1..Master mode
   */
  #define I2C_C1_MST(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
  #define I2C_C1_IICIE_MASK                        (0x40U)
  #define I2C_C1_IICIE_SHIFT                       (6U)
  /*! IICIE - I2C Interrupt Enable
   *  0b0..Disabled
   *  0b1..Enabled
   */
  #define I2C_C1_IICIE(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
  #define I2C_C1_IICEN_MASK                        (0x80U)
  #define I2C_C1_IICEN_SHIFT                       (7U)
  /*! IICEN - I2C Enable
   *  0b0..Disabled
   *  0b1..Enabled
   */
  #define I2C_C1_IICEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
  /*! @} */
  
  /*! @name S - I2C Status register */
  /*! @{ */
  #define I2C_S_RXAK_MASK                          (0x1U)
  #define I2C_S_RXAK_SHIFT                         (0U)
  /*! RXAK - Receive Acknowledge
   *  0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus
   *  0b1..No acknowledge signal detected
   */
  #define I2C_S_RXAK(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
  #define I2C_S_IICIF_MASK                         (0x2U)
  #define I2C_S_IICIF_SHIFT                        (1U)
  /*! IICIF - Interrupt Flag
   *  0b0..No interrupt pending
   *  0b1..Interrupt pending
   */
  #define I2C_S_IICIF(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
  #define I2C_S_SRW_MASK                           (0x4U)
  #define I2C_S_SRW_SHIFT                          (2U)
  /*! SRW - Slave Read/Write
   *  0b0..Slave receive, master writing to slave
   *  0b1..Slave transmit, master reading from slave
   */
  #define I2C_S_SRW(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
  #define I2C_S_RAM_MASK                           (0x8U)
  #define I2C_S_RAM_SHIFT                          (3U)
  /*! RAM - Range Address Match
   *  0b0..Not addressed
   *  0b1..Addressed as a slave
   */
  #define I2C_S_RAM(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
  #define I2C_S_ARBL_MASK                          (0x10U)
  #define I2C_S_ARBL_SHIFT                         (4U)
  /*! ARBL - Arbitration Lost
   *  0b0..Standard bus operation.
   *  0b1..Loss of arbitration.
   */
  #define I2C_S_ARBL(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
  #define I2C_S_BUSY_MASK                          (0x20U)
  #define I2C_S_BUSY_SHIFT                         (5U)
  /*! BUSY - Bus Busy
   *  0b0..Bus is idle
   *  0b1..Bus is busy
   */
  #define I2C_S_BUSY(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
  #define I2C_S_IAAS_MASK                          (0x40U)
  #define I2C_S_IAAS_SHIFT                         (6U)
  /*! IAAS - Addressed As A Slave
   *  0b0..Not addressed
   *  0b1..Addressed as a slave
   */
  #define I2C_S_IAAS(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
  #define I2C_S_TCF_MASK                           (0x80U)
  #define I2C_S_TCF_SHIFT                          (7U)
  /*! TCF - Transfer Complete Flag
   *  0b0..Transfer in progress
   *  0b1..Transfer complete
   */
  #define I2C_S_TCF(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
  /*! @} */
  
  /*! @name D - I2C Data I/O register */
  /*! @{ */
  #define I2C_D_DATA_MASK                          (0xFFU)
  #define I2C_D_DATA_SHIFT                         (0U)
  #define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
  /*! @} */
  
  /*! @name C2 - I2C Control Register 2 */
  /*! @{ */
  #define I2C_C2_AD_MASK                           (0x7U)
  #define I2C_C2_AD_SHIFT                          (0U)
  #define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
  #define I2C_C2_RMEN_MASK                         (0x8U)
  #define I2C_C2_RMEN_SHIFT                        (3U)
  /*! RMEN - Range Address Matching Enable
   *  0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
   *  0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
   */
  #define I2C_C2_RMEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
  #define I2C_C2_SBRC_MASK                         (0x10U)
  #define I2C_C2_SBRC_SHIFT                        (4U)
  /*! SBRC - Slave Baud Rate Control
   *  0b0..The slave baud rate follows the master baud rate and clock stretching may occur
   *  0b1..Slave baud rate is independent of the master baud rate
   */
  #define I2C_C2_SBRC(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
  #define I2C_C2_HDRS_MASK                         (0x20U)
  #define I2C_C2_HDRS_SHIFT                        (5U)
  /*! HDRS - High Drive Select
   *  0b0..Normal drive mode
   *  0b1..High drive mode
   */
  #define I2C_C2_HDRS(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
  #define I2C_C2_ADEXT_MASK                        (0x40U)
  #define I2C_C2_ADEXT_SHIFT                       (6U)
  /*! ADEXT - Address Extension
   *  0b0..7-bit address scheme
   *  0b1..10-bit address scheme
   */
  #define I2C_C2_ADEXT(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
  #define I2C_C2_GCAEN_MASK                        (0x80U)
  #define I2C_C2_GCAEN_SHIFT                       (7U)
  /*! GCAEN - General Call Address Enable
   *  0b0..Disabled
   *  0b1..Enabled
   */
  #define I2C_C2_GCAEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
  /*! @} */
  
  /*! @name FLT - I2C Programmable Input Glitch Filter register */
  /*! @{ */
  #define I2C_FLT_FLT_MASK                         (0xFU)
  #define I2C_FLT_FLT_SHIFT                        (0U)
  /*! FLT - I2C Programmable Filter Factor
   *  0b0000..No filter/bypass
   */
  #define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
  #define I2C_FLT_STARTF_MASK                      (0x10U)
  #define I2C_FLT_STARTF_SHIFT                     (4U)
  /*! STARTF - I2C Bus Start Detect Flag
   *  0b0..No start happens on I2C bus
   *  0b1..Start detected on I2C bus
   */
  #define I2C_FLT_STARTF(x)                        (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
  #define I2C_FLT_SSIE_MASK                        (0x20U)
  #define I2C_FLT_SSIE_SHIFT                       (5U)
  /*! SSIE - I2C Bus Stop or Start Interrupt Enable
   *  0b0..Stop or start detection interrupt is disabled
   *  0b1..Stop or start detection interrupt is enabled
   */
  #define I2C_FLT_SSIE(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
  #define I2C_FLT_STOPF_MASK                       (0x40U)
  #define I2C_FLT_STOPF_SHIFT                      (6U)
  /*! STOPF - I2C Bus Stop Detect Flag
   *  0b0..No stop happens on I2C bus
   *  0b1..Stop detected on I2C bus
   */
  #define I2C_FLT_STOPF(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
  #define I2C_FLT_SHEN_MASK                        (0x80U)
  #define I2C_FLT_SHEN_SHIFT                       (7U)
  /*! SHEN - Stop Hold Enable
   *  0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
   *  0b1..Stop holdoff is enabled.
   */
  #define I2C_FLT_SHEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
  /*! @} */
  
  /*! @name RA - I2C Range Address register */
  /*! @{ */
  #define I2C_RA_RAD_MASK                          (0xFEU)
  #define I2C_RA_RAD_SHIFT                         (1U)
  #define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
  /*! @} */
  
  /*! @name SMB - I2C SMBus Control and Status register */
  /*! @{ */
  #define I2C_SMB_SHTF2IE_MASK                     (0x1U)
  #define I2C_SMB_SHTF2IE_SHIFT                    (0U)
  /*! SHTF2IE - SHTF2 Interrupt Enable
   *  0b0..SHTF2 interrupt is disabled
   *  0b1..SHTF2 interrupt is enabled
   */
  #define I2C_SMB_SHTF2IE(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
  #define I2C_SMB_SHTF2_MASK                       (0x2U)
  #define I2C_SMB_SHTF2_SHIFT                      (1U)
  /*! SHTF2 - SCL High Timeout Flag 2
   *  0b0..No SCL high and SDA low timeout occurs
   *  0b1..SCL high and SDA low timeout occurs
   */
  #define I2C_SMB_SHTF2(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
  #define I2C_SMB_SHTF1_MASK                       (0x4U)
  #define I2C_SMB_SHTF1_SHIFT                      (2U)
  /*! SHTF1 - SCL High Timeout Flag 1
   *  0b0..No SCL high and SDA high timeout occurs
   *  0b1..SCL high and SDA high timeout occurs
   */
  #define I2C_SMB_SHTF1(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
  #define I2C_SMB_SLTF_MASK                        (0x8U)
  #define I2C_SMB_SLTF_SHIFT                       (3U)
  /*! SLTF - SCL Low Timeout Flag
   *  0b0..No low timeout occurs
   *  0b1..Low timeout occurs
   */
  #define I2C_SMB_SLTF(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
  #define I2C_SMB_TCKSEL_MASK                      (0x10U)
  #define I2C_SMB_TCKSEL_SHIFT                     (4U)
  /*! TCKSEL - Timeout Counter Clock Select
   *  0b0..Timeout counter counts at the frequency of the I2C module clock / 64
   *  0b1..Timeout counter counts at the frequency of the I2C module clock
   */
  #define I2C_SMB_TCKSEL(x)                        (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
  #define I2C_SMB_SIICAEN_MASK                     (0x20U)
  #define I2C_SMB_SIICAEN_SHIFT                    (5U)
  /*! SIICAEN - Second I2C Address Enable
   *  0b0..I2C address register 2 matching is disabled
   *  0b1..I2C address register 2 matching is enabled
   */
  #define I2C_SMB_SIICAEN(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
  #define I2C_SMB_ALERTEN_MASK                     (0x40U)
  #define I2C_SMB_ALERTEN_SHIFT                    (6U)
  /*! ALERTEN - SMBus Alert Response Address Enable
   *  0b0..SMBus alert response address matching is disabled
   *  0b1..SMBus alert response address matching is enabled
   */
  #define I2C_SMB_ALERTEN(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
  #define I2C_SMB_FACK_MASK                        (0x80U)
  #define I2C_SMB_FACK_SHIFT                       (7U)
  /*! FACK - Fast NACK/ACK Enable
   *  0b0..An ACK or NACK is sent on the following receiving data byte
   *  0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
   */
  #define I2C_SMB_FACK(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
  /*! @} */
  
  /*! @name A2 - I2C Address Register 2 */
  /*! @{ */
  #define I2C_A2_SAD_MASK                          (0xFEU)
  #define I2C_A2_SAD_SHIFT                         (1U)
  #define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
  /*! @} */
  
  /*! @name SLTH - I2C SCL Low Timeout Register High */
  /*! @{ */
  #define I2C_SLTH_SSLT_MASK                       (0xFFU)
  #define I2C_SLTH_SSLT_SHIFT                      (0U)
  #define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
  /*! @} */
  
  /*! @name SLTL - I2C SCL Low Timeout Register Low */
  /*! @{ */
  #define I2C_SLTL_SSLT_MASK                       (0xFFU)
  #define I2C_SLTL_SSLT_SHIFT                      (0U)
  #define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group I2C_Register_Masks */
  
  
  /* I2C - Peripheral instance base addresses */
  /** Peripheral I2C0 base address */
  #define I2C0_BASE                                (0x40066000u)
  /** Peripheral I2C0 base pointer */
  #define I2C0                                     ((I2C_Type *)I2C0_BASE)
  /** Peripheral I2C1 base address */
  #define I2C1_BASE                                (0x40067000u)
  /** Peripheral I2C1 base pointer */
  #define I2C1                                     ((I2C_Type *)I2C1_BASE)
  /** Array initializer of I2C peripheral base addresses */
  #define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE }
  /** Array initializer of I2C peripheral base pointers */
  #define I2C_BASE_PTRS                            { I2C0, I2C1 }
  /** Interrupt vectors for the I2C peripheral type */
  #define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn }
  
  /*!
   * @}
   */ /* end of group I2C_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- LLWU Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
   * @{
   */
  
  /** LLWU - Register Layout Typedef */
  typedef struct {
    __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
    __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
    __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
    __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
    __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x4 */
    __IO uint8_t F1;                                 /**< LLWU Flag 1 register, offset: 0x5 */
    __IO uint8_t F2;                                 /**< LLWU Flag 2 register, offset: 0x6 */
    __I  uint8_t F3;                                 /**< LLWU Flag 3 register, offset: 0x7 */
    __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x8 */
    __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x9 */
  } LLWU_Type;
  
  /* ----------------------------------------------------------------------------
     -- LLWU Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LLWU_Register_Masks LLWU Register Masks
   * @{
   */
  
  /*! @name PE1 - LLWU Pin Enable 1 register */
  /*! @{ */
  #define LLWU_PE1_WUPE0_MASK                      (0x3U)
  #define LLWU_PE1_WUPE0_SHIFT                     (0U)
  /*! WUPE0 - Wakeup Pin Enable For LLWU_P0
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
  #define LLWU_PE1_WUPE1_MASK                      (0xCU)
  #define LLWU_PE1_WUPE1_SHIFT                     (2U)
  /*! WUPE1 - Wakeup Pin Enable For LLWU_P1
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
  #define LLWU_PE1_WUPE2_MASK                      (0x30U)
  #define LLWU_PE1_WUPE2_SHIFT                     (4U)
  /*! WUPE2 - Wakeup Pin Enable For LLWU_P2
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
  #define LLWU_PE1_WUPE3_MASK                      (0xC0U)
  #define LLWU_PE1_WUPE3_SHIFT                     (6U)
  /*! WUPE3 - Wakeup Pin Enable For LLWU_P3
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
  /*! @} */
  
  /*! @name PE2 - LLWU Pin Enable 2 register */
  /*! @{ */
  #define LLWU_PE2_WUPE4_MASK                      (0x3U)
  #define LLWU_PE2_WUPE4_SHIFT                     (0U)
  /*! WUPE4 - Wakeup Pin Enable For LLWU_P4
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
  #define LLWU_PE2_WUPE5_MASK                      (0xCU)
  #define LLWU_PE2_WUPE5_SHIFT                     (2U)
  /*! WUPE5 - Wakeup Pin Enable For LLWU_P5
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
  #define LLWU_PE2_WUPE6_MASK                      (0x30U)
  #define LLWU_PE2_WUPE6_SHIFT                     (4U)
  /*! WUPE6 - Wakeup Pin Enable For LLWU_P6
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
  #define LLWU_PE2_WUPE7_MASK                      (0xC0U)
  #define LLWU_PE2_WUPE7_SHIFT                     (6U)
  /*! WUPE7 - Wakeup Pin Enable For LLWU_P7
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
  /*! @} */
  
  /*! @name PE3 - LLWU Pin Enable 3 register */
  /*! @{ */
  #define LLWU_PE3_WUPE8_MASK                      (0x3U)
  #define LLWU_PE3_WUPE8_SHIFT                     (0U)
  /*! WUPE8 - Wakeup Pin Enable For LLWU_P8
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
  #define LLWU_PE3_WUPE9_MASK                      (0xCU)
  #define LLWU_PE3_WUPE9_SHIFT                     (2U)
  /*! WUPE9 - Wakeup Pin Enable For LLWU_P9
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
  #define LLWU_PE3_WUPE10_MASK                     (0x30U)
  #define LLWU_PE3_WUPE10_SHIFT                    (4U)
  /*! WUPE10 - Wakeup Pin Enable For LLWU_P10
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
  #define LLWU_PE3_WUPE11_MASK                     (0xC0U)
  #define LLWU_PE3_WUPE11_SHIFT                    (6U)
  /*! WUPE11 - Wakeup Pin Enable For LLWU_P11
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
  /*! @} */
  
  /*! @name PE4 - LLWU Pin Enable 4 register */
  /*! @{ */
  #define LLWU_PE4_WUPE12_MASK                     (0x3U)
  #define LLWU_PE4_WUPE12_SHIFT                    (0U)
  /*! WUPE12 - Wakeup Pin Enable For LLWU_P12
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
  #define LLWU_PE4_WUPE13_MASK                     (0xCU)
  #define LLWU_PE4_WUPE13_SHIFT                    (2U)
  /*! WUPE13 - Wakeup Pin Enable For LLWU_P13
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
  #define LLWU_PE4_WUPE14_MASK                     (0x30U)
  #define LLWU_PE4_WUPE14_SHIFT                    (4U)
  /*! WUPE14 - Wakeup Pin Enable For LLWU_P14
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
  #define LLWU_PE4_WUPE15_MASK                     (0xC0U)
  #define LLWU_PE4_WUPE15_SHIFT                    (6U)
  /*! WUPE15 - Wakeup Pin Enable For LLWU_P15
   *  0b00..External input pin disabled as wakeup input
   *  0b01..External input pin enabled with rising edge detection
   *  0b10..External input pin enabled with falling edge detection
   *  0b11..External input pin enabled with any change detection
   */
  #define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
  /*! @} */
  
  /*! @name ME - LLWU Module Enable register */
  /*! @{ */
  #define LLWU_ME_WUME0_MASK                       (0x1U)
  #define LLWU_ME_WUME0_SHIFT                      (0U)
  /*! WUME0 - Wakeup Module Enable For Module 0
   *  0b0..Internal module flag not used as wakeup source
   *  0b1..Internal module flag used as wakeup source
   */
  #define LLWU_ME_WUME0(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
  #define LLWU_ME_WUME1_MASK                       (0x2U)
  #define LLWU_ME_WUME1_SHIFT                      (1U)
  /*! WUME1 - Wakeup Module Enable for Module 1
   *  0b0..Internal module flag not used as wakeup source
   *  0b1..Internal module flag used as wakeup source
   */
  #define LLWU_ME_WUME1(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
  #define LLWU_ME_WUME2_MASK                       (0x4U)
  #define LLWU_ME_WUME2_SHIFT                      (2U)
  /*! WUME2 - Wakeup Module Enable For Module 2
   *  0b0..Internal module flag not used as wakeup source
   *  0b1..Internal module flag used as wakeup source
   */
  #define LLWU_ME_WUME2(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
  #define LLWU_ME_WUME3_MASK                       (0x8U)
  #define LLWU_ME_WUME3_SHIFT                      (3U)
  /*! WUME3 - Wakeup Module Enable For Module 3
   *  0b0..Internal module flag not used as wakeup source
   *  0b1..Internal module flag used as wakeup source
   */
  #define LLWU_ME_WUME3(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
  #define LLWU_ME_WUME4_MASK                       (0x10U)
  #define LLWU_ME_WUME4_SHIFT                      (4U)
  /*! WUME4 - Wakeup Module Enable For Module 4
   *  0b0..Internal module flag not used as wakeup source
   *  0b1..Internal module flag used as wakeup source
   */
  #define LLWU_ME_WUME4(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
  #define LLWU_ME_WUME5_MASK                       (0x20U)
  #define LLWU_ME_WUME5_SHIFT                      (5U)
  /*! WUME5 - Wakeup Module Enable For Module 5
   *  0b0..Internal module flag not used as wakeup source
   *  0b1..Internal module flag used as wakeup source
   */
  #define LLWU_ME_WUME5(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
  #define LLWU_ME_WUME6_MASK                       (0x40U)
  #define LLWU_ME_WUME6_SHIFT                      (6U)
  /*! WUME6 - Wakeup Module Enable For Module 6
   *  0b0..Internal module flag not used as wakeup source
   *  0b1..Internal module flag used as wakeup source
   */
  #define LLWU_ME_WUME6(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
  #define LLWU_ME_WUME7_MASK                       (0x80U)
  #define LLWU_ME_WUME7_SHIFT                      (7U)
  /*! WUME7 - Wakeup Module Enable For Module 7
   *  0b0..Internal module flag not used as wakeup source
   *  0b1..Internal module flag used as wakeup source
   */
  #define LLWU_ME_WUME7(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
  /*! @} */
  
  /*! @name F1 - LLWU Flag 1 register */
  /*! @{ */
  #define LLWU_F1_WUF0_MASK                        (0x1U)
  #define LLWU_F1_WUF0_SHIFT                       (0U)
  /*! WUF0 - Wakeup Flag For LLWU_P0
   *  0b0..LLWU_P0 input was not a wakeup source
   *  0b1..LLWU_P0 input was a wakeup source
   */
  #define LLWU_F1_WUF0(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
  #define LLWU_F1_WUF1_MASK                        (0x2U)
  #define LLWU_F1_WUF1_SHIFT                       (1U)
  /*! WUF1 - Wakeup Flag For LLWU_P1
   *  0b0..LLWU_P1 input was not a wakeup source
   *  0b1..LLWU_P1 input was a wakeup source
   */
  #define LLWU_F1_WUF1(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
  #define LLWU_F1_WUF2_MASK                        (0x4U)
  #define LLWU_F1_WUF2_SHIFT                       (2U)
  /*! WUF2 - Wakeup Flag For LLWU_P2
   *  0b0..LLWU_P2 input was not a wakeup source
   *  0b1..LLWU_P2 input was a wakeup source
   */
  #define LLWU_F1_WUF2(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
  #define LLWU_F1_WUF3_MASK                        (0x8U)
  #define LLWU_F1_WUF3_SHIFT                       (3U)
  /*! WUF3 - Wakeup Flag For LLWU_P3
   *  0b0..LLWU_P3 input was not a wake-up source
   *  0b1..LLWU_P3 input was a wake-up source
   */
  #define LLWU_F1_WUF3(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
  #define LLWU_F1_WUF4_MASK                        (0x10U)
  #define LLWU_F1_WUF4_SHIFT                       (4U)
  /*! WUF4 - Wakeup Flag For LLWU_P4
   *  0b0..LLWU_P4 input was not a wakeup source
   *  0b1..LLWU_P4 input was a wakeup source
   */
  #define LLWU_F1_WUF4(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
  #define LLWU_F1_WUF5_MASK                        (0x20U)
  #define LLWU_F1_WUF5_SHIFT                       (5U)
  /*! WUF5 - Wakeup Flag For LLWU_P5
   *  0b0..LLWU_P5 input was not a wakeup source
   *  0b1..LLWU_P5 input was a wakeup source
   */
  #define LLWU_F1_WUF5(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
  #define LLWU_F1_WUF6_MASK                        (0x40U)
  #define LLWU_F1_WUF6_SHIFT                       (6U)
  /*! WUF6 - Wakeup Flag For LLWU_P6
   *  0b0..LLWU_P6 input was not a wakeup source
   *  0b1..LLWU_P6 input was a wakeup source
   */
  #define LLWU_F1_WUF6(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
  #define LLWU_F1_WUF7_MASK                        (0x80U)
  #define LLWU_F1_WUF7_SHIFT                       (7U)
  /*! WUF7 - Wakeup Flag For LLWU_P7
   *  0b0..LLWU_P7 input was not a wakeup source
   *  0b1..LLWU_P7 input was a wakeup source
   */
  #define LLWU_F1_WUF7(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
  /*! @} */
  
  /*! @name F2 - LLWU Flag 2 register */
  /*! @{ */
  #define LLWU_F2_WUF8_MASK                        (0x1U)
  #define LLWU_F2_WUF8_SHIFT                       (0U)
  /*! WUF8 - Wakeup Flag For LLWU_P8
   *  0b0..LLWU_P8 input was not a wakeup source
   *  0b1..LLWU_P8 input was a wakeup source
   */
  #define LLWU_F2_WUF8(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
  #define LLWU_F2_WUF9_MASK                        (0x2U)
  #define LLWU_F2_WUF9_SHIFT                       (1U)
  /*! WUF9 - Wakeup Flag For LLWU_P9
   *  0b0..LLWU_P9 input was not a wakeup source
   *  0b1..LLWU_P9 input was a wakeup source
   */
  #define LLWU_F2_WUF9(x)                          (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
  #define LLWU_F2_WUF10_MASK                       (0x4U)
  #define LLWU_F2_WUF10_SHIFT                      (2U)
  /*! WUF10 - Wakeup Flag For LLWU_P10
   *  0b0..LLWU_P10 input was not a wakeup source
   *  0b1..LLWU_P10 input was a wakeup source
   */
  #define LLWU_F2_WUF10(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
  #define LLWU_F2_WUF11_MASK                       (0x8U)
  #define LLWU_F2_WUF11_SHIFT                      (3U)
  /*! WUF11 - Wakeup Flag For LLWU_P11
   *  0b0..LLWU_P11 input was not a wakeup source
   *  0b1..LLWU_P11 input was a wakeup source
   */
  #define LLWU_F2_WUF11(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
  #define LLWU_F2_WUF12_MASK                       (0x10U)
  #define LLWU_F2_WUF12_SHIFT                      (4U)
  /*! WUF12 - Wakeup Flag For LLWU_P12
   *  0b0..LLWU_P12 input was not a wakeup source
   *  0b1..LLWU_P12 input was a wakeup source
   */
  #define LLWU_F2_WUF12(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
  #define LLWU_F2_WUF13_MASK                       (0x20U)
  #define LLWU_F2_WUF13_SHIFT                      (5U)
  /*! WUF13 - Wakeup Flag For LLWU_P13
   *  0b0..LLWU_P13 input was not a wakeup source
   *  0b1..LLWU_P13 input was a wakeup source
   */
  #define LLWU_F2_WUF13(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
  #define LLWU_F2_WUF14_MASK                       (0x40U)
  #define LLWU_F2_WUF14_SHIFT                      (6U)
  /*! WUF14 - Wakeup Flag For LLWU_P14
   *  0b0..LLWU_P14 input was not a wakeup source
   *  0b1..LLWU_P14 input was a wakeup source
   */
  #define LLWU_F2_WUF14(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
  #define LLWU_F2_WUF15_MASK                       (0x80U)
  #define LLWU_F2_WUF15_SHIFT                      (7U)
  /*! WUF15 - Wakeup Flag For LLWU_P15
   *  0b0..LLWU_P15 input was not a wakeup source
   *  0b1..LLWU_P15 input was a wakeup source
   */
  #define LLWU_F2_WUF15(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
  /*! @} */
  
  /*! @name F3 - LLWU Flag 3 register */
  /*! @{ */
  #define LLWU_F3_MWUF0_MASK                       (0x1U)
  #define LLWU_F3_MWUF0_SHIFT                      (0U)
  /*! MWUF0 - Wakeup flag For module 0
   *  0b0..Module 0 input was not a wakeup source
   *  0b1..Module 0 input was a wakeup source
   */
  #define LLWU_F3_MWUF0(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
  #define LLWU_F3_MWUF1_MASK                       (0x2U)
  #define LLWU_F3_MWUF1_SHIFT                      (1U)
  /*! MWUF1 - Wakeup flag For module 1
   *  0b0..Module 1 input was not a wakeup source
   *  0b1..Module 1 input was a wakeup source
   */
  #define LLWU_F3_MWUF1(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
  #define LLWU_F3_MWUF2_MASK                       (0x4U)
  #define LLWU_F3_MWUF2_SHIFT                      (2U)
  /*! MWUF2 - Wakeup flag For module 2
   *  0b0..Module 2 input was not a wakeup source
   *  0b1..Module 2 input was a wakeup source
   */
  #define LLWU_F3_MWUF2(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
  #define LLWU_F3_MWUF3_MASK                       (0x8U)
  #define LLWU_F3_MWUF3_SHIFT                      (3U)
  /*! MWUF3 - Wakeup flag For module 3
   *  0b0..Module 3 input was not a wakeup source
   *  0b1..Module 3 input was a wakeup source
   */
  #define LLWU_F3_MWUF3(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
  #define LLWU_F3_MWUF4_MASK                       (0x10U)
  #define LLWU_F3_MWUF4_SHIFT                      (4U)
  /*! MWUF4 - Wakeup flag For module 4
   *  0b0..Module 4 input was not a wakeup source
   *  0b1..Module 4 input was a wakeup source
   */
  #define LLWU_F3_MWUF4(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
  #define LLWU_F3_MWUF5_MASK                       (0x20U)
  #define LLWU_F3_MWUF5_SHIFT                      (5U)
  /*! MWUF5 - Wakeup flag For module 5
   *  0b0..Module 5 input was not a wakeup source
   *  0b1..Module 5 input was a wakeup source
   */
  #define LLWU_F3_MWUF5(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
  #define LLWU_F3_MWUF6_MASK                       (0x40U)
  #define LLWU_F3_MWUF6_SHIFT                      (6U)
  /*! MWUF6 - Wakeup flag For module 6
   *  0b0..Module 6 input was not a wakeup source
   *  0b1..Module 6 input was a wakeup source
   */
  #define LLWU_F3_MWUF6(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
  #define LLWU_F3_MWUF7_MASK                       (0x80U)
  #define LLWU_F3_MWUF7_SHIFT                      (7U)
  /*! MWUF7 - Wakeup flag For module 7
   *  0b0..Module 7 input was not a wakeup source
   *  0b1..Module 7 input was a wakeup source
   */
  #define LLWU_F3_MWUF7(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
  /*! @} */
  
  /*! @name FILT1 - LLWU Pin Filter 1 register */
  /*! @{ */
  #define LLWU_FILT1_FILTSEL_MASK                  (0xFU)
  #define LLWU_FILT1_FILTSEL_SHIFT                 (0U)
  /*! FILTSEL - Filter Pin Select
   *  0b0000..Select LLWU_P0 for filter
   *  0b1111..Select LLWU_P15 for filter
   */
  #define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
  #define LLWU_FILT1_FILTE_MASK                    (0x60U)
  #define LLWU_FILT1_FILTE_SHIFT                   (5U)
  /*! FILTE - Digital Filter On External Pin
   *  0b00..Filter disabled
   *  0b01..Filter posedge detect enabled
   *  0b10..Filter negedge detect enabled
   *  0b11..Filter any edge detect enabled
   */
  #define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
  #define LLWU_FILT1_FILTF_MASK                    (0x80U)
  #define LLWU_FILT1_FILTF_SHIFT                   (7U)
  /*! FILTF - Filter Detect Flag
   *  0b0..Pin Filter 1 was not a wakeup source
   *  0b1..Pin Filter 1 was a wakeup source
   */
  #define LLWU_FILT1_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
  /*! @} */
  
  /*! @name FILT2 - LLWU Pin Filter 2 register */
  /*! @{ */
  #define LLWU_FILT2_FILTSEL_MASK                  (0xFU)
  #define LLWU_FILT2_FILTSEL_SHIFT                 (0U)
  /*! FILTSEL - Filter Pin Select
   *  0b0000..Select LLWU_P0 for filter
   *  0b1111..Select LLWU_P15 for filter
   */
  #define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
  #define LLWU_FILT2_FILTE_MASK                    (0x60U)
  #define LLWU_FILT2_FILTE_SHIFT                   (5U)
  /*! FILTE - Digital Filter On External Pin
   *  0b00..Filter disabled
   *  0b01..Filter posedge detect enabled
   *  0b10..Filter negedge detect enabled
   *  0b11..Filter any edge detect enabled
   */
  #define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
  #define LLWU_FILT2_FILTF_MASK                    (0x80U)
  #define LLWU_FILT2_FILTF_SHIFT                   (7U)
  /*! FILTF - Filter Detect Flag
   *  0b0..Pin Filter 2 was not a wakeup source
   *  0b1..Pin Filter 2 was a wakeup source
   */
  #define LLWU_FILT2_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group LLWU_Register_Masks */
  
  
  /* LLWU - Peripheral instance base addresses */
  /** Peripheral LLWU base address */
  #define LLWU_BASE                                (0x4007C000u)
  /** Peripheral LLWU base pointer */
  #define LLWU                                     ((LLWU_Type *)LLWU_BASE)
  /** Array initializer of LLWU peripheral base addresses */
  #define LLWU_BASE_ADDRS                          { LLWU_BASE }
  /** Array initializer of LLWU peripheral base pointers */
  #define LLWU_BASE_PTRS                           { LLWU }
  /** Interrupt vectors for the LLWU peripheral type */
  #define LLWU_IRQS                                { LLWU_IRQn }
  
  /*!
   * @}
   */ /* end of group LLWU_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- LPTMR Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
   * @{
   */
  
  /** LPTMR - Register Layout Typedef */
  typedef struct {
    __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
    __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
    __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
    __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
  } LPTMR_Type;
  
  /* ----------------------------------------------------------------------------
     -- LPTMR Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
   * @{
   */
  
  /*! @name CSR - Low Power Timer Control Status Register */
  /*! @{ */
  #define LPTMR_CSR_TEN_MASK                       (0x1U)
  #define LPTMR_CSR_TEN_SHIFT                      (0U)
  /*! TEN - Timer Enable
   *  0b0..LPTMR is disabled and internal logic is reset.
   *  0b1..LPTMR is enabled.
   */
  #define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
  #define LPTMR_CSR_TMS_MASK                       (0x2U)
  #define LPTMR_CSR_TMS_SHIFT                      (1U)
  /*! TMS - Timer Mode Select
   *  0b0..Time Counter mode.
   *  0b1..Pulse Counter mode.
   */
  #define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
  #define LPTMR_CSR_TFC_MASK                       (0x4U)
  #define LPTMR_CSR_TFC_SHIFT                      (2U)
  /*! TFC - Timer Free-Running Counter
   *  0b0..CNR is reset whenever TCF is set.
   *  0b1..CNR is reset on overflow.
   */
  #define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
  #define LPTMR_CSR_TPP_MASK                       (0x8U)
  #define LPTMR_CSR_TPP_SHIFT                      (3U)
  /*! TPP - Timer Pin Polarity
   *  0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
   *  0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
   */
  #define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
  #define LPTMR_CSR_TPS_MASK                       (0x30U)
  #define LPTMR_CSR_TPS_SHIFT                      (4U)
  /*! TPS - Timer Pin Select
   *  0b00..Pulse counter input 0 is selected.
   *  0b01..Pulse counter input 1 is selected.
   *  0b10..Pulse counter input 2 is selected.
   *  0b11..Pulse counter input 3 is selected.
   */
  #define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
  #define LPTMR_CSR_TIE_MASK                       (0x40U)
  #define LPTMR_CSR_TIE_SHIFT                      (6U)
  /*! TIE - Timer Interrupt Enable
   *  0b0..Timer interrupt disabled.
   *  0b1..Timer interrupt enabled.
   */
  #define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
  #define LPTMR_CSR_TCF_MASK                       (0x80U)
  #define LPTMR_CSR_TCF_SHIFT                      (7U)
  /*! TCF - Timer Compare Flag
   *  0b0..The value of CNR is not equal to CMR and increments.
   *  0b1..The value of CNR is equal to CMR and increments.
   */
  #define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
  /*! @} */
  
  /*! @name PSR - Low Power Timer Prescale Register */
  /*! @{ */
  #define LPTMR_PSR_PCS_MASK                       (0x3U)
  #define LPTMR_PSR_PCS_SHIFT                      (0U)
  /*! PCS - Prescaler Clock Select
   *  0b00..Prescaler/glitch filter clock 0 selected.
   *  0b01..Prescaler/glitch filter clock 1 selected.
   *  0b10..Prescaler/glitch filter clock 2 selected.
   *  0b11..Prescaler/glitch filter clock 3 selected.
   */
  #define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
  #define LPTMR_PSR_PBYP_MASK                      (0x4U)
  #define LPTMR_PSR_PBYP_SHIFT                     (2U)
  /*! PBYP - Prescaler Bypass
   *  0b0..Prescaler/glitch filter is enabled.
   *  0b1..Prescaler/glitch filter is bypassed.
   */
  #define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
  #define LPTMR_PSR_PRESCALE_MASK                  (0x78U)
  #define LPTMR_PSR_PRESCALE_SHIFT                 (3U)
  /*! PRESCALE - Prescale Value
   *  0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
   *  0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
   *  0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
   *  0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
   *  0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
   *  0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
   *  0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
   *  0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
   *  0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
   *  0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
   *  0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
   *  0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
   *  0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
   *  0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
   *  0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
   *  0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
   */
  #define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
  /*! @} */
  
  /*! @name CMR - Low Power Timer Compare Register */
  /*! @{ */
  #define LPTMR_CMR_COMPARE_MASK                   (0xFFFFU)
  #define LPTMR_CMR_COMPARE_SHIFT                  (0U)
  #define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
  /*! @} */
  
  /*! @name CNR - Low Power Timer Counter Register */
  /*! @{ */
  #define LPTMR_CNR_COUNTER_MASK                   (0xFFFFU)
  #define LPTMR_CNR_COUNTER_SHIFT                  (0U)
  #define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group LPTMR_Register_Masks */
  
  
  /* LPTMR - Peripheral instance base addresses */
  /** Peripheral LPTMR0 base address */
  #define LPTMR0_BASE                              (0x40040000u)
  /** Peripheral LPTMR0 base pointer */
  #define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
  /** Array initializer of LPTMR peripheral base addresses */
  #define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
  /** Array initializer of LPTMR peripheral base pointers */
  #define LPTMR_BASE_PTRS                          { LPTMR0 }
  /** Interrupt vectors for the LPTMR peripheral type */
  #define LPTMR_IRQS                               { LPTMR0_IRQn }
  
  /*!
   * @}
   */ /* end of group LPTMR_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- LPUART Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
   * @{
   */
  
  /** LPUART - Register Layout Typedef */
  typedef struct {
    __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x0 */
    __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x4 */
    __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x8 */
    __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0xC */
    __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x10 */
    __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x14 */
  } LPUART_Type;
  
  /* ----------------------------------------------------------------------------
     -- LPUART Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup LPUART_Register_Masks LPUART Register Masks
   * @{
   */
  
  /*! @name BAUD - LPUART Baud Rate Register */
  /*! @{ */
  #define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
  #define LPUART_BAUD_SBR_SHIFT                    (0U)
  #define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
  #define LPUART_BAUD_SBNS_MASK                    (0x2000U)
  #define LPUART_BAUD_SBNS_SHIFT                   (13U)
  /*! SBNS - Stop Bit Number Select
   *  0b0..One stop bit.
   *  0b1..Two stop bits.
   */
  #define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
  #define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
  #define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
  /*! RXEDGIE - RX Input Active Edge Interrupt Enable
   *  0b0..Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).
   *  0b1..Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
   */
  #define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
  #define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
  #define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
  /*! LBKDIE - LIN Break Detect Interrupt Enable
   *  0b0..Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
   *  0b1..Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
   */
  #define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
  #define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
  #define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
  /*! RESYNCDIS - Resynchronization Disable
   *  0b0..Resynchronization during received data word is supported
   *  0b1..Resynchronization during received data word is disabled
   */
  #define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
  #define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
  #define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
  /*! BOTHEDGE - Both Edge Sampling
   *  0b0..Receiver samples input data using the rising edge of the baud rate clock.
   *  0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
   */
  #define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
  #define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
  #define LPUART_BAUD_MATCFG_SHIFT                 (18U)
  /*! MATCFG - Match Configuration
   *  0b00..Address Match Wakeup
   *  0b01..Idle Match Wakeup
   *  0b10..Match On and Match Off
   *  0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
   */
  #define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
  #define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
  #define LPUART_BAUD_RDMAE_SHIFT                  (21U)
  /*! RDMAE - Receiver Full DMA Enable
   *  0b0..DMA request disabled.
   *  0b1..DMA request enabled.
   */
  #define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
  #define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
  #define LPUART_BAUD_TDMAE_SHIFT                  (23U)
  /*! TDMAE - Transmitter DMA Enable
   *  0b0..DMA request disabled.
   *  0b1..DMA request enabled.
   */
  #define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
  #define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
  #define LPUART_BAUD_OSR_SHIFT                    (24U)
  #define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
  #define LPUART_BAUD_M10_MASK                     (0x20000000U)
  #define LPUART_BAUD_M10_SHIFT                    (29U)
  /*! M10 - 10-bit Mode select
   *  0b0..Receiver and transmitter use 8-bit or 9-bit data characters.
   *  0b1..Receiver and transmitter use 10-bit data characters.
   */
  #define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
  #define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
  #define LPUART_BAUD_MAEN2_SHIFT                  (30U)
  /*! MAEN2 - Match Address Mode Enable 2
   *  0b0..Normal operation.
   *  0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
   */
  #define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
  #define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
  #define LPUART_BAUD_MAEN1_SHIFT                  (31U)
  /*! MAEN1 - Match Address Mode Enable 1
   *  0b0..Normal operation.
   *  0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
   */
  #define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
  /*! @} */
  
  /*! @name STAT - LPUART Status Register */
  /*! @{ */
  #define LPUART_STAT_MA2F_MASK                    (0x4000U)
  #define LPUART_STAT_MA2F_SHIFT                   (14U)
  /*! MA2F - Match 2 Flag
   *  0b0..Received data is not equal to MA2
   *  0b1..Received data is equal to MA2
   */
  #define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
  #define LPUART_STAT_MA1F_MASK                    (0x8000U)
  #define LPUART_STAT_MA1F_SHIFT                   (15U)
  /*! MA1F - Match 1 Flag
   *  0b0..Received data is not equal to MA1
   *  0b1..Received data is equal to MA1
   */
  #define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
  #define LPUART_STAT_PF_MASK                      (0x10000U)
  #define LPUART_STAT_PF_SHIFT                     (16U)
  /*! PF - Parity Error Flag
   *  0b0..No parity error.
   *  0b1..Parity error.
   */
  #define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
  #define LPUART_STAT_FE_MASK                      (0x20000U)
  #define LPUART_STAT_FE_SHIFT                     (17U)
  /*! FE - Framing Error Flag
   *  0b0..No framing error detected. This does not guarantee the framing is correct.
   *  0b1..Framing error.
   */
  #define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
  #define LPUART_STAT_NF_MASK                      (0x40000U)
  #define LPUART_STAT_NF_SHIFT                     (18U)
  /*! NF - Noise Flag
   *  0b0..No noise detected.
   *  0b1..Noise detected in the received character in LPUART_DATA.
   */
  #define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
  #define LPUART_STAT_OR_MASK                      (0x80000U)
  #define LPUART_STAT_OR_SHIFT                     (19U)
  /*! OR - Receiver Overrun Flag
   *  0b0..No overrun.
   *  0b1..Receive overrun (new LPUART data lost).
   */
  #define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
  #define LPUART_STAT_IDLE_MASK                    (0x100000U)
  #define LPUART_STAT_IDLE_SHIFT                   (20U)
  /*! IDLE - Idle Line Flag
   *  0b0..No idle line detected.
   *  0b1..Idle line was detected.
   */
  #define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
  #define LPUART_STAT_RDRF_MASK                    (0x200000U)
  #define LPUART_STAT_RDRF_SHIFT                   (21U)
  /*! RDRF - Receive Data Register Full Flag
   *  0b0..Receive data buffer empty.
   *  0b1..Receive data buffer full.
   */
  #define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
  #define LPUART_STAT_TC_MASK                      (0x400000U)
  #define LPUART_STAT_TC_SHIFT                     (22U)
  /*! TC - Transmission Complete Flag
   *  0b0..Transmitter active (sending data, a preamble, or a break).
   *  0b1..Transmitter idle (transmission activity complete).
   */
  #define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
  #define LPUART_STAT_TDRE_MASK                    (0x800000U)
  #define LPUART_STAT_TDRE_SHIFT                   (23U)
  /*! TDRE - Transmit Data Register Empty Flag
   *  0b0..Transmit data buffer full.
   *  0b1..Transmit data buffer empty.
   */
  #define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
  #define LPUART_STAT_RAF_MASK                     (0x1000000U)
  #define LPUART_STAT_RAF_SHIFT                    (24U)
  /*! RAF - Receiver Active Flag
   *  0b0..LPUART receiver idle waiting for a start bit.
   *  0b1..LPUART receiver active (LPUART_RX input not idle).
   */
  #define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
  #define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
  #define LPUART_STAT_LBKDE_SHIFT                  (25U)
  /*! LBKDE - LIN Break Detection Enable
   *  0b0..Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
   *  0b1..Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
   */
  #define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
  #define LPUART_STAT_BRK13_MASK                   (0x4000000U)
  #define LPUART_STAT_BRK13_SHIFT                  (26U)
  /*! BRK13 - Break Character Generation Length
   *  0b0..Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
   *  0b1..Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
   */
  #define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
  #define LPUART_STAT_RWUID_MASK                   (0x8000000U)
  #define LPUART_STAT_RWUID_SHIFT                  (27U)
  /*! RWUID - Receive Wake Up Idle Detect
   *  0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.
   *  0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.
   */
  #define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
  #define LPUART_STAT_RXINV_MASK                   (0x10000000U)
  #define LPUART_STAT_RXINV_SHIFT                  (28U)
  /*! RXINV - Receive Data Inversion
   *  0b0..Receive data not inverted.
   *  0b1..Receive data inverted.
   */
  #define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
  #define LPUART_STAT_MSBF_MASK                    (0x20000000U)
  #define LPUART_STAT_MSBF_SHIFT                   (29U)
  /*! MSBF - MSB First
   *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
   *  0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
   */
  #define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
  #define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
  #define LPUART_STAT_RXEDGIF_SHIFT                (30U)
  /*! RXEDGIF - LPUART_RX Pin Active Edge Interrupt Flag
   *  0b0..No active edge on the receive pin has occurred.
   *  0b1..An active edge on the receive pin has occurred.
   */
  #define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
  #define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
  #define LPUART_STAT_LBKDIF_SHIFT                 (31U)
  /*! LBKDIF - LIN Break Detect Interrupt Flag
   *  0b0..No LIN break character has been detected.
   *  0b1..LIN break character has been detected.
   */
  #define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
  /*! @} */
  
  /*! @name CTRL - LPUART Control Register */
  /*! @{ */
  #define LPUART_CTRL_PT_MASK                      (0x1U)
  #define LPUART_CTRL_PT_SHIFT                     (0U)
  /*! PT - Parity Type
   *  0b0..Even parity.
   *  0b1..Odd parity.
   */
  #define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
  #define LPUART_CTRL_PE_MASK                      (0x2U)
  #define LPUART_CTRL_PE_SHIFT                     (1U)
  /*! PE - Parity Enable
   *  0b0..No hardware parity generation or checking.
   *  0b1..Parity enabled.
   */
  #define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
  #define LPUART_CTRL_ILT_MASK                     (0x4U)
  #define LPUART_CTRL_ILT_SHIFT                    (2U)
  /*! ILT - Idle Line Type Select
   *  0b0..Idle character bit count starts after start bit.
   *  0b1..Idle character bit count starts after stop bit.
   */
  #define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
  #define LPUART_CTRL_WAKE_MASK                    (0x8U)
  #define LPUART_CTRL_WAKE_SHIFT                   (3U)
  /*! WAKE - Receiver Wakeup Method Select
   *  0b0..Configures RWU for idle-line wakeup.
   *  0b1..Configures RWU with address-mark wakeup.
   */
  #define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
  #define LPUART_CTRL_M_MASK                       (0x10U)
  #define LPUART_CTRL_M_SHIFT                      (4U)
  /*! M - 9-Bit or 8-Bit Mode Select
   *  0b0..Receiver and transmitter use 8-bit data characters.
   *  0b1..Receiver and transmitter use 9-bit data characters.
   */
  #define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
  #define LPUART_CTRL_RSRC_MASK                    (0x20U)
  #define LPUART_CTRL_RSRC_SHIFT                   (5U)
  /*! RSRC - Receiver Source Select
   *  0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin.
   *  0b1..Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input.
   */
  #define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
  #define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
  #define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
  /*! DOZEEN - Doze Enable
   *  0b0..LPUART is enabled in Doze mode.
   *  0b1..LPUART is disabled in Doze mode.
   */
  #define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
  #define LPUART_CTRL_LOOPS_MASK                   (0x80U)
  #define LPUART_CTRL_LOOPS_SHIFT                  (7U)
  /*! LOOPS - Loop Mode Select
   *  0b0..Normal operation - LPUART_RX and LPUART_TX use separate pins.
   *  0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
   */
  #define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
  #define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
  #define LPUART_CTRL_IDLECFG_SHIFT                (8U)
  /*! IDLECFG - Idle Configuration
   *  0b000..1 idle character
   *  0b001..2 idle characters
   *  0b010..4 idle characters
   *  0b011..8 idle characters
   *  0b100..16 idle characters
   *  0b101..32 idle characters
   *  0b110..64 idle characters
   *  0b111..128 idle characters
   */
  #define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
  #define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
  #define LPUART_CTRL_MA2IE_SHIFT                  (14U)
  /*! MA2IE - Match 2 Interrupt Enable
   *  0b0..MA2F interrupt disabled
   *  0b1..MA2F interrupt enabled
   */
  #define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
  #define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
  #define LPUART_CTRL_MA1IE_SHIFT                  (15U)
  /*! MA1IE - Match 1 Interrupt Enable
   *  0b0..MA1F interrupt disabled
   *  0b1..MA1F interrupt enabled
   */
  #define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
  #define LPUART_CTRL_SBK_MASK                     (0x10000U)
  #define LPUART_CTRL_SBK_SHIFT                    (16U)
  /*! SBK - Send Break
   *  0b0..Normal transmitter operation.
   *  0b1..Queue break character(s) to be sent.
   */
  #define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
  #define LPUART_CTRL_RWU_MASK                     (0x20000U)
  #define LPUART_CTRL_RWU_SHIFT                    (17U)
  /*! RWU - Receiver Wakeup Control
   *  0b0..Normal receiver operation.
   *  0b1..LPUART receiver in standby waiting for wakeup condition.
   */
  #define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
  #define LPUART_CTRL_RE_MASK                      (0x40000U)
  #define LPUART_CTRL_RE_SHIFT                     (18U)
  /*! RE - Receiver Enable
   *  0b0..Receiver disabled.
   *  0b1..Receiver enabled.
   */
  #define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
  #define LPUART_CTRL_TE_MASK                      (0x80000U)
  #define LPUART_CTRL_TE_SHIFT                     (19U)
  /*! TE - Transmitter Enable
   *  0b0..Transmitter disabled.
   *  0b1..Transmitter enabled.
   */
  #define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
  #define LPUART_CTRL_ILIE_MASK                    (0x100000U)
  #define LPUART_CTRL_ILIE_SHIFT                   (20U)
  /*! ILIE - Idle Line Interrupt Enable
   *  0b0..Hardware interrupts from IDLE disabled; use polling.
   *  0b1..Hardware interrupt requested when IDLE flag is 1.
   */
  #define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
  #define LPUART_CTRL_RIE_MASK                     (0x200000U)
  #define LPUART_CTRL_RIE_SHIFT                    (21U)
  /*! RIE - Receiver Interrupt Enable
   *  0b0..Hardware interrupts from RDRF disabled; use polling.
   *  0b1..Hardware interrupt requested when RDRF flag is 1.
   */
  #define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
  #define LPUART_CTRL_TCIE_MASK                    (0x400000U)
  #define LPUART_CTRL_TCIE_SHIFT                   (22U)
  /*! TCIE - Transmission Complete Interrupt Enable for
   *  0b0..Hardware interrupts from TC disabled; use polling.
   *  0b1..Hardware interrupt requested when TC flag is 1.
   */
  #define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
  #define LPUART_CTRL_TIE_MASK                     (0x800000U)
  #define LPUART_CTRL_TIE_SHIFT                    (23U)
  /*! TIE - Transmit Interrupt Enable
   *  0b0..Hardware interrupts from TDRE disabled; use polling.
   *  0b1..Hardware interrupt requested when TDRE flag is 1.
   */
  #define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
  #define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
  #define LPUART_CTRL_PEIE_SHIFT                   (24U)
  /*! PEIE - Parity Error Interrupt Enable
   *  0b0..PF interrupts disabled; use polling).
   *  0b1..Hardware interrupt requested when PF is set.
   */
  #define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
  #define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
  #define LPUART_CTRL_FEIE_SHIFT                   (25U)
  /*! FEIE - Framing Error Interrupt Enable
   *  0b0..FE interrupts disabled; use polling.
   *  0b1..Hardware interrupt requested when FE is set.
   */
  #define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
  #define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
  #define LPUART_CTRL_NEIE_SHIFT                   (26U)
  /*! NEIE - Noise Error Interrupt Enable
   *  0b0..NF interrupts disabled; use polling.
   *  0b1..Hardware interrupt requested when NF is set.
   */
  #define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
  #define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
  #define LPUART_CTRL_ORIE_SHIFT                   (27U)
  /*! ORIE - Overrun Interrupt Enable
   *  0b0..OR interrupts disabled; use polling.
   *  0b1..Hardware interrupt requested when OR is set.
   */
  #define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
  #define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
  #define LPUART_CTRL_TXINV_SHIFT                  (28U)
  /*! TXINV - Transmit Data Inversion
   *  0b0..Transmit data not inverted.
   *  0b1..Transmit data inverted.
   */
  #define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
  #define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
  #define LPUART_CTRL_TXDIR_SHIFT                  (29U)
  /*! TXDIR - LPUART_TX Pin Direction in Single-Wire Mode
   *  0b0..LPUART_TX pin is an input in single-wire mode.
   *  0b1..LPUART_TX pin is an output in single-wire mode.
   */
  #define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
  #define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
  #define LPUART_CTRL_R9T8_SHIFT                   (30U)
  #define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
  #define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
  #define LPUART_CTRL_R8T9_SHIFT                   (31U)
  #define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
  /*! @} */
  
  /*! @name DATA - LPUART Data Register */
  /*! @{ */
  #define LPUART_DATA_R0T0_MASK                    (0x1U)
  #define LPUART_DATA_R0T0_SHIFT                   (0U)
  #define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
  #define LPUART_DATA_R1T1_MASK                    (0x2U)
  #define LPUART_DATA_R1T1_SHIFT                   (1U)
  #define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
  #define LPUART_DATA_R2T2_MASK                    (0x4U)
  #define LPUART_DATA_R2T2_SHIFT                   (2U)
  #define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
  #define LPUART_DATA_R3T3_MASK                    (0x8U)
  #define LPUART_DATA_R3T3_SHIFT                   (3U)
  #define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
  #define LPUART_DATA_R4T4_MASK                    (0x10U)
  #define LPUART_DATA_R4T4_SHIFT                   (4U)
  #define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
  #define LPUART_DATA_R5T5_MASK                    (0x20U)
  #define LPUART_DATA_R5T5_SHIFT                   (5U)
  #define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
  #define LPUART_DATA_R6T6_MASK                    (0x40U)
  #define LPUART_DATA_R6T6_SHIFT                   (6U)
  #define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
  #define LPUART_DATA_R7T7_MASK                    (0x80U)
  #define LPUART_DATA_R7T7_SHIFT                   (7U)
  #define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
  #define LPUART_DATA_R8T8_MASK                    (0x100U)
  #define LPUART_DATA_R8T8_SHIFT                   (8U)
  #define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
  #define LPUART_DATA_R9T9_MASK                    (0x200U)
  #define LPUART_DATA_R9T9_SHIFT                   (9U)
  #define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
  #define LPUART_DATA_IDLINE_MASK                  (0x800U)
  #define LPUART_DATA_IDLINE_SHIFT                 (11U)
  /*! IDLINE - Idle Line
   *  0b0..Receiver was not idle before receiving this character.
   *  0b1..Receiver was idle before receiving this character.
   */
  #define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
  #define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
  #define LPUART_DATA_RXEMPT_SHIFT                 (12U)
  /*! RXEMPT - Receive Buffer Empty
   *  0b0..Receive buffer contains valid data.
   *  0b1..Receive buffer is empty, data returned on read is not valid.
   */
  #define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
  #define LPUART_DATA_FRETSC_MASK                  (0x2000U)
  #define LPUART_DATA_FRETSC_SHIFT                 (13U)
  /*! FRETSC - Frame Error / Transmit Special Character
   *  0b0..The dataword was received without a frame error on read, transmit a normal character on write.
   *  0b1..The dataword was received with a frame error, transmit an idle or break character on transmit.
   */
  #define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
  #define LPUART_DATA_PARITYE_MASK                 (0x4000U)
  #define LPUART_DATA_PARITYE_SHIFT                (14U)
  /*! PARITYE
   *  0b0..The dataword was received without a parity error.
   *  0b1..The dataword was received with a parity error.
   */
  #define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
  #define LPUART_DATA_NOISY_MASK                   (0x8000U)
  #define LPUART_DATA_NOISY_SHIFT                  (15U)
  /*! NOISY
   *  0b0..The dataword was received without noise.
   *  0b1..The data was received with noise.
   */
  #define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
  /*! @} */
  
  /*! @name MATCH - LPUART Match Address Register */
  /*! @{ */
  #define LPUART_MATCH_MA1_MASK                    (0x3FFU)
  #define LPUART_MATCH_MA1_SHIFT                   (0U)
  #define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
  #define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
  #define LPUART_MATCH_MA2_SHIFT                   (16U)
  #define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
  /*! @} */
  
  /*! @name MODIR - LPUART Modem IrDA Register */
  /*! @{ */
  #define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
  #define LPUART_MODIR_TXCTSE_SHIFT                (0U)
  /*! TXCTSE - Transmitter clear-to-send enable
   *  0b0..CTS has no effect on the transmitter.
   *  0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
   */
  #define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
  #define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
  #define LPUART_MODIR_TXRTSE_SHIFT                (1U)
  /*! TXRTSE - Transmitter request-to-send enable
   *  0b0..The transmitter has no effect on RTS.
   *  0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.
   */
  #define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
  #define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
  #define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
  /*! TXRTSPOL - Transmitter request-to-send polarity
   *  0b0..Transmitter RTS is active low.
   *  0b1..Transmitter RTS is active high.
   */
  #define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
  #define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
  #define LPUART_MODIR_RXRTSE_SHIFT                (3U)
  /*! RXRTSE - Receiver request-to-send enable
   *  0b0..The receiver has no effect on RTS.
   *  0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full.
   */
  #define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
  #define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
  #define LPUART_MODIR_TXCTSC_SHIFT                (4U)
  /*! TXCTSC - Transmit CTS Configuration
   *  0b0..CTS input is sampled at the start of each character.
   *  0b1..CTS input is sampled when the transmitter is idle.
   */
  #define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
  #define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
  #define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
  /*! TXCTSSRC - Transmit CTS Source
   *  0b0..CTS input is the LPUART_CTS pin.
   *  0b1..CTS input is the inverted Receiver Match result.
   */
  #define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
  #define LPUART_MODIR_TNP_MASK                    (0x30000U)
  #define LPUART_MODIR_TNP_SHIFT                   (16U)
  /*! TNP - Transmitter narrow pulse
   *  0b00..1/OSR.
   *  0b01..2/OSR.
   *  0b10..3/OSR.
   *  0b11..4/OSR.
   */
  #define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
  #define LPUART_MODIR_IREN_MASK                   (0x40000U)
  #define LPUART_MODIR_IREN_SHIFT                  (18U)
  /*! IREN - Infrared enable
   *  0b0..IR disabled.
   *  0b1..IR enabled.
   */
  #define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group LPUART_Register_Masks */
  
  
  /* LPUART - Peripheral instance base addresses */
  /** Peripheral LPUART0 base address */
  #define LPUART0_BASE                             (0x4002A000u)
  /** Peripheral LPUART0 base pointer */
  #define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
  /** Array initializer of LPUART peripheral base addresses */
  #define LPUART_BASE_ADDRS                        { LPUART0_BASE }
  /** Array initializer of LPUART peripheral base pointers */
  #define LPUART_BASE_PTRS                         { LPUART0 }
  /** Interrupt vectors for the LPUART peripheral type */
  #define LPUART_RX_TX_IRQS                        { LPUART0_IRQn }
  #define LPUART_ERR_IRQS                          { LPUART0_IRQn }
  
  /*!
   * @}
   */ /* end of group LPUART_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- MCG Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
   * @{
   */
  
  /** MCG - Register Layout Typedef */
  typedef struct {
    __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
    __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
    __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
    __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
         uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
    __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
    __I  uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
         uint8_t RESERVED_0[1];
    __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
         uint8_t RESERVED_1[1];
    __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
    __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
    __IO uint8_t C7;                                 /**< MCG Control 7 Register, offset: 0xC */
    __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
  } MCG_Type;
  
  /* ----------------------------------------------------------------------------
     -- MCG Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup MCG_Register_Masks MCG Register Masks
   * @{
   */
  
  /*! @name C1 - MCG Control 1 Register */
  /*! @{ */
  #define MCG_C1_IREFSTEN_MASK                     (0x1U)
  #define MCG_C1_IREFSTEN_SHIFT                    (0U)
  /*! IREFSTEN - Internal Reference Stop Enable
   *  0b0..Internal reference clock is disabled in Stop mode.
   *  0b1..Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
   */
  #define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
  #define MCG_C1_IRCLKEN_MASK                      (0x2U)
  #define MCG_C1_IRCLKEN_SHIFT                     (1U)
  /*! IRCLKEN - Internal Reference Clock Enable
   *  0b0..MCGIRCLK inactive.
   *  0b1..MCGIRCLK active.
   */
  #define MCG_C1_IRCLKEN(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
  #define MCG_C1_IREFS_MASK                        (0x4U)
  #define MCG_C1_IREFS_SHIFT                       (2U)
  /*! IREFS - Internal Reference Select
   *  0b0..External reference clock is selected.
   *  0b1..The slow internal reference clock is selected.
   */
  #define MCG_C1_IREFS(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
  #define MCG_C1_FRDIV_MASK                        (0x38U)
  #define MCG_C1_FRDIV_SHIFT                       (3U)
  /*! FRDIV - FLL External Reference Divider
   *  0b000..If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.
   *  0b001..If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.
   *  0b010..If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.
   *  0b011..If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
   *  0b100..If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.
   *  0b101..If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.
   *  0b110..If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 .
   *  0b111..If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .
   */
  #define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
  #define MCG_C1_CLKS_MASK                         (0xC0U)
  #define MCG_C1_CLKS_SHIFT                        (6U)
  /*! CLKS - Clock Source Select
   *  0b00..Encoding 0 - Output of FLL is selected.
   *  0b01..Encoding 1 - Internal reference clock is selected.
   *  0b10..Encoding 2 - External reference clock is selected.
   *  0b11..Encoding 3 - Reserved.
   */
  #define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
  /*! @} */
  
  /*! @name C2 - MCG Control 2 Register */
  /*! @{ */
  #define MCG_C2_IRCS_MASK                         (0x1U)
  #define MCG_C2_IRCS_SHIFT                        (0U)
  /*! IRCS - Internal Reference Clock Select
   *  0b0..Slow internal reference clock selected.
   *  0b1..Fast internal reference clock selected.
   */
  #define MCG_C2_IRCS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
  #define MCG_C2_LP_MASK                           (0x2U)
  #define MCG_C2_LP_SHIFT                          (1U)
  /*! LP - Low Power Select
   *  0b0..FLL is not disabled in bypass modes.
   *  0b1..FLL is disabled in bypass modes (lower power)
   */
  #define MCG_C2_LP(x)                             (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
  #define MCG_C2_EREFS_MASK                        (0x4U)
  #define MCG_C2_EREFS_SHIFT                       (2U)
  /*! EREFS - External Reference Select
   *  0b0..External reference clock requested.
   *  0b1..Oscillator requested.
   */
  #define MCG_C2_EREFS(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
  #define MCG_C2_HGO_MASK                          (0x8U)
  #define MCG_C2_HGO_SHIFT                         (3U)
  /*! HGO - High Gain Oscillator Select
   *  0b0..Configure crystal oscillator for low-power operation.
   *  0b1..Configure crystal oscillator for high-gain operation.
   */
  #define MCG_C2_HGO(x)                            (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
  #define MCG_C2_RANGE_MASK                        (0x30U)
  #define MCG_C2_RANGE_SHIFT                       (4U)
  /*! RANGE - Frequency Range Select
   *  0b00..Encoding 0 - Low frequency range selected for the crystal oscillator .
   *  0b01..Encoding 1 - High frequency range selected for the crystal oscillator .
   *  0b1x..Encoding 2 - Very high frequency range selected for the crystal oscillator .
   */
  #define MCG_C2_RANGE(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
  #define MCG_C2_FCFTRIM_MASK                      (0x40U)
  #define MCG_C2_FCFTRIM_SHIFT                     (6U)
  #define MCG_C2_FCFTRIM(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
  #define MCG_C2_LOCRE0_MASK                       (0x80U)
  #define MCG_C2_LOCRE0_SHIFT                      (7U)
  /*! LOCRE0 - Loss of Clock Reset Enable
   *  0b0..Interrupt request is generated on a loss of OSC0 external reference clock.
   *  0b1..Generate a reset request on a loss of OSC0 external reference clock.
   */
  #define MCG_C2_LOCRE0(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
  /*! @} */
  
  /*! @name C3 - MCG Control 3 Register */
  /*! @{ */
  #define MCG_C3_SCTRIM_MASK                       (0xFFU)
  #define MCG_C3_SCTRIM_SHIFT                      (0U)
  #define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
  /*! @} */
  
  /*! @name C4 - MCG Control 4 Register */
  /*! @{ */
  #define MCG_C4_SCFTRIM_MASK                      (0x1U)
  #define MCG_C4_SCFTRIM_SHIFT                     (0U)
  #define MCG_C4_SCFTRIM(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
  #define MCG_C4_FCTRIM_MASK                       (0x1EU)
  #define MCG_C4_FCTRIM_SHIFT                      (1U)
  #define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
  #define MCG_C4_DRST_DRS_MASK                     (0x60U)
  #define MCG_C4_DRST_DRS_SHIFT                    (5U)
  /*! DRST_DRS - DCO Range Select
   *  0b00..Encoding 0 - Low range (reset default).
   *  0b01..Encoding 1 - Mid range.
   *  0b10..Encoding 2 - Mid-high range.
   *  0b11..Encoding 3 - High range.
   */
  #define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
  #define MCG_C4_DMX32_MASK                        (0x80U)
  #define MCG_C4_DMX32_SHIFT                       (7U)
  /*! DMX32 - DCO Maximum Frequency with 32.768 kHz Reference
   *  0b0..DCO has a default range of 25%.
   *  0b1..DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
   */
  #define MCG_C4_DMX32(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
  /*! @} */
  
  /*! @name C6 - MCG Control 6 Register */
  /*! @{ */
  #define MCG_C6_CME_MASK                          (0x20U)
  #define MCG_C6_CME_SHIFT                         (5U)
  /*! CME - Clock Monitor Enable
   *  0b0..External clock monitor is disabled.
   *  0b1..Generate a reset request on loss of external clock.
   */
  #define MCG_C6_CME(x)                            (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME_SHIFT)) & MCG_C6_CME_MASK)
  /*! @} */
  
  /*! @name S - MCG Status Register */
  /*! @{ */
  #define MCG_S_IRCST_MASK                         (0x1U)
  #define MCG_S_IRCST_SHIFT                        (0U)
  /*! IRCST - Internal Reference Clock Status
   *  0b0..Source of internal reference clock is the slow clock (32 kHz IRC).
   *  0b1..Source of internal reference clock is the fast clock (4 MHz IRC).
   */
  #define MCG_S_IRCST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
  #define MCG_S_OSCINIT0_MASK                      (0x2U)
  #define MCG_S_OSCINIT0_SHIFT                     (1U)
  #define MCG_S_OSCINIT0(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
  #define MCG_S_CLKST_MASK                         (0xCU)
  #define MCG_S_CLKST_SHIFT                        (2U)
  /*! CLKST - Clock Mode Status
   *  0b00..Encoding 0 - Output of the FLL is selected (reset default).
   *  0b01..Encoding 1 - Internal reference clock is selected.
   *  0b10..Encoding 2 - External reference clock is selected.
   *  0b11..Reserved.
   */
  #define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
  #define MCG_S_IREFST_MASK                        (0x10U)
  #define MCG_S_IREFST_SHIFT                       (4U)
  /*! IREFST - Internal Reference Status
   *  0b0..Source of FLL reference clock is the external reference clock.
   *  0b1..Source of FLL reference clock is the internal reference clock.
   */
  #define MCG_S_IREFST(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
  /*! @} */
  
  /*! @name SC - MCG Status and Control Register */
  /*! @{ */
  #define MCG_SC_LOCS0_MASK                        (0x1U)
  #define MCG_SC_LOCS0_SHIFT                       (0U)
  /*! LOCS0 - OSC0 Loss of Clock Status
   *  0b0..Loss of OSC0 has not occurred.
   *  0b1..Loss of OSC0 has occurred.
   */
  #define MCG_SC_LOCS0(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
  #define MCG_SC_FCRDIV_MASK                       (0xEU)
  #define MCG_SC_FCRDIV_SHIFT                      (1U)
  /*! FCRDIV - Fast Clock Internal Reference Divider
   *  0b000..Divide Factor is 1
   *  0b001..Divide Factor is 2.
   *  0b010..Divide Factor is 4.
   *  0b011..Divide Factor is 8.
   *  0b100..Divide Factor is 16
   *  0b101..Divide Factor is 32
   *  0b110..Divide Factor is 64
   *  0b111..Divide Factor is 128.
   */
  #define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
  #define MCG_SC_FLTPRSRV_MASK                     (0x10U)
  #define MCG_SC_FLTPRSRV_SHIFT                    (4U)
  /*! FLTPRSRV - FLL Filter Preserve Enable
   *  0b0..FLL filter and FLL frequency will reset on changes to currect clock mode.
   *  0b1..Fll filter and FLL frequency retain their previous values during new clock mode change.
   */
  #define MCG_SC_FLTPRSRV(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
  #define MCG_SC_ATMF_MASK                         (0x20U)
  #define MCG_SC_ATMF_SHIFT                        (5U)
  /*! ATMF - Automatic Trim Machine Fail Flag
   *  0b0..Automatic Trim Machine completed normally.
   *  0b1..Automatic Trim Machine failed.
   */
  #define MCG_SC_ATMF(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
  #define MCG_SC_ATMS_MASK                         (0x40U)
  #define MCG_SC_ATMS_SHIFT                        (6U)
  /*! ATMS - Automatic Trim Machine Select
   *  0b0..32 kHz Internal Reference Clock selected.
   *  0b1..4 MHz Internal Reference Clock selected.
   */
  #define MCG_SC_ATMS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
  #define MCG_SC_ATME_MASK                         (0x80U)
  #define MCG_SC_ATME_SHIFT                        (7U)
  /*! ATME - Automatic Trim Machine Enable
   *  0b0..Auto Trim Machine disabled.
   *  0b1..Auto Trim Machine enabled.
   */
  #define MCG_SC_ATME(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
  /*! @} */
  
  /*! @name ATCVH - MCG Auto Trim Compare Value High Register */
  /*! @{ */
  #define MCG_ATCVH_ATCVH_MASK                     (0xFFU)
  #define MCG_ATCVH_ATCVH_SHIFT                    (0U)
  #define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
  /*! @} */
  
  /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
  /*! @{ */
  #define MCG_ATCVL_ATCVL_MASK                     (0xFFU)
  #define MCG_ATCVL_ATCVL_SHIFT                    (0U)
  #define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
  /*! @} */
  
  /*! @name C7 - MCG Control 7 Register */
  /*! @{ */
  #define MCG_C7_OSCSEL_MASK                       (0x3U)
  #define MCG_C7_OSCSEL_SHIFT                      (0U)
  /*! OSCSEL - MCG OSC Clock Select
   *  0b00..Selects Oscillator (OSCCLK0).
   *  0b01..Selects 32 kHz RTC Oscillator.
   *  0b10..Selects Oscillator (OSCCLK1).
   *  0b11..RESERVED
   */
  #define MCG_C7_OSCSEL(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
  /*! @} */
  
  /*! @name C8 - MCG Control 8 Register */
  /*! @{ */
  #define MCG_C8_LOCS1_MASK                        (0x1U)
  #define MCG_C8_LOCS1_SHIFT                       (0U)
  /*! LOCS1 - RTC Loss of Clock Status
   *  0b0..Loss of RTC has not occur.
   *  0b1..Loss of RTC has occur
   */
  #define MCG_C8_LOCS1(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
  #define MCG_C8_CME1_MASK                         (0x20U)
  #define MCG_C8_CME1_SHIFT                        (5U)
  /*! CME1 - Clock Monitor Enable1
   *  0b0..External clock monitor is disabled for RTC clock.
   *  0b1..External clock monitor is enabled for RTC clock.
   */
  #define MCG_C8_CME1(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
  #define MCG_C8_LOCRE1_MASK                       (0x80U)
  #define MCG_C8_LOCRE1_SHIFT                      (7U)
  /*! LOCRE1 - Loss of Clock Reset Enable
   *  0b0..Interrupt request is generated on a loss of RTC external reference clock.
   *  0b1..Generate a reset request on a loss of RTC external reference clock
   */
  #define MCG_C8_LOCRE1(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group MCG_Register_Masks */
  
  
  /* MCG - Peripheral instance base addresses */
  /** Peripheral MCG base address */
  #define MCG_BASE                                 (0x40064000u)
  /** Peripheral MCG base pointer */
  #define MCG                                      ((MCG_Type *)MCG_BASE)
  /** Array initializer of MCG peripheral base addresses */
  #define MCG_BASE_ADDRS                           { MCG_BASE }
  /** Array initializer of MCG peripheral base pointers */
  #define MCG_BASE_PTRS                            { MCG }
  
  /*!
   * @}
   */ /* end of group MCG_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- MCM Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
   * @{
   */
  
  /** MCM - Register Layout Typedef */
  typedef struct {
         uint8_t RESERVED_0[8];
    __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
    __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
    __IO uint32_t PLACR;                             /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
    __IO uint32_t ISCR;                              /**< Interrupt Status and Control Register, offset: 0x10 */
         uint8_t RESERVED_1[44];
    __IO uint32_t CPO;                               /**< Compute Operation Control Register, offset: 0x40 */
  } MCM_Type;
  
  /* ----------------------------------------------------------------------------
     -- MCM Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup MCM_Register_Masks MCM Register Masks
   * @{
   */
  
  /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
  /*! @{ */
  #define MCM_PLASC_ASC_MASK                       (0xFFU)
  #define MCM_PLASC_ASC_SHIFT                      (0U)
  /*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
   *  0b00000000..A bus slave connection to AXBS input port n is absent
   *  0b00000001..A bus slave connection to AXBS input port n is present
   */
  #define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
  /*! @} */
  
  /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
  /*! @{ */
  #define MCM_PLAMC_AMC_MASK                       (0xFFU)
  #define MCM_PLAMC_AMC_SHIFT                      (0U)
  /*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
   *  0b00000000..A bus master connection to AXBS input port n is absent
   *  0b00000001..A bus master connection to AXBS input port n is present
   */
  #define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
  /*! @} */
  
  /*! @name PLACR - Crossbar Switch (AXBS) Control Register */
  /*! @{ */
  #define MCM_PLACR_ARB_MASK                       (0x200U)
  #define MCM_PLACR_ARB_SHIFT                      (9U)
  /*! ARB - Arbitration select
   *  0b0..Fixed-priority arbitration for the crossbar masters
   *  0b1..Round-robin arbitration for the crossbar masters
   */
  #define MCM_PLACR_ARB(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
  /*! @} */
  
  /*! @name ISCR - Interrupt Status and Control Register */
  /*! @{ */
  #define MCM_ISCR_FIOC_MASK                       (0x100U)
  #define MCM_ISCR_FIOC_SHIFT                      (8U)
  /*! FIOC - FPU invalid operation interrupt status
   *  0b0..No interrupt
   *  0b1..Interrupt occurred
   */
  #define MCM_ISCR_FIOC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
  #define MCM_ISCR_FDZC_MASK                       (0x200U)
  #define MCM_ISCR_FDZC_SHIFT                      (9U)
  /*! FDZC - FPU divide-by-zero interrupt status
   *  0b0..No interrupt
   *  0b1..Interrupt occurred
   */
  #define MCM_ISCR_FDZC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
  #define MCM_ISCR_FOFC_MASK                       (0x400U)
  #define MCM_ISCR_FOFC_SHIFT                      (10U)
  /*! FOFC - FPU overflow interrupt status
   *  0b0..No interrupt
   *  0b1..Interrupt occurred
   */
  #define MCM_ISCR_FOFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
  #define MCM_ISCR_FUFC_MASK                       (0x800U)
  #define MCM_ISCR_FUFC_SHIFT                      (11U)
  /*! FUFC - FPU underflow interrupt status
   *  0b0..No interrupt
   *  0b1..Interrupt occurred
   */
  #define MCM_ISCR_FUFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
  #define MCM_ISCR_FIXC_MASK                       (0x1000U)
  #define MCM_ISCR_FIXC_SHIFT                      (12U)
  /*! FIXC - FPU inexact interrupt status
   *  0b0..No interrupt
   *  0b1..Interrupt occurred
   */
  #define MCM_ISCR_FIXC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
  #define MCM_ISCR_FIDC_MASK                       (0x8000U)
  #define MCM_ISCR_FIDC_SHIFT                      (15U)
  /*! FIDC - FPU input denormal interrupt status
   *  0b0..No interrupt
   *  0b1..Interrupt occurred
   */
  #define MCM_ISCR_FIDC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
  #define MCM_ISCR_FIOCE_MASK                      (0x1000000U)
  #define MCM_ISCR_FIOCE_SHIFT                     (24U)
  /*! FIOCE - FPU invalid operation interrupt enable
   *  0b0..Disable interrupt
   *  0b1..Enable interrupt
   */
  #define MCM_ISCR_FIOCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
  #define MCM_ISCR_FDZCE_MASK                      (0x2000000U)
  #define MCM_ISCR_FDZCE_SHIFT                     (25U)
  /*! FDZCE - FPU divide-by-zero interrupt enable
   *  0b0..Disable interrupt
   *  0b1..Enable interrupt
   */
  #define MCM_ISCR_FDZCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
  #define MCM_ISCR_FOFCE_MASK                      (0x4000000U)
  #define MCM_ISCR_FOFCE_SHIFT                     (26U)
  /*! FOFCE - FPU overflow interrupt enable
   *  0b0..Disable interrupt
   *  0b1..Enable interrupt
   */
  #define MCM_ISCR_FOFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
  #define MCM_ISCR_FUFCE_MASK                      (0x8000000U)
  #define MCM_ISCR_FUFCE_SHIFT                     (27U)
  /*! FUFCE - FPU underflow interrupt enable
   *  0b0..Disable interrupt
   *  0b1..Enable interrupt
   */
  #define MCM_ISCR_FUFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
  #define MCM_ISCR_FIXCE_MASK                      (0x10000000U)
  #define MCM_ISCR_FIXCE_SHIFT                     (28U)
  /*! FIXCE - FPU inexact interrupt enable
   *  0b0..Disable interrupt
   *  0b1..Enable interrupt
   */
  #define MCM_ISCR_FIXCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
  #define MCM_ISCR_FIDCE_MASK                      (0x80000000U)
  #define MCM_ISCR_FIDCE_SHIFT                     (31U)
  /*! FIDCE - FPU input denormal interrupt enable
   *  0b0..Disable interrupt
   *  0b1..Enable interrupt
   */
  #define MCM_ISCR_FIDCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
  /*! @} */
  
  /*! @name CPO - Compute Operation Control Register */
  /*! @{ */
  #define MCM_CPO_CPOREQ_MASK                      (0x1U)
  #define MCM_CPO_CPOREQ_SHIFT                     (0U)
  /*! CPOREQ - Compute Operation request
   *  0b0..Request is cleared.
   *  0b1..Request Compute Operation.
   */
  #define MCM_CPO_CPOREQ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
  #define MCM_CPO_CPOACK_MASK                      (0x2U)
  #define MCM_CPO_CPOACK_SHIFT                     (1U)
  /*! CPOACK - Compute Operation acknowledge
   *  0b0..Compute operation entry has not completed or compute operation exit has completed.
   *  0b1..Compute operation entry has completed or compute operation exit has not completed.
   */
  #define MCM_CPO_CPOACK(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
  #define MCM_CPO_CPOWOI_MASK                      (0x4U)
  #define MCM_CPO_CPOWOI_SHIFT                     (2U)
  /*! CPOWOI - Compute Operation wakeup on interrupt
   *  0b0..No effect.
   *  0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
   */
  #define MCM_CPO_CPOWOI(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group MCM_Register_Masks */
  
  
  /* MCM - Peripheral instance base addresses */
  /** Peripheral MCM base address */
  #define MCM_BASE                                 (0xE0080000u)
  /** Peripheral MCM base pointer */
  #define MCM                                      ((MCM_Type *)MCM_BASE)
  /** Array initializer of MCM peripheral base addresses */
  #define MCM_BASE_ADDRS                           { MCM_BASE }
  /** Array initializer of MCM peripheral base pointers */
  #define MCM_BASE_PTRS                            { MCM }
  /** Interrupt vectors for the MCM peripheral type */
  #define MCM_IRQS                                 { MCM_IRQn }
  
  /*!
   * @}
   */ /* end of group MCM_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- NV Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
   * @{
   */
  
  /** NV - Register Layout Typedef */
  typedef struct {
    __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
    __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
    __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
    __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
    __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
    __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
    __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
    __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
    __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
    __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
    __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
    __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
    __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
    __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
  } NV_Type;
  
  /* ----------------------------------------------------------------------------
     -- NV Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup NV_Register_Masks NV Register Masks
   * @{
   */
  
  /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
  /*! @{ */
  #define NV_BACKKEY3_KEY_MASK                     (0xFFU)
  #define NV_BACKKEY3_KEY_SHIFT                    (0U)
  #define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
  /*! @} */
  
  /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
  /*! @{ */
  #define NV_BACKKEY2_KEY_MASK                     (0xFFU)
  #define NV_BACKKEY2_KEY_SHIFT                    (0U)
  #define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
  /*! @} */
  
  /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
  /*! @{ */
  #define NV_BACKKEY1_KEY_MASK                     (0xFFU)
  #define NV_BACKKEY1_KEY_SHIFT                    (0U)
  #define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
  /*! @} */
  
  /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
  /*! @{ */
  #define NV_BACKKEY0_KEY_MASK                     (0xFFU)
  #define NV_BACKKEY0_KEY_SHIFT                    (0U)
  #define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
  /*! @} */
  
  /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
  /*! @{ */
  #define NV_BACKKEY7_KEY_MASK                     (0xFFU)
  #define NV_BACKKEY7_KEY_SHIFT                    (0U)
  #define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
  /*! @} */
  
  /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
  /*! @{ */
  #define NV_BACKKEY6_KEY_MASK                     (0xFFU)
  #define NV_BACKKEY6_KEY_SHIFT                    (0U)
  #define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
  /*! @} */
  
  /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
  /*! @{ */
  #define NV_BACKKEY5_KEY_MASK                     (0xFFU)
  #define NV_BACKKEY5_KEY_SHIFT                    (0U)
  #define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
  /*! @} */
  
  /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
  /*! @{ */
  #define NV_BACKKEY4_KEY_MASK                     (0xFFU)
  #define NV_BACKKEY4_KEY_SHIFT                    (0U)
  #define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
  /*! @} */
  
  /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
  /*! @{ */
  #define NV_FPROT3_PROT_MASK                      (0xFFU)
  #define NV_FPROT3_PROT_SHIFT                     (0U)
  #define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
  /*! @} */
  
  /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
  /*! @{ */
  #define NV_FPROT2_PROT_MASK                      (0xFFU)
  #define NV_FPROT2_PROT_SHIFT                     (0U)
  #define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
  /*! @} */
  
  /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
  /*! @{ */
  #define NV_FPROT1_PROT_MASK                      (0xFFU)
  #define NV_FPROT1_PROT_SHIFT                     (0U)
  #define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
  /*! @} */
  
  /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
  /*! @{ */
  #define NV_FPROT0_PROT_MASK                      (0xFFU)
  #define NV_FPROT0_PROT_SHIFT                     (0U)
  #define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
  /*! @} */
  
  /*! @name FSEC - Non-volatile Flash Security Register */
  /*! @{ */
  #define NV_FSEC_SEC_MASK                         (0x3U)
  #define NV_FSEC_SEC_SHIFT                        (0U)
  /*! SEC - Flash Security
   *  0b10..MCU security status is unsecure
   *  0b11..MCU security status is secure
   */
  #define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
  #define NV_FSEC_FSLACC_MASK                      (0xCU)
  #define NV_FSEC_FSLACC_SHIFT                     (2U)
  /*! FSLACC - Freescale Failure Analysis Access Code
   *  0b10..Freescale factory access denied
   *  0b11..Freescale factory access granted
   */
  #define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
  #define NV_FSEC_MEEN_MASK                        (0x30U)
  #define NV_FSEC_MEEN_SHIFT                       (4U)
  /*! MEEN
   *  0b10..Mass erase is disabled
   *  0b11..Mass erase is enabled
   */
  #define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
  #define NV_FSEC_KEYEN_MASK                       (0xC0U)
  #define NV_FSEC_KEYEN_SHIFT                      (6U)
  /*! KEYEN - Backdoor Key Security Enable
   *  0b10..Backdoor key access enabled
   *  0b11..Backdoor key access disabled
   */
  #define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
  /*! @} */
  
  /*! @name FOPT - Non-volatile Flash Option Register */
  /*! @{ */
  #define NV_FOPT_LPBOOT_MASK                      (0x1U)
  #define NV_FOPT_LPBOOT_SHIFT                     (0U)
  /*! LPBOOT
   *  0b0..Low-power boot
   *  0b1..Normal boot
   */
  #define NV_FOPT_LPBOOT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
  #define NV_FOPT_EZPORT_DIS_MASK                  (0x2U)
  #define NV_FOPT_EZPORT_DIS_SHIFT                 (1U)
  /*! EZPORT_DIS
   *  0b0..EzPort operation is disabled
   *  0b1..EzPort operation is enabled
   */
  #define NV_FOPT_EZPORT_DIS(x)                    (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
  #define NV_FOPT_NMI_DIS_MASK                     (0x4U)
  #define NV_FOPT_NMI_DIS_SHIFT                    (2U)
  /*! NMI_DIS
   *  0b0..NMI interrupts are always blocked
   *  0b1..NMI_b pin/interrupts reset default to enabled
   */
  #define NV_FOPT_NMI_DIS(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
  #define NV_FOPT_FAST_INIT_MASK                   (0x20U)
  #define NV_FOPT_FAST_INIT_SHIFT                  (5U)
  /*! FAST_INIT
   *  0b0..Slower initialization
   *  0b1..Fast Initialization
   */
  #define NV_FOPT_FAST_INIT(x)                     (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group NV_Register_Masks */
  
  
  /* NV - Peripheral instance base addresses */
  /** Peripheral FTFA_FlashConfig base address */
  #define FTFA_FlashConfig_BASE                    (0x400u)
  /** Peripheral FTFA_FlashConfig base pointer */
  #define FTFA_FlashConfig                         ((NV_Type *)FTFA_FlashConfig_BASE)
  /** Array initializer of NV peripheral base addresses */
  #define NV_BASE_ADDRS                            { FTFA_FlashConfig_BASE }
  /** Array initializer of NV peripheral base pointers */
  #define NV_BASE_PTRS                             { FTFA_FlashConfig }
  
  /*!
   * @}
   */ /* end of group NV_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- OSC Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
   * @{
   */
  
  /** OSC - Register Layout Typedef */
  typedef struct {
    __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
         uint8_t RESERVED_0[1];
    __IO uint8_t DIV;                                /**< OSC_DIV, offset: 0x2 */
  } OSC_Type;
  
  /* ----------------------------------------------------------------------------
     -- OSC Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup OSC_Register_Masks OSC Register Masks
   * @{
   */
  
  /*! @name CR - OSC Control Register */
  /*! @{ */
  #define OSC_CR_SC16P_MASK                        (0x1U)
  #define OSC_CR_SC16P_SHIFT                       (0U)
  /*! SC16P - Oscillator 16 pF Capacitor Load Configure
   *  0b0..Disable the selection.
   *  0b1..Add 16 pF capacitor to the oscillator load.
   */
  #define OSC_CR_SC16P(x)                          (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
  #define OSC_CR_SC8P_MASK                         (0x2U)
  #define OSC_CR_SC8P_SHIFT                        (1U)
  /*! SC8P - Oscillator 8 pF Capacitor Load Configure
   *  0b0..Disable the selection.
   *  0b1..Add 8 pF capacitor to the oscillator load.
   */
  #define OSC_CR_SC8P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
  #define OSC_CR_SC4P_MASK                         (0x4U)
  #define OSC_CR_SC4P_SHIFT                        (2U)
  /*! SC4P - Oscillator 4 pF Capacitor Load Configure
   *  0b0..Disable the selection.
   *  0b1..Add 4 pF capacitor to the oscillator load.
   */
  #define OSC_CR_SC4P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
  #define OSC_CR_SC2P_MASK                         (0x8U)
  #define OSC_CR_SC2P_SHIFT                        (3U)
  /*! SC2P - Oscillator 2 pF Capacitor Load Configure
   *  0b0..Disable the selection.
   *  0b1..Add 2 pF capacitor to the oscillator load.
   */
  #define OSC_CR_SC2P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
  #define OSC_CR_EREFSTEN_MASK                     (0x20U)
  #define OSC_CR_EREFSTEN_SHIFT                    (5U)
  /*! EREFSTEN - External Reference Stop Enable
   *  0b0..External reference clock is disabled in Stop mode.
   *  0b1..External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.
   */
  #define OSC_CR_EREFSTEN(x)                       (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
  #define OSC_CR_ERCLKEN_MASK                      (0x80U)
  #define OSC_CR_ERCLKEN_SHIFT                     (7U)
  /*! ERCLKEN - External Reference Enable
   *  0b0..External reference clock is inactive.
   *  0b1..External reference clock is enabled.
   */
  #define OSC_CR_ERCLKEN(x)                        (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
  /*! @} */
  
  /*! @name DIV - OSC_DIV */
  /*! @{ */
  #define OSC_DIV_ERPS_MASK                        (0xC0U)
  #define OSC_DIV_ERPS_SHIFT                       (6U)
  /*! ERPS
   *  0b00..The divisor ratio is 1.
   *  0b01..The divisor ratio is 2.
   *  0b10..The divisor ratio is 4.
   *  0b11..The divisor ratio is 8.
   */
  #define OSC_DIV_ERPS(x)                          (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group OSC_Register_Masks */
  
  
  /* OSC - Peripheral instance base addresses */
  /** Peripheral OSC base address */
  #define OSC_BASE                                 (0x40065000u)
  /** Peripheral OSC base pointer */
  #define OSC                                      ((OSC_Type *)OSC_BASE)
  /** Array initializer of OSC peripheral base addresses */
  #define OSC_BASE_ADDRS                           { OSC_BASE }
  /** Array initializer of OSC peripheral base pointers */
  #define OSC_BASE_PTRS                            { OSC }
  
  /*!
   * @}
   */ /* end of group OSC_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- PDB Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
   * @{
   */
  
  /** PDB - Register Layout Typedef */
  typedef struct {
    __IO uint32_t SC;                                /**< Status and Control register, offset: 0x0 */
    __IO uint32_t MOD;                               /**< Modulus register, offset: 0x4 */
    __I  uint32_t CNT;                               /**< Counter register, offset: 0x8 */
    __IO uint32_t IDLY;                              /**< Interrupt Delay register, offset: 0xC */
    struct {                                         /* offset: 0x10, array step: 0x28 */
      __IO uint32_t C1;                                /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
      __IO uint32_t S;                                 /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
      __IO uint32_t DLY[2];                            /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
           uint8_t RESERVED_0[24];
    } CH[2];
         uint8_t RESERVED_0[240];
    struct {                                         /* offset: 0x150, array step: 0x8 */
      __IO uint32_t INTC;                              /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
      __IO uint32_t INT;                               /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
    } DAC[1];
         uint8_t RESERVED_1[56];
    __IO uint32_t POEN;                              /**< Pulse-Out n Enable register, offset: 0x190 */
    __IO uint32_t PODLY[2];                          /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
  } PDB_Type;
  
  /* ----------------------------------------------------------------------------
     -- PDB Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PDB_Register_Masks PDB Register Masks
   * @{
   */
  
  /*! @name SC - Status and Control register */
  /*! @{ */
  #define PDB_SC_LDOK_MASK                         (0x1U)
  #define PDB_SC_LDOK_SHIFT                        (0U)
  #define PDB_SC_LDOK(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
  #define PDB_SC_CONT_MASK                         (0x2U)
  #define PDB_SC_CONT_SHIFT                        (1U)
  /*! CONT - Continuous Mode Enable
   *  0b0..PDB operation in One-Shot mode
   *  0b1..PDB operation in Continuous mode
   */
  #define PDB_SC_CONT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
  #define PDB_SC_MULT_MASK                         (0xCU)
  #define PDB_SC_MULT_SHIFT                        (2U)
  /*! MULT - Multiplication Factor Select for Prescaler
   *  0b00..Multiplication factor is 1.
   *  0b01..Multiplication factor is 10.
   *  0b10..Multiplication factor is 20.
   *  0b11..Multiplication factor is 40.
   */
  #define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
  #define PDB_SC_PDBIE_MASK                        (0x20U)
  #define PDB_SC_PDBIE_SHIFT                       (5U)
  /*! PDBIE - PDB Interrupt Enable
   *  0b0..PDB interrupt disabled.
   *  0b1..PDB interrupt enabled.
   */
  #define PDB_SC_PDBIE(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
  #define PDB_SC_PDBIF_MASK                        (0x40U)
  #define PDB_SC_PDBIF_SHIFT                       (6U)
  #define PDB_SC_PDBIF(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
  #define PDB_SC_PDBEN_MASK                        (0x80U)
  #define PDB_SC_PDBEN_SHIFT                       (7U)
  /*! PDBEN - PDB Enable
   *  0b0..PDB disabled. Counter is off.
   *  0b1..PDB enabled.
   */
  #define PDB_SC_PDBEN(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
  #define PDB_SC_TRGSEL_MASK                       (0xF00U)
  #define PDB_SC_TRGSEL_SHIFT                      (8U)
  /*! TRGSEL - Trigger Input Source Select
   *  0b0000..Trigger-In 0 is selected.
   *  0b0001..Trigger-In 1 is selected.
   *  0b0010..Trigger-In 2 is selected.
   *  0b0011..Trigger-In 3 is selected.
   *  0b0100..Trigger-In 4 is selected.
   *  0b0101..Trigger-In 5 is selected.
   *  0b0110..Trigger-In 6 is selected.
   *  0b0111..Trigger-In 7 is selected.
   *  0b1000..Trigger-In 8 is selected.
   *  0b1001..Trigger-In 9 is selected.
   *  0b1010..Trigger-In 10 is selected.
   *  0b1011..Trigger-In 11 is selected.
   *  0b1100..Trigger-In 12 is selected.
   *  0b1101..Trigger-In 13 is selected.
   *  0b1110..Trigger-In 14 is selected.
   *  0b1111..Software trigger is selected.
   */
  #define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
  #define PDB_SC_PRESCALER_MASK                    (0x7000U)
  #define PDB_SC_PRESCALER_SHIFT                   (12U)
  /*! PRESCALER - Prescaler Divider Select
   *  0b000..Counting uses the peripheral clock divided by multiplication factor selected by MULT.
   *  0b001..Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT.
   *  0b010..Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT.
   *  0b011..Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT.
   *  0b100..Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT.
   *  0b101..Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT.
   *  0b110..Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT.
   *  0b111..Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT.
   */
  #define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
  #define PDB_SC_DMAEN_MASK                        (0x8000U)
  #define PDB_SC_DMAEN_SHIFT                       (15U)
  /*! DMAEN - DMA Enable
   *  0b0..DMA disabled.
   *  0b1..DMA enabled.
   */
  #define PDB_SC_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
  #define PDB_SC_SWTRIG_MASK                       (0x10000U)
  #define PDB_SC_SWTRIG_SHIFT                      (16U)
  #define PDB_SC_SWTRIG(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
  #define PDB_SC_PDBEIE_MASK                       (0x20000U)
  #define PDB_SC_PDBEIE_SHIFT                      (17U)
  /*! PDBEIE - PDB Sequence Error Interrupt Enable
   *  0b0..PDB sequence error interrupt disabled.
   *  0b1..PDB sequence error interrupt enabled.
   */
  #define PDB_SC_PDBEIE(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
  #define PDB_SC_LDMOD_MASK                        (0xC0000U)
  #define PDB_SC_LDMOD_SHIFT                       (18U)
  /*! LDMOD - Load Mode Select
   *  0b00..The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK.
   *  0b01..The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK.
   *  0b10..The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK.
   *  0b11..The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.
   */
  #define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
  /*! @} */
  
  /*! @name MOD - Modulus register */
  /*! @{ */
  #define PDB_MOD_MOD_MASK                         (0xFFFFU)
  #define PDB_MOD_MOD_SHIFT                        (0U)
  #define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
  /*! @} */
  
  /*! @name CNT - Counter register */
  /*! @{ */
  #define PDB_CNT_CNT_MASK                         (0xFFFFU)
  #define PDB_CNT_CNT_SHIFT                        (0U)
  #define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
  /*! @} */
  
  /*! @name IDLY - Interrupt Delay register */
  /*! @{ */
  #define PDB_IDLY_IDLY_MASK                       (0xFFFFU)
  #define PDB_IDLY_IDLY_SHIFT                      (0U)
  #define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
  /*! @} */
  
  /*! @name C1 - Channel n Control register 1 */
  /*! @{ */
  #define PDB_C1_EN_MASK                           (0xFFU)
  #define PDB_C1_EN_SHIFT                          (0U)
  /*! EN - PDB Channel Pre-Trigger Enable
   *  0b00000000..PDB channel's corresponding pre-trigger disabled.
   *  0b00000001..PDB channel's corresponding pre-trigger enabled.
   */
  #define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
  #define PDB_C1_TOS_MASK                          (0xFF00U)
  #define PDB_C1_TOS_SHIFT                         (8U)
  /*! TOS - PDB Channel Pre-Trigger Output Select
   *  0b00000000..PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
   *  0b00000001..PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
   */
  #define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
  #define PDB_C1_BB_MASK                           (0xFF0000U)
  #define PDB_C1_BB_SHIFT                          (16U)
  /*! BB - PDB Channel Pre-Trigger Back-to-Back Operation Enable
   *  0b00000000..PDB channel's corresponding pre-trigger back-to-back operation disabled.
   *  0b00000001..PDB channel's corresponding pre-trigger back-to-back operation enabled.
   */
  #define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
  /*! @} */
  
  /* The count of PDB_C1 */
  #define PDB_C1_COUNT                             (2U)
  
  /*! @name S - Channel n Status register */
  /*! @{ */
  #define PDB_S_ERR_MASK                           (0xFFU)
  #define PDB_S_ERR_SHIFT                          (0U)
  /*! ERR - PDB Channel Sequence Error Flags
   *  0b00000000..Sequence error not detected on PDB channel's corresponding pre-trigger.
   *  0b00000001..Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
   */
  #define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
  #define PDB_S_CF_MASK                            (0xFF0000U)
  #define PDB_S_CF_SHIFT                           (16U)
  #define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
  /*! @} */
  
  /* The count of PDB_S */
  #define PDB_S_COUNT                              (2U)
  
  /*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
  /*! @{ */
  #define PDB_DLY_DLY_MASK                         (0xFFFFU)
  #define PDB_DLY_DLY_SHIFT                        (0U)
  #define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
  /*! @} */
  
  /* The count of PDB_DLY */
  #define PDB_DLY_COUNT                            (2U)
  
  /* The count of PDB_DLY */
  #define PDB_DLY_COUNT2                           (2U)
  
  /*! @name INTC - DAC Interval Trigger n Control register */
  /*! @{ */
  #define PDB_INTC_TOE_MASK                        (0x1U)
  #define PDB_INTC_TOE_SHIFT                       (0U)
  /*! TOE - DAC Interval Trigger Enable
   *  0b0..DAC interval trigger disabled.
   *  0b1..DAC interval trigger enabled.
   */
  #define PDB_INTC_TOE(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
  #define PDB_INTC_EXT_MASK                        (0x2U)
  #define PDB_INTC_EXT_SHIFT                       (1U)
  /*! EXT - DAC External Trigger Input Enable
   *  0b0..DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
   *  0b1..DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger.
   */
  #define PDB_INTC_EXT(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
  /*! @} */
  
  /* The count of PDB_INTC */
  #define PDB_INTC_COUNT                           (1U)
  
  /*! @name INT - DAC Interval n register */
  /*! @{ */
  #define PDB_INT_INT_MASK                         (0xFFFFU)
  #define PDB_INT_INT_SHIFT                        (0U)
  #define PDB_INT_INT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
  /*! @} */
  
  /* The count of PDB_INT */
  #define PDB_INT_COUNT                            (1U)
  
  /*! @name POEN - Pulse-Out n Enable register */
  /*! @{ */
  #define PDB_POEN_POEN_MASK                       (0xFFU)
  #define PDB_POEN_POEN_SHIFT                      (0U)
  /*! POEN - PDB Pulse-Out Enable
   *  0b00000000..PDB Pulse-Out disabled
   *  0b00000001..PDB Pulse-Out enabled
   */
  #define PDB_POEN_POEN(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
  /*! @} */
  
  /*! @name PODLY - Pulse-Out n Delay register */
  /*! @{ */
  #define PDB_PODLY_DLY2_MASK                      (0xFFFFU)
  #define PDB_PODLY_DLY2_SHIFT                     (0U)
  #define PDB_PODLY_DLY2(x)                        (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
  #define PDB_PODLY_DLY1_MASK                      (0xFFFF0000U)
  #define PDB_PODLY_DLY1_SHIFT                     (16U)
  #define PDB_PODLY_DLY1(x)                        (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
  /*! @} */
  
  /* The count of PDB_PODLY */
  #define PDB_PODLY_COUNT                          (2U)
  
  
  /*!
   * @}
   */ /* end of group PDB_Register_Masks */
  
  
  /* PDB - Peripheral instance base addresses */
  /** Peripheral PDB0 base address */
  #define PDB0_BASE                                (0x40036000u)
  /** Peripheral PDB0 base pointer */
  #define PDB0                                     ((PDB_Type *)PDB0_BASE)
  /** Array initializer of PDB peripheral base addresses */
  #define PDB_BASE_ADDRS                           { PDB0_BASE }
  /** Array initializer of PDB peripheral base pointers */
  #define PDB_BASE_PTRS                            { PDB0 }
  /** Interrupt vectors for the PDB peripheral type */
  #define PDB_IRQS                                 { PDB0_IRQn }
  
  /*!
   * @}
   */ /* end of group PDB_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- PIT Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
   * @{
   */
  
  /** PIT - Register Layout Typedef */
  typedef struct {
    __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
         uint8_t RESERVED_0[252];
    struct {                                         /* offset: 0x100, array step: 0x10 */
      __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
      __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
      __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
      __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
    } CHANNEL[4];
  } PIT_Type;
  
  /* ----------------------------------------------------------------------------
     -- PIT Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PIT_Register_Masks PIT Register Masks
   * @{
   */
  
  /*! @name MCR - PIT Module Control Register */
  /*! @{ */
  #define PIT_MCR_FRZ_MASK                         (0x1U)
  #define PIT_MCR_FRZ_SHIFT                        (0U)
  /*! FRZ - Freeze
   *  0b0..Timers continue to run in Debug mode.
   *  0b1..Timers are stopped in Debug mode.
   */
  #define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
  #define PIT_MCR_MDIS_MASK                        (0x2U)
  #define PIT_MCR_MDIS_SHIFT                       (1U)
  /*! MDIS - Module Disable - (PIT section)
   *  0b0..Clock for standard PIT timers is enabled.
   *  0b1..Clock for standard PIT timers is disabled.
   */
  #define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
  /*! @} */
  
  /*! @name LDVAL - Timer Load Value Register */
  /*! @{ */
  #define PIT_LDVAL_TSV_MASK                       (0xFFFFFFFFU)
  #define PIT_LDVAL_TSV_SHIFT                      (0U)
  #define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
  /*! @} */
  
  /* The count of PIT_LDVAL */
  #define PIT_LDVAL_COUNT                          (4U)
  
  /*! @name CVAL - Current Timer Value Register */
  /*! @{ */
  #define PIT_CVAL_TVL_MASK                        (0xFFFFFFFFU)
  #define PIT_CVAL_TVL_SHIFT                       (0U)
  #define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
  /*! @} */
  
  /* The count of PIT_CVAL */
  #define PIT_CVAL_COUNT                           (4U)
  
  /*! @name TCTRL - Timer Control Register */
  /*! @{ */
  #define PIT_TCTRL_TEN_MASK                       (0x1U)
  #define PIT_TCTRL_TEN_SHIFT                      (0U)
  /*! TEN - Timer Enable
   *  0b0..Timer n is disabled.
   *  0b1..Timer n is enabled.
   */
  #define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
  #define PIT_TCTRL_TIE_MASK                       (0x2U)
  #define PIT_TCTRL_TIE_SHIFT                      (1U)
  /*! TIE - Timer Interrupt Enable
   *  0b0..Interrupt requests from Timer n are disabled.
   *  0b1..Interrupt will be requested whenever TIF is set.
   */
  #define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
  #define PIT_TCTRL_CHN_MASK                       (0x4U)
  #define PIT_TCTRL_CHN_SHIFT                      (2U)
  /*! CHN - Chain Mode
   *  0b0..Timer is not chained.
   *  0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
   */
  #define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
  /*! @} */
  
  /* The count of PIT_TCTRL */
  #define PIT_TCTRL_COUNT                          (4U)
  
  /*! @name TFLG - Timer Flag Register */
  /*! @{ */
  #define PIT_TFLG_TIF_MASK                        (0x1U)
  #define PIT_TFLG_TIF_SHIFT                       (0U)
  /*! TIF - Timer Interrupt Flag
   *  0b0..Timeout has not yet occurred.
   *  0b1..Timeout has occurred.
   */
  #define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
  /*! @} */
  
  /* The count of PIT_TFLG */
  #define PIT_TFLG_COUNT                           (4U)
  
  
  /*!
   * @}
   */ /* end of group PIT_Register_Masks */
  
  
  /* PIT - Peripheral instance base addresses */
  /** Peripheral PIT base address */
  #define PIT_BASE                                 (0x40037000u)
  /** Peripheral PIT base pointer */
  #define PIT                                      ((PIT_Type *)PIT_BASE)
  /** Array initializer of PIT peripheral base addresses */
  #define PIT_BASE_ADDRS                           { PIT_BASE }
  /** Array initializer of PIT peripheral base pointers */
  #define PIT_BASE_PTRS                            { PIT }
  /** Interrupt vectors for the PIT peripheral type */
  #define PIT_IRQS                                 { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
  
  /*!
   * @}
   */ /* end of group PIT_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- PMC Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
   * @{
   */
  
  /** PMC - Register Layout Typedef */
  typedef struct {
    __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
    __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
    __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
  } PMC_Type;
  
  /* ----------------------------------------------------------------------------
     -- PMC Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PMC_Register_Masks PMC Register Masks
   * @{
   */
  
  /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
  /*! @{ */
  #define PMC_LVDSC1_LVDV_MASK                     (0x3U)
  #define PMC_LVDSC1_LVDV_SHIFT                    (0U)
  /*! LVDV - Low-Voltage Detect Voltage Select
   *  0b00..Low trip point selected (V LVD = V LVDL )
   *  0b01..High trip point selected (V LVD = V LVDH )
   *  0b10..Reserved
   *  0b11..Reserved
   */
  #define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
  #define PMC_LVDSC1_LVDRE_MASK                    (0x10U)
  #define PMC_LVDSC1_LVDRE_SHIFT                   (4U)
  /*! LVDRE - Low-Voltage Detect Reset Enable
   *  0b0..LVDF does not generate hardware resets
   *  0b1..Force an MCU reset when LVDF = 1
   */
  #define PMC_LVDSC1_LVDRE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
  #define PMC_LVDSC1_LVDIE_MASK                    (0x20U)
  #define PMC_LVDSC1_LVDIE_SHIFT                   (5U)
  /*! LVDIE - Low-Voltage Detect Interrupt Enable
   *  0b0..Hardware interrupt disabled (use polling)
   *  0b1..Request a hardware interrupt when LVDF = 1
   */
  #define PMC_LVDSC1_LVDIE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
  #define PMC_LVDSC1_LVDACK_MASK                   (0x40U)
  #define PMC_LVDSC1_LVDACK_SHIFT                  (6U)
  #define PMC_LVDSC1_LVDACK(x)                     (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
  #define PMC_LVDSC1_LVDF_MASK                     (0x80U)
  #define PMC_LVDSC1_LVDF_SHIFT                    (7U)
  /*! LVDF - Low-Voltage Detect Flag
   *  0b0..Low-voltage event not detected
   *  0b1..Low-voltage event detected
   */
  #define PMC_LVDSC1_LVDF(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
  /*! @} */
  
  /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
  /*! @{ */
  #define PMC_LVDSC2_LVWV_MASK                     (0x3U)
  #define PMC_LVDSC2_LVWV_SHIFT                    (0U)
  /*! LVWV - Low-Voltage Warning Voltage Select
   *  0b00..Low trip point selected (VLVW = VLVW1)
   *  0b01..Mid 1 trip point selected (VLVW = VLVW2)
   *  0b10..Mid 2 trip point selected (VLVW = VLVW3)
   *  0b11..High trip point selected (VLVW = VLVW4)
   */
  #define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
  #define PMC_LVDSC2_LVWIE_MASK                    (0x20U)
  #define PMC_LVDSC2_LVWIE_SHIFT                   (5U)
  /*! LVWIE - Low-Voltage Warning Interrupt Enable
   *  0b0..Hardware interrupt disabled (use polling)
   *  0b1..Request a hardware interrupt when LVWF = 1
   */
  #define PMC_LVDSC2_LVWIE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
  #define PMC_LVDSC2_LVWACK_MASK                   (0x40U)
  #define PMC_LVDSC2_LVWACK_SHIFT                  (6U)
  #define PMC_LVDSC2_LVWACK(x)                     (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
  #define PMC_LVDSC2_LVWF_MASK                     (0x80U)
  #define PMC_LVDSC2_LVWF_SHIFT                    (7U)
  /*! LVWF - Low-Voltage Warning Flag
   *  0b0..Low-voltage warning event not detected
   *  0b1..Low-voltage warning event detected
   */
  #define PMC_LVDSC2_LVWF(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
  /*! @} */
  
  /*! @name REGSC - Regulator Status And Control register */
  /*! @{ */
  #define PMC_REGSC_BGBE_MASK                      (0x1U)
  #define PMC_REGSC_BGBE_SHIFT                     (0U)
  /*! BGBE - Bandgap Buffer Enable
   *  0b0..Bandgap buffer not enabled
   *  0b1..Bandgap buffer enabled
   */
  #define PMC_REGSC_BGBE(x)                        (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
  #define PMC_REGSC_REGONS_MASK                    (0x4U)
  #define PMC_REGSC_REGONS_SHIFT                   (2U)
  /*! REGONS - Regulator In Run Regulation Status
   *  0b0..Regulator is in stop regulation or in transition to/from it
   *  0b1..Regulator is in run regulation
   */
  #define PMC_REGSC_REGONS(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
  #define PMC_REGSC_ACKISO_MASK                    (0x8U)
  #define PMC_REGSC_ACKISO_SHIFT                   (3U)
  /*! ACKISO - Acknowledge Isolation
   *  0b0..Peripherals and I/O pads are in normal run state.
   *  0b1..Certain peripherals and I/O pads are in an isolated and latched state.
   */
  #define PMC_REGSC_ACKISO(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
  #define PMC_REGSC_BGEN_MASK                      (0x10U)
  #define PMC_REGSC_BGEN_SHIFT                     (4U)
  /*! BGEN - Bandgap Enable In VLPx Operation
   *  0b0..Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
   *  0b1..Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
   */
  #define PMC_REGSC_BGEN(x)                        (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group PMC_Register_Masks */
  
  
  /* PMC - Peripheral instance base addresses */
  /** Peripheral PMC base address */
  #define PMC_BASE                                 (0x4007D000u)
  /** Peripheral PMC base pointer */
  #define PMC                                      ((PMC_Type *)PMC_BASE)
  /** Array initializer of PMC peripheral base addresses */
  #define PMC_BASE_ADDRS                           { PMC_BASE }
  /** Array initializer of PMC peripheral base pointers */
  #define PMC_BASE_PTRS                            { PMC }
  /** Interrupt vectors for the PMC peripheral type */
  #define PMC_IRQS                                 { LVD_LVW_IRQn }
  
  /*!
   * @}
   */ /* end of group PMC_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- PORT Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
   * @{
   */
  
  /** PORT - Register Layout Typedef */
  typedef struct {
    __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
    __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
    __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
         uint8_t RESERVED_0[24];
    __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
         uint8_t RESERVED_1[28];
    __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
    __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
    __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
  } PORT_Type;
  
  /* ----------------------------------------------------------------------------
     -- PORT Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup PORT_Register_Masks PORT Register Masks
   * @{
   */
  
  /*! @name PCR - Pin Control Register n */
  /*! @{ */
  #define PORT_PCR_PS_MASK                         (0x1U)
  #define PORT_PCR_PS_SHIFT                        (0U)
  /*! PS - Pull Select
   *  0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
   *  0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
   */
  #define PORT_PCR_PS(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
  #define PORT_PCR_PE_MASK                         (0x2U)
  #define PORT_PCR_PE_SHIFT                        (1U)
  /*! PE - Pull Enable
   *  0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin.
   *  0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
   */
  #define PORT_PCR_PE(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
  #define PORT_PCR_SRE_MASK                        (0x4U)
  #define PORT_PCR_SRE_SHIFT                       (2U)
  /*! SRE - Slew Rate Enable
   *  0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
   *  0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
   */
  #define PORT_PCR_SRE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
  #define PORT_PCR_PFE_MASK                        (0x10U)
  #define PORT_PCR_PFE_SHIFT                       (4U)
  /*! PFE - Passive Filter Enable
   *  0b0..Passive input filter is disabled on the corresponding pin.
   *  0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
   */
  #define PORT_PCR_PFE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
  #define PORT_PCR_ODE_MASK                        (0x20U)
  #define PORT_PCR_ODE_SHIFT                       (5U)
  /*! ODE - Open Drain Enable
   *  0b0..Open drain output is disabled on the corresponding pin.
   *  0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
   */
  #define PORT_PCR_ODE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
  #define PORT_PCR_DSE_MASK                        (0x40U)
  #define PORT_PCR_DSE_SHIFT                       (6U)
  /*! DSE - Drive Strength Enable
   *  0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
   *  0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
   */
  #define PORT_PCR_DSE(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
  #define PORT_PCR_MUX_MASK                        (0x700U)
  #define PORT_PCR_MUX_SHIFT                       (8U)
  /*! MUX - Pin Mux Control
   *  0b000..Pin disabled (analog).
   *  0b001..Alternative 1 (GPIO).
   *  0b010..Alternative 2 (chip-specific).
   *  0b011..Alternative 3 (chip-specific).
   *  0b100..Alternative 4 (chip-specific).
   *  0b101..Alternative 5 (chip-specific).
   *  0b110..Alternative 6 (chip-specific).
   *  0b111..Alternative 7 (chip-specific).
   */
  #define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
  #define PORT_PCR_LK_MASK                         (0x8000U)
  #define PORT_PCR_LK_SHIFT                        (15U)
  /*! LK - Lock Register
   *  0b0..Pin Control Register fields [15:0] are not locked.
   *  0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
   */
  #define PORT_PCR_LK(x)                           (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
  #define PORT_PCR_IRQC_MASK                       (0xF0000U)
  #define PORT_PCR_IRQC_SHIFT                      (16U)
  /*! IRQC - Interrupt Configuration
   *  0b0000..Interrupt/DMA request disabled.
   *  0b0001..DMA request on rising edge.
   *  0b0010..DMA request on falling edge.
   *  0b0011..DMA request on either edge.
   *  0b1000..Interrupt when logic 0.
   *  0b1001..Interrupt on rising-edge.
   *  0b1010..Interrupt on falling-edge.
   *  0b1011..Interrupt on either edge.
   *  0b1100..Interrupt when logic 1.
   */
  #define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
  #define PORT_PCR_ISF_MASK                        (0x1000000U)
  #define PORT_PCR_ISF_SHIFT                       (24U)
  /*! ISF - Interrupt Status Flag
   *  0b0..Configured interrupt is not detected.
   *  0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
   */
  #define PORT_PCR_ISF(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
  /*! @} */
  
  /* The count of PORT_PCR */
  #define PORT_PCR_COUNT                           (32U)
  
  /*! @name GPCLR - Global Pin Control Low Register */
  /*! @{ */
  #define PORT_GPCLR_GPWD_MASK                     (0xFFFFU)
  #define PORT_GPCLR_GPWD_SHIFT                    (0U)
  #define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
  #define PORT_GPCLR_GPWE_MASK                     (0xFFFF0000U)
  #define PORT_GPCLR_GPWE_SHIFT                    (16U)
  /*! GPWE - Global Pin Write Enable
   *  0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
   *  0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
   */
  #define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
  /*! @} */
  
  /*! @name GPCHR - Global Pin Control High Register */
  /*! @{ */
  #define PORT_GPCHR_GPWD_MASK                     (0xFFFFU)
  #define PORT_GPCHR_GPWD_SHIFT                    (0U)
  #define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
  #define PORT_GPCHR_GPWE_MASK                     (0xFFFF0000U)
  #define PORT_GPCHR_GPWE_SHIFT                    (16U)
  /*! GPWE - Global Pin Write Enable
   *  0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
   *  0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
   */
  #define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
  /*! @} */
  
  /*! @name ISFR - Interrupt Status Flag Register */
  /*! @{ */
  #define PORT_ISFR_ISF_MASK                       (0xFFFFFFFFU)
  #define PORT_ISFR_ISF_SHIFT                      (0U)
  /*! ISF - Interrupt Status Flag
   *  0b00000000000000000000000000000000..Configured interrupt is not detected.
   *  0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
   */
  #define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
  /*! @} */
  
  /*! @name DFER - Digital Filter Enable Register */
  /*! @{ */
  #define PORT_DFER_DFE_MASK                       (0xFFFFFFFFU)
  #define PORT_DFER_DFE_SHIFT                      (0U)
  /*! DFE - Digital Filter Enable
   *  0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
   *  0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
   */
  #define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
  /*! @} */
  
  /*! @name DFCR - Digital Filter Clock Register */
  /*! @{ */
  #define PORT_DFCR_CS_MASK                        (0x1U)
  #define PORT_DFCR_CS_SHIFT                       (0U)
  /*! CS - Clock Source
   *  0b0..Digital filters are clocked by the bus clock.
   *  0b1..Digital filters are clocked by the 1 kHz LPO clock.
   */
  #define PORT_DFCR_CS(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
  /*! @} */
  
  /*! @name DFWR - Digital Filter Width Register */
  /*! @{ */
  #define PORT_DFWR_FILT_MASK                      (0x1FU)
  #define PORT_DFWR_FILT_SHIFT                     (0U)
  #define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group PORT_Register_Masks */
  
  
  /* PORT - Peripheral instance base addresses */
  /** Peripheral PORTA base address */
  #define PORTA_BASE                               (0x40049000u)
  /** Peripheral PORTA base pointer */
  #define PORTA                                    ((PORT_Type *)PORTA_BASE)
  /** Peripheral PORTB base address */
  #define PORTB_BASE                               (0x4004A000u)
  /** Peripheral PORTB base pointer */
  #define PORTB                                    ((PORT_Type *)PORTB_BASE)
  /** Peripheral PORTC base address */
  #define PORTC_BASE                               (0x4004B000u)
  /** Peripheral PORTC base pointer */
  #define PORTC                                    ((PORT_Type *)PORTC_BASE)
  /** Peripheral PORTD base address */
  #define PORTD_BASE                               (0x4004C000u)
  /** Peripheral PORTD base pointer */
  #define PORTD                                    ((PORT_Type *)PORTD_BASE)
  /** Peripheral PORTE base address */
  #define PORTE_BASE                               (0x4004D000u)
  /** Peripheral PORTE base pointer */
  #define PORTE                                    ((PORT_Type *)PORTE_BASE)
  /** Array initializer of PORT peripheral base addresses */
  #define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
  /** Array initializer of PORT peripheral base pointers */
  #define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD, PORTE }
  /** Interrupt vectors for the PORT peripheral type */
  #define PORT_IRQS                                { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
  
  /*!
   * @}
   */ /* end of group PORT_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- RCM Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
   * @{
   */
  
  /** RCM - Register Layout Typedef */
  typedef struct {
    __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
    __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
         uint8_t RESERVED_0[2];
    __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
    __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
         uint8_t RESERVED_1[1];
    __I  uint8_t MR;                                 /**< Mode Register, offset: 0x7 */
    __IO uint8_t SSRS0;                              /**< Sticky System Reset Status Register 0, offset: 0x8 */
    __IO uint8_t SSRS1;                              /**< Sticky System Reset Status Register 1, offset: 0x9 */
  } RCM_Type;
  
  /* ----------------------------------------------------------------------------
     -- RCM Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RCM_Register_Masks RCM Register Masks
   * @{
   */
  
  /*! @name SRS0 - System Reset Status Register 0 */
  /*! @{ */
  #define RCM_SRS0_WAKEUP_MASK                     (0x1U)
  #define RCM_SRS0_WAKEUP_SHIFT                    (0U)
  /*! WAKEUP - Low Leakage Wakeup Reset
   *  0b0..Reset not caused by LLWU module wakeup source
   *  0b1..Reset caused by LLWU module wakeup source
   */
  #define RCM_SRS0_WAKEUP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
  #define RCM_SRS0_LVD_MASK                        (0x2U)
  #define RCM_SRS0_LVD_SHIFT                       (1U)
  /*! LVD - Low-Voltage Detect Reset
   *  0b0..Reset not caused by LVD trip or POR
   *  0b1..Reset caused by LVD trip or POR
   */
  #define RCM_SRS0_LVD(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
  #define RCM_SRS0_LOC_MASK                        (0x4U)
  #define RCM_SRS0_LOC_SHIFT                       (2U)
  /*! LOC - Loss-of-Clock Reset
   *  0b0..Reset not caused by a loss of external clock.
   *  0b1..Reset caused by a loss of external clock.
   */
  #define RCM_SRS0_LOC(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
  #define RCM_SRS0_WDOG_MASK                       (0x20U)
  #define RCM_SRS0_WDOG_SHIFT                      (5U)
  /*! WDOG - Watchdog
   *  0b0..Reset not caused by watchdog timeout
   *  0b1..Reset caused by watchdog timeout
   */
  #define RCM_SRS0_WDOG(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
  #define RCM_SRS0_PIN_MASK                        (0x40U)
  #define RCM_SRS0_PIN_SHIFT                       (6U)
  /*! PIN - External Reset Pin
   *  0b0..Reset not caused by external reset pin
   *  0b1..Reset caused by external reset pin
   */
  #define RCM_SRS0_PIN(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
  #define RCM_SRS0_POR_MASK                        (0x80U)
  #define RCM_SRS0_POR_SHIFT                       (7U)
  /*! POR - Power-On Reset
   *  0b0..Reset not caused by POR
   *  0b1..Reset caused by POR
   */
  #define RCM_SRS0_POR(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
  /*! @} */
  
  /*! @name SRS1 - System Reset Status Register 1 */
  /*! @{ */
  #define RCM_SRS1_JTAG_MASK                       (0x1U)
  #define RCM_SRS1_JTAG_SHIFT                      (0U)
  /*! JTAG - JTAG Generated Reset
   *  0b0..Reset not caused by JTAG
   *  0b1..Reset caused by JTAG
   */
  #define RCM_SRS1_JTAG(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
  #define RCM_SRS1_LOCKUP_MASK                     (0x2U)
  #define RCM_SRS1_LOCKUP_SHIFT                    (1U)
  /*! LOCKUP - Core Lockup
   *  0b0..Reset not caused by core LOCKUP event
   *  0b1..Reset caused by core LOCKUP event
   */
  #define RCM_SRS1_LOCKUP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
  #define RCM_SRS1_SW_MASK                         (0x4U)
  #define RCM_SRS1_SW_SHIFT                        (2U)
  /*! SW - Software
   *  0b0..Reset not caused by software setting of SYSRESETREQ bit
   *  0b1..Reset caused by software setting of SYSRESETREQ bit
   */
  #define RCM_SRS1_SW(x)                           (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
  #define RCM_SRS1_MDM_AP_MASK                     (0x8U)
  #define RCM_SRS1_MDM_AP_SHIFT                    (3U)
  /*! MDM_AP - MDM-AP System Reset Request
   *  0b0..Reset not caused by host debugger system setting of the System Reset Request bit
   *  0b1..Reset caused by host debugger system setting of the System Reset Request bit
   */
  #define RCM_SRS1_MDM_AP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
  #define RCM_SRS1_EZPT_MASK                       (0x10U)
  #define RCM_SRS1_EZPT_SHIFT                      (4U)
  /*! EZPT - EzPort Reset
   *  0b0..Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode
   *  0b1..Reset caused by EzPort receiving the RESET command while the device is in EzPort mode
   */
  #define RCM_SRS1_EZPT(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
  #define RCM_SRS1_SACKERR_MASK                    (0x20U)
  #define RCM_SRS1_SACKERR_SHIFT                   (5U)
  /*! SACKERR - Stop Mode Acknowledge Error Reset
   *  0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
   *  0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
   */
  #define RCM_SRS1_SACKERR(x)                      (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
  /*! @} */
  
  /*! @name RPFC - Reset Pin Filter Control register */
  /*! @{ */
  #define RCM_RPFC_RSTFLTSRW_MASK                  (0x3U)
  #define RCM_RPFC_RSTFLTSRW_SHIFT                 (0U)
  /*! RSTFLTSRW - Reset Pin Filter Select in Run and Wait Modes
   *  0b00..All filtering disabled
   *  0b01..Bus clock filter enabled for normal operation
   *  0b10..LPO clock filter enabled for normal operation
   *  0b11..Reserved
   */
  #define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
  #define RCM_RPFC_RSTFLTSS_MASK                   (0x4U)
  #define RCM_RPFC_RSTFLTSS_SHIFT                  (2U)
  /*! RSTFLTSS - Reset Pin Filter Select in Stop Mode
   *  0b0..All filtering disabled
   *  0b1..LPO clock filter enabled
   */
  #define RCM_RPFC_RSTFLTSS(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
  /*! @} */
  
  /*! @name RPFW - Reset Pin Filter Width register */
  /*! @{ */
  #define RCM_RPFW_RSTFLTSEL_MASK                  (0x1FU)
  #define RCM_RPFW_RSTFLTSEL_SHIFT                 (0U)
  /*! RSTFLTSEL - Reset Pin Filter Bus Clock Select
   *  0b00000..Bus clock filter count is 1
   *  0b00001..Bus clock filter count is 2
   *  0b00010..Bus clock filter count is 3
   *  0b00011..Bus clock filter count is 4
   *  0b00100..Bus clock filter count is 5
   *  0b00101..Bus clock filter count is 6
   *  0b00110..Bus clock filter count is 7
   *  0b00111..Bus clock filter count is 8
   *  0b01000..Bus clock filter count is 9
   *  0b01001..Bus clock filter count is 10
   *  0b01010..Bus clock filter count is 11
   *  0b01011..Bus clock filter count is 12
   *  0b01100..Bus clock filter count is 13
   *  0b01101..Bus clock filter count is 14
   *  0b01110..Bus clock filter count is 15
   *  0b01111..Bus clock filter count is 16
   *  0b10000..Bus clock filter count is 17
   *  0b10001..Bus clock filter count is 18
   *  0b10010..Bus clock filter count is 19
   *  0b10011..Bus clock filter count is 20
   *  0b10100..Bus clock filter count is 21
   *  0b10101..Bus clock filter count is 22
   *  0b10110..Bus clock filter count is 23
   *  0b10111..Bus clock filter count is 24
   *  0b11000..Bus clock filter count is 25
   *  0b11001..Bus clock filter count is 26
   *  0b11010..Bus clock filter count is 27
   *  0b11011..Bus clock filter count is 28
   *  0b11100..Bus clock filter count is 29
   *  0b11101..Bus clock filter count is 30
   *  0b11110..Bus clock filter count is 31
   *  0b11111..Bus clock filter count is 32
   */
  #define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
  /*! @} */
  
  /*! @name MR - Mode Register */
  /*! @{ */
  #define RCM_MR_EZP_MS_MASK                       (0x2U)
  #define RCM_MR_EZP_MS_SHIFT                      (1U)
  /*! EZP_MS - EZP_MS_B pin state
   *  0b0..Pin deasserted (logic 1)
   *  0b1..Pin asserted (logic 0)
   */
  #define RCM_MR_EZP_MS(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
  /*! @} */
  
  /*! @name SSRS0 - Sticky System Reset Status Register 0 */
  /*! @{ */
  #define RCM_SSRS0_SWAKEUP_MASK                   (0x1U)
  #define RCM_SSRS0_SWAKEUP_SHIFT                  (0U)
  /*! SWAKEUP - Sticky Low Leakage Wakeup Reset
   *  0b0..Reset not caused by LLWU module wakeup source
   *  0b1..Reset caused by LLWU module wakeup source
   */
  #define RCM_SSRS0_SWAKEUP(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
  #define RCM_SSRS0_SLVD_MASK                      (0x2U)
  #define RCM_SSRS0_SLVD_SHIFT                     (1U)
  /*! SLVD - Sticky Low-Voltage Detect Reset
   *  0b0..Reset not caused by LVD trip or POR
   *  0b1..Reset caused by LVD trip or POR
   */
  #define RCM_SSRS0_SLVD(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
  #define RCM_SSRS0_SLOC_MASK                      (0x4U)
  #define RCM_SSRS0_SLOC_SHIFT                     (2U)
  /*! SLOC - Sticky Loss-of-Clock Reset
   *  0b0..Reset not caused by a loss of external clock.
   *  0b1..Reset caused by a loss of external clock.
   */
  #define RCM_SSRS0_SLOC(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
  #define RCM_SSRS0_SWDOG_MASK                     (0x20U)
  #define RCM_SSRS0_SWDOG_SHIFT                    (5U)
  /*! SWDOG - Sticky Watchdog
   *  0b0..Reset not caused by watchdog timeout
   *  0b1..Reset caused by watchdog timeout
   */
  #define RCM_SSRS0_SWDOG(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
  #define RCM_SSRS0_SPIN_MASK                      (0x40U)
  #define RCM_SSRS0_SPIN_SHIFT                     (6U)
  /*! SPIN - Sticky External Reset Pin
   *  0b0..Reset not caused by external reset pin
   *  0b1..Reset caused by external reset pin
   */
  #define RCM_SSRS0_SPIN(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
  #define RCM_SSRS0_SPOR_MASK                      (0x80U)
  #define RCM_SSRS0_SPOR_SHIFT                     (7U)
  /*! SPOR - Sticky Power-On Reset
   *  0b0..Reset not caused by POR
   *  0b1..Reset caused by POR
   */
  #define RCM_SSRS0_SPOR(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
  /*! @} */
  
  /*! @name SSRS1 - Sticky System Reset Status Register 1 */
  /*! @{ */
  #define RCM_SSRS1_SJTAG_MASK                     (0x1U)
  #define RCM_SSRS1_SJTAG_SHIFT                    (0U)
  /*! SJTAG - Sticky JTAG Generated Reset
   *  0b0..Reset not caused by JTAG
   *  0b1..Reset caused by JTAG
   */
  #define RCM_SSRS1_SJTAG(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
  #define RCM_SSRS1_SLOCKUP_MASK                   (0x2U)
  #define RCM_SSRS1_SLOCKUP_SHIFT                  (1U)
  /*! SLOCKUP - Sticky Core Lockup
   *  0b0..Reset not caused by core LOCKUP event
   *  0b1..Reset caused by core LOCKUP event
   */
  #define RCM_SSRS1_SLOCKUP(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
  #define RCM_SSRS1_SSW_MASK                       (0x4U)
  #define RCM_SSRS1_SSW_SHIFT                      (2U)
  /*! SSW - Sticky Software
   *  0b0..Reset not caused by software setting of SYSRESETREQ bit
   *  0b1..Reset caused by software setting of SYSRESETREQ bit
   */
  #define RCM_SSRS1_SSW(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
  #define RCM_SSRS1_SMDM_AP_MASK                   (0x8U)
  #define RCM_SSRS1_SMDM_AP_SHIFT                  (3U)
  /*! SMDM_AP - Sticky MDM-AP System Reset Request
   *  0b0..Reset not caused by host debugger system setting of the System Reset Request bit
   *  0b1..Reset caused by host debugger system setting of the System Reset Request bit
   */
  #define RCM_SSRS1_SMDM_AP(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
  #define RCM_SSRS1_SEZPT_MASK                     (0x10U)
  #define RCM_SSRS1_SEZPT_SHIFT                    (4U)
  /*! SEZPT - Sticky EzPort Reset
   *  0b0..Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode
   *  0b1..Reset caused by EzPort receiving the RESET command while the device is in EzPort mode
   */
  #define RCM_SSRS1_SEZPT(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SEZPT_SHIFT)) & RCM_SSRS1_SEZPT_MASK)
  #define RCM_SSRS1_SSACKERR_MASK                  (0x20U)
  #define RCM_SSRS1_SSACKERR_SHIFT                 (5U)
  /*! SSACKERR - Sticky Stop Mode Acknowledge Error Reset
   *  0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
   *  0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
   */
  #define RCM_SSRS1_SSACKERR(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group RCM_Register_Masks */
  
  
  /* RCM - Peripheral instance base addresses */
  /** Peripheral RCM base address */
  #define RCM_BASE                                 (0x4007F000u)
  /** Peripheral RCM base pointer */
  #define RCM                                      ((RCM_Type *)RCM_BASE)
  /** Array initializer of RCM peripheral base addresses */
  #define RCM_BASE_ADDRS                           { RCM_BASE }
  /** Array initializer of RCM peripheral base pointers */
  #define RCM_BASE_PTRS                            { RCM }
  
  /*!
   * @}
   */ /* end of group RCM_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- RFSYS Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
   * @{
   */
  
  /** RFSYS - Register Layout Typedef */
  typedef struct {
    __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
  } RFSYS_Type;
  
  /* ----------------------------------------------------------------------------
     -- RFSYS Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
   * @{
   */
  
  /*! @name REG - Register file register */
  /*! @{ */
  #define RFSYS_REG_LL_MASK                        (0xFFU)
  #define RFSYS_REG_LL_SHIFT                       (0U)
  #define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
  #define RFSYS_REG_LH_MASK                        (0xFF00U)
  #define RFSYS_REG_LH_SHIFT                       (8U)
  #define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
  #define RFSYS_REG_HL_MASK                        (0xFF0000U)
  #define RFSYS_REG_HL_SHIFT                       (16U)
  #define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
  #define RFSYS_REG_HH_MASK                        (0xFF000000U)
  #define RFSYS_REG_HH_SHIFT                       (24U)
  #define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
  /*! @} */
  
  /* The count of RFSYS_REG */
  #define RFSYS_REG_COUNT                          (8U)
  
  
  /*!
   * @}
   */ /* end of group RFSYS_Register_Masks */
  
  
  /* RFSYS - Peripheral instance base addresses */
  /** Peripheral RFSYS base address */
  #define RFSYS_BASE                               (0x40041000u)
  /** Peripheral RFSYS base pointer */
  #define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
  /** Array initializer of RFSYS peripheral base addresses */
  #define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
  /** Array initializer of RFSYS peripheral base pointers */
  #define RFSYS_BASE_PTRS                          { RFSYS }
  
  /*!
   * @}
   */ /* end of group RFSYS_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- SIM Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
   * @{
   */
  
  /** SIM - Register Layout Typedef */
  typedef struct {
    __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
         uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
         uint8_t RESERVED_0[4092];
    __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
         uint8_t RESERVED_1[4];
    __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
    __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
         uint8_t RESERVED_2[4];
    __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
    __IO uint32_t SOPT8;                             /**< System Options Register 8, offset: 0x101C */
         uint8_t RESERVED_3[4];
    __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
         uint8_t RESERVED_4[12];
    __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
    __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
    __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
    __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
    __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
         uint8_t RESERVED_5[4];
    __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
    __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
    __I  uint32_t UIDH;                              /**< Unique Identification Register High, offset: 0x1054 */
    __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
    __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
    __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
  } SIM_Type;
  
  /* ----------------------------------------------------------------------------
     -- SIM Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SIM_Register_Masks SIM Register Masks
   * @{
   */
  
  /*! @name SOPT1 - System Options Register 1 */
  /*! @{ */
  #define SIM_SOPT1_RAMSIZE_MASK                   (0xF000U)
  #define SIM_SOPT1_RAMSIZE_SHIFT                  (12U)
  /*! RAMSIZE - RAM size
   *  0b0001..8 KB
   *  0b0011..16 KB
   *  0b0100..24 KB
   *  0b0101..32 KB
   *  0b0110..48 KB
   *  0b0111..64 KB
   *  0b1000..96 KB
   *  0b1001..128 KB
   *  0b1011..256 KB
   */
  #define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
  #define SIM_SOPT1_OSC32KOUT_MASK                 (0x30000U)
  #define SIM_SOPT1_OSC32KOUT_SHIFT                (16U)
  /*! OSC32KOUT - 32K Oscillator Clock Output
   *  0b00..ERCLK32K is not output.
   *  0b01..ERCLK32K is output on PTE0.
   *  0b10..ERCLK32K is output on PTE26.
   *  0b11..Reserved.
   */
  #define SIM_SOPT1_OSC32KOUT(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK)
  #define SIM_SOPT1_OSC32KSEL_MASK                 (0xC0000U)
  #define SIM_SOPT1_OSC32KSEL_SHIFT                (18U)
  /*! OSC32KSEL - 32K oscillator clock select
   *  0b00..System oscillator (OSC32KCLK)
   *  0b01..Reserved
   *  0b10..Reserved
   *  0b11..LPO 1 kHz
   */
  #define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
  /*! @} */
  
  /*! @name SOPT2 - System Options Register 2 */
  /*! @{ */
  #define SIM_SOPT2_CLKOUTSEL_MASK                 (0xE0U)
  #define SIM_SOPT2_CLKOUTSEL_SHIFT                (5U)
  /*! CLKOUTSEL - CLKOUT select
   *  0b000..Reserved
   *  0b001..Reserved
   *  0b010..Flash clock
   *  0b011..LPO clock (1 kHz)
   *  0b100..MCGIRCLK
   *  0b101..Reserved
   *  0b110..OSCERCLK0
   *  0b111..IRC 48 MHz clock
   */
  #define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
  #define SIM_SOPT2_TRACECLKSEL_MASK               (0x1000U)
  #define SIM_SOPT2_TRACECLKSEL_SHIFT              (12U)
  /*! TRACECLKSEL - Debug trace clock select
   *  0b0..MCGOUTCLK
   *  0b1..Core/system clock
   */
  #define SIM_SOPT2_TRACECLKSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
  #define SIM_SOPT2_PLLFLLSEL_MASK                 (0x30000U)
  #define SIM_SOPT2_PLLFLLSEL_SHIFT                (16U)
  /*! PLLFLLSEL - PLL/FLL clock select
   *  0b00..MCGFLLCLK clock
   *  0b01..Reserved
   *  0b10..Reserved
   *  0b11..IRC48 MHz clock
   */
  #define SIM_SOPT2_PLLFLLSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
  #define SIM_SOPT2_LPUARTSRC_MASK                 (0xC000000U)
  #define SIM_SOPT2_LPUARTSRC_SHIFT                (26U)
  /*! LPUARTSRC - LPUART clock source select
   *  0b00..Clock disabled
   *  0b01..MCGFLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL].
   *  0b10..OSCERCLK clock
   *  0b11..MCGIRCLK clock
   */
  #define SIM_SOPT2_LPUARTSRC(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
  /*! @} */
  
  /*! @name SOPT4 - System Options Register 4 */
  /*! @{ */
  #define SIM_SOPT4_FTM0FLT0_MASK                  (0x1U)
  #define SIM_SOPT4_FTM0FLT0_SHIFT                 (0U)
  /*! FTM0FLT0 - FTM0 Fault 0 Select
   *  0b0..FTM0_FLT0 pin
   *  0b1..CMP0 out
   */
  #define SIM_SOPT4_FTM0FLT0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
  #define SIM_SOPT4_FTM0FLT1_MASK                  (0x2U)
  #define SIM_SOPT4_FTM0FLT1_SHIFT                 (1U)
  /*! FTM0FLT1 - FTM0 Fault 1 Select
   *  0b0..FTM0_FLT1 pin
   *  0b1..CMP1 out
   */
  #define SIM_SOPT4_FTM0FLT1(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
  #define SIM_SOPT4_FTM1FLT0_MASK                  (0x10U)
  #define SIM_SOPT4_FTM1FLT0_SHIFT                 (4U)
  /*! FTM1FLT0 - FTM1 Fault 0 Select
   *  0b0..FTM1_FLT0 pin
   *  0b1..CMP0 out
   */
  #define SIM_SOPT4_FTM1FLT0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
  #define SIM_SOPT4_FTM2FLT0_MASK                  (0x100U)
  #define SIM_SOPT4_FTM2FLT0_SHIFT                 (8U)
  /*! FTM2FLT0 - FTM2 Fault 0 Select
   *  0b0..FTM2_FLT0 pin
   *  0b1..CMP0 out
   */
  #define SIM_SOPT4_FTM2FLT0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
  #define SIM_SOPT4_FTM1CH0SRC_MASK                (0xC0000U)
  #define SIM_SOPT4_FTM1CH0SRC_SHIFT               (18U)
  /*! FTM1CH0SRC - FTM1 channel 0 input capture source select
   *  0b00..FTM1_CH0 signal
   *  0b01..CMP0 output
   *  0b10..CMP1 output
   *  0b11..Reserved
   */
  #define SIM_SOPT4_FTM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
  #define SIM_SOPT4_FTM2CH0SRC_MASK                (0x300000U)
  #define SIM_SOPT4_FTM2CH0SRC_SHIFT               (20U)
  /*! FTM2CH0SRC - FTM2 channel 0 input capture source select
   *  0b00..FTM2_CH0 signal
   *  0b01..CMP0 output
   *  0b10..CMP1 output
   *  0b11..Reserved
   */
  #define SIM_SOPT4_FTM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
  #define SIM_SOPT4_FTM2CH1SRC_MASK                (0x400000U)
  #define SIM_SOPT4_FTM2CH1SRC_SHIFT               (22U)
  /*! FTM2CH1SRC - FTM2 channel 1 input capture source select
   *  0b0..FTM2_CH1 signal
   *  0b1..Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1.
   */
  #define SIM_SOPT4_FTM2CH1SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
  #define SIM_SOPT4_FTM0CLKSEL_MASK                (0x1000000U)
  #define SIM_SOPT4_FTM0CLKSEL_SHIFT               (24U)
  /*! FTM0CLKSEL - FlexTimer 0 External Clock Pin Select
   *  0b0..FTM_CLK0 pin
   *  0b1..FTM_CLK1 pin
   */
  #define SIM_SOPT4_FTM0CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
  #define SIM_SOPT4_FTM1CLKSEL_MASK                (0x2000000U)
  #define SIM_SOPT4_FTM1CLKSEL_SHIFT               (25U)
  /*! FTM1CLKSEL - FTM1 External Clock Pin Select
   *  0b0..FTM_CLK0 pin
   *  0b1..FTM_CLK1 pin
   */
  #define SIM_SOPT4_FTM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
  #define SIM_SOPT4_FTM2CLKSEL_MASK                (0x4000000U)
  #define SIM_SOPT4_FTM2CLKSEL_SHIFT               (26U)
  /*! FTM2CLKSEL - FlexTimer 2 External Clock Pin Select
   *  0b0..FTM2 external clock driven by FTM_CLK0 pin.
   *  0b1..FTM2 external clock driven by FTM_CLK1 pin.
   */
  #define SIM_SOPT4_FTM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
  #define SIM_SOPT4_FTM0TRG0SRC_MASK               (0x10000000U)
  #define SIM_SOPT4_FTM0TRG0SRC_SHIFT              (28U)
  /*! FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select
   *  0b0..HSCMP0 output drives FTM0 hardware trigger 0
   *  0b1..FTM1 channel match drives FTM0 hardware trigger 0
   */
  #define SIM_SOPT4_FTM0TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
  #define SIM_SOPT4_FTM0TRG1SRC_MASK               (0x20000000U)
  #define SIM_SOPT4_FTM0TRG1SRC_SHIFT              (29U)
  /*! FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select
   *  0b0..PDB output trigger 1 drives FTM0 hardware trigger 1
   *  0b1..FTM2 channel match drives FTM0 hardware trigger 1
   */
  #define SIM_SOPT4_FTM0TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
  /*! @} */
  
  /*! @name SOPT5 - System Options Register 5 */
  /*! @{ */
  #define SIM_SOPT5_UART0TXSRC_MASK                (0x3U)
  #define SIM_SOPT5_UART0TXSRC_SHIFT               (0U)
  /*! UART0TXSRC - UART 0 transmit data source select
   *  0b00..UART0_TX pin
   *  0b01..UART0_TX pin modulated with FTM1 channel 0 output
   *  0b10..UART0_TX pin modulated with FTM2 channel 0 output
   *  0b11..Reserved
   */
  #define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
  #define SIM_SOPT5_UART0RXSRC_MASK                (0xCU)
  #define SIM_SOPT5_UART0RXSRC_SHIFT               (2U)
  /*! UART0RXSRC - UART 0 receive data source select
   *  0b00..UART0_RX pin
   *  0b01..CMP0
   *  0b10..CMP1
   *  0b11..Reserved
   */
  #define SIM_SOPT5_UART0RXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
  #define SIM_SOPT5_UART1TXSRC_MASK                (0x30U)
  #define SIM_SOPT5_UART1TXSRC_SHIFT               (4U)
  /*! UART1TXSRC - UART 1 transmit data source select
   *  0b00..UART1_TX pin
   *  0b01..UART1_TX pin modulated with FTM1 channel 0 output
   *  0b10..UART1_TX pin modulated with FTM2 channel 0 output
   *  0b11..Reserved
   */
  #define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
  #define SIM_SOPT5_UART1RXSRC_MASK                (0xC0U)
  #define SIM_SOPT5_UART1RXSRC_SHIFT               (6U)
  /*! UART1RXSRC - UART 1 receive data source select
   *  0b00..UART1_RX pin
   *  0b01..CMP0
   *  0b10..CMP1
   *  0b11..Reserved
   */
  #define SIM_SOPT5_UART1RXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
  #define SIM_SOPT5_LPUART0RXSRC_MASK              (0xC0000U)
  #define SIM_SOPT5_LPUART0RXSRC_SHIFT             (18U)
  /*! LPUART0RXSRC - LPUART0 receive data source select
   *  0b00..LPUART0_RX pin
   *  0b01..CMP0 output
   *  0b10..CMP1 output
   *  0b11..Reserved
   */
  #define SIM_SOPT5_LPUART0RXSRC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
  /*! @} */
  
  /*! @name SOPT7 - System Options Register 7 */
  /*! @{ */
  #define SIM_SOPT7_ADC0TRGSEL_MASK                (0xFU)
  #define SIM_SOPT7_ADC0TRGSEL_SHIFT               (0U)
  /*! ADC0TRGSEL - ADC0 trigger select
   *  0b0000..PDB external trigger pin input (PDB0_EXTRG)
   *  0b0001..High speed comparator 0 output
   *  0b0010..High speed comparator 1 output
   *  0b0011..Reserved
   *  0b0100..PIT trigger 0
   *  0b0101..PIT trigger 1
   *  0b0110..PIT trigger 2
   *  0b0111..PIT trigger 3
   *  0b1000..FTM0 trigger
   *  0b1001..FTM1 trigger
   *  0b1010..FTM2 trigger
   *  0b1011..Reserved
   *  0b1100..Reserved
   *  0b1101..Reserved
   *  0b1110..Low-power timer (LPTMR) trigger
   *  0b1111..Reserved
   */
  #define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
  #define SIM_SOPT7_ADC0PRETRGSEL_MASK             (0x10U)
  #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            (4U)
  /*! ADC0PRETRGSEL - ADC0 pretrigger select
   *  0b0..Pre-trigger A
   *  0b1..Pre-trigger B
   */
  #define SIM_SOPT7_ADC0PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
  #define SIM_SOPT7_ADC0ALTTRGEN_MASK              (0x80U)
  #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             (7U)
  /*! ADC0ALTTRGEN - ADC0 alternate trigger enable
   *  0b0..PDB trigger selected for ADC0.
   *  0b1..Alternate trigger selected for ADC0.
   */
  #define SIM_SOPT7_ADC0ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
  #define SIM_SOPT7_ADC1TRGSEL_MASK                (0xF00U)
  #define SIM_SOPT7_ADC1TRGSEL_SHIFT               (8U)
  /*! ADC1TRGSEL - ADC1 trigger select
   *  0b0000..PDB external trigger pin input (PDB0_EXTRG)
   *  0b0001..High speed comparator 0 output
   *  0b0010..High speed comparator 1 output
   *  0b0011..Reserved
   *  0b0100..PIT trigger 0
   *  0b0101..PIT trigger 1
   *  0b0110..PIT trigger 2
   *  0b0111..PIT trigger 3
   *  0b1000..FTM0 trigger
   *  0b1001..FTM1 trigger
   *  0b1010..FTM2 trigger
   *  0b1011..Reserved
   *  0b1100..Reserved
   *  0b1101..Reserved
   *  0b1110..Low-power timer (LPTMR) trigger
   *  0b1111..Reserved
   */
  #define SIM_SOPT7_ADC1TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
  #define SIM_SOPT7_ADC1PRETRGSEL_MASK             (0x1000U)
  #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT            (12U)
  /*! ADC1PRETRGSEL - ADC1 pre-trigger select
   *  0b0..Pre-trigger A selected for ADC1.
   *  0b1..Pre-trigger B selected for ADC1.
   */
  #define SIM_SOPT7_ADC1PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
  #define SIM_SOPT7_ADC1ALTTRGEN_MASK              (0x8000U)
  #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT             (15U)
  /*! ADC1ALTTRGEN - ADC1 alternate trigger enable
   *  0b0..PDB trigger selected for ADC1
   *  0b1..Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
   */
  #define SIM_SOPT7_ADC1ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
  /*! @} */
  
  /*! @name SOPT8 - System Options Register 8 */
  /*! @{ */
  #define SIM_SOPT8_FTM0SYNCBIT_MASK               (0x1U)
  #define SIM_SOPT8_FTM0SYNCBIT_SHIFT              (0U)
  /*! FTM0SYNCBIT - FTM0 Hardware Trigger 0 Software Synchronization
   *  0b0..No effect
   *  0b1..Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert.
   */
  #define SIM_SOPT8_FTM0SYNCBIT(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
  #define SIM_SOPT8_FTM1SYNCBIT_MASK               (0x2U)
  #define SIM_SOPT8_FTM1SYNCBIT_SHIFT              (1U)
  /*! FTM1SYNCBIT - FTM1 Hardware Trigger 0 Software Synchronization
   *  0b0..No effect.
   *  0b1..Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert.
   */
  #define SIM_SOPT8_FTM1SYNCBIT(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
  #define SIM_SOPT8_FTM2SYNCBIT_MASK               (0x4U)
  #define SIM_SOPT8_FTM2SYNCBIT_SHIFT              (2U)
  /*! FTM2SYNCBIT - FTM2 Hardware Trigger 0 Software Synchronization
   *  0b0..No effect.
   *  0b1..Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert.
   */
  #define SIM_SOPT8_FTM2SYNCBIT(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
  #define SIM_SOPT8_FTM0OCH0SRC_MASK               (0x10000U)
  #define SIM_SOPT8_FTM0OCH0SRC_SHIFT              (16U)
  /*! FTM0OCH0SRC - FTM0 channel 0 output source
   *  0b0..FTM0_CH0 pin is output of FTM0 channel 0 output
   *  0b1..FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output
   */
  #define SIM_SOPT8_FTM0OCH0SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
  #define SIM_SOPT8_FTM0OCH1SRC_MASK               (0x20000U)
  #define SIM_SOPT8_FTM0OCH1SRC_SHIFT              (17U)
  /*! FTM0OCH1SRC - FTM0 channel 1 output source
   *  0b0..FTM0_CH1 pin is output of FTM0 channel 1 output
   *  0b1..FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output
   */
  #define SIM_SOPT8_FTM0OCH1SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
  #define SIM_SOPT8_FTM0OCH2SRC_MASK               (0x40000U)
  #define SIM_SOPT8_FTM0OCH2SRC_SHIFT              (18U)
  /*! FTM0OCH2SRC - FTM0 channel 2 output source
   *  0b0..FTM0_CH2 pin is output of FTM0 channel 2 output
   *  0b1..FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output
   */
  #define SIM_SOPT8_FTM0OCH2SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
  #define SIM_SOPT8_FTM0OCH3SRC_MASK               (0x80000U)
  #define SIM_SOPT8_FTM0OCH3SRC_SHIFT              (19U)
  /*! FTM0OCH3SRC - FTM0 channel 3 output source
   *  0b0..FTM0_CH3 pin is output of FTM0 channel 3 output
   *  0b1..FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output
   */
  #define SIM_SOPT8_FTM0OCH3SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
  #define SIM_SOPT8_FTM0OCH4SRC_MASK               (0x100000U)
  #define SIM_SOPT8_FTM0OCH4SRC_SHIFT              (20U)
  /*! FTM0OCH4SRC - FTM0 channel 4 output source
   *  0b0..FTM0_CH4 pin is output of FTM0 channel 4 output
   *  0b1..FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output
   */
  #define SIM_SOPT8_FTM0OCH4SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
  #define SIM_SOPT8_FTM0OCH5SRC_MASK               (0x200000U)
  #define SIM_SOPT8_FTM0OCH5SRC_SHIFT              (21U)
  /*! FTM0OCH5SRC - FTM0 channel 5 output source
   *  0b0..FTM0_CH5 pin is output of FTM0 channel 5 output
   *  0b1..FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output
   */
  #define SIM_SOPT8_FTM0OCH5SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
  #define SIM_SOPT8_FTM0OCH6SRC_MASK               (0x400000U)
  #define SIM_SOPT8_FTM0OCH6SRC_SHIFT              (22U)
  /*! FTM0OCH6SRC - FTM0 channel 6 output source
   *  0b0..FTM0_CH6 pin is output of FTM0 channel 6 output
   *  0b1..FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output
   */
  #define SIM_SOPT8_FTM0OCH6SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
  #define SIM_SOPT8_FTM0OCH7SRC_MASK               (0x800000U)
  #define SIM_SOPT8_FTM0OCH7SRC_SHIFT              (23U)
  /*! FTM0OCH7SRC - FTM0 channel 7 output source
   *  0b0..FTM0_CH7 pin is output of FTM0 channel 7 output
   *  0b1..FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output
   */
  #define SIM_SOPT8_FTM0OCH7SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
  /*! @} */
  
  /*! @name SDID - System Device Identification Register */
  /*! @{ */
  #define SIM_SDID_PINID_MASK                      (0xFU)
  #define SIM_SDID_PINID_SHIFT                     (0U)
  /*! PINID - Pincount identification
   *  0b0000..Reserved
   *  0b0001..Reserved
   *  0b0010..32-pin
   *  0b0011..Reserved
   *  0b0100..48-pin
   *  0b0101..64-pin
   *  0b0110..80-pin
   *  0b0111..81-pin or 121-pin
   *  0b1000..100-pin
   *  0b1001..121-pin
   *  0b1010..144-pin
   *  0b1011..Custom pinout (WLCSP)
   *  0b1100..169-pin
   *  0b1101..Reserved
   *  0b1110..256-pin
   *  0b1111..Reserved
   */
  #define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
  #define SIM_SDID_DIEID_MASK                      (0xF80U)
  #define SIM_SDID_DIEID_SHIFT                     (7U)
  #define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
  #define SIM_SDID_REVID_MASK                      (0xF000U)
  #define SIM_SDID_REVID_SHIFT                     (12U)
  #define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
  #define SIM_SDID_SERIESID_MASK                   (0xF00000U)
  #define SIM_SDID_SERIESID_SHIFT                  (20U)
  /*! SERIESID - Kinetis Series ID
   *  0b0000..Kinetis K series
   *  0b0001..Kinetis L series
   *  0b0101..Kinetis W series
   *  0b0110..Kinetis V series
   */
  #define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
  #define SIM_SDID_SUBFAMID_MASK                   (0xF000000U)
  #define SIM_SDID_SUBFAMID_SHIFT                  (24U)
  /*! SUBFAMID - Kinetis Sub-Family ID
   *  0b0000..KVx0 Subfamily
   *  0b0001..KVx1 Subfamily
   *  0b0010..KVx2 Subfamily
   *  0b0011..KVx3 Subfamily
   *  0b0100..KVx4 Subfamily
   *  0b0101..KVx5 Subfamily
   *  0b0110..KVx6 Subfamily
   */
  #define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
  #define SIM_SDID_FAMILYID_MASK                   (0xF0000000U)
  #define SIM_SDID_FAMILYID_SHIFT                  (28U)
  /*! FAMILYID - Kinetis Family ID
   *  0b0001..KV1x Family
   *  0b0010..KV2x Family
   *  0b0011..KV3x Family
   *  0b0100..KV4x Family
   *  0b0110..KV6x Family
   *  0b0111..KV7x Family
   */
  #define SIM_SDID_FAMILYID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
  /*! @} */
  
  /*! @name SCGC4 - System Clock Gating Control Register 4 */
  /*! @{ */
  #define SIM_SCGC4_EWM_MASK                       (0x2U)
  #define SIM_SCGC4_EWM_SHIFT                      (1U)
  /*! EWM - EWM Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC4_EWM(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
  #define SIM_SCGC4_I2C0_MASK                      (0x40U)
  #define SIM_SCGC4_I2C0_SHIFT                     (6U)
  /*! I2C0 - I2C0 Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC4_I2C0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
  #define SIM_SCGC4_I2C1_MASK                      (0x80U)
  #define SIM_SCGC4_I2C1_SHIFT                     (7U)
  /*! I2C1 - I2C1 Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC4_I2C1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
  #define SIM_SCGC4_UART0_MASK                     (0x400U)
  #define SIM_SCGC4_UART0_SHIFT                    (10U)
  /*! UART0 - UART0 Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC4_UART0(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
  #define SIM_SCGC4_UART1_MASK                     (0x800U)
  #define SIM_SCGC4_UART1_SHIFT                    (11U)
  /*! UART1 - UART1 Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC4_UART1(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
  #define SIM_SCGC4_UART2_MASK                     (0x1000U)
  #define SIM_SCGC4_UART2_SHIFT                    (12U)
  /*! UART2 - UART2 Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC4_UART2(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
  #define SIM_SCGC4_CMP_MASK                       (0x80000U)
  #define SIM_SCGC4_CMP_SHIFT                      (19U)
  /*! CMP - Comparator Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC4_CMP(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
  #define SIM_SCGC4_VREF_MASK                      (0x100000U)
  #define SIM_SCGC4_VREF_SHIFT                     (20U)
  /*! VREF - VREF Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC4_VREF(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
  /*! @} */
  
  /*! @name SCGC5 - System Clock Gating Control Register 5 */
  /*! @{ */
  #define SIM_SCGC5_LPTMR_MASK                     (0x1U)
  #define SIM_SCGC5_LPTMR_SHIFT                    (0U)
  /*! LPTMR - Low Power Timer Access Control
   *  0b0..Access disabled
   *  0b1..Access enabled
   */
  #define SIM_SCGC5_LPTMR(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
  #define SIM_SCGC5_PORTA_MASK                     (0x200U)
  #define SIM_SCGC5_PORTA_SHIFT                    (9U)
  /*! PORTA - Port A Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC5_PORTA(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
  #define SIM_SCGC5_PORTB_MASK                     (0x400U)
  #define SIM_SCGC5_PORTB_SHIFT                    (10U)
  /*! PORTB - Port B Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC5_PORTB(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
  #define SIM_SCGC5_PORTC_MASK                     (0x800U)
  #define SIM_SCGC5_PORTC_SHIFT                    (11U)
  /*! PORTC - Port C Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC5_PORTC(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
  #define SIM_SCGC5_PORTD_MASK                     (0x1000U)
  #define SIM_SCGC5_PORTD_SHIFT                    (12U)
  /*! PORTD - Port D Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC5_PORTD(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
  #define SIM_SCGC5_PORTE_MASK                     (0x2000U)
  #define SIM_SCGC5_PORTE_SHIFT                    (13U)
  /*! PORTE - Port E Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC5_PORTE(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
  /*! @} */
  
  /*! @name SCGC6 - System Clock Gating Control Register 6 */
  /*! @{ */
  #define SIM_SCGC6_FTF_MASK                       (0x1U)
  #define SIM_SCGC6_FTF_SHIFT                      (0U)
  /*! FTF - Flash Memory Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC6_FTF(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
  #define SIM_SCGC6_DMAMUX_MASK                    (0x2U)
  #define SIM_SCGC6_DMAMUX_SHIFT                   (1U)
  /*! DMAMUX - DMA Mux Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC6_DMAMUX(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
  #define SIM_SCGC6_ADC1_MASK                      (0x80U)
  #define SIM_SCGC6_ADC1_SHIFT                     (7U)
  /*! ADC1 - ADC1 Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC6_ADC1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC1_SHIFT)) & SIM_SCGC6_ADC1_MASK)
  #define SIM_SCGC6_LPUART0_MASK                   (0x400U)
  #define SIM_SCGC6_LPUART0_SHIFT                  (10U)
  /*! LPUART0 - LPUART0 Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC6_LPUART0(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_LPUART0_SHIFT)) & SIM_SCGC6_LPUART0_MASK)
  #define SIM_SCGC6_SPI0_MASK                      (0x1000U)
  #define SIM_SCGC6_SPI0_SHIFT                     (12U)
  /*! SPI0 - SPI0 Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC6_SPI0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
  #define SIM_SCGC6_SPI1_MASK                      (0x2000U)
  #define SIM_SCGC6_SPI1_SHIFT                     (13U)
  /*! SPI1 - SPI1 Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC6_SPI1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
  #define SIM_SCGC6_CRC_MASK                       (0x40000U)
  #define SIM_SCGC6_CRC_SHIFT                      (18U)
  /*! CRC - CRC Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC6_CRC(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
  #define SIM_SCGC6_PDB_MASK                       (0x400000U)
  #define SIM_SCGC6_PDB_SHIFT                      (22U)
  /*! PDB - PDB Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC6_PDB(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
  #define SIM_SCGC6_PIT_MASK                       (0x800000U)
  #define SIM_SCGC6_PIT_SHIFT                      (23U)
  /*! PIT - PIT Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC6_PIT(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
  #define SIM_SCGC6_FTM0_MASK                      (0x1000000U)
  #define SIM_SCGC6_FTM0_SHIFT                     (24U)
  /*! FTM0 - FTM0 Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC6_FTM0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
  #define SIM_SCGC6_FTM1_MASK                      (0x2000000U)
  #define SIM_SCGC6_FTM1_SHIFT                     (25U)
  /*! FTM1 - FTM1 Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC6_FTM1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
  #define SIM_SCGC6_FTM2_MASK                      (0x4000000U)
  #define SIM_SCGC6_FTM2_SHIFT                     (26U)
  /*! FTM2 - FTM2 Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC6_FTM2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
  #define SIM_SCGC6_ADC0_MASK                      (0x8000000U)
  #define SIM_SCGC6_ADC0_SHIFT                     (27U)
  /*! ADC0 - ADC0 Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC6_ADC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
  #define SIM_SCGC6_DAC0_MASK                      (0x80000000U)
  #define SIM_SCGC6_DAC0_SHIFT                     (31U)
  /*! DAC0 - DAC0 Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC6_DAC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
  /*! @} */
  
  /*! @name SCGC7 - System Clock Gating Control Register 7 */
  /*! @{ */
  #define SIM_SCGC7_DMA_MASK                       (0x2U)
  #define SIM_SCGC7_DMA_SHIFT                      (1U)
  /*! DMA - DMA Clock Gate Control
   *  0b0..Clock disabled
   *  0b1..Clock enabled
   */
  #define SIM_SCGC7_DMA(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
  /*! @} */
  
  /*! @name CLKDIV1 - System Clock Divider Register 1 */
  /*! @{ */
  #define SIM_CLKDIV1_OUTDIV4_MASK                 (0xF0000U)
  #define SIM_CLKDIV1_OUTDIV4_SHIFT                (16U)
  /*! OUTDIV4 - Clock 4 output divider value
   *  0b0000..Divide-by-1.
   *  0b0001..Divide-by-2.
   *  0b0010..Divide-by-3.
   *  0b0011..Divide-by-4.
   *  0b0100..Divide-by-5.
   *  0b0101..Divide-by-6.
   *  0b0110..Divide-by-7.
   *  0b0111..Divide-by-8.
   *  0b1000..Divide-by-9.
   *  0b1001..Divide-by-10.
   *  0b1010..Divide-by-11.
   *  0b1011..Divide-by-12.
   *  0b1100..Divide-by-13.
   *  0b1101..Divide-by-14.
   *  0b1110..Divide-by-15.
   *  0b1111..Divide-by-16.
   */
  #define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
  #define SIM_CLKDIV1_OUTDIV2_MASK                 (0xF000000U)
  #define SIM_CLKDIV1_OUTDIV2_SHIFT                (24U)
  /*! OUTDIV2 - Clock 2 output divider value
   *  0b0000..Divide-by-1.
   *  0b0001..Divide-by-2.
   *  0b0010..Divide-by-3.
   *  0b0011..Divide-by-4.
   *  0b0100..Divide-by-5.
   *  0b0101..Divide-by-6.
   *  0b0110..Divide-by-7.
   *  0b0111..Divide-by-8.
   *  0b1000..Divide-by-9.
   *  0b1001..Divide-by-10.
   *  0b1010..Divide-by-11.
   *  0b1011..Divide-by-12.
   *  0b1100..Divide-by-13.
   *  0b1101..Divide-by-14.
   *  0b1110..Divide-by-15.
   *  0b1111..Divide-by-16.
   */
  #define SIM_CLKDIV1_OUTDIV2(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
  #define SIM_CLKDIV1_OUTDIV1_MASK                 (0xF0000000U)
  #define SIM_CLKDIV1_OUTDIV1_SHIFT                (28U)
  /*! OUTDIV1 - Clock 1 output divider value
   *  0b0000..Divide-by-1.
   *  0b0001..Divide-by-2.
   *  0b0010..Divide-by-3.
   *  0b0011..Divide-by-4.
   *  0b0100..Divide-by-5.
   *  0b0101..Divide-by-6.
   *  0b0110..Divide-by-7.
   *  0b0111..Divide-by-8.
   *  0b1000..Divide-by-9.
   *  0b1001..Divide-by-10.
   *  0b1010..Divide-by-11.
   *  0b1011..Divide-by-12.
   *  0b1100..Divide-by-13.
   *  0b1101..Divide-by-14.
   *  0b1110..Divide-by-15.
   *  0b1111..Divide-by-16.
   */
  #define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
  /*! @} */
  
  /*! @name FCFG1 - Flash Configuration Register 1 */
  /*! @{ */
  #define SIM_FCFG1_FLASHDIS_MASK                  (0x1U)
  #define SIM_FCFG1_FLASHDIS_SHIFT                 (0U)
  /*! FLASHDIS - Flash Disable
   *  0b0..Flash is enabled
   *  0b1..Flash is disabled
   */
  #define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
  #define SIM_FCFG1_FLASHDOZE_MASK                 (0x2U)
  #define SIM_FCFG1_FLASHDOZE_SHIFT                (1U)
  /*! FLASHDOZE - Flash Doze
   *  0b0..Flash remains enabled during Wait mode
   *  0b1..Flash is disabled for the duration of Wait mode
   */
  #define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
  #define SIM_FCFG1_PFSIZE_MASK                    (0xF000000U)
  #define SIM_FCFG1_PFSIZE_SHIFT                   (24U)
  /*! PFSIZE - Program flash size
   *  0b0011..32 KB of program flash memory
   *  0b0101..64 KB of program flash memory
   *  0b0111..128 KB of program flash memory
   *  0b1001..256 KB of program flash memory
   *  0b1011..512 KB of program flash memory
   *  0b1101..1024 KB of program flash memory
   *  0b1111..128 KB of program flash memory
   */
  #define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
  /*! @} */
  
  /*! @name FCFG2 - Flash Configuration Register 2 */
  /*! @{ */
  #define SIM_FCFG2_MAXADDR1_MASK                  (0x7F0000U)
  #define SIM_FCFG2_MAXADDR1_SHIFT                 (16U)
  #define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
  #define SIM_FCFG2_MAXADDR0_MASK                  (0x7F000000U)
  #define SIM_FCFG2_MAXADDR0_SHIFT                 (24U)
  #define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
  /*! @} */
  
  /*! @name UIDH - Unique Identification Register High */
  /*! @{ */
  #define SIM_UIDH_UID_MASK                        (0xFFFFFFFFU)
  #define SIM_UIDH_UID_SHIFT                       (0U)
  #define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
  /*! @} */
  
  /*! @name UIDMH - Unique Identification Register Mid-High */
  /*! @{ */
  #define SIM_UIDMH_UID_MASK                       (0xFFFFFFFFU)
  #define SIM_UIDMH_UID_SHIFT                      (0U)
  #define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
  /*! @} */
  
  /*! @name UIDML - Unique Identification Register Mid Low */
  /*! @{ */
  #define SIM_UIDML_UID_MASK                       (0xFFFFFFFFU)
  #define SIM_UIDML_UID_SHIFT                      (0U)
  #define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
  /*! @} */
  
  /*! @name UIDL - Unique Identification Register Low */
  /*! @{ */
  #define SIM_UIDL_UID_MASK                        (0xFFFFFFFFU)
  #define SIM_UIDL_UID_SHIFT                       (0U)
  #define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group SIM_Register_Masks */
  
  
  /* SIM - Peripheral instance base addresses */
  /** Peripheral SIM base address */
  #define SIM_BASE                                 (0x40047000u)
  /** Peripheral SIM base pointer */
  #define SIM                                      ((SIM_Type *)SIM_BASE)
  /** Array initializer of SIM peripheral base addresses */
  #define SIM_BASE_ADDRS                           { SIM_BASE }
  /** Array initializer of SIM peripheral base pointers */
  #define SIM_BASE_PTRS                            { SIM }
  
  /*!
   * @}
   */ /* end of group SIM_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- SMC Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
   * @{
   */
  
  /** SMC - Register Layout Typedef */
  typedef struct {
    __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
    __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
    __IO uint8_t STOPCTRL;                           /**< Stop Control Register, offset: 0x2 */
    __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
  } SMC_Type;
  
  /* ----------------------------------------------------------------------------
     -- SMC Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SMC_Register_Masks SMC Register Masks
   * @{
   */
  
  /*! @name PMPROT - Power Mode Protection register */
  /*! @{ */
  #define SMC_PMPROT_AVLLS_MASK                    (0x2U)
  #define SMC_PMPROT_AVLLS_SHIFT                   (1U)
  /*! AVLLS - Allow Very-Low-Leakage Stop Mode
   *  0b0..Any VLLSx mode is not allowed
   *  0b1..Any VLLSx mode is allowed
   */
  #define SMC_PMPROT_AVLLS(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
  #define SMC_PMPROT_ALLS_MASK                     (0x8U)
  #define SMC_PMPROT_ALLS_SHIFT                    (3U)
  /*! ALLS - Allow Low-Leakage Stop Mode
   *  0b0..Any LLSx mode is not allowed
   *  0b1..Any LLSx mode is allowed
   */
  #define SMC_PMPROT_ALLS(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
  #define SMC_PMPROT_AVLP_MASK                     (0x20U)
  #define SMC_PMPROT_AVLP_SHIFT                    (5U)
  /*! AVLP - Allow Very-Low-Power Modes
   *  0b0..VLPR, VLPW, and VLPS are not allowed.
   *  0b1..VLPR, VLPW, and VLPS are allowed.
   */
  #define SMC_PMPROT_AVLP(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
  #define SMC_PMPROT_AHSRUN_MASK                   (0x80U)
  #define SMC_PMPROT_AHSRUN_SHIFT                  (7U)
  /*! AHSRUN - Allow High Speed Run mode
   *  0b0..HSRUN is not allowed
   *  0b1..HSRUN is allowed
   */
  #define SMC_PMPROT_AHSRUN(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
  /*! @} */
  
  /*! @name PMCTRL - Power Mode Control register */
  /*! @{ */
  #define SMC_PMCTRL_STOPM_MASK                    (0x7U)
  #define SMC_PMCTRL_STOPM_SHIFT                   (0U)
  /*! STOPM - Stop Mode Control
   *  0b000..Normal Stop (STOP)
   *  0b001..Reserved
   *  0b010..Very-Low-Power Stop (VLPS)
   *  0b011..Low-Leakage Stop (LLSx)
   *  0b100..Very-Low-Leakage Stop (VLLSx)
   *  0b101..Reserved
   *  0b110..Reseved
   *  0b111..Reserved
   */
  #define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
  #define SMC_PMCTRL_STOPA_MASK                    (0x8U)
  #define SMC_PMCTRL_STOPA_SHIFT                   (3U)
  /*! STOPA - Stop Aborted
   *  0b0..The previous stop mode entry was successsful.
   *  0b1..The previous stop mode entry was aborted.
   */
  #define SMC_PMCTRL_STOPA(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
  #define SMC_PMCTRL_RUNM_MASK                     (0x60U)
  #define SMC_PMCTRL_RUNM_SHIFT                    (5U)
  /*! RUNM - Run Mode Control
   *  0b00..Normal Run mode (RUN)
   *  0b01..Reserved
   *  0b10..Very-Low-Power Run mode (VLPR)
   *  0b11..High Speed Run mode (HSRUN)
   */
  #define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
  /*! @} */
  
  /*! @name STOPCTRL - Stop Control Register */
  /*! @{ */
  #define SMC_STOPCTRL_LLSM_MASK                   (0x7U)
  #define SMC_STOPCTRL_LLSM_SHIFT                  (0U)
  /*! LLSM - LLS or VLLS Mode Control
   *  0b000..VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
   *  0b001..VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
   *  0b010..VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
   *  0b011..VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx
   *  0b100..Reserved
   *  0b101..Reserved
   *  0b110..Reserved
   *  0b111..Reserved
   */
  #define SMC_STOPCTRL_LLSM(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
  #define SMC_STOPCTRL_PORPO_MASK                  (0x20U)
  #define SMC_STOPCTRL_PORPO_SHIFT                 (5U)
  /*! PORPO - POR Power Option
   *  0b0..POR detect circuit is enabled in VLLS0
   *  0b1..POR detect circuit is disabled in VLLS0
   */
  #define SMC_STOPCTRL_PORPO(x)                    (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
  #define SMC_STOPCTRL_PSTOPO_MASK                 (0xC0U)
  #define SMC_STOPCTRL_PSTOPO_SHIFT                (6U)
  /*! PSTOPO - Partial Stop Option
   *  0b00..STOP - Normal Stop mode
   *  0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled
   *  0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
   *  0b11..Reserved
   */
  #define SMC_STOPCTRL_PSTOPO(x)                   (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
  /*! @} */
  
  /*! @name PMSTAT - Power Mode Status register */
  /*! @{ */
  #define SMC_PMSTAT_PMSTAT_MASK                   (0xFFU)
  #define SMC_PMSTAT_PMSTAT_SHIFT                  (0U)
  #define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group SMC_Register_Masks */
  
  
  /* SMC - Peripheral instance base addresses */
  /** Peripheral SMC base address */
  #define SMC_BASE                                 (0x4007E000u)
  /** Peripheral SMC base pointer */
  #define SMC                                      ((SMC_Type *)SMC_BASE)
  /** Array initializer of SMC peripheral base addresses */
  #define SMC_BASE_ADDRS                           { SMC_BASE }
  /** Array initializer of SMC peripheral base pointers */
  #define SMC_BASE_PTRS                            { SMC }
  
  /*!
   * @}
   */ /* end of group SMC_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- SPI Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
   * @{
   */
  
  /** SPI - Register Layout Typedef */
  typedef struct {
    __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
         uint8_t RESERVED_0[4];
    __IO uint32_t TCR;                               /**< Transfer Count Register, offset: 0x8 */
    union {                                          /* offset: 0xC */
      __IO uint32_t CTAR[2];                           /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
      __IO uint32_t CTAR_SLAVE[1];                     /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
    };
         uint8_t RESERVED_1[24];
    __IO uint32_t SR;                                /**< Status Register, offset: 0x2C */
    __IO uint32_t RSER;                              /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
    union {                                          /* offset: 0x34 */
      __IO uint32_t PUSHR;                             /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
      __IO uint32_t PUSHR_SLAVE;                       /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
    };
    __I  uint32_t POPR;                              /**< POP RX FIFO Register, offset: 0x38 */
    __I  uint32_t TXFR0;                             /**< Transmit FIFO Registers, offset: 0x3C */
    __I  uint32_t TXFR1;                             /**< Transmit FIFO Registers, offset: 0x40 */
    __I  uint32_t TXFR2;                             /**< Transmit FIFO Registers, offset: 0x44 */
    __I  uint32_t TXFR3;                             /**< Transmit FIFO Registers, offset: 0x48 */
         uint8_t RESERVED_2[48];
    __I  uint32_t RXFR0;                             /**< Receive FIFO Registers, offset: 0x7C */
    __I  uint32_t RXFR1;                             /**< Receive FIFO Registers, offset: 0x80 */
    __I  uint32_t RXFR2;                             /**< Receive FIFO Registers, offset: 0x84 */
    __I  uint32_t RXFR3;                             /**< Receive FIFO Registers, offset: 0x88 */
  } SPI_Type;
  
  /* ----------------------------------------------------------------------------
     -- SPI Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SPI_Register_Masks SPI Register Masks
   * @{
   */
  
  /*! @name MCR - Module Configuration Register */
  /*! @{ */
  #define SPI_MCR_HALT_MASK                        (0x1U)
  #define SPI_MCR_HALT_SHIFT                       (0U)
  /*! HALT - Halt
   *  0b0..Start transfers.
   *  0b1..Stop transfers.
   */
  #define SPI_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
  #define SPI_MCR_SMPL_PT_MASK                     (0x300U)
  #define SPI_MCR_SMPL_PT_SHIFT                    (8U)
  /*! SMPL_PT - Sample Point
   *  0b00..0 protocol clock cycles between SCK edge and SIN sample
   *  0b01..1 protocol clock cycle between SCK edge and SIN sample
   *  0b10..2 protocol clock cycles between SCK edge and SIN sample
   *  0b11..Reserved
   */
  #define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
  #define SPI_MCR_CLR_RXF_MASK                     (0x400U)
  #define SPI_MCR_CLR_RXF_SHIFT                    (10U)
  /*! CLR_RXF
   *  0b0..Do not clear the RX FIFO counter.
   *  0b1..Clear the RX FIFO counter.
   */
  #define SPI_MCR_CLR_RXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
  #define SPI_MCR_CLR_TXF_MASK                     (0x800U)
  #define SPI_MCR_CLR_TXF_SHIFT                    (11U)
  /*! CLR_TXF - Clear TX FIFO
   *  0b0..Do not clear the TX FIFO counter.
   *  0b1..Clear the TX FIFO counter.
   */
  #define SPI_MCR_CLR_TXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
  #define SPI_MCR_DIS_RXF_MASK                     (0x1000U)
  #define SPI_MCR_DIS_RXF_SHIFT                    (12U)
  /*! DIS_RXF - Disable Receive FIFO
   *  0b0..RX FIFO is enabled.
   *  0b1..RX FIFO is disabled.
   */
  #define SPI_MCR_DIS_RXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
  #define SPI_MCR_DIS_TXF_MASK                     (0x2000U)
  #define SPI_MCR_DIS_TXF_SHIFT                    (13U)
  /*! DIS_TXF - Disable Transmit FIFO
   *  0b0..TX FIFO is enabled.
   *  0b1..TX FIFO is disabled.
   */
  #define SPI_MCR_DIS_TXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
  #define SPI_MCR_MDIS_MASK                        (0x4000U)
  #define SPI_MCR_MDIS_SHIFT                       (14U)
  /*! MDIS - Module Disable
   *  0b0..Enables the module clocks.
   *  0b1..Allows external logic to disable the module clocks.
   */
  #define SPI_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
  #define SPI_MCR_DOZE_MASK                        (0x8000U)
  #define SPI_MCR_DOZE_SHIFT                       (15U)
  /*! DOZE - Doze Enable
   *  0b0..Doze mode has no effect on the module.
   *  0b1..Doze mode disables the module.
   */
  #define SPI_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
  #define SPI_MCR_PCSIS_MASK                       (0x3F0000U)
  #define SPI_MCR_PCSIS_SHIFT                      (16U)
  /*! PCSIS - Peripheral Chip Select x Inactive State
   *  0b000000..The inactive state of PCSx is low.
   *  0b000001..The inactive state of PCSx is high.
   */
  #define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
  #define SPI_MCR_ROOE_MASK                        (0x1000000U)
  #define SPI_MCR_ROOE_SHIFT                       (24U)
  /*! ROOE - Receive FIFO Overflow Overwrite Enable
   *  0b0..Incoming data is ignored.
   *  0b1..Incoming data is shifted into the shift register.
   */
  #define SPI_MCR_ROOE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
  #define SPI_MCR_PCSSE_MASK                       (0x2000000U)
  #define SPI_MCR_PCSSE_SHIFT                      (25U)
  /*! PCSSE - Peripheral Chip Select Strobe Enable
   *  0b0..PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
   *  0b1..PCS5/ PCSS is used as an active-low PCS Strobe signal.
   */
  #define SPI_MCR_PCSSE(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
  #define SPI_MCR_MTFE_MASK                        (0x4000000U)
  #define SPI_MCR_MTFE_SHIFT                       (26U)
  /*! MTFE - Modified Timing Format Enable
   *  0b0..Modified SPI transfer format disabled.
   *  0b1..Modified SPI transfer format enabled.
   */
  #define SPI_MCR_MTFE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
  #define SPI_MCR_FRZ_MASK                         (0x8000000U)
  #define SPI_MCR_FRZ_SHIFT                        (27U)
  /*! FRZ - Freeze
   *  0b0..Do not halt serial transfers in Debug mode.
   *  0b1..Halt serial transfers in Debug mode.
   */
  #define SPI_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
  #define SPI_MCR_DCONF_MASK                       (0x30000000U)
  #define SPI_MCR_DCONF_SHIFT                      (28U)
  /*! DCONF - SPI Configuration.
   *  0b00..SPI
   *  0b01..Reserved
   *  0b10..Reserved
   *  0b11..Reserved
   */
  #define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
  #define SPI_MCR_CONT_SCKE_MASK                   (0x40000000U)
  #define SPI_MCR_CONT_SCKE_SHIFT                  (30U)
  /*! CONT_SCKE - Continuous SCK Enable
   *  0b0..Continuous SCK disabled.
   *  0b1..Continuous SCK enabled.
   */
  #define SPI_MCR_CONT_SCKE(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
  #define SPI_MCR_MSTR_MASK                        (0x80000000U)
  #define SPI_MCR_MSTR_SHIFT                       (31U)
  /*! MSTR - Master/Slave Mode Select
   *  0b0..Enables Slave mode
   *  0b1..Enables Master mode
   */
  #define SPI_MCR_MSTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
  /*! @} */
  
  /*! @name TCR - Transfer Count Register */
  /*! @{ */
  #define SPI_TCR_SPI_TCNT_MASK                    (0xFFFF0000U)
  #define SPI_TCR_SPI_TCNT_SHIFT                   (16U)
  #define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
  /*! @} */
  
  /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
  /*! @{ */
  #define SPI_CTAR_BR_MASK                         (0xFU)
  #define SPI_CTAR_BR_SHIFT                        (0U)
  #define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
  #define SPI_CTAR_DT_MASK                         (0xF0U)
  #define SPI_CTAR_DT_SHIFT                        (4U)
  #define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
  #define SPI_CTAR_ASC_MASK                        (0xF00U)
  #define SPI_CTAR_ASC_SHIFT                       (8U)
  #define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
  #define SPI_CTAR_CSSCK_MASK                      (0xF000U)
  #define SPI_CTAR_CSSCK_SHIFT                     (12U)
  #define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
  #define SPI_CTAR_PBR_MASK                        (0x30000U)
  #define SPI_CTAR_PBR_SHIFT                       (16U)
  /*! PBR - Baud Rate Prescaler
   *  0b00..Baud Rate Prescaler value is 2.
   *  0b01..Baud Rate Prescaler value is 3.
   *  0b10..Baud Rate Prescaler value is 5.
   *  0b11..Baud Rate Prescaler value is 7.
   */
  #define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
  #define SPI_CTAR_PDT_MASK                        (0xC0000U)
  #define SPI_CTAR_PDT_SHIFT                       (18U)
  /*! PDT - Delay after Transfer Prescaler
   *  0b00..Delay after Transfer Prescaler value is 1.
   *  0b01..Delay after Transfer Prescaler value is 3.
   *  0b10..Delay after Transfer Prescaler value is 5.
   *  0b11..Delay after Transfer Prescaler value is 7.
   */
  #define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
  #define SPI_CTAR_PASC_MASK                       (0x300000U)
  #define SPI_CTAR_PASC_SHIFT                      (20U)
  /*! PASC - After SCK Delay Prescaler
   *  0b00..Delay after Transfer Prescaler value is 1.
   *  0b01..Delay after Transfer Prescaler value is 3.
   *  0b10..Delay after Transfer Prescaler value is 5.
   *  0b11..Delay after Transfer Prescaler value is 7.
   */
  #define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
  #define SPI_CTAR_PCSSCK_MASK                     (0xC00000U)
  #define SPI_CTAR_PCSSCK_SHIFT                    (22U)
  /*! PCSSCK - PCS to SCK Delay Prescaler
   *  0b00..PCS to SCK Prescaler value is 1.
   *  0b01..PCS to SCK Prescaler value is 3.
   *  0b10..PCS to SCK Prescaler value is 5.
   *  0b11..PCS to SCK Prescaler value is 7.
   */
  #define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
  #define SPI_CTAR_LSBFE_MASK                      (0x1000000U)
  #define SPI_CTAR_LSBFE_SHIFT                     (24U)
  /*! LSBFE - LSB First
   *  0b0..Data is transferred MSB first.
   *  0b1..Data is transferred LSB first.
   */
  #define SPI_CTAR_LSBFE(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
  #define SPI_CTAR_CPHA_MASK                       (0x2000000U)
  #define SPI_CTAR_CPHA_SHIFT                      (25U)
  /*! CPHA - Clock Phase
   *  0b0..Data is captured on the leading edge of SCK and changed on the following edge.
   *  0b1..Data is changed on the leading edge of SCK and captured on the following edge.
   */
  #define SPI_CTAR_CPHA(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
  #define SPI_CTAR_CPOL_MASK                       (0x4000000U)
  #define SPI_CTAR_CPOL_SHIFT                      (26U)
  /*! CPOL - Clock Polarity
   *  0b0..The inactive state value of SCK is low.
   *  0b1..The inactive state value of SCK is high.
   */
  #define SPI_CTAR_CPOL(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
  #define SPI_CTAR_FMSZ_MASK                       (0x78000000U)
  #define SPI_CTAR_FMSZ_SHIFT                      (27U)
  #define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
  #define SPI_CTAR_DBR_MASK                        (0x80000000U)
  #define SPI_CTAR_DBR_SHIFT                       (31U)
  /*! DBR - Double Baud Rate
   *  0b0..The baud rate is computed normally with a 50/50 duty cycle.
   *  0b1..The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.
   */
  #define SPI_CTAR_DBR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
  /*! @} */
  
  /* The count of SPI_CTAR */
  #define SPI_CTAR_COUNT                           (2U)
  
  /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
  /*! @{ */
  #define SPI_CTAR_SLAVE_CPHA_MASK                 (0x2000000U)
  #define SPI_CTAR_SLAVE_CPHA_SHIFT                (25U)
  /*! CPHA - Clock Phase
   *  0b0..Data is captured on the leading edge of SCK and changed on the following edge.
   *  0b1..Data is changed on the leading edge of SCK and captured on the following edge.
   */
  #define SPI_CTAR_SLAVE_CPHA(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
  #define SPI_CTAR_SLAVE_CPOL_MASK                 (0x4000000U)
  #define SPI_CTAR_SLAVE_CPOL_SHIFT                (26U)
  /*! CPOL - Clock Polarity
   *  0b0..The inactive state value of SCK is low.
   *  0b1..The inactive state value of SCK is high.
   */
  #define SPI_CTAR_SLAVE_CPOL(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
  #define SPI_CTAR_SLAVE_FMSZ_MASK                 (0xF8000000U)
  #define SPI_CTAR_SLAVE_FMSZ_SHIFT                (27U)
  #define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
  /*! @} */
  
  /* The count of SPI_CTAR_SLAVE */
  #define SPI_CTAR_SLAVE_COUNT                     (1U)
  
  /*! @name SR - Status Register */
  /*! @{ */
  #define SPI_SR_POPNXTPTR_MASK                    (0xFU)
  #define SPI_SR_POPNXTPTR_SHIFT                   (0U)
  #define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
  #define SPI_SR_RXCTR_MASK                        (0xF0U)
  #define SPI_SR_RXCTR_SHIFT                       (4U)
  #define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
  #define SPI_SR_TXNXTPTR_MASK                     (0xF00U)
  #define SPI_SR_TXNXTPTR_SHIFT                    (8U)
  #define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
  #define SPI_SR_TXCTR_MASK                        (0xF000U)
  #define SPI_SR_TXCTR_SHIFT                       (12U)
  #define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
  #define SPI_SR_RFDF_MASK                         (0x20000U)
  #define SPI_SR_RFDF_SHIFT                        (17U)
  /*! RFDF - Receive FIFO Drain Flag
   *  0b0..RX FIFO is empty.
   *  0b1..RX FIFO is not empty.
   */
  #define SPI_SR_RFDF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
  #define SPI_SR_RFOF_MASK                         (0x80000U)
  #define SPI_SR_RFOF_SHIFT                        (19U)
  /*! RFOF - Receive FIFO Overflow Flag
   *  0b0..No Rx FIFO overflow.
   *  0b1..Rx FIFO overflow has occurred.
   */
  #define SPI_SR_RFOF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
  #define SPI_SR_TFFF_MASK                         (0x2000000U)
  #define SPI_SR_TFFF_SHIFT                        (25U)
  /*! TFFF - Transmit FIFO Fill Flag
   *  0b0..TX FIFO is full.
   *  0b1..TX FIFO is not full.
   */
  #define SPI_SR_TFFF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
  #define SPI_SR_TFUF_MASK                         (0x8000000U)
  #define SPI_SR_TFUF_SHIFT                        (27U)
  /*! TFUF - Transmit FIFO Underflow Flag
   *  0b0..No TX FIFO underflow.
   *  0b1..TX FIFO underflow has occurred.
   */
  #define SPI_SR_TFUF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
  #define SPI_SR_EOQF_MASK                         (0x10000000U)
  #define SPI_SR_EOQF_SHIFT                        (28U)
  /*! EOQF - End of Queue Flag
   *  0b0..EOQ is not set in the executing command.
   *  0b1..EOQ is set in the executing SPI command.
   */
  #define SPI_SR_EOQF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
  #define SPI_SR_TXRXS_MASK                        (0x40000000U)
  #define SPI_SR_TXRXS_SHIFT                       (30U)
  /*! TXRXS - TX and RX Status
   *  0b0..Transmit and receive operations are disabled (The module is in Stopped state).
   *  0b1..Transmit and receive operations are enabled (The module is in Running state).
   */
  #define SPI_SR_TXRXS(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
  #define SPI_SR_TCF_MASK                          (0x80000000U)
  #define SPI_SR_TCF_SHIFT                         (31U)
  /*! TCF - Transfer Complete Flag
   *  0b0..Transfer not complete.
   *  0b1..Transfer complete.
   */
  #define SPI_SR_TCF(x)                            (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
  /*! @} */
  
  /*! @name RSER - DMA/Interrupt Request Select and Enable Register */
  /*! @{ */
  #define SPI_RSER_RFDF_DIRS_MASK                  (0x10000U)
  #define SPI_RSER_RFDF_DIRS_SHIFT                 (16U)
  /*! RFDF_DIRS - Receive FIFO Drain DMA or Interrupt Request Select
   *  0b0..Interrupt request.
   *  0b1..DMA request.
   */
  #define SPI_RSER_RFDF_DIRS(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
  #define SPI_RSER_RFDF_RE_MASK                    (0x20000U)
  #define SPI_RSER_RFDF_RE_SHIFT                   (17U)
  /*! RFDF_RE - Receive FIFO Drain Request Enable
   *  0b0..RFDF interrupt or DMA requests are disabled.
   *  0b1..RFDF interrupt or DMA requests are enabled.
   */
  #define SPI_RSER_RFDF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
  #define SPI_RSER_RFOF_RE_MASK                    (0x80000U)
  #define SPI_RSER_RFOF_RE_SHIFT                   (19U)
  /*! RFOF_RE - Receive FIFO Overflow Request Enable
   *  0b0..RFOF interrupt requests are disabled.
   *  0b1..RFOF interrupt requests are enabled.
   */
  #define SPI_RSER_RFOF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
  #define SPI_RSER_TFFF_DIRS_MASK                  (0x1000000U)
  #define SPI_RSER_TFFF_DIRS_SHIFT                 (24U)
  /*! TFFF_DIRS - Transmit FIFO Fill DMA or Interrupt Request Select
   *  0b0..TFFF flag generates interrupt requests.
   *  0b1..TFFF flag generates DMA requests.
   */
  #define SPI_RSER_TFFF_DIRS(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
  #define SPI_RSER_TFFF_RE_MASK                    (0x2000000U)
  #define SPI_RSER_TFFF_RE_SHIFT                   (25U)
  /*! TFFF_RE - Transmit FIFO Fill Request Enable
   *  0b0..TFFF interrupts or DMA requests are disabled.
   *  0b1..TFFF interrupts or DMA requests are enabled.
   */
  #define SPI_RSER_TFFF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
  #define SPI_RSER_TFUF_RE_MASK                    (0x8000000U)
  #define SPI_RSER_TFUF_RE_SHIFT                   (27U)
  /*! TFUF_RE - Transmit FIFO Underflow Request Enable
   *  0b0..TFUF interrupt requests are disabled.
   *  0b1..TFUF interrupt requests are enabled.
   */
  #define SPI_RSER_TFUF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
  #define SPI_RSER_EOQF_RE_MASK                    (0x10000000U)
  #define SPI_RSER_EOQF_RE_SHIFT                   (28U)
  /*! EOQF_RE - Finished Request Enable
   *  0b0..EOQF interrupt requests are disabled.
   *  0b1..EOQF interrupt requests are enabled.
   */
  #define SPI_RSER_EOQF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
  #define SPI_RSER_TCF_RE_MASK                     (0x80000000U)
  #define SPI_RSER_TCF_RE_SHIFT                    (31U)
  /*! TCF_RE - Transmission Complete Request Enable
   *  0b0..TCF interrupt requests are disabled.
   *  0b1..TCF interrupt requests are enabled.
   */
  #define SPI_RSER_TCF_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
  /*! @} */
  
  /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
  /*! @{ */
  #define SPI_PUSHR_TXDATA_MASK                    (0xFFFFU)
  #define SPI_PUSHR_TXDATA_SHIFT                   (0U)
  #define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
  #define SPI_PUSHR_PCS_MASK                       (0x3F0000U)
  #define SPI_PUSHR_PCS_SHIFT                      (16U)
  /*! PCS
   *  0b000000..Negate the PCS[x] signal.
   *  0b000001..Assert the PCS[x] signal.
   */
  #define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
  #define SPI_PUSHR_CTCNT_MASK                     (0x4000000U)
  #define SPI_PUSHR_CTCNT_SHIFT                    (26U)
  /*! CTCNT - Clear Transfer Counter
   *  0b0..Do not clear the TCR[TCNT] field.
   *  0b1..Clear the TCR[TCNT] field.
   */
  #define SPI_PUSHR_CTCNT(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
  #define SPI_PUSHR_EOQ_MASK                       (0x8000000U)
  #define SPI_PUSHR_EOQ_SHIFT                      (27U)
  /*! EOQ - End Of Queue
   *  0b0..The SPI data is not the last data to transfer.
   *  0b1..The SPI data is the last data to transfer.
   */
  #define SPI_PUSHR_EOQ(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
  #define SPI_PUSHR_CTAS_MASK                      (0x70000000U)
  #define SPI_PUSHR_CTAS_SHIFT                     (28U)
  /*! CTAS - Clock and Transfer Attributes Select
   *  0b000..CTAR0
   *  0b001..CTAR1
   *  0b010..Reserved
   *  0b011..Reserved
   *  0b100..Reserved
   *  0b101..Reserved
   *  0b110..Reserved
   *  0b111..Reserved
   */
  #define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
  #define SPI_PUSHR_CONT_MASK                      (0x80000000U)
  #define SPI_PUSHR_CONT_SHIFT                     (31U)
  /*! CONT - Continuous Peripheral Chip Select Enable
   *  0b0..Return PCSn signals to their inactive state between transfers.
   *  0b1..Keep PCSn signals asserted between transfers.
   */
  #define SPI_PUSHR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
  /*! @} */
  
  /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
  /*! @{ */
  #define SPI_PUSHR_SLAVE_TXDATA_MASK              (0xFFFFFFFFU)
  #define SPI_PUSHR_SLAVE_TXDATA_SHIFT             (0U)
  #define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
  /*! @} */
  
  /*! @name POPR - POP RX FIFO Register */
  /*! @{ */
  #define SPI_POPR_RXDATA_MASK                     (0xFFFFFFFFU)
  #define SPI_POPR_RXDATA_SHIFT                    (0U)
  #define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
  /*! @} */
  
  /*! @name TXFR0 - Transmit FIFO Registers */
  /*! @{ */
  #define SPI_TXFR0_TXDATA_MASK                    (0xFFFFU)
  #define SPI_TXFR0_TXDATA_SHIFT                   (0U)
  #define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
  #define SPI_TXFR0_TXCMD_TXDATA_MASK              (0xFFFF0000U)
  #define SPI_TXFR0_TXCMD_TXDATA_SHIFT             (16U)
  #define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
  /*! @} */
  
  /*! @name TXFR1 - Transmit FIFO Registers */
  /*! @{ */
  #define SPI_TXFR1_TXDATA_MASK                    (0xFFFFU)
  #define SPI_TXFR1_TXDATA_SHIFT                   (0U)
  #define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
  #define SPI_TXFR1_TXCMD_TXDATA_MASK              (0xFFFF0000U)
  #define SPI_TXFR1_TXCMD_TXDATA_SHIFT             (16U)
  #define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
  /*! @} */
  
  /*! @name TXFR2 - Transmit FIFO Registers */
  /*! @{ */
  #define SPI_TXFR2_TXDATA_MASK                    (0xFFFFU)
  #define SPI_TXFR2_TXDATA_SHIFT                   (0U)
  #define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
  #define SPI_TXFR2_TXCMD_TXDATA_MASK              (0xFFFF0000U)
  #define SPI_TXFR2_TXCMD_TXDATA_SHIFT             (16U)
  #define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
  /*! @} */
  
  /*! @name TXFR3 - Transmit FIFO Registers */
  /*! @{ */
  #define SPI_TXFR3_TXDATA_MASK                    (0xFFFFU)
  #define SPI_TXFR3_TXDATA_SHIFT                   (0U)
  #define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
  #define SPI_TXFR3_TXCMD_TXDATA_MASK              (0xFFFF0000U)
  #define SPI_TXFR3_TXCMD_TXDATA_SHIFT             (16U)
  #define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
  /*! @} */
  
  /*! @name RXFR0 - Receive FIFO Registers */
  /*! @{ */
  #define SPI_RXFR0_RXDATA_MASK                    (0xFFFFFFFFU)
  #define SPI_RXFR0_RXDATA_SHIFT                   (0U)
  #define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
  /*! @} */
  
  /*! @name RXFR1 - Receive FIFO Registers */
  /*! @{ */
  #define SPI_RXFR1_RXDATA_MASK                    (0xFFFFFFFFU)
  #define SPI_RXFR1_RXDATA_SHIFT                   (0U)
  #define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
  /*! @} */
  
  /*! @name RXFR2 - Receive FIFO Registers */
  /*! @{ */
  #define SPI_RXFR2_RXDATA_MASK                    (0xFFFFFFFFU)
  #define SPI_RXFR2_RXDATA_SHIFT                   (0U)
  #define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
  /*! @} */
  
  /*! @name RXFR3 - Receive FIFO Registers */
  /*! @{ */
  #define SPI_RXFR3_RXDATA_MASK                    (0xFFFFFFFFU)
  #define SPI_RXFR3_RXDATA_SHIFT                   (0U)
  #define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group SPI_Register_Masks */
  
  
  /* SPI - Peripheral instance base addresses */
  /** Peripheral SPI0 base address */
  #define SPI0_BASE                                (0x4002C000u)
  /** Peripheral SPI0 base pointer */
  #define SPI0                                     ((SPI_Type *)SPI0_BASE)
  /** Peripheral SPI1 base address */
  #define SPI1_BASE                                (0x4002D000u)
  /** Peripheral SPI1 base pointer */
  #define SPI1                                     ((SPI_Type *)SPI1_BASE)
  /** Array initializer of SPI peripheral base addresses */
  #define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE }
  /** Array initializer of SPI peripheral base pointers */
  #define SPI_BASE_PTRS                            { SPI0, SPI1 }
  /** Interrupt vectors for the SPI peripheral type */
  #define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn }
  
  /*!
   * @}
   */ /* end of group SPI_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- UART Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
   * @{
   */
  
  /** UART - Register Layout Typedef */
  typedef struct {
    __IO uint8_t BDH;                                /**< UART Baud Rate Registers: High, offset: 0x0 */
    __IO uint8_t BDL;                                /**< UART Baud Rate Registers: Low, offset: 0x1 */
    __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
    __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
    __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
    __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
    __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
    __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
    __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
    __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
    __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
    __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
    __I  uint8_t ED;                                 /**< UART Extended Data Register, offset: 0xC */
    __IO uint8_t MODEM;                              /**< UART Modem Register, offset: 0xD */
    __IO uint8_t IR;                                 /**< UART Infrared Register, offset: 0xE */
         uint8_t RESERVED_0[1];
    __IO uint8_t PFIFO;                              /**< UART FIFO Parameters, offset: 0x10 */
    __IO uint8_t CFIFO;                              /**< UART FIFO Control Register, offset: 0x11 */
    __IO uint8_t SFIFO;                              /**< UART FIFO Status Register, offset: 0x12 */
    __IO uint8_t TWFIFO;                             /**< UART FIFO Transmit Watermark, offset: 0x13 */
    __I  uint8_t TCFIFO;                             /**< UART FIFO Transmit Count, offset: 0x14 */
    __IO uint8_t RWFIFO;                             /**< UART FIFO Receive Watermark, offset: 0x15 */
    __I  uint8_t RCFIFO;                             /**< UART FIFO Receive Count, offset: 0x16 */
         uint8_t RESERVED_1[1];
    __IO uint8_t C7816;                              /**< UART 7816 Control Register, offset: 0x18 */
    __IO uint8_t IE7816;                             /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
    __IO uint8_t IS7816;                             /**< UART 7816 Interrupt Status Register, offset: 0x1A */
    __IO uint8_t WP7816;                             /**< UART 7816 Wait Parameter Register, offset: 0x1B */
    __IO uint8_t WN7816;                             /**< UART 7816 Wait N Register, offset: 0x1C */
    __IO uint8_t WF7816;                             /**< UART 7816 Wait FD Register, offset: 0x1D */
    __IO uint8_t ET7816;                             /**< UART 7816 Error Threshold Register, offset: 0x1E */
    __IO uint8_t TL7816;                             /**< UART 7816 Transmit Length Register, offset: 0x1F */
         uint8_t RESERVED_2[26];
    __IO uint8_t AP7816A_T0;                         /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
    __IO uint8_t AP7816B_T0;                         /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
    union {                                          /* offset: 0x3C */
      struct {                                         /* offset: 0x3C */
        __IO uint8_t WP7816A_T0;                         /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
        __IO uint8_t WP7816B_T0;                         /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
      } TYPE0;
      struct {                                         /* offset: 0x3C */
        __IO uint8_t WP7816A_T1;                         /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
        __IO uint8_t WP7816B_T1;                         /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
      } TYPE1;
    };
    __IO uint8_t WGP7816_T1;                         /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
    __IO uint8_t WP7816C_T1;                         /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
  } UART_Type;
  
  /* ----------------------------------------------------------------------------
     -- UART Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup UART_Register_Masks UART Register Masks
   * @{
   */
  
  /*! @name BDH - UART Baud Rate Registers: High */
  /*! @{ */
  #define UART_BDH_SBR_MASK                        (0x1FU)
  #define UART_BDH_SBR_SHIFT                       (0U)
  #define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
  #define UART_BDH_RXEDGIE_MASK                    (0x40U)
  #define UART_BDH_RXEDGIE_SHIFT                   (6U)
  /*! RXEDGIE - RxD Input Active Edge Interrupt Enable
   *  0b0..Hardware interrupts from RXEDGIF disabled using polling.
   *  0b1..RXEDGIF interrupt request enabled.
   */
  #define UART_BDH_RXEDGIE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
  #define UART_BDH_LBKDIE_MASK                     (0x80U)
  #define UART_BDH_LBKDIE_SHIFT                    (7U)
  /*! LBKDIE - LIN Break Detect Interrupt Enable
   *  0b0..LBKDIF interrupt requests disabled.
   *  0b1..LBKDIF interrupt requests enabled.
   */
  #define UART_BDH_LBKDIE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
  /*! @} */
  
  /*! @name BDL - UART Baud Rate Registers: Low */
  /*! @{ */
  #define UART_BDL_SBR_MASK                        (0xFFU)
  #define UART_BDL_SBR_SHIFT                       (0U)
  #define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
  /*! @} */
  
  /*! @name C1 - UART Control Register 1 */
  /*! @{ */
  #define UART_C1_PT_MASK                          (0x1U)
  #define UART_C1_PT_SHIFT                         (0U)
  /*! PT - Parity Type
   *  0b0..Even parity.
   *  0b1..Odd parity.
   */
  #define UART_C1_PT(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
  #define UART_C1_PE_MASK                          (0x2U)
  #define UART_C1_PE_SHIFT                         (1U)
  /*! PE - Parity Enable
   *  0b0..Parity function disabled.
   *  0b1..Parity function enabled.
   */
  #define UART_C1_PE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
  #define UART_C1_ILT_MASK                         (0x4U)
  #define UART_C1_ILT_SHIFT                        (2U)
  /*! ILT - Idle Line Type Select
   *  0b0..Idle character bit count starts after start bit.
   *  0b1..Idle character bit count starts after stop bit.
   */
  #define UART_C1_ILT(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
  #define UART_C1_WAKE_MASK                        (0x8U)
  #define UART_C1_WAKE_SHIFT                       (3U)
  /*! WAKE - Receiver Wakeup Method Select
   *  0b0..Idle line wakeup.
   *  0b1..Address mark wakeup.
   */
  #define UART_C1_WAKE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
  #define UART_C1_M_MASK                           (0x10U)
  #define UART_C1_M_SHIFT                          (4U)
  /*! M - 9-bit or 8-bit Mode Select
   *  0b0..Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
   *  0b1..Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
   */
  #define UART_C1_M(x)                             (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
  #define UART_C1_RSRC_MASK                        (0x20U)
  #define UART_C1_RSRC_SHIFT                       (5U)
  /*! RSRC - Receiver Source Select
   *  0b0..Selects internal loop back mode. The receiver input is internally connected to transmitter output.
   *  0b1..Single wire UART mode where the receiver input is connected to the transmit pin input signal.
   */
  #define UART_C1_RSRC(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
  #define UART_C1_UARTSWAI_MASK                    (0x40U)
  #define UART_C1_UARTSWAI_SHIFT                   (6U)
  /*! UARTSWAI - UART Stops in Wait Mode
   *  0b0..UART clock continues to run in Wait mode.
   *  0b1..UART clock freezes while CPU is in Wait mode.
   */
  #define UART_C1_UARTSWAI(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
  #define UART_C1_LOOPS_MASK                       (0x80U)
  #define UART_C1_LOOPS_SHIFT                      (7U)
  /*! LOOPS - Loop Mode Select
   *  0b0..Normal operation.
   *  0b1..Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
   */
  #define UART_C1_LOOPS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
  /*! @} */
  
  /*! @name C2 - UART Control Register 2 */
  /*! @{ */
  #define UART_C2_SBK_MASK                         (0x1U)
  #define UART_C2_SBK_SHIFT                        (0U)
  /*! SBK - Send Break
   *  0b0..Normal transmitter operation.
   *  0b1..Queue break characters to be sent.
   */
  #define UART_C2_SBK(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
  #define UART_C2_RWU_MASK                         (0x2U)
  #define UART_C2_RWU_SHIFT                        (1U)
  /*! RWU - Receiver Wakeup Control
   *  0b0..Normal operation.
   *  0b1..RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
   */
  #define UART_C2_RWU(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
  #define UART_C2_RE_MASK                          (0x4U)
  #define UART_C2_RE_SHIFT                         (2U)
  /*! RE - Receiver Enable
   *  0b0..Receiver off.
   *  0b1..Receiver on.
   */
  #define UART_C2_RE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
  #define UART_C2_TE_MASK                          (0x8U)
  #define UART_C2_TE_SHIFT                         (3U)
  /*! TE - Transmitter Enable
   *  0b0..Transmitter off.
   *  0b1..Transmitter on.
   */
  #define UART_C2_TE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
  #define UART_C2_ILIE_MASK                        (0x10U)
  #define UART_C2_ILIE_SHIFT                       (4U)
  /*! ILIE - Idle Line Interrupt Enable
   *  0b0..IDLE interrupt requests disabled.
   *  0b1..IDLE interrupt requests enabled.
   */
  #define UART_C2_ILIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
  #define UART_C2_RIE_MASK                         (0x20U)
  #define UART_C2_RIE_SHIFT                        (5U)
  /*! RIE - Receiver Full Interrupt or DMA Transfer Enable
   *  0b0..RDRF interrupt and DMA transfer requests disabled.
   *  0b1..RDRF interrupt or DMA transfer requests enabled.
   */
  #define UART_C2_RIE(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
  #define UART_C2_TCIE_MASK                        (0x40U)
  #define UART_C2_TCIE_SHIFT                       (6U)
  /*! TCIE - Transmission Complete Interrupt Enable
   *  0b0..TC interrupt requests disabled.
   *  0b1..TC interrupt requests enabled.
   */
  #define UART_C2_TCIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
  #define UART_C2_TIE_MASK                         (0x80U)
  #define UART_C2_TIE_SHIFT                        (7U)
  /*! TIE - Transmitter Interrupt or DMA Transfer Enable.
   *  0b0..TDRE interrupt and DMA transfer requests disabled.
   *  0b1..TDRE interrupt or DMA transfer requests enabled.
   */
  #define UART_C2_TIE(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
  /*! @} */
  
  /*! @name S1 - UART Status Register 1 */
  /*! @{ */
  #define UART_S1_PF_MASK                          (0x1U)
  #define UART_S1_PF_SHIFT                         (0U)
  /*! PF - Parity Error Flag
   *  0b0..No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
   *  0b1..At least one dataword was received with a parity error since the last time this flag was cleared.
   */
  #define UART_S1_PF(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
  #define UART_S1_FE_MASK                          (0x2U)
  #define UART_S1_FE_SHIFT                         (1U)
  /*! FE - Framing Error Flag
   *  0b0..No framing error detected.
   *  0b1..Framing error.
   */
  #define UART_S1_FE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
  #define UART_S1_NF_MASK                          (0x4U)
  #define UART_S1_NF_SHIFT                         (2U)
  /*! NF - Noise Flag
   *  0b0..No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
   *  0b1..At least one dataword was received with noise detected since the last time the flag was cleared.
   */
  #define UART_S1_NF(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
  #define UART_S1_OR_MASK                          (0x8U)
  #define UART_S1_OR_SHIFT                         (3U)
  /*! OR - Receiver Overrun Flag
   *  0b0..No overrun has occurred since the last time the flag was cleared.
   *  0b1..Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
   */
  #define UART_S1_OR(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
  #define UART_S1_IDLE_MASK                        (0x10U)
  #define UART_S1_IDLE_SHIFT                       (4U)
  /*! IDLE - Idle Line Flag
   *  0b0..Receiver input is either active now or has never become active since the IDLE flag was last cleared.
   *  0b1..Receiver input has become idle or the flag has not been cleared since it last asserted.
   */
  #define UART_S1_IDLE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
  #define UART_S1_RDRF_MASK                        (0x20U)
  #define UART_S1_RDRF_SHIFT                       (5U)
  /*! RDRF - Receive Data Register Full Flag
   *  0b0..The number of datawords in the receive buffer is less than the number indicated by RXWATER.
   *  0b1..The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
   */
  #define UART_S1_RDRF(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
  #define UART_S1_TC_MASK                          (0x40U)
  #define UART_S1_TC_SHIFT                         (6U)
  /*! TC - Transmit Complete Flag
   *  0b0..Transmitter active (sending data, a preamble, or a break).
   *  0b1..Transmitter idle (transmission activity complete).
   */
  #define UART_S1_TC(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
  #define UART_S1_TDRE_MASK                        (0x80U)
  #define UART_S1_TDRE_SHIFT                       (7U)
  /*! TDRE - Transmit Data Register Empty Flag
   *  0b0..The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
   *  0b1..The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.
   */
  #define UART_S1_TDRE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
  /*! @} */
  
  /*! @name S2 - UART Status Register 2 */
  /*! @{ */
  #define UART_S2_RAF_MASK                         (0x1U)
  #define UART_S2_RAF_SHIFT                        (0U)
  /*! RAF - Receiver Active Flag
   *  0b0..UART receiver idle/inactive waiting for a start bit.
   *  0b1..UART receiver active, RxD input not idle.
   */
  #define UART_S2_RAF(x)                           (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
  #define UART_S2_LBKDE_MASK                       (0x2U)
  #define UART_S2_LBKDE_SHIFT                      (1U)
  /*! LBKDE - LIN Break Detection Enable
   *  0b0..Break character detection is disabled.
   *  0b1..Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.
   */
  #define UART_S2_LBKDE(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
  #define UART_S2_BRK13_MASK                       (0x4U)
  #define UART_S2_BRK13_SHIFT                      (2U)
  /*! BRK13 - Break Transmit Character Length
   *  0b0..Break character is 10, 11, or 12 bits long.
   *  0b1..Break character is 13 or 14 bits long.
   */
  #define UART_S2_BRK13(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
  #define UART_S2_RWUID_MASK                       (0x8U)
  #define UART_S2_RWUID_SHIFT                      (3U)
  /*! RWUID - Receive Wakeup Idle Detect
   *  0b0..S1[IDLE] is not set upon detection of an idle character.
   *  0b1..S1[IDLE] is set upon detection of an idle character.
   */
  #define UART_S2_RWUID(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
  #define UART_S2_RXINV_MASK                       (0x10U)
  #define UART_S2_RXINV_SHIFT                      (4U)
  /*! RXINV - Receive Data Inversion
   *  0b0..Receive data is not inverted.
   *  0b1..Receive data is inverted.
   */
  #define UART_S2_RXINV(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
  #define UART_S2_MSBF_MASK                        (0x20U)
  #define UART_S2_MSBF_SHIFT                       (5U)
  /*! MSBF - Most Significant Bit First
   *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
   *  0b1..MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
   */
  #define UART_S2_MSBF(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
  #define UART_S2_RXEDGIF_MASK                     (0x40U)
  #define UART_S2_RXEDGIF_SHIFT                    (6U)
  /*! RXEDGIF - RxD Pin Active Edge Interrupt Flag
   *  0b0..No active edge on the receive pin has occurred.
   *  0b1..An active edge on the receive pin has occurred.
   */
  #define UART_S2_RXEDGIF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
  #define UART_S2_LBKDIF_MASK                      (0x80U)
  #define UART_S2_LBKDIF_SHIFT                     (7U)
  /*! LBKDIF - LIN Break Detect Interrupt Flag
   *  0b0..No LIN break character detected.
   *  0b1..LIN break character detected.
   */
  #define UART_S2_LBKDIF(x)                        (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
  /*! @} */
  
  /*! @name C3 - UART Control Register 3 */
  /*! @{ */
  #define UART_C3_PEIE_MASK                        (0x1U)
  #define UART_C3_PEIE_SHIFT                       (0U)
  /*! PEIE - Parity Error Interrupt Enable
   *  0b0..PF interrupt requests are disabled.
   *  0b1..PF interrupt requests are enabled.
   */
  #define UART_C3_PEIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
  #define UART_C3_FEIE_MASK                        (0x2U)
  #define UART_C3_FEIE_SHIFT                       (1U)
  /*! FEIE - Framing Error Interrupt Enable
   *  0b0..FE interrupt requests are disabled.
   *  0b1..FE interrupt requests are enabled.
   */
  #define UART_C3_FEIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
  #define UART_C3_NEIE_MASK                        (0x4U)
  #define UART_C3_NEIE_SHIFT                       (2U)
  /*! NEIE - Noise Error Interrupt Enable
   *  0b0..NF interrupt requests are disabled.
   *  0b1..NF interrupt requests are enabled.
   */
  #define UART_C3_NEIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
  #define UART_C3_ORIE_MASK                        (0x8U)
  #define UART_C3_ORIE_SHIFT                       (3U)
  /*! ORIE - Overrun Error Interrupt Enable
   *  0b0..OR interrupts are disabled.
   *  0b1..OR interrupt requests are enabled.
   */
  #define UART_C3_ORIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
  #define UART_C3_TXINV_MASK                       (0x10U)
  #define UART_C3_TXINV_SHIFT                      (4U)
  /*! TXINV - Transmit Data Inversion.
   *  0b0..Transmit data is not inverted.
   *  0b1..Transmit data is inverted.
   */
  #define UART_C3_TXINV(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
  #define UART_C3_TXDIR_MASK                       (0x20U)
  #define UART_C3_TXDIR_SHIFT                      (5U)
  /*! TXDIR - Transmitter Pin Data Direction in Single-Wire mode
   *  0b0..TXD pin is an input in single wire mode.
   *  0b1..TXD pin is an output in single wire mode.
   */
  #define UART_C3_TXDIR(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
  #define UART_C3_T8_MASK                          (0x40U)
  #define UART_C3_T8_SHIFT                         (6U)
  #define UART_C3_T8(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
  #define UART_C3_R8_MASK                          (0x80U)
  #define UART_C3_R8_SHIFT                         (7U)
  #define UART_C3_R8(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
  /*! @} */
  
  /*! @name D - UART Data Register */
  /*! @{ */
  #define UART_D_RT_MASK                           (0xFFU)
  #define UART_D_RT_SHIFT                          (0U)
  #define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
  /*! @} */
  
  /*! @name MA1 - UART Match Address Registers 1 */
  /*! @{ */
  #define UART_MA1_MA_MASK                         (0xFFU)
  #define UART_MA1_MA_SHIFT                        (0U)
  #define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
  /*! @} */
  
  /*! @name MA2 - UART Match Address Registers 2 */
  /*! @{ */
  #define UART_MA2_MA_MASK                         (0xFFU)
  #define UART_MA2_MA_SHIFT                        (0U)
  #define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
  /*! @} */
  
  /*! @name C4 - UART Control Register 4 */
  /*! @{ */
  #define UART_C4_BRFA_MASK                        (0x1FU)
  #define UART_C4_BRFA_SHIFT                       (0U)
  #define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
  #define UART_C4_M10_MASK                         (0x20U)
  #define UART_C4_M10_SHIFT                        (5U)
  /*! M10 - 10-bit Mode select
   *  0b0..The parity bit is the ninth bit in the serial transmission.
   *  0b1..The parity bit is the tenth bit in the serial transmission.
   */
  #define UART_C4_M10(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
  #define UART_C4_MAEN2_MASK                       (0x40U)
  #define UART_C4_MAEN2_SHIFT                      (6U)
  /*! MAEN2 - Match Address Mode Enable 2
   *  0b0..All data received is transferred to the data buffer if MAEN1 is cleared.
   *  0b1..All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
   */
  #define UART_C4_MAEN2(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
  #define UART_C4_MAEN1_MASK                       (0x80U)
  #define UART_C4_MAEN1_SHIFT                      (7U)
  /*! MAEN1 - Match Address Mode Enable 1
   *  0b0..All data received is transferred to the data buffer if MAEN2 is cleared.
   *  0b1..All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
   */
  #define UART_C4_MAEN1(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
  /*! @} */
  
  /*! @name C5 - UART Control Register 5 */
  /*! @{ */
  #define UART_C5_RDMAS_MASK                       (0x20U)
  #define UART_C5_RDMAS_SHIFT                      (5U)
  /*! RDMAS - Receiver Full DMA Select
   *  0b0..If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
   *  0b1..If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
   */
  #define UART_C5_RDMAS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
  #define UART_C5_TDMAS_MASK                       (0x80U)
  #define UART_C5_TDMAS_SHIFT                      (7U)
  /*! TDMAS - Transmitter DMA Select
   *  0b0..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
   *  0b1..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
   */
  #define UART_C5_TDMAS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
  /*! @} */
  
  /*! @name ED - UART Extended Data Register */
  /*! @{ */
  #define UART_ED_PARITYE_MASK                     (0x40U)
  #define UART_ED_PARITYE_SHIFT                    (6U)
  /*! PARITYE
   *  0b0..The dataword was received without a parity error.
   *  0b1..The dataword was received with a parity error.
   */
  #define UART_ED_PARITYE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
  #define UART_ED_NOISY_MASK                       (0x80U)
  #define UART_ED_NOISY_SHIFT                      (7U)
  /*! NOISY
   *  0b0..The dataword was received without noise.
   *  0b1..The data was received with noise.
   */
  #define UART_ED_NOISY(x)                         (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
  /*! @} */
  
  /*! @name MODEM - UART Modem Register */
  /*! @{ */
  #define UART_MODEM_TXCTSE_MASK                   (0x1U)
  #define UART_MODEM_TXCTSE_SHIFT                  (0U)
  /*! TXCTSE - Transmitter clear-to-send enable
   *  0b0..CTS has no effect on the transmitter.
   *  0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
   */
  #define UART_MODEM_TXCTSE(x)                     (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
  #define UART_MODEM_TXRTSE_MASK                   (0x2U)
  #define UART_MODEM_TXRTSE_SHIFT                  (1U)
  /*! TXRTSE - Transmitter request-to-send enable
   *  0b0..The transmitter has no effect on RTS.
   *  0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
   */
  #define UART_MODEM_TXRTSE(x)                     (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
  #define UART_MODEM_TXRTSPOL_MASK                 (0x4U)
  #define UART_MODEM_TXRTSPOL_SHIFT                (2U)
  /*! TXRTSPOL - Transmitter request-to-send polarity
   *  0b0..Transmitter RTS is active low.
   *  0b1..Transmitter RTS is active high.
   */
  #define UART_MODEM_TXRTSPOL(x)                   (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
  #define UART_MODEM_RXRTSE_MASK                   (0x8U)
  #define UART_MODEM_RXRTSE_SHIFT                  (3U)
  /*! RXRTSE - Receiver request-to-send enable
   *  0b0..The receiver has no effect on RTS.
   *  0b1..RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
   */
  #define UART_MODEM_RXRTSE(x)                     (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
  /*! @} */
  
  /*! @name IR - UART Infrared Register */
  /*! @{ */
  #define UART_IR_TNP_MASK                         (0x3U)
  #define UART_IR_TNP_SHIFT                        (0U)
  /*! TNP - Transmitter narrow pulse
   *  0b00..3/16.
   *  0b01..1/16.
   *  0b10..1/32.
   *  0b11..1/4.
   */
  #define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
  #define UART_IR_IREN_MASK                        (0x4U)
  #define UART_IR_IREN_SHIFT                       (2U)
  /*! IREN - Infrared enable
   *  0b0..IR disabled.
   *  0b1..IR enabled.
   */
  #define UART_IR_IREN(x)                          (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
  /*! @} */
  
  /*! @name PFIFO - UART FIFO Parameters */
  /*! @{ */
  #define UART_PFIFO_RXFIFOSIZE_MASK               (0x7U)
  #define UART_PFIFO_RXFIFOSIZE_SHIFT              (0U)
  /*! RXFIFOSIZE - Receive FIFO. Buffer Depth
   *  0b000..Receive FIFO/Buffer depth = 1 dataword.
   *  0b001..Receive FIFO/Buffer depth = 4 datawords.
   *  0b010..Receive FIFO/Buffer depth = 8 datawords.
   *  0b011..Receive FIFO/Buffer depth = 16 datawords.
   *  0b100..Receive FIFO/Buffer depth = 32 datawords.
   *  0b101..Receive FIFO/Buffer depth = 64 datawords.
   *  0b110..Receive FIFO/Buffer depth = 128 datawords.
   *  0b111..Reserved.
   */
  #define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
  #define UART_PFIFO_RXFE_MASK                     (0x8U)
  #define UART_PFIFO_RXFE_SHIFT                    (3U)
  /*! RXFE - Receive FIFO Enable
   *  0b0..Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
   *  0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
   */
  #define UART_PFIFO_RXFE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
  #define UART_PFIFO_TXFIFOSIZE_MASK               (0x70U)
  #define UART_PFIFO_TXFIFOSIZE_SHIFT              (4U)
  /*! TXFIFOSIZE - Transmit FIFO. Buffer Depth
   *  0b000..Transmit FIFO/Buffer depth = 1 dataword.
   *  0b001..Transmit FIFO/Buffer depth = 4 datawords.
   *  0b010..Transmit FIFO/Buffer depth = 8 datawords.
   *  0b011..Transmit FIFO/Buffer depth = 16 datawords.
   *  0b100..Transmit FIFO/Buffer depth = 32 datawords.
   *  0b101..Transmit FIFO/Buffer depth = 64 datawords.
   *  0b110..Transmit FIFO/Buffer depth = 128 datawords.
   *  0b111..Reserved.
   */
  #define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
  #define UART_PFIFO_TXFE_MASK                     (0x80U)
  #define UART_PFIFO_TXFE_SHIFT                    (7U)
  /*! TXFE - Transmit FIFO Enable
   *  0b0..Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
   *  0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
   */
  #define UART_PFIFO_TXFE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
  /*! @} */
  
  /*! @name CFIFO - UART FIFO Control Register */
  /*! @{ */
  #define UART_CFIFO_RXUFE_MASK                    (0x1U)
  #define UART_CFIFO_RXUFE_SHIFT                   (0U)
  /*! RXUFE - Receive FIFO Underflow Interrupt Enable
   *  0b0..RXUF flag does not generate an interrupt to the host.
   *  0b1..RXUF flag generates an interrupt to the host.
   */
  #define UART_CFIFO_RXUFE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
  #define UART_CFIFO_TXOFE_MASK                    (0x2U)
  #define UART_CFIFO_TXOFE_SHIFT                   (1U)
  /*! TXOFE - Transmit FIFO Overflow Interrupt Enable
   *  0b0..TXOF flag does not generate an interrupt to the host.
   *  0b1..TXOF flag generates an interrupt to the host.
   */
  #define UART_CFIFO_TXOFE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
  #define UART_CFIFO_RXOFE_MASK                    (0x4U)
  #define UART_CFIFO_RXOFE_SHIFT                   (2U)
  /*! RXOFE - Receive FIFO Overflow Interrupt Enable
   *  0b0..RXOF flag does not generate an interrupt to the host.
   *  0b1..RXOF flag generates an interrupt to the host.
   */
  #define UART_CFIFO_RXOFE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
  #define UART_CFIFO_RXFLUSH_MASK                  (0x40U)
  #define UART_CFIFO_RXFLUSH_SHIFT                 (6U)
  /*! RXFLUSH - Receive FIFO/Buffer Flush
   *  0b0..No flush operation occurs.
   *  0b1..All data in the receive FIFO/buffer is cleared out.
   */
  #define UART_CFIFO_RXFLUSH(x)                    (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
  #define UART_CFIFO_TXFLUSH_MASK                  (0x80U)
  #define UART_CFIFO_TXFLUSH_SHIFT                 (7U)
  /*! TXFLUSH - Transmit FIFO/Buffer Flush
   *  0b0..No flush operation occurs.
   *  0b1..All data in the transmit FIFO/Buffer is cleared out.
   */
  #define UART_CFIFO_TXFLUSH(x)                    (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
  /*! @} */
  
  /*! @name SFIFO - UART FIFO Status Register */
  /*! @{ */
  #define UART_SFIFO_RXUF_MASK                     (0x1U)
  #define UART_SFIFO_RXUF_SHIFT                    (0U)
  /*! RXUF - Receiver Buffer Underflow Flag
   *  0b0..No receive buffer underflow has occurred since the last time the flag was cleared.
   *  0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared.
   */
  #define UART_SFIFO_RXUF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
  #define UART_SFIFO_TXOF_MASK                     (0x2U)
  #define UART_SFIFO_TXOF_SHIFT                    (1U)
  /*! TXOF - Transmitter Buffer Overflow Flag
   *  0b0..No transmit buffer overflow has occurred since the last time the flag was cleared.
   *  0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared.
   */
  #define UART_SFIFO_TXOF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
  #define UART_SFIFO_RXOF_MASK                     (0x4U)
  #define UART_SFIFO_RXOF_SHIFT                    (2U)
  /*! RXOF - Receiver Buffer Overflow Flag
   *  0b0..No receive buffer overflow has occurred since the last time the flag was cleared.
   *  0b1..At least one receive buffer overflow has occurred since the last time the flag was cleared.
   */
  #define UART_SFIFO_RXOF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
  #define UART_SFIFO_RXEMPT_MASK                   (0x40U)
  #define UART_SFIFO_RXEMPT_SHIFT                  (6U)
  /*! RXEMPT - Receive Buffer/FIFO Empty
   *  0b0..Receive buffer is not empty.
   *  0b1..Receive buffer is empty.
   */
  #define UART_SFIFO_RXEMPT(x)                     (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
  #define UART_SFIFO_TXEMPT_MASK                   (0x80U)
  #define UART_SFIFO_TXEMPT_SHIFT                  (7U)
  /*! TXEMPT - Transmit Buffer/FIFO Empty
   *  0b0..Transmit buffer is not empty.
   *  0b1..Transmit buffer is empty.
   */
  #define UART_SFIFO_TXEMPT(x)                     (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
  /*! @} */
  
  /*! @name TWFIFO - UART FIFO Transmit Watermark */
  /*! @{ */
  #define UART_TWFIFO_TXWATER_MASK                 (0xFFU)
  #define UART_TWFIFO_TXWATER_SHIFT                (0U)
  #define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
  /*! @} */
  
  /*! @name TCFIFO - UART FIFO Transmit Count */
  /*! @{ */
  #define UART_TCFIFO_TXCOUNT_MASK                 (0xFFU)
  #define UART_TCFIFO_TXCOUNT_SHIFT                (0U)
  #define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
  /*! @} */
  
  /*! @name RWFIFO - UART FIFO Receive Watermark */
  /*! @{ */
  #define UART_RWFIFO_RXWATER_MASK                 (0xFFU)
  #define UART_RWFIFO_RXWATER_SHIFT                (0U)
  #define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
  /*! @} */
  
  /*! @name RCFIFO - UART FIFO Receive Count */
  /*! @{ */
  #define UART_RCFIFO_RXCOUNT_MASK                 (0xFFU)
  #define UART_RCFIFO_RXCOUNT_SHIFT                (0U)
  #define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
  /*! @} */
  
  /*! @name C7816 - UART 7816 Control Register */
  /*! @{ */
  #define UART_C7816_ISO_7816E_MASK                (0x1U)
  #define UART_C7816_ISO_7816E_SHIFT               (0U)
  /*! ISO_7816E - ISO-7816 Functionality Enabled
   *  0b0..ISO-7816 functionality is turned off/not enabled.
   *  0b1..ISO-7816 functionality is turned on/enabled.
   */
  #define UART_C7816_ISO_7816E(x)                  (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
  #define UART_C7816_TTYPE_MASK                    (0x2U)
  #define UART_C7816_TTYPE_SHIFT                   (1U)
  /*! TTYPE - Transfer Type
   *  0b0..T = 0 per the ISO-7816 specification.
   *  0b1..T = 1 per the ISO-7816 specification.
   */
  #define UART_C7816_TTYPE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
  #define UART_C7816_INIT_MASK                     (0x4U)
  #define UART_C7816_INIT_SHIFT                    (2U)
  /*! INIT - Detect Initial Character
   *  0b0..Normal operating mode. Receiver does not seek to identify initial character.
   *  0b1..Receiver searches for initial character.
   */
  #define UART_C7816_INIT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
  #define UART_C7816_ANACK_MASK                    (0x8U)
  #define UART_C7816_ANACK_SHIFT                   (3U)
  /*! ANACK - Generate NACK on Error
   *  0b0..No NACK is automatically generated.
   *  0b1..A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected.
   */
  #define UART_C7816_ANACK(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
  #define UART_C7816_ONACK_MASK                    (0x10U)
  #define UART_C7816_ONACK_SHIFT                   (4U)
  /*! ONACK - Generate NACK on Overflow
   *  0b0..The received data does not generate a NACK when the receipt of the data results in an overflow event.
   *  0b1..If the receiver buffer overflows, a NACK is automatically sent on a received character.
   */
  #define UART_C7816_ONACK(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
  /*! @} */
  
  /*! @name IE7816 - UART 7816 Interrupt Enable Register */
  /*! @{ */
  #define UART_IE7816_RXTE_MASK                    (0x1U)
  #define UART_IE7816_RXTE_SHIFT                   (0U)
  /*! RXTE - Receive Threshold Exceeded Interrupt Enable
   *  0b0..The assertion of IS7816[RXT] does not result in the generation of an interrupt.
   *  0b1..The assertion of IS7816[RXT] results in the generation of an interrupt.
   */
  #define UART_IE7816_RXTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
  #define UART_IE7816_TXTE_MASK                    (0x2U)
  #define UART_IE7816_TXTE_SHIFT                   (1U)
  /*! TXTE - Transmit Threshold Exceeded Interrupt Enable
   *  0b0..The assertion of IS7816[TXT] does not result in the generation of an interrupt.
   *  0b1..The assertion of IS7816[TXT] results in the generation of an interrupt.
   */
  #define UART_IE7816_TXTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
  #define UART_IE7816_GTVE_MASK                    (0x4U)
  #define UART_IE7816_GTVE_SHIFT                   (2U)
  /*! GTVE - Guard Timer Violated Interrupt Enable
   *  0b0..The assertion of IS7816[GTV] does not result in the generation of an interrupt.
   *  0b1..The assertion of IS7816[GTV] results in the generation of an interrupt.
   */
  #define UART_IE7816_GTVE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
  #define UART_IE7816_ADTE_MASK                    (0x8U)
  #define UART_IE7816_ADTE_SHIFT                   (3U)
  /*! ADTE - ATR Duration Timer Interrupt Enable
   *  0b0..The assertion of IS7816[ADT] does not result in the generation of an interrupt.
   *  0b1..The assertion of IS7816[ADT] results in the generation of an interrupt.
   */
  #define UART_IE7816_ADTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
  #define UART_IE7816_INITDE_MASK                  (0x10U)
  #define UART_IE7816_INITDE_SHIFT                 (4U)
  /*! INITDE - Initial Character Detected Interrupt Enable
   *  0b0..The assertion of IS7816[INITD] does not result in the generation of an interrupt.
   *  0b1..The assertion of IS7816[INITD] results in the generation of an interrupt.
   */
  #define UART_IE7816_INITDE(x)                    (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
  #define UART_IE7816_BWTE_MASK                    (0x20U)
  #define UART_IE7816_BWTE_SHIFT                   (5U)
  /*! BWTE - Block Wait Timer Interrupt Enable
   *  0b0..The assertion of IS7816[BWT] does not result in the generation of an interrupt.
   *  0b1..The assertion of IS7816[BWT] results in the generation of an interrupt.
   */
  #define UART_IE7816_BWTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
  #define UART_IE7816_CWTE_MASK                    (0x40U)
  #define UART_IE7816_CWTE_SHIFT                   (6U)
  /*! CWTE - Character Wait Timer Interrupt Enable
   *  0b0..The assertion of IS7816[CWT] does not result in the generation of an interrupt.
   *  0b1..The assertion of IS7816[CWT] results in the generation of an interrupt.
   */
  #define UART_IE7816_CWTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
  #define UART_IE7816_WTE_MASK                     (0x80U)
  #define UART_IE7816_WTE_SHIFT                    (7U)
  /*! WTE - Wait Timer Interrupt Enable
   *  0b0..The assertion of IS7816[WT] does not result in the generation of an interrupt.
   *  0b1..The assertion of IS7816[WT] results in the generation of an interrupt.
   */
  #define UART_IE7816_WTE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
  /*! @} */
  
  /*! @name IS7816 - UART 7816 Interrupt Status Register */
  /*! @{ */
  #define UART_IS7816_RXT_MASK                     (0x1U)
  #define UART_IS7816_RXT_SHIFT                    (0U)
  /*! RXT - Receive Threshold Exceeded Interrupt
   *  0b0..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD].
   *  0b1..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
   */
  #define UART_IS7816_RXT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
  #define UART_IS7816_TXT_MASK                     (0x2U)
  #define UART_IS7816_TXT_SHIFT                    (1U)
  /*! TXT - Transmit Threshold Exceeded Interrupt
   *  0b0..The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD].
   *  0b1..The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD].
   */
  #define UART_IS7816_TXT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
  #define UART_IS7816_GTV_MASK                     (0x4U)
  #define UART_IS7816_GTV_SHIFT                    (2U)
  /*! GTV - Guard Timer Violated Interrupt
   *  0b0..A guard time (GT, CGT, or BGT) has not been violated.
   *  0b1..A guard time (GT, CGT, or BGT) has been violated.
   */
  #define UART_IS7816_GTV(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
  #define UART_IS7816_ADT_MASK                     (0x8U)
  #define UART_IS7816_ADT_SHIFT                    (3U)
  /*! ADT - ATR Duration Time Interrupt
   *  0b0..ATR Duration time (ADT) has not been violated.
   *  0b1..ATR Duration time (ADT) has been violated.
   */
  #define UART_IS7816_ADT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
  #define UART_IS7816_INITD_MASK                   (0x10U)
  #define UART_IS7816_INITD_SHIFT                  (4U)
  /*! INITD - Initial Character Detected Interrupt
   *  0b0..A valid initial character has not been received.
   *  0b1..A valid initial character has been received.
   */
  #define UART_IS7816_INITD(x)                     (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
  #define UART_IS7816_BWT_MASK                     (0x20U)
  #define UART_IS7816_BWT_SHIFT                    (5U)
  /*! BWT - Block Wait Timer Interrupt
   *  0b0..Block wait time (BWT) has not been violated.
   *  0b1..Block wait time (BWT) has been violated.
   */
  #define UART_IS7816_BWT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
  #define UART_IS7816_CWT_MASK                     (0x40U)
  #define UART_IS7816_CWT_SHIFT                    (6U)
  /*! CWT - Character Wait Timer Interrupt
   *  0b0..Character wait time (CWT) has not been violated.
   *  0b1..Character wait time (CWT) has been violated.
   */
  #define UART_IS7816_CWT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
  #define UART_IS7816_WT_MASK                      (0x80U)
  #define UART_IS7816_WT_SHIFT                     (7U)
  /*! WT - Wait Timer Interrupt
   *  0b0..Wait time (WT) has not been violated.
   *  0b1..Wait time (WT) has been violated.
   */
  #define UART_IS7816_WT(x)                        (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
  /*! @} */
  
  /*! @name WP7816 - UART 7816 Wait Parameter Register */
  /*! @{ */
  #define UART_WP7816_WTX_MASK                     (0xFFU)
  #define UART_WP7816_WTX_SHIFT                    (0U)
  #define UART_WP7816_WTX(x)                       (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
  /*! @} */
  
  /*! @name WN7816 - UART 7816 Wait N Register */
  /*! @{ */
  #define UART_WN7816_GTN_MASK                     (0xFFU)
  #define UART_WN7816_GTN_SHIFT                    (0U)
  #define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
  /*! @} */
  
  /*! @name WF7816 - UART 7816 Wait FD Register */
  /*! @{ */
  #define UART_WF7816_GTFD_MASK                    (0xFFU)
  #define UART_WF7816_GTFD_SHIFT                   (0U)
  #define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
  /*! @} */
  
  /*! @name ET7816 - UART 7816 Error Threshold Register */
  /*! @{ */
  #define UART_ET7816_RXTHRESHOLD_MASK             (0xFU)
  #define UART_ET7816_RXTHRESHOLD_SHIFT            (0U)
  #define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
  #define UART_ET7816_TXTHRESHOLD_MASK             (0xF0U)
  #define UART_ET7816_TXTHRESHOLD_SHIFT            (4U)
  /*! TXTHRESHOLD - Transmit NACK Threshold
   *  0b0000..TXT asserts on the first NACK that is received.
   *  0b0001..TXT asserts on the second NACK that is received.
   */
  #define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
  /*! @} */
  
  /*! @name TL7816 - UART 7816 Transmit Length Register */
  /*! @{ */
  #define UART_TL7816_TLEN_MASK                    (0xFFU)
  #define UART_TL7816_TLEN_SHIFT                   (0U)
  #define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
  /*! @} */
  
  /*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */
  /*! @{ */
  #define UART_AP7816A_T0_ADTI_H_MASK              (0xFFU)
  #define UART_AP7816A_T0_ADTI_H_SHIFT             (0U)
  #define UART_AP7816A_T0_ADTI_H(x)                (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
  /*! @} */
  
  /*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */
  /*! @{ */
  #define UART_AP7816B_T0_ADTI_L_MASK              (0xFFU)
  #define UART_AP7816B_T0_ADTI_L_SHIFT             (0U)
  #define UART_AP7816B_T0_ADTI_L(x)                (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
  /*! @} */
  
  /*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */
  /*! @{ */
  #define UART_WP7816A_T0_WI_H_MASK                (0xFFU)
  #define UART_WP7816A_T0_WI_H_SHIFT               (0U)
  #define UART_WP7816A_T0_WI_H(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
  /*! @} */
  
  /*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */
  /*! @{ */
  #define UART_WP7816B_T0_WI_L_MASK                (0xFFU)
  #define UART_WP7816B_T0_WI_L_SHIFT               (0U)
  #define UART_WP7816B_T0_WI_L(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
  /*! @} */
  
  /*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */
  /*! @{ */
  #define UART_WP7816A_T1_BWI_H_MASK               (0xFFU)
  #define UART_WP7816A_T1_BWI_H_SHIFT              (0U)
  #define UART_WP7816A_T1_BWI_H(x)                 (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
  /*! @} */
  
  /*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */
  /*! @{ */
  #define UART_WP7816B_T1_BWI_L_MASK               (0xFFU)
  #define UART_WP7816B_T1_BWI_L_SHIFT              (0U)
  #define UART_WP7816B_T1_BWI_L(x)                 (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
  /*! @} */
  
  /*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */
  /*! @{ */
  #define UART_WGP7816_T1_BGI_MASK                 (0xFU)
  #define UART_WGP7816_T1_BGI_SHIFT                (0U)
  #define UART_WGP7816_T1_BGI(x)                   (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
  #define UART_WGP7816_T1_CWI1_MASK                (0xF0U)
  #define UART_WGP7816_T1_CWI1_SHIFT               (4U)
  #define UART_WGP7816_T1_CWI1(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
  /*! @} */
  
  /*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */
  /*! @{ */
  #define UART_WP7816C_T1_CWI2_MASK                (0x1FU)
  #define UART_WP7816C_T1_CWI2_SHIFT               (0U)
  #define UART_WP7816C_T1_CWI2(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group UART_Register_Masks */
  
  
  /* UART - Peripheral instance base addresses */
  /** Peripheral UART0 base address */
  #define UART0_BASE                               (0x4006A000u)
  /** Peripheral UART0 base pointer */
  #define UART0                                    ((UART_Type *)UART0_BASE)
  /** Peripheral UART1 base address */
  #define UART1_BASE                               (0x4006B000u)
  /** Peripheral UART1 base pointer */
  #define UART1                                    ((UART_Type *)UART1_BASE)
  /** Peripheral UART2 base address */
  #define UART2_BASE                               (0x4006C000u)
  /** Peripheral UART2 base pointer */
  #define UART2                                    ((UART_Type *)UART2_BASE)
  /** Array initializer of UART peripheral base addresses */
  #define UART_BASE_ADDRS                          { UART0_BASE, UART1_BASE, UART2_BASE }
  /** Array initializer of UART peripheral base pointers */
  #define UART_BASE_PTRS                           { UART0, UART1, UART2 }
  /** Interrupt vectors for the UART peripheral type */
  #define UART_RX_TX_IRQS                          { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn }
  #define UART_ERR_IRQS                            { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn }
  
  /*!
   * @}
   */ /* end of group UART_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- VREF Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
   * @{
   */
  
  /** VREF - Register Layout Typedef */
  typedef struct {
    __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
    __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
  } VREF_Type;
  
  /* ----------------------------------------------------------------------------
     -- VREF Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup VREF_Register_Masks VREF Register Masks
   * @{
   */
  
  /*! @name TRM - VREF Trim Register */
  /*! @{ */
  #define VREF_TRM_TRIM_MASK                       (0x3FU)
  #define VREF_TRM_TRIM_SHIFT                      (0U)
  /*! TRIM - Trim bits
   *  0b000000..Min
   *  0b111111..Max
   */
  #define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
  #define VREF_TRM_CHOPEN_MASK                     (0x40U)
  #define VREF_TRM_CHOPEN_SHIFT                    (6U)
  /*! CHOPEN - Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized.
   *  0b0..Chop oscillator is disabled.
   *  0b1..Chop oscillator is enabled.
   */
  #define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
  /*! @} */
  
  /*! @name SC - VREF Status and Control Register */
  /*! @{ */
  #define VREF_SC_MODE_LV_MASK                     (0x3U)
  #define VREF_SC_MODE_LV_SHIFT                    (0U)
  /*! MODE_LV - Buffer Mode selection
   *  0b00..Bandgap on only, for stabilization and startup
   *  0b01..High power buffer mode enabled
   *  0b10..Low-power buffer mode enabled
   *  0b11..Reserved
   */
  #define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
  #define VREF_SC_VREFST_MASK                      (0x4U)
  #define VREF_SC_VREFST_SHIFT                     (2U)
  /*! VREFST - Internal Voltage Reference stable
   *  0b0..The module is disabled or not stable.
   *  0b1..The module is stable.
   */
  #define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
  #define VREF_SC_ICOMPEN_MASK                     (0x20U)
  #define VREF_SC_ICOMPEN_SHIFT                    (5U)
  /*! ICOMPEN - Second order curvature compensation enable
   *  0b0..Disabled
   *  0b1..Enabled
   */
  #define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
  #define VREF_SC_REGEN_MASK                       (0x40U)
  #define VREF_SC_REGEN_SHIFT                      (6U)
  /*! REGEN - Regulator enable
   *  0b0..Internal 1.75 V regulator is disabled.
   *  0b1..Internal 1.75 V regulator is enabled.
   */
  #define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
  #define VREF_SC_VREFEN_MASK                      (0x80U)
  #define VREF_SC_VREFEN_SHIFT                     (7U)
  /*! VREFEN - Internal Voltage Reference enable
   *  0b0..The module is disabled.
   *  0b1..The module is enabled.
   */
  #define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group VREF_Register_Masks */
  
  
  /* VREF - Peripheral instance base addresses */
  /** Peripheral VREF base address */
  #define VREF_BASE                                (0x40074000u)
  /** Peripheral VREF base pointer */
  #define VREF                                     ((VREF_Type *)VREF_BASE)
  /** Array initializer of VREF peripheral base addresses */
  #define VREF_BASE_ADDRS                          { VREF_BASE }
  /** Array initializer of VREF peripheral base pointers */
  #define VREF_BASE_PTRS                           { VREF }
  
  /*!
   * @}
   */ /* end of group VREF_Peripheral_Access_Layer */
  
  
  /* ----------------------------------------------------------------------------
     -- WDOG Peripheral Access Layer
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
   * @{
   */
  
  /** WDOG - Register Layout Typedef */
  typedef struct {
    __IO uint16_t STCTRLH;                           /**< Watchdog Status and Control Register High, offset: 0x0 */
    __IO uint16_t STCTRLL;                           /**< Watchdog Status and Control Register Low, offset: 0x2 */
    __IO uint16_t TOVALH;                            /**< Watchdog Time-out Value Register High, offset: 0x4 */
    __IO uint16_t TOVALL;                            /**< Watchdog Time-out Value Register Low, offset: 0x6 */
    __IO uint16_t WINH;                              /**< Watchdog Window Register High, offset: 0x8 */
    __IO uint16_t WINL;                              /**< Watchdog Window Register Low, offset: 0xA */
    __IO uint16_t REFRESH;                           /**< Watchdog Refresh register, offset: 0xC */
    __IO uint16_t UNLOCK;                            /**< Watchdog Unlock register, offset: 0xE */
    __IO uint16_t TMROUTH;                           /**< Watchdog Timer Output Register High, offset: 0x10 */
    __IO uint16_t TMROUTL;                           /**< Watchdog Timer Output Register Low, offset: 0x12 */
    __IO uint16_t RSTCNT;                            /**< Watchdog Reset Count register, offset: 0x14 */
    __IO uint16_t PRESC;                             /**< Watchdog Prescaler register, offset: 0x16 */
  } WDOG_Type;
  
  /* ----------------------------------------------------------------------------
     -- WDOG Register Masks
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup WDOG_Register_Masks WDOG Register Masks
   * @{
   */
  
  /*! @name STCTRLH - Watchdog Status and Control Register High */
  /*! @{ */
  #define WDOG_STCTRLH_WDOGEN_MASK                 (0x1U)
  #define WDOG_STCTRLH_WDOGEN_SHIFT                (0U)
  /*! WDOGEN
   *  0b0..WDOG is disabled.
   *  0b1..WDOG is enabled.
   */
  #define WDOG_STCTRLH_WDOGEN(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
  #define WDOG_STCTRLH_CLKSRC_MASK                 (0x2U)
  #define WDOG_STCTRLH_CLKSRC_SHIFT                (1U)
  /*! CLKSRC
   *  0b0..WDOG clock sourced from LPO .
   *  0b1..WDOG clock sourced from alternate clock source.
   */
  #define WDOG_STCTRLH_CLKSRC(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
  #define WDOG_STCTRLH_IRQRSTEN_MASK               (0x4U)
  #define WDOG_STCTRLH_IRQRSTEN_SHIFT              (2U)
  /*! IRQRSTEN
   *  0b0..WDOG time-out generates reset only.
   *  0b1..WDOG time-out initially generates an interrupt. After WCT, it generates a reset.
   */
  #define WDOG_STCTRLH_IRQRSTEN(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
  #define WDOG_STCTRLH_WINEN_MASK                  (0x8U)
  #define WDOG_STCTRLH_WINEN_SHIFT                 (3U)
  /*! WINEN
   *  0b0..Windowing mode is disabled.
   *  0b1..Windowing mode is enabled.
   */
  #define WDOG_STCTRLH_WINEN(x)                    (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
  #define WDOG_STCTRLH_ALLOWUPDATE_MASK            (0x10U)
  #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT           (4U)
  /*! ALLOWUPDATE
   *  0b0..No further updates allowed to WDOG write-once registers.
   *  0b1..WDOG write-once registers can be unlocked for updating.
   */
  #define WDOG_STCTRLH_ALLOWUPDATE(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
  #define WDOG_STCTRLH_DBGEN_MASK                  (0x20U)
  #define WDOG_STCTRLH_DBGEN_SHIFT                 (5U)
  /*! DBGEN
   *  0b0..WDOG is disabled in CPU Debug mode.
   *  0b1..WDOG is enabled in CPU Debug mode.
   */
  #define WDOG_STCTRLH_DBGEN(x)                    (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
  #define WDOG_STCTRLH_STOPEN_MASK                 (0x40U)
  #define WDOG_STCTRLH_STOPEN_SHIFT                (6U)
  /*! STOPEN
   *  0b0..WDOG is disabled in CPU Stop mode.
   *  0b1..WDOG is enabled in CPU Stop mode.
   */
  #define WDOG_STCTRLH_STOPEN(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
  #define WDOG_STCTRLH_WAITEN_MASK                 (0x80U)
  #define WDOG_STCTRLH_WAITEN_SHIFT                (7U)
  /*! WAITEN
   *  0b0..WDOG is disabled in CPU Wait mode.
   *  0b1..WDOG is enabled in CPU Wait mode.
   */
  #define WDOG_STCTRLH_WAITEN(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
  #define WDOG_STCTRLH_TESTWDOG_MASK               (0x400U)
  #define WDOG_STCTRLH_TESTWDOG_SHIFT              (10U)
  #define WDOG_STCTRLH_TESTWDOG(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
  #define WDOG_STCTRLH_TESTSEL_MASK                (0x800U)
  #define WDOG_STCTRLH_TESTSEL_SHIFT               (11U)
  /*! TESTSEL
   *  0b0..Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test.
   *  0b1..Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing.
   */
  #define WDOG_STCTRLH_TESTSEL(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
  #define WDOG_STCTRLH_BYTESEL_MASK                (0x3000U)
  #define WDOG_STCTRLH_BYTESEL_SHIFT               (12U)
  /*! BYTESEL
   *  0b00..Byte 0 selected
   *  0b01..Byte 1 selected
   *  0b10..Byte 2 selected
   *  0b11..Byte 3 selected
   */
  #define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
  #define WDOG_STCTRLH_DISTESTWDOG_MASK            (0x4000U)
  #define WDOG_STCTRLH_DISTESTWDOG_SHIFT           (14U)
  /*! DISTESTWDOG
   *  0b0..WDOG functional test mode is not disabled.
   *  0b1..WDOG functional test mode is disabled permanently until reset.
   */
  #define WDOG_STCTRLH_DISTESTWDOG(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
  /*! @} */
  
  /*! @name STCTRLL - Watchdog Status and Control Register Low */
  /*! @{ */
  #define WDOG_STCTRLL_INTFLG_MASK                 (0x8000U)
  #define WDOG_STCTRLL_INTFLG_SHIFT                (15U)
  #define WDOG_STCTRLL_INTFLG(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
  /*! @} */
  
  /*! @name TOVALH - Watchdog Time-out Value Register High */
  /*! @{ */
  #define WDOG_TOVALH_TOVALHIGH_MASK               (0xFFFFU)
  #define WDOG_TOVALH_TOVALHIGH_SHIFT              (0U)
  #define WDOG_TOVALH_TOVALHIGH(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
  /*! @} */
  
  /*! @name TOVALL - Watchdog Time-out Value Register Low */
  /*! @{ */
  #define WDOG_TOVALL_TOVALLOW_MASK                (0xFFFFU)
  #define WDOG_TOVALL_TOVALLOW_SHIFT               (0U)
  #define WDOG_TOVALL_TOVALLOW(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
  /*! @} */
  
  /*! @name WINH - Watchdog Window Register High */
  /*! @{ */
  #define WDOG_WINH_WINHIGH_MASK                   (0xFFFFU)
  #define WDOG_WINH_WINHIGH_SHIFT                  (0U)
  #define WDOG_WINH_WINHIGH(x)                     (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
  /*! @} */
  
  /*! @name WINL - Watchdog Window Register Low */
  /*! @{ */
  #define WDOG_WINL_WINLOW_MASK                    (0xFFFFU)
  #define WDOG_WINL_WINLOW_SHIFT                   (0U)
  #define WDOG_WINL_WINLOW(x)                      (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
  /*! @} */
  
  /*! @name REFRESH - Watchdog Refresh register */
  /*! @{ */
  #define WDOG_REFRESH_WDOGREFRESH_MASK            (0xFFFFU)
  #define WDOG_REFRESH_WDOGREFRESH_SHIFT           (0U)
  #define WDOG_REFRESH_WDOGREFRESH(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
  /*! @} */
  
  /*! @name UNLOCK - Watchdog Unlock register */
  /*! @{ */
  #define WDOG_UNLOCK_WDOGUNLOCK_MASK              (0xFFFFU)
  #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT             (0U)
  #define WDOG_UNLOCK_WDOGUNLOCK(x)                (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
  /*! @} */
  
  /*! @name TMROUTH - Watchdog Timer Output Register High */
  /*! @{ */
  #define WDOG_TMROUTH_TIMEROUTHIGH_MASK           (0xFFFFU)
  #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT          (0U)
  #define WDOG_TMROUTH_TIMEROUTHIGH(x)             (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
  /*! @} */
  
  /*! @name TMROUTL - Watchdog Timer Output Register Low */
  /*! @{ */
  #define WDOG_TMROUTL_TIMEROUTLOW_MASK            (0xFFFFU)
  #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT           (0U)
  #define WDOG_TMROUTL_TIMEROUTLOW(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
  /*! @} */
  
  /*! @name RSTCNT - Watchdog Reset Count register */
  /*! @{ */
  #define WDOG_RSTCNT_RSTCNT_MASK                  (0xFFFFU)
  #define WDOG_RSTCNT_RSTCNT_SHIFT                 (0U)
  #define WDOG_RSTCNT_RSTCNT(x)                    (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
  /*! @} */
  
  /*! @name PRESC - Watchdog Prescaler register */
  /*! @{ */
  #define WDOG_PRESC_PRESCVAL_MASK                 (0x700U)
  #define WDOG_PRESC_PRESCVAL_SHIFT                (8U)
  #define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
  /*! @} */
  
  
  /*!
   * @}
   */ /* end of group WDOG_Register_Masks */
  
  
  /* WDOG - Peripheral instance base addresses */
  /** Peripheral WDOG base address */
  #define WDOG_BASE                                (0x40052000u)
  /** Peripheral WDOG base pointer */
  #define WDOG                                     ((WDOG_Type *)WDOG_BASE)
  /** Array initializer of WDOG peripheral base addresses */
  #define WDOG_BASE_ADDRS                          { WDOG_BASE }
  /** Array initializer of WDOG peripheral base pointers */
  #define WDOG_BASE_PTRS                           { WDOG }
  /** Interrupt vectors for the WDOG peripheral type */
  #define WDOG_IRQS                                { WDOG_EWM_IRQn }
  
  /*!
   * @}
   */ /* end of group WDOG_Peripheral_Access_Layer */
  
  
  /*
  ** End of section using anonymous unions
  */
  
  #if defined(__ARMCC_VERSION)
    #if (__ARMCC_VERSION >= 6010050)
      #pragma clang diagnostic pop
    #else
      #pragma pop
    #endif
  #elif defined(__CWCC__)
    #pragma pop
  #elif defined(__GNUC__)
    /* leave anonymous unions enabled */
  #elif defined(__IAR_SYSTEMS_ICC__)
    #pragma language=default
  #else
    #error Not supported compiler type
  #endif
  
  /*!
   * @}
   */ /* end of group Peripheral_access_layer */
  
  
  /* ----------------------------------------------------------------------------
     -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
   * @{
   */
  
  #if defined(__ARMCC_VERSION)
    #if (__ARMCC_VERSION >= 6010050)
      #pragma clang system_header
    #endif
  #elif defined(__IAR_SYSTEMS_ICC__)
    #pragma system_include
  #endif
  
  /**
   * @brief Mask and left-shift a bit field value for use in a register bit range.
   * @param field Name of the register bit field.
   * @param value Value of the bit field.
   * @return Masked and shifted value.
   */
  #define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
  /**
   * @brief Mask and right-shift a register value to extract a bit field value.
   * @param field Name of the register bit field.
   * @param value Value of the register.
   * @return Masked and shifted bit field value.
   */
  #define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
  
  /*!
   * @}
   */ /* end of group Bit_Field_Generic_Macros */
  
  
  /* ----------------------------------------------------------------------------
     -- SDK Compatibility
     ---------------------------------------------------------------------------- */
  
  /*!
   * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
   * @{
   */
  
  #define I2C0_S1                      I2C0_S
  #define I2C1_S1                      I2C1_S
  #define MCM_ISR_REG(base)            MCM_ISCR_REG(base)
  #define MCM_ISR_FIOC_MASK            MCM_ISCR_FIOC_MASK
  #define MCM_ISR_FIOC_SHIFT           MCM_ISCR_FIOC_SHIFT
  #define MCM_ISR_FDZC_MASK            MCM_ISCR_FDZC_MASK
  #define MCM_ISR_FDZC_SHIFT           MCM_ISCR_FDZC_SHIFT
  #define MCM_ISR_FOFC_MASK            MCM_ISCR_FOFC_MASK
  #define MCM_ISR_FOFC_SHIFT           MCM_ISCR_FOFC_SHIFT
  #define MCM_ISR_FUFC_MASK            MCM_ISCR_FUFC_MASK
  #define MCM_ISR_FUFC_SHIFT           MCM_ISCR_FUFC_SHIFT
  #define MCM_ISR_FIXC_MASK            MCM_ISCR_FIXC_MASK
  #define MCM_ISR_FIXC_SHIFT           MCM_ISCR_FIXC_SHIFT
  #define MCM_ISR_FIDC_MASK            MCM_ISCR_FIDC_MASK
  #define MCM_ISR_FIDC_SHIFT           MCM_ISCR_FIDC_SHIFT
  #define MCM_ISR_FIOCE_MASK           MCM_ISCR_FIOCE_MASK
  #define MCM_ISR_FIOCE_SHIFT          MCM_ISCR_FIOCE_SHIFT
  #define MCM_ISR_FDZCE_MASK           MCM_ISCR_FDZCE_MASK
  #define MCM_ISR_FDZCE_SHIFT          MCM_ISCR_FDZCE_SHIFT
  #define MCM_ISR_FOFCE_MASK           MCM_ISCR_FOFCE_MASK
  #define MCM_ISR_FOFCE_SHIFT          MCM_ISCR_FOFCE_SHIFT
  #define MCM_ISR_FUFCE_MASK           MCM_ISCR_FUFCE_MASK
  #define MCM_ISR_FUFCE_SHIFT          MCM_ISCR_FUFCE_SHIFT
  #define MCM_ISR_FIXCE_MASK           MCM_ISCR_FIXCE_MASK
  #define MCM_ISR_FIXCE_SHIFT          MCM_ISCR_FIXCE_SHIFT
  #define MCM_ISR_FIDCE_MASK           MCM_ISCR_FIDCE_MASK
  #define MCM_ISR_FIDCE_SHIFT          MCM_ISCR_FIDCE_SHIFT
  #define PDB0_DACINTC1                This_symbol_has_been_deprecated
  #define PDB0_DACINT1                 This_symbol_has_been_deprecated
  #define DSPI0                        SPI0
  #define DSPI1                        SPI1
  #define PTA_BASE                     GPIOA_BASE
  #define PTA                          GPIOA
  #define PTB_BASE                     GPIOB_BASE
  #define PTB                          GPIOB
  #define PTC_BASE                     GPIOC_BASE
  #define PTC                          GPIOC
  #define PTD_BASE                     GPIOD_BASE
  #define PTD                          GPIOD
  #define PTE_BASE                     GPIOE_BASE
  #define PTE                          GPIOE
  #define DMAMUX0                      DMAMUX
  #define SMC_STOPCTRL_LPOPO_MASK      This_symbol_has_been_deprecated
  #define SMC_STOPCTRL_LPOPO_SHIFT     This_symbol_has_been_deprecated
  #define USB0_OTGCTL0                 USB0_OTGCTL
  #define USB0_CTL1                    USB0_CTL
  #define Watchdog_IRQn                WDOG_EWM_IRQn
  #define Watchdog_IRQHandler          WDOG_EWM_IRQHandler
  #define LPTimer_IRQn                 LPTMR0_IRQn
  #define LPTimer_IRQHandler           LPTMR0_IRQHandler
  #define LLW_IRQn                     LLWU_IRQn
  #define LLW_IRQHandler               LLWU_IRQHandler
  
  /*!
   * @}
   */ /* end of group SDK_Compatibility_Symbols */
  
  
  #endif  /* _MKV31F12810_H_ */
  
  