text: DECL|BACKUP_BASE|macro|BACKUP_BASE
  DECL|BACKUP|macro|BACKUP
  DECL|BLE_BASE|macro|BLE_BASE
  DECL|BLE_BLELL|macro|BLE_BLELL
  DECL|BLE_BLESS|macro|BLE_BLESS
  DECL|BLE_RCB_RCBLL|macro|BLE_RCB_RCBLL
  DECL|BLE_RCB|macro|BLE_RCB
  DECL|BLE|macro|BLE
  DECL|CPUSS_BASE|macro|CPUSS_BASE
  DECL|CPUSS_FLASHC_PA_SIZE_LOG2|macro|CPUSS_FLASHC_PA_SIZE_LOG2
  DECL|CPUSS|macro|CPUSS
  DECL|CSD0_BASE|macro|CSD0_BASE
  DECL|CSD0|macro|CSD0
  DECL|CTDAC0_BASE|macro|CTDAC0_BASE
  DECL|CTDAC0|macro|CTDAC0
  DECL|CY_DEVICE_PSOC6ABLE2|macro|CY_DEVICE_PSOC6ABLE2
  DECL|CY_EFUSE_BASE|macro|CY_EFUSE_BASE
  DECL|CY_EFUSE_BASE|macro|CY_EFUSE_BASE
  DECL|CY_EFUSE_SIZE|macro|CY_EFUSE_SIZE
  DECL|CY_EFUSE_SIZE|macro|CY_EFUSE_SIZE
  DECL|CY_EM_EEPROM_BASE|macro|CY_EM_EEPROM_BASE
  DECL|CY_EM_EEPROM_BASE|macro|CY_EM_EEPROM_BASE
  DECL|CY_EM_EEPROM_SIZE|macro|CY_EM_EEPROM_SIZE
  DECL|CY_EM_EEPROM_SIZE|macro|CY_EM_EEPROM_SIZE
  DECL|CY_FLASH_BASE|macro|CY_FLASH_BASE
  DECL|CY_FLASH_BASE|macro|CY_FLASH_BASE
  DECL|CY_FLASH_SIZE|macro|CY_FLASH_SIZE
  DECL|CY_FLASH_SIZE|macro|CY_FLASH_SIZE
  DECL|CY_HF_CLK_MAX_FREQ|macro|CY_HF_CLK_MAX_FREQ
  DECL|CY_IP_M4CPUSS_DMA_INSTANCES|macro|CY_IP_M4CPUSS_DMA_INSTANCES
  DECL|CY_IP_M4CPUSS_DMA_VERSION|macro|CY_IP_M4CPUSS_DMA_VERSION
  DECL|CY_IP_M4CPUSS_DMA|macro|CY_IP_M4CPUSS_DMA
  DECL|CY_IP_M4CPUSS_INSTANCES|macro|CY_IP_M4CPUSS_INSTANCES
  DECL|CY_IP_M4CPUSS_VERSION|macro|CY_IP_M4CPUSS_VERSION
  DECL|CY_IP_M4CPUSS|macro|CY_IP_M4CPUSS
  DECL|CY_IP_MXAUDIOSS_INSTANCES|macro|CY_IP_MXAUDIOSS_INSTANCES
  DECL|CY_IP_MXAUDIOSS_VERSION|macro|CY_IP_MXAUDIOSS_VERSION
  DECL|CY_IP_MXAUDIOSS|macro|CY_IP_MXAUDIOSS
  DECL|CY_IP_MXBLESS_INSTANCES|macro|CY_IP_MXBLESS_INSTANCES
  DECL|CY_IP_MXBLESS_VERSION|macro|CY_IP_MXBLESS_VERSION
  DECL|CY_IP_MXBLESS|macro|CY_IP_MXBLESS
  DECL|CY_IP_MXCSDV2_INSTANCES|macro|CY_IP_MXCSDV2_INSTANCES
  DECL|CY_IP_MXCSDV2_VERSION|macro|CY_IP_MXCSDV2_VERSION
  DECL|CY_IP_MXCSDV2|macro|CY_IP_MXCSDV2
  DECL|CY_IP_MXEFUSE_INSTANCES|macro|CY_IP_MXEFUSE_INSTANCES
  DECL|CY_IP_MXEFUSE_VERSION|macro|CY_IP_MXEFUSE_VERSION
  DECL|CY_IP_MXEFUSE|macro|CY_IP_MXEFUSE
  DECL|CY_IP_MXLCD_INSTANCES|macro|CY_IP_MXLCD_INSTANCES
  DECL|CY_IP_MXLCD_VERSION|macro|CY_IP_MXLCD_VERSION
  DECL|CY_IP_MXLCD|macro|CY_IP_MXLCD
  DECL|CY_IP_MXLPCOMP_INSTANCES|macro|CY_IP_MXLPCOMP_INSTANCES
  DECL|CY_IP_MXLPCOMP_VERSION|macro|CY_IP_MXLPCOMP_VERSION
  DECL|CY_IP_MXLPCOMP|macro|CY_IP_MXLPCOMP
  DECL|CY_IP_MXPERI_INSTANCES|macro|CY_IP_MXPERI_INSTANCES
  DECL|CY_IP_MXPERI_TR_INSTANCES|macro|CY_IP_MXPERI_TR_INSTANCES
  DECL|CY_IP_MXPERI_TR_VERSION|macro|CY_IP_MXPERI_TR_VERSION
  DECL|CY_IP_MXPERI_TR|macro|CY_IP_MXPERI_TR
  DECL|CY_IP_MXPERI_VERSION|macro|CY_IP_MXPERI_VERSION
  DECL|CY_IP_MXPERI|macro|CY_IP_MXPERI
  DECL|CY_IP_MXPROFILE_INSTANCES|macro|CY_IP_MXPROFILE_INSTANCES
  DECL|CY_IP_MXPROFILE_VERSION|macro|CY_IP_MXPROFILE_VERSION
  DECL|CY_IP_MXPROFILE|macro|CY_IP_MXPROFILE
  DECL|CY_IP_MXS40IOSS_INSTANCES|macro|CY_IP_MXS40IOSS_INSTANCES
  DECL|CY_IP_MXS40IOSS_VERSION|macro|CY_IP_MXS40IOSS_VERSION
  DECL|CY_IP_MXS40IOSS|macro|CY_IP_MXS40IOSS
  DECL|CY_IP_MXS40PASS_CTDAC_INSTANCES|macro|CY_IP_MXS40PASS_CTDAC_INSTANCES
  DECL|CY_IP_MXS40PASS_CTDAC_VERSION|macro|CY_IP_MXS40PASS_CTDAC_VERSION
  DECL|CY_IP_MXS40PASS_CTDAC|macro|CY_IP_MXS40PASS_CTDAC
  DECL|CY_IP_MXS40PASS_INSTANCES|macro|CY_IP_MXS40PASS_INSTANCES
  DECL|CY_IP_MXS40PASS_SAR_INSTANCES|macro|CY_IP_MXS40PASS_SAR_INSTANCES
  DECL|CY_IP_MXS40PASS_SAR_VERSION|macro|CY_IP_MXS40PASS_SAR_VERSION
  DECL|CY_IP_MXS40PASS_SAR|macro|CY_IP_MXS40PASS_SAR
  DECL|CY_IP_MXS40PASS_VERSION|macro|CY_IP_MXS40PASS_VERSION
  DECL|CY_IP_MXS40PASS|macro|CY_IP_MXS40PASS
  DECL|CY_IP_MXS40SRSS_INSTANCES|macro|CY_IP_MXS40SRSS_INSTANCES
  DECL|CY_IP_MXS40SRSS_MCWDT_INSTANCES|macro|CY_IP_MXS40SRSS_MCWDT_INSTANCES
  DECL|CY_IP_MXS40SRSS_MCWDT_VERSION|macro|CY_IP_MXS40SRSS_MCWDT_VERSION
  DECL|CY_IP_MXS40SRSS_MCWDT|macro|CY_IP_MXS40SRSS_MCWDT
  DECL|CY_IP_MXS40SRSS_RTC_INSTANCES|macro|CY_IP_MXS40SRSS_RTC_INSTANCES
  DECL|CY_IP_MXS40SRSS_RTC_VERSION|macro|CY_IP_MXS40SRSS_RTC_VERSION
  DECL|CY_IP_MXS40SRSS_RTC|macro|CY_IP_MXS40SRSS_RTC
  DECL|CY_IP_MXS40SRSS_VERSION|macro|CY_IP_MXS40SRSS_VERSION
  DECL|CY_IP_MXS40SRSS|macro|CY_IP_MXS40SRSS
  DECL|CY_IP_MXSCB_INSTANCES|macro|CY_IP_MXSCB_INSTANCES
  DECL|CY_IP_MXSCB_VERSION|macro|CY_IP_MXSCB_VERSION
  DECL|CY_IP_MXSCB|macro|CY_IP_MXSCB
  DECL|CY_IP_MXSMIF_INSTANCES|macro|CY_IP_MXSMIF_INSTANCES
  DECL|CY_IP_MXSMIF_VERSION|macro|CY_IP_MXSMIF_VERSION
  DECL|CY_IP_MXSMIF|macro|CY_IP_MXSMIF
  DECL|CY_IP_MXTCPWM_INSTANCES|macro|CY_IP_MXTCPWM_INSTANCES
  DECL|CY_IP_MXTCPWM_VERSION|macro|CY_IP_MXTCPWM_VERSION
  DECL|CY_IP_MXTCPWM|macro|CY_IP_MXTCPWM
  DECL|CY_IP_MXUSBFS_INSTANCES|macro|CY_IP_MXUSBFS_INSTANCES
  DECL|CY_IP_MXUSBFS_VERSION|macro|CY_IP_MXUSBFS_VERSION
  DECL|CY_IP_MXUSBFS|macro|CY_IP_MXUSBFS
  DECL|CY_ROM_BASE|macro|CY_ROM_BASE
  DECL|CY_ROM_BASE|macro|CY_ROM_BASE
  DECL|CY_ROM_SIZE|macro|CY_ROM_SIZE
  DECL|CY_ROM_SIZE|macro|CY_ROM_SIZE
  DECL|CY_SFLASH_BASE|macro|CY_SFLASH_BASE
  DECL|CY_SFLASH_BASE|macro|CY_SFLASH_BASE
  DECL|CY_SFLASH_SIZE|macro|CY_SFLASH_SIZE
  DECL|CY_SFLASH_SIZE|macro|CY_SFLASH_SIZE
  DECL|CY_SILICON_ID|macro|CY_SILICON_ID
  DECL|CY_SRAM0_BASE|macro|CY_SRAM0_BASE
  DECL|CY_SRAM0_BASE|macro|CY_SRAM0_BASE
  DECL|CY_SRAM0_SIZE|macro|CY_SRAM0_SIZE
  DECL|CY_SRAM0_SIZE|macro|CY_SRAM0_SIZE
  DECL|CY_XIP_BASE|macro|CY_XIP_BASE
  DECL|CY_XIP_BASE|macro|CY_XIP_BASE
  DECL|CY_XIP_SIZE|macro|CY_XIP_SIZE
  DECL|CY_XIP_SIZE|macro|CY_XIP_SIZE
  DECL|DW0_BASE|macro|DW0_BASE
  DECL|DW0_CH_STRUCT0|macro|DW0_CH_STRUCT0
  DECL|DW0_CH_STRUCT10|macro|DW0_CH_STRUCT10
  DECL|DW0_CH_STRUCT11|macro|DW0_CH_STRUCT11
  DECL|DW0_CH_STRUCT12|macro|DW0_CH_STRUCT12
  DECL|DW0_CH_STRUCT13|macro|DW0_CH_STRUCT13
  DECL|DW0_CH_STRUCT14|macro|DW0_CH_STRUCT14
  DECL|DW0_CH_STRUCT15|macro|DW0_CH_STRUCT15
  DECL|DW0_CH_STRUCT1|macro|DW0_CH_STRUCT1
  DECL|DW0_CH_STRUCT2|macro|DW0_CH_STRUCT2
  DECL|DW0_CH_STRUCT3|macro|DW0_CH_STRUCT3
  DECL|DW0_CH_STRUCT4|macro|DW0_CH_STRUCT4
  DECL|DW0_CH_STRUCT5|macro|DW0_CH_STRUCT5
  DECL|DW0_CH_STRUCT6|macro|DW0_CH_STRUCT6
  DECL|DW0_CH_STRUCT7|macro|DW0_CH_STRUCT7
  DECL|DW0_CH_STRUCT8|macro|DW0_CH_STRUCT8
  DECL|DW0_CH_STRUCT9|macro|DW0_CH_STRUCT9
  DECL|DW0|macro|DW0
  DECL|DW1_BASE|macro|DW1_BASE
  DECL|DW1_CH_STRUCT0|macro|DW1_CH_STRUCT0
  DECL|DW1_CH_STRUCT10|macro|DW1_CH_STRUCT10
  DECL|DW1_CH_STRUCT11|macro|DW1_CH_STRUCT11
  DECL|DW1_CH_STRUCT12|macro|DW1_CH_STRUCT12
  DECL|DW1_CH_STRUCT13|macro|DW1_CH_STRUCT13
  DECL|DW1_CH_STRUCT14|macro|DW1_CH_STRUCT14
  DECL|DW1_CH_STRUCT15|macro|DW1_CH_STRUCT15
  DECL|DW1_CH_STRUCT1|macro|DW1_CH_STRUCT1
  DECL|DW1_CH_STRUCT2|macro|DW1_CH_STRUCT2
  DECL|DW1_CH_STRUCT3|macro|DW1_CH_STRUCT3
  DECL|DW1_CH_STRUCT4|macro|DW1_CH_STRUCT4
  DECL|DW1_CH_STRUCT5|macro|DW1_CH_STRUCT5
  DECL|DW1_CH_STRUCT6|macro|DW1_CH_STRUCT6
  DECL|DW1_CH_STRUCT7|macro|DW1_CH_STRUCT7
  DECL|DW1_CH_STRUCT8|macro|DW1_CH_STRUCT8
  DECL|DW1_CH_STRUCT9|macro|DW1_CH_STRUCT9
  DECL|DW1|macro|DW1
  DECL|EFUSE_BASE|macro|EFUSE_BASE
  DECL|EFUSE|macro|EFUSE
  DECL|FAULT_BASE|macro|FAULT_BASE
  DECL|FAULT_STRUCT0|macro|FAULT_STRUCT0
  DECL|FAULT_STRUCT1|macro|FAULT_STRUCT1
  DECL|FAULT|macro|FAULT
  DECL|FLASHC_BASE|macro|FLASHC_BASE
  DECL|FLASHC_FM_CTL|macro|FLASHC_FM_CTL
  DECL|FLASHC|macro|FLASHC
  DECL|GPIO_BASE|macro|GPIO_BASE
  DECL|GPIO_PRT0|macro|GPIO_PRT0
  DECL|GPIO_PRT10|macro|GPIO_PRT10
  DECL|GPIO_PRT11|macro|GPIO_PRT11
  DECL|GPIO_PRT12|macro|GPIO_PRT12
  DECL|GPIO_PRT13|macro|GPIO_PRT13
  DECL|GPIO_PRT14|macro|GPIO_PRT14
  DECL|GPIO_PRT1|macro|GPIO_PRT1
  DECL|GPIO_PRT2|macro|GPIO_PRT2
  DECL|GPIO_PRT3|macro|GPIO_PRT3
  DECL|GPIO_PRT4|macro|GPIO_PRT4
  DECL|GPIO_PRT5|macro|GPIO_PRT5
  DECL|GPIO_PRT6|macro|GPIO_PRT6
  DECL|GPIO_PRT7|macro|GPIO_PRT7
  DECL|GPIO_PRT8|macro|GPIO_PRT8
  DECL|GPIO_PRT9|macro|GPIO_PRT9
  DECL|GPIO|macro|GPIO
  DECL|HSIOM_BASE|macro|HSIOM_BASE
  DECL|HSIOM_PRT0|macro|HSIOM_PRT0
  DECL|HSIOM_PRT10|macro|HSIOM_PRT10
  DECL|HSIOM_PRT11|macro|HSIOM_PRT11
  DECL|HSIOM_PRT12|macro|HSIOM_PRT12
  DECL|HSIOM_PRT13|macro|HSIOM_PRT13
  DECL|HSIOM_PRT14|macro|HSIOM_PRT14
  DECL|HSIOM_PRT1|macro|HSIOM_PRT1
  DECL|HSIOM_PRT2|macro|HSIOM_PRT2
  DECL|HSIOM_PRT3|macro|HSIOM_PRT3
  DECL|HSIOM_PRT4|macro|HSIOM_PRT4
  DECL|HSIOM_PRT5|macro|HSIOM_PRT5
  DECL|HSIOM_PRT6|macro|HSIOM_PRT6
  DECL|HSIOM_PRT7|macro|HSIOM_PRT7
  DECL|HSIOM_PRT8|macro|HSIOM_PRT8
  DECL|HSIOM_PRT9|macro|HSIOM_PRT9
  DECL|HSIOM|macro|HSIOM
  DECL|HardFault_IRQn|enumerator|HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
  DECL|I2S0_BASE|macro|I2S0_BASE
  DECL|I2S0|macro|I2S0
  DECL|I2S|macro|I2S
  DECL|IPC_BASE|macro|IPC_BASE
  DECL|IPC_INTR_STRUCT0|macro|IPC_INTR_STRUCT0
  DECL|IPC_INTR_STRUCT10|macro|IPC_INTR_STRUCT10
  DECL|IPC_INTR_STRUCT11|macro|IPC_INTR_STRUCT11
  DECL|IPC_INTR_STRUCT12|macro|IPC_INTR_STRUCT12
  DECL|IPC_INTR_STRUCT13|macro|IPC_INTR_STRUCT13
  DECL|IPC_INTR_STRUCT14|macro|IPC_INTR_STRUCT14
  DECL|IPC_INTR_STRUCT15|macro|IPC_INTR_STRUCT15
  DECL|IPC_INTR_STRUCT1|macro|IPC_INTR_STRUCT1
  DECL|IPC_INTR_STRUCT2|macro|IPC_INTR_STRUCT2
  DECL|IPC_INTR_STRUCT3|macro|IPC_INTR_STRUCT3
  DECL|IPC_INTR_STRUCT4|macro|IPC_INTR_STRUCT4
  DECL|IPC_INTR_STRUCT5|macro|IPC_INTR_STRUCT5
  DECL|IPC_INTR_STRUCT6|macro|IPC_INTR_STRUCT6
  DECL|IPC_INTR_STRUCT7|macro|IPC_INTR_STRUCT7
  DECL|IPC_INTR_STRUCT8|macro|IPC_INTR_STRUCT8
  DECL|IPC_INTR_STRUCT9|macro|IPC_INTR_STRUCT9
  DECL|IPC_STRUCT0|macro|IPC_STRUCT0
  DECL|IPC_STRUCT10|macro|IPC_STRUCT10
  DECL|IPC_STRUCT11|macro|IPC_STRUCT11
  DECL|IPC_STRUCT12|macro|IPC_STRUCT12
  DECL|IPC_STRUCT13|macro|IPC_STRUCT13
  DECL|IPC_STRUCT14|macro|IPC_STRUCT14
  DECL|IPC_STRUCT15|macro|IPC_STRUCT15
  DECL|IPC_STRUCT1|macro|IPC_STRUCT1
  DECL|IPC_STRUCT2|macro|IPC_STRUCT2
  DECL|IPC_STRUCT3|macro|IPC_STRUCT3
  DECL|IPC_STRUCT4|macro|IPC_STRUCT4
  DECL|IPC_STRUCT5|macro|IPC_STRUCT5
  DECL|IPC_STRUCT6|macro|IPC_STRUCT6
  DECL|IPC_STRUCT7|macro|IPC_STRUCT7
  DECL|IPC_STRUCT8|macro|IPC_STRUCT8
  DECL|IPC_STRUCT9|macro|IPC_STRUCT9
  DECL|IPC|macro|IPC
  DECL|IRQn_Type|typedef|} IRQn_Type;
  DECL|LCD0_BASE|macro|LCD0_BASE
  DECL|LCD0|macro|LCD0
  DECL|LPCOMP_BASE|macro|LPCOMP_BASE
  DECL|LPCOMP|macro|LPCOMP
  DECL|MCWDT_STRUCT0|macro|MCWDT_STRUCT0
  DECL|MCWDT_STRUCT1|macro|MCWDT_STRUCT1
  DECL|NonMaskableInt_IRQn|enumerator|NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
  DECL|NvicMux0_IRQn|enumerator|NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CM0+ NVIC Mux input 0 */
  DECL|NvicMux10_IRQn|enumerator|NvicMux10_IRQn = 10, /*!< 10 [Active] CM0+ NVIC Mux input 10 */
  DECL|NvicMux11_IRQn|enumerator|NvicMux11_IRQn = 11, /*!< 11 [Active] CM0+ NVIC Mux input 11 */
  DECL|NvicMux12_IRQn|enumerator|NvicMux12_IRQn = 12, /*!< 12 [Active] CM0+ NVIC Mux input 12 */
  DECL|NvicMux13_IRQn|enumerator|NvicMux13_IRQn = 13, /*!< 13 [Active] CM0+ NVIC Mux input 13 */
  DECL|NvicMux14_IRQn|enumerator|NvicMux14_IRQn = 14, /*!< 14 [Active] CM0+ NVIC Mux input 14 */
  DECL|NvicMux15_IRQn|enumerator|NvicMux15_IRQn = 15, /*!< 15 [Active] CM0+ NVIC Mux input 15 */
  DECL|NvicMux16_IRQn|enumerator|NvicMux16_IRQn = 16, /*!< 16 [Active] CM0+ NVIC Mux input 16 */
  DECL|NvicMux17_IRQn|enumerator|NvicMux17_IRQn = 17, /*!< 17 [Active] CM0+ NVIC Mux input 17 */
  DECL|NvicMux18_IRQn|enumerator|NvicMux18_IRQn = 18, /*!< 18 [Active] CM0+ NVIC Mux input 18 */
  DECL|NvicMux19_IRQn|enumerator|NvicMux19_IRQn = 19, /*!< 19 [Active] CM0+ NVIC Mux input 19 */
  DECL|NvicMux1_IRQn|enumerator|NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CM0+ NVIC Mux input 1 */
  DECL|NvicMux20_IRQn|enumerator|NvicMux20_IRQn = 20, /*!< 20 [Active] CM0+ NVIC Mux input 20 */
  DECL|NvicMux21_IRQn|enumerator|NvicMux21_IRQn = 21, /*!< 21 [Active] CM0+ NVIC Mux input 21 */
  DECL|NvicMux22_IRQn|enumerator|NvicMux22_IRQn = 22, /*!< 22 [Active] CM0+ NVIC Mux input 22 */
  DECL|NvicMux23_IRQn|enumerator|NvicMux23_IRQn = 23, /*!< 23 [Active] CM0+ NVIC Mux input 23 */
  DECL|NvicMux24_IRQn|enumerator|NvicMux24_IRQn = 24, /*!< 24 [Active] CM0+ NVIC Mux input 24 */
  DECL|NvicMux25_IRQn|enumerator|NvicMux25_IRQn = 25, /*!< 25 [Active] CM0+ NVIC Mux input 25 */
  DECL|NvicMux26_IRQn|enumerator|NvicMux26_IRQn = 26, /*!< 26 [Active] CM0+ NVIC Mux input 26 */
  DECL|NvicMux27_IRQn|enumerator|NvicMux27_IRQn = 27, /*!< 27 [Active] CM0+ NVIC Mux input 27 */
  DECL|NvicMux28_IRQn|enumerator|NvicMux28_IRQn = 28, /*!< 28 [Active] CM0+ NVIC Mux input 28 */
  DECL|NvicMux29_IRQn|enumerator|NvicMux29_IRQn = 29, /*!< 29 [Active] CM0+ NVIC Mux input 29 */
  DECL|NvicMux2_IRQn|enumerator|NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CM0+ NVIC Mux input 2 */
  DECL|NvicMux30_IRQn|enumerator|NvicMux30_IRQn = 30, /*!< 30 [Active] CM0+ NVIC Mux input 30 */
  DECL|NvicMux31_IRQn|enumerator|NvicMux31_IRQn = 31, /*!< 31 [Active] CM0+ NVIC Mux input 31 */
  DECL|NvicMux3_IRQn|enumerator|NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CM0+ NVIC Mux input 3 */
  DECL|NvicMux4_IRQn|enumerator|NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CM0+ NVIC Mux input 4 */
  DECL|NvicMux5_IRQn|enumerator|NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CM0+ NVIC Mux input 5 */
  DECL|NvicMux6_IRQn|enumerator|NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CM0+ NVIC Mux input 6 */
  DECL|NvicMux7_IRQn|enumerator|NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CM0+ NVIC Mux input 7 */
  DECL|NvicMux8_IRQn|enumerator|NvicMux8_IRQn = 8, /*!< 8 [Active] CM0+ NVIC Mux input 8 */
  DECL|NvicMux9_IRQn|enumerator|NvicMux9_IRQn = 9, /*!< 9 [Active] CM0+ NVIC Mux input 9 */
  DECL|PASS_AREF|macro|PASS_AREF
  DECL|PASS_BASE|macro|PASS_BASE
  DECL|PASS|macro|PASS
  DECL|PDM0_BASE|macro|PDM0_BASE
  DECL|PDM0|macro|PDM0
  DECL|PDM|macro|PDM
  DECL|PERI_BASE|macro|PERI_BASE
  DECL|PERI_GR0|macro|PERI_GR0
  DECL|PERI_GR10|macro|PERI_GR10
  DECL|PERI_GR1|macro|PERI_GR1
  DECL|PERI_GR2|macro|PERI_GR2
  DECL|PERI_GR3|macro|PERI_GR3
  DECL|PERI_GR4|macro|PERI_GR4
  DECL|PERI_GR6|macro|PERI_GR6
  DECL|PERI_GR9|macro|PERI_GR9
  DECL|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE|macro|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE
  DECL|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0|macro|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0
  DECL|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE|macro|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE
  DECL|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1|macro|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1
  DECL|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE|macro|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE
  DECL|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2|macro|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2
  DECL|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE|macro|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE
  DECL|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3|macro|PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3
  DECL|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE|macro|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE
  DECL|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0|macro|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0
  DECL|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE|macro|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE
  DECL|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1|macro|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1
  DECL|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE|macro|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE
  DECL|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2|macro|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2
  DECL|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE|macro|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE
  DECL|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3|macro|PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT0|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT0
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT1|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT1
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT2|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT2
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT3|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT3
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT4|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT4
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT5|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT5
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT6|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT6
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE
  DECL|PERI_GR_PPU_RG_IPC_INTR_STRUCT7|macro|PERI_GR_PPU_RG_IPC_INTR_STRUCT7
  DECL|PERI_GR_PPU_RG_IPC_STRUCT0_BASE|macro|PERI_GR_PPU_RG_IPC_STRUCT0_BASE
  DECL|PERI_GR_PPU_RG_IPC_STRUCT0|macro|PERI_GR_PPU_RG_IPC_STRUCT0
  DECL|PERI_GR_PPU_RG_IPC_STRUCT1_BASE|macro|PERI_GR_PPU_RG_IPC_STRUCT1_BASE
  DECL|PERI_GR_PPU_RG_IPC_STRUCT1|macro|PERI_GR_PPU_RG_IPC_STRUCT1
  DECL|PERI_GR_PPU_RG_IPC_STRUCT2_BASE|macro|PERI_GR_PPU_RG_IPC_STRUCT2_BASE
  DECL|PERI_GR_PPU_RG_IPC_STRUCT2|macro|PERI_GR_PPU_RG_IPC_STRUCT2
  DECL|PERI_GR_PPU_RG_IPC_STRUCT3_BASE|macro|PERI_GR_PPU_RG_IPC_STRUCT3_BASE
  DECL|PERI_GR_PPU_RG_IPC_STRUCT3|macro|PERI_GR_PPU_RG_IPC_STRUCT3
  DECL|PERI_GR_PPU_RG_IPC_STRUCT4_BASE|macro|PERI_GR_PPU_RG_IPC_STRUCT4_BASE
  DECL|PERI_GR_PPU_RG_IPC_STRUCT4|macro|PERI_GR_PPU_RG_IPC_STRUCT4
  DECL|PERI_GR_PPU_RG_IPC_STRUCT5_BASE|macro|PERI_GR_PPU_RG_IPC_STRUCT5_BASE
  DECL|PERI_GR_PPU_RG_IPC_STRUCT5|macro|PERI_GR_PPU_RG_IPC_STRUCT5
  DECL|PERI_GR_PPU_RG_IPC_STRUCT6_BASE|macro|PERI_GR_PPU_RG_IPC_STRUCT6_BASE
  DECL|PERI_GR_PPU_RG_IPC_STRUCT6|macro|PERI_GR_PPU_RG_IPC_STRUCT6
  DECL|PERI_GR_PPU_RG_IPC_STRUCT7_BASE|macro|PERI_GR_PPU_RG_IPC_STRUCT7_BASE
  DECL|PERI_GR_PPU_RG_IPC_STRUCT7|macro|PERI_GR_PPU_RG_IPC_STRUCT7
  DECL|PERI_GR_PPU_RG_MPU_CM0P_BASE|macro|PERI_GR_PPU_RG_MPU_CM0P_BASE
  DECL|PERI_GR_PPU_RG_MPU_CM0P|macro|PERI_GR_PPU_RG_MPU_CM0P
  DECL|PERI_GR_PPU_RG_MPU_CM4_BASE|macro|PERI_GR_PPU_RG_MPU_CM4_BASE
  DECL|PERI_GR_PPU_RG_MPU_CM4|macro|PERI_GR_PPU_RG_MPU_CM4
  DECL|PERI_GR_PPU_RG_MPU_CRYPTO_BASE|macro|PERI_GR_PPU_RG_MPU_CRYPTO_BASE
  DECL|PERI_GR_PPU_RG_MPU_CRYPTO|macro|PERI_GR_PPU_RG_MPU_CRYPTO
  DECL|PERI_GR_PPU_RG_MPU_TC_BASE|macro|PERI_GR_PPU_RG_MPU_TC_BASE
  DECL|PERI_GR_PPU_RG_MPU_TC|macro|PERI_GR_PPU_RG_MPU_TC
  DECL|PERI_GR_PPU_RG_SMPU_BASE|macro|PERI_GR_PPU_RG_SMPU_BASE
  DECL|PERI_GR_PPU_RG_SMPU|macro|PERI_GR_PPU_RG_SMPU
  DECL|PERI_GR_PPU_SL_BACKUP_BASE|macro|PERI_GR_PPU_SL_BACKUP_BASE
  DECL|PERI_GR_PPU_SL_BACKUP|macro|PERI_GR_PPU_SL_BACKUP
  DECL|PERI_GR_PPU_SL_BLE_BASE|macro|PERI_GR_PPU_SL_BLE_BASE
  DECL|PERI_GR_PPU_SL_BLE|macro|PERI_GR_PPU_SL_BLE
  DECL|PERI_GR_PPU_SL_CPUSS_BASE|macro|PERI_GR_PPU_SL_CPUSS_BASE
  DECL|PERI_GR_PPU_SL_CPUSS|macro|PERI_GR_PPU_SL_CPUSS
  DECL|PERI_GR_PPU_SL_CRYPTO_BASE|macro|PERI_GR_PPU_SL_CRYPTO_BASE
  DECL|PERI_GR_PPU_SL_CRYPTO|macro|PERI_GR_PPU_SL_CRYPTO
  DECL|PERI_GR_PPU_SL_CSD_BASE|macro|PERI_GR_PPU_SL_CSD_BASE
  DECL|PERI_GR_PPU_SL_CSD|macro|PERI_GR_PPU_SL_CSD
  DECL|PERI_GR_PPU_SL_DW0_BASE|macro|PERI_GR_PPU_SL_DW0_BASE
  DECL|PERI_GR_PPU_SL_DW0|macro|PERI_GR_PPU_SL_DW0
  DECL|PERI_GR_PPU_SL_DW1_BASE|macro|PERI_GR_PPU_SL_DW1_BASE
  DECL|PERI_GR_PPU_SL_DW1|macro|PERI_GR_PPU_SL_DW1
  DECL|PERI_GR_PPU_SL_EFUSE_BASE|macro|PERI_GR_PPU_SL_EFUSE_BASE
  DECL|PERI_GR_PPU_SL_EFUSE|macro|PERI_GR_PPU_SL_EFUSE
  DECL|PERI_GR_PPU_SL_FAULT_BASE|macro|PERI_GR_PPU_SL_FAULT_BASE
  DECL|PERI_GR_PPU_SL_FAULT|macro|PERI_GR_PPU_SL_FAULT
  DECL|PERI_GR_PPU_SL_FLASHC_BASE|macro|PERI_GR_PPU_SL_FLASHC_BASE
  DECL|PERI_GR_PPU_SL_FLASHC|macro|PERI_GR_PPU_SL_FLASHC
  DECL|PERI_GR_PPU_SL_GPIO_BASE|macro|PERI_GR_PPU_SL_GPIO_BASE
  DECL|PERI_GR_PPU_SL_GPIO|macro|PERI_GR_PPU_SL_GPIO
  DECL|PERI_GR_PPU_SL_HSIOM_BASE|macro|PERI_GR_PPU_SL_HSIOM_BASE
  DECL|PERI_GR_PPU_SL_HSIOM|macro|PERI_GR_PPU_SL_HSIOM
  DECL|PERI_GR_PPU_SL_I2S_BASE|macro|PERI_GR_PPU_SL_I2S_BASE
  DECL|PERI_GR_PPU_SL_I2S|macro|PERI_GR_PPU_SL_I2S
  DECL|PERI_GR_PPU_SL_IPC_BASE|macro|PERI_GR_PPU_SL_IPC_BASE
  DECL|PERI_GR_PPU_SL_IPC|macro|PERI_GR_PPU_SL_IPC
  DECL|PERI_GR_PPU_SL_LCD_BASE|macro|PERI_GR_PPU_SL_LCD_BASE
  DECL|PERI_GR_PPU_SL_LCD|macro|PERI_GR_PPU_SL_LCD
  DECL|PERI_GR_PPU_SL_LPCOMP_BASE|macro|PERI_GR_PPU_SL_LPCOMP_BASE
  DECL|PERI_GR_PPU_SL_LPCOMP|macro|PERI_GR_PPU_SL_LPCOMP
  DECL|PERI_GR_PPU_SL_PASS_BASE|macro|PERI_GR_PPU_SL_PASS_BASE
  DECL|PERI_GR_PPU_SL_PASS|macro|PERI_GR_PPU_SL_PASS
  DECL|PERI_GR_PPU_SL_PDM_BASE|macro|PERI_GR_PPU_SL_PDM_BASE
  DECL|PERI_GR_PPU_SL_PDM|macro|PERI_GR_PPU_SL_PDM
  DECL|PERI_GR_PPU_SL_PERI_GR10_BASE|macro|PERI_GR_PPU_SL_PERI_GR10_BASE
  DECL|PERI_GR_PPU_SL_PERI_GR10|macro|PERI_GR_PPU_SL_PERI_GR10
  DECL|PERI_GR_PPU_SL_PERI_GR1_BASE|macro|PERI_GR_PPU_SL_PERI_GR1_BASE
  DECL|PERI_GR_PPU_SL_PERI_GR1|macro|PERI_GR_PPU_SL_PERI_GR1
  DECL|PERI_GR_PPU_SL_PERI_GR2_BASE|macro|PERI_GR_PPU_SL_PERI_GR2_BASE
  DECL|PERI_GR_PPU_SL_PERI_GR2|macro|PERI_GR_PPU_SL_PERI_GR2
  DECL|PERI_GR_PPU_SL_PERI_GR3_BASE|macro|PERI_GR_PPU_SL_PERI_GR3_BASE
  DECL|PERI_GR_PPU_SL_PERI_GR3|macro|PERI_GR_PPU_SL_PERI_GR3
  DECL|PERI_GR_PPU_SL_PERI_GR4_BASE|macro|PERI_GR_PPU_SL_PERI_GR4_BASE
  DECL|PERI_GR_PPU_SL_PERI_GR4|macro|PERI_GR_PPU_SL_PERI_GR4
  DECL|PERI_GR_PPU_SL_PERI_GR6_BASE|macro|PERI_GR_PPU_SL_PERI_GR6_BASE
  DECL|PERI_GR_PPU_SL_PERI_GR6|macro|PERI_GR_PPU_SL_PERI_GR6
  DECL|PERI_GR_PPU_SL_PERI_GR9_BASE|macro|PERI_GR_PPU_SL_PERI_GR9_BASE
  DECL|PERI_GR_PPU_SL_PERI_GR9|macro|PERI_GR_PPU_SL_PERI_GR9
  DECL|PERI_GR_PPU_SL_PROFILE_BASE|macro|PERI_GR_PPU_SL_PROFILE_BASE
  DECL|PERI_GR_PPU_SL_PROFILE|macro|PERI_GR_PPU_SL_PROFILE
  DECL|PERI_GR_PPU_SL_PROT_BASE|macro|PERI_GR_PPU_SL_PROT_BASE
  DECL|PERI_GR_PPU_SL_PROT|macro|PERI_GR_PPU_SL_PROT
  DECL|PERI_GR_PPU_SL_SCB0_BASE|macro|PERI_GR_PPU_SL_SCB0_BASE
  DECL|PERI_GR_PPU_SL_SCB0|macro|PERI_GR_PPU_SL_SCB0
  DECL|PERI_GR_PPU_SL_SCB1_BASE|macro|PERI_GR_PPU_SL_SCB1_BASE
  DECL|PERI_GR_PPU_SL_SCB1|macro|PERI_GR_PPU_SL_SCB1
  DECL|PERI_GR_PPU_SL_SCB2_BASE|macro|PERI_GR_PPU_SL_SCB2_BASE
  DECL|PERI_GR_PPU_SL_SCB2|macro|PERI_GR_PPU_SL_SCB2
  DECL|PERI_GR_PPU_SL_SCB3_BASE|macro|PERI_GR_PPU_SL_SCB3_BASE
  DECL|PERI_GR_PPU_SL_SCB3|macro|PERI_GR_PPU_SL_SCB3
  DECL|PERI_GR_PPU_SL_SCB4_BASE|macro|PERI_GR_PPU_SL_SCB4_BASE
  DECL|PERI_GR_PPU_SL_SCB4|macro|PERI_GR_PPU_SL_SCB4
  DECL|PERI_GR_PPU_SL_SCB5_BASE|macro|PERI_GR_PPU_SL_SCB5_BASE
  DECL|PERI_GR_PPU_SL_SCB5|macro|PERI_GR_PPU_SL_SCB5
  DECL|PERI_GR_PPU_SL_SCB6_BASE|macro|PERI_GR_PPU_SL_SCB6_BASE
  DECL|PERI_GR_PPU_SL_SCB6|macro|PERI_GR_PPU_SL_SCB6
  DECL|PERI_GR_PPU_SL_SCB7_BASE|macro|PERI_GR_PPU_SL_SCB7_BASE
  DECL|PERI_GR_PPU_SL_SCB7|macro|PERI_GR_PPU_SL_SCB7
  DECL|PERI_GR_PPU_SL_SCB8_BASE|macro|PERI_GR_PPU_SL_SCB8_BASE
  DECL|PERI_GR_PPU_SL_SCB8|macro|PERI_GR_PPU_SL_SCB8
  DECL|PERI_GR_PPU_SL_SMARTIO_BASE|macro|PERI_GR_PPU_SL_SMARTIO_BASE
  DECL|PERI_GR_PPU_SL_SMARTIO|macro|PERI_GR_PPU_SL_SMARTIO
  DECL|PERI_GR_PPU_SL_SMIF_BASE|macro|PERI_GR_PPU_SL_SMIF_BASE
  DECL|PERI_GR_PPU_SL_SMIF|macro|PERI_GR_PPU_SL_SMIF
  DECL|PERI_GR_PPU_SL_SRSS_BASE|macro|PERI_GR_PPU_SL_SRSS_BASE
  DECL|PERI_GR_PPU_SL_SRSS|macro|PERI_GR_PPU_SL_SRSS
  DECL|PERI_GR_PPU_SL_TCPWM0_BASE|macro|PERI_GR_PPU_SL_TCPWM0_BASE
  DECL|PERI_GR_PPU_SL_TCPWM0|macro|PERI_GR_PPU_SL_TCPWM0
  DECL|PERI_GR_PPU_SL_TCPWM1_BASE|macro|PERI_GR_PPU_SL_TCPWM1_BASE
  DECL|PERI_GR_PPU_SL_TCPWM1|macro|PERI_GR_PPU_SL_TCPWM1
  DECL|PERI_GR_PPU_SL_UDB_BASE|macro|PERI_GR_PPU_SL_UDB_BASE
  DECL|PERI_GR_PPU_SL_UDB|macro|PERI_GR_PPU_SL_UDB
  DECL|PERI_GR_PPU_SL_USBFS_BASE|macro|PERI_GR_PPU_SL_USBFS_BASE
  DECL|PERI_GR_PPU_SL_USBFS|macro|PERI_GR_PPU_SL_USBFS
  DECL|PERI_PPU_GR0|macro|PERI_PPU_GR0
  DECL|PERI_PPU_GR10|macro|PERI_PPU_GR10
  DECL|PERI_PPU_GR1|macro|PERI_PPU_GR1
  DECL|PERI_PPU_GR2|macro|PERI_PPU_GR2
  DECL|PERI_PPU_GR3|macro|PERI_PPU_GR3
  DECL|PERI_PPU_GR4|macro|PERI_PPU_GR4
  DECL|PERI_PPU_GR6|macro|PERI_PPU_GR6
  DECL|PERI_PPU_GR9|macro|PERI_PPU_GR9
  DECL|PERI_PPU_GR_MMIO0_BASE|macro|PERI_PPU_GR_MMIO0_BASE
  DECL|PERI_PPU_GR_MMIO0|macro|PERI_PPU_GR_MMIO0
  DECL|PERI_PPU_GR_MMIO10_BASE|macro|PERI_PPU_GR_MMIO10_BASE
  DECL|PERI_PPU_GR_MMIO10|macro|PERI_PPU_GR_MMIO10
  DECL|PERI_PPU_GR_MMIO1_BASE|macro|PERI_PPU_GR_MMIO1_BASE
  DECL|PERI_PPU_GR_MMIO1|macro|PERI_PPU_GR_MMIO1
  DECL|PERI_PPU_GR_MMIO2_BASE|macro|PERI_PPU_GR_MMIO2_BASE
  DECL|PERI_PPU_GR_MMIO2|macro|PERI_PPU_GR_MMIO2
  DECL|PERI_PPU_GR_MMIO3_BASE|macro|PERI_PPU_GR_MMIO3_BASE
  DECL|PERI_PPU_GR_MMIO3|macro|PERI_PPU_GR_MMIO3
  DECL|PERI_PPU_GR_MMIO4_BASE|macro|PERI_PPU_GR_MMIO4_BASE
  DECL|PERI_PPU_GR_MMIO4|macro|PERI_PPU_GR_MMIO4
  DECL|PERI_PPU_GR_MMIO6_BASE|macro|PERI_PPU_GR_MMIO6_BASE
  DECL|PERI_PPU_GR_MMIO6|macro|PERI_PPU_GR_MMIO6
  DECL|PERI_PPU_GR_MMIO9_BASE|macro|PERI_PPU_GR_MMIO9_BASE
  DECL|PERI_PPU_GR_MMIO9|macro|PERI_PPU_GR_MMIO9
  DECL|PERI_PPU_PR0|macro|PERI_PPU_PR0
  DECL|PERI_PPU_PR10|macro|PERI_PPU_PR10
  DECL|PERI_PPU_PR11|macro|PERI_PPU_PR11
  DECL|PERI_PPU_PR12|macro|PERI_PPU_PR12
  DECL|PERI_PPU_PR13|macro|PERI_PPU_PR13
  DECL|PERI_PPU_PR14|macro|PERI_PPU_PR14
  DECL|PERI_PPU_PR15|macro|PERI_PPU_PR15
  DECL|PERI_PPU_PR1|macro|PERI_PPU_PR1
  DECL|PERI_PPU_PR2|macro|PERI_PPU_PR2
  DECL|PERI_PPU_PR3|macro|PERI_PPU_PR3
  DECL|PERI_PPU_PR4|macro|PERI_PPU_PR4
  DECL|PERI_PPU_PR5|macro|PERI_PPU_PR5
  DECL|PERI_PPU_PR6|macro|PERI_PPU_PR6
  DECL|PERI_PPU_PR7|macro|PERI_PPU_PR7
  DECL|PERI_PPU_PR8|macro|PERI_PPU_PR8
  DECL|PERI_PPU_PR9|macro|PERI_PPU_PR9
  DECL|PERI_TR_GR0|macro|PERI_TR_GR0
  DECL|PERI_TR_GR10|macro|PERI_TR_GR10
  DECL|PERI_TR_GR11|macro|PERI_TR_GR11
  DECL|PERI_TR_GR12|macro|PERI_TR_GR12
  DECL|PERI_TR_GR13|macro|PERI_TR_GR13
  DECL|PERI_TR_GR14|macro|PERI_TR_GR14
  DECL|PERI_TR_GR1|macro|PERI_TR_GR1
  DECL|PERI_TR_GR2|macro|PERI_TR_GR2
  DECL|PERI_TR_GR3|macro|PERI_TR_GR3
  DECL|PERI_TR_GR4|macro|PERI_TR_GR4
  DECL|PERI_TR_GR5|macro|PERI_TR_GR5
  DECL|PERI_TR_GR6|macro|PERI_TR_GR6
  DECL|PERI_TR_GR7|macro|PERI_TR_GR7
  DECL|PERI_TR_GR8|macro|PERI_TR_GR8
  DECL|PERI_TR_GR9|macro|PERI_TR_GR9
  DECL|PERI|macro|PERI
  DECL|PROFILE_BASE|macro|PROFILE_BASE
  DECL|PROFILE_CNT_STRUCT0|macro|PROFILE_CNT_STRUCT0
  DECL|PROFILE_CNT_STRUCT1|macro|PROFILE_CNT_STRUCT1
  DECL|PROFILE_CNT_STRUCT2|macro|PROFILE_CNT_STRUCT2
  DECL|PROFILE_CNT_STRUCT3|macro|PROFILE_CNT_STRUCT3
  DECL|PROFILE_CNT_STRUCT4|macro|PROFILE_CNT_STRUCT4
  DECL|PROFILE_CNT_STRUCT5|macro|PROFILE_CNT_STRUCT5
  DECL|PROFILE_CNT_STRUCT6|macro|PROFILE_CNT_STRUCT6
  DECL|PROFILE_CNT_STRUCT7|macro|PROFILE_CNT_STRUCT7
  DECL|PROFILE|macro|PROFILE
  DECL|PROT_BASE|macro|PROT_BASE
  DECL|PROT_MPU0|macro|PROT_MPU0
  DECL|PROT_MPU10|macro|PROT_MPU10
  DECL|PROT_MPU11|macro|PROT_MPU11
  DECL|PROT_MPU12|macro|PROT_MPU12
  DECL|PROT_MPU13|macro|PROT_MPU13
  DECL|PROT_MPU14|macro|PROT_MPU14
  DECL|PROT_MPU15_MPU_STRUCT0|macro|PROT_MPU15_MPU_STRUCT0
  DECL|PROT_MPU15_MPU_STRUCT1|macro|PROT_MPU15_MPU_STRUCT1
  DECL|PROT_MPU15_MPU_STRUCT2|macro|PROT_MPU15_MPU_STRUCT2
  DECL|PROT_MPU15_MPU_STRUCT3|macro|PROT_MPU15_MPU_STRUCT3
  DECL|PROT_MPU15_MPU_STRUCT4|macro|PROT_MPU15_MPU_STRUCT4
  DECL|PROT_MPU15_MPU_STRUCT5|macro|PROT_MPU15_MPU_STRUCT5
  DECL|PROT_MPU15_MPU_STRUCT6|macro|PROT_MPU15_MPU_STRUCT6
  DECL|PROT_MPU15_MPU_STRUCT7|macro|PROT_MPU15_MPU_STRUCT7
  DECL|PROT_MPU15|macro|PROT_MPU15
  DECL|PROT_MPU1_MPU_STRUCT0|macro|PROT_MPU1_MPU_STRUCT0
  DECL|PROT_MPU1_MPU_STRUCT1|macro|PROT_MPU1_MPU_STRUCT1
  DECL|PROT_MPU1_MPU_STRUCT2|macro|PROT_MPU1_MPU_STRUCT2
  DECL|PROT_MPU1_MPU_STRUCT3|macro|PROT_MPU1_MPU_STRUCT3
  DECL|PROT_MPU1_MPU_STRUCT4|macro|PROT_MPU1_MPU_STRUCT4
  DECL|PROT_MPU1_MPU_STRUCT5|macro|PROT_MPU1_MPU_STRUCT5
  DECL|PROT_MPU1_MPU_STRUCT6|macro|PROT_MPU1_MPU_STRUCT6
  DECL|PROT_MPU1_MPU_STRUCT7|macro|PROT_MPU1_MPU_STRUCT7
  DECL|PROT_MPU1|macro|PROT_MPU1
  DECL|PROT_MPU2|macro|PROT_MPU2
  DECL|PROT_MPU3|macro|PROT_MPU3
  DECL|PROT_MPU4|macro|PROT_MPU4
  DECL|PROT_MPU5|macro|PROT_MPU5
  DECL|PROT_MPU6|macro|PROT_MPU6
  DECL|PROT_MPU7|macro|PROT_MPU7
  DECL|PROT_MPU8|macro|PROT_MPU8
  DECL|PROT_MPU9|macro|PROT_MPU9
  DECL|PROT_SMPU_SMPU_STRUCT0|macro|PROT_SMPU_SMPU_STRUCT0
  DECL|PROT_SMPU_SMPU_STRUCT10|macro|PROT_SMPU_SMPU_STRUCT10
  DECL|PROT_SMPU_SMPU_STRUCT11|macro|PROT_SMPU_SMPU_STRUCT11
  DECL|PROT_SMPU_SMPU_STRUCT12|macro|PROT_SMPU_SMPU_STRUCT12
  DECL|PROT_SMPU_SMPU_STRUCT13|macro|PROT_SMPU_SMPU_STRUCT13
  DECL|PROT_SMPU_SMPU_STRUCT14|macro|PROT_SMPU_SMPU_STRUCT14
  DECL|PROT_SMPU_SMPU_STRUCT15|macro|PROT_SMPU_SMPU_STRUCT15
  DECL|PROT_SMPU_SMPU_STRUCT1|macro|PROT_SMPU_SMPU_STRUCT1
  DECL|PROT_SMPU_SMPU_STRUCT2|macro|PROT_SMPU_SMPU_STRUCT2
  DECL|PROT_SMPU_SMPU_STRUCT3|macro|PROT_SMPU_SMPU_STRUCT3
  DECL|PROT_SMPU_SMPU_STRUCT4|macro|PROT_SMPU_SMPU_STRUCT4
  DECL|PROT_SMPU_SMPU_STRUCT5|macro|PROT_SMPU_SMPU_STRUCT5
  DECL|PROT_SMPU_SMPU_STRUCT6|macro|PROT_SMPU_SMPU_STRUCT6
  DECL|PROT_SMPU_SMPU_STRUCT7|macro|PROT_SMPU_SMPU_STRUCT7
  DECL|PROT_SMPU_SMPU_STRUCT8|macro|PROT_SMPU_SMPU_STRUCT8
  DECL|PROT_SMPU_SMPU_STRUCT9|macro|PROT_SMPU_SMPU_STRUCT9
  DECL|PROT_SMPU|macro|PROT_SMPU
  DECL|PROT|macro|PROT
  DECL|PendSV_IRQn|enumerator|PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
  DECL|Reset_IRQn|enumerator|Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
  DECL|SAR_BASE|macro|SAR_BASE
  DECL|SAR|macro|SAR
  DECL|SCB0_BASE|macro|SCB0_BASE
  DECL|SCB0|macro|SCB0
  DECL|SCB1_BASE|macro|SCB1_BASE
  DECL|SCB1|macro|SCB1
  DECL|SCB2_BASE|macro|SCB2_BASE
  DECL|SCB2|macro|SCB2
  DECL|SCB3_BASE|macro|SCB3_BASE
  DECL|SCB3|macro|SCB3
  DECL|SCB4_BASE|macro|SCB4_BASE
  DECL|SCB4|macro|SCB4
  DECL|SCB5_BASE|macro|SCB5_BASE
  DECL|SCB5|macro|SCB5
  DECL|SCB6_BASE|macro|SCB6_BASE
  DECL|SCB6|macro|SCB6
  DECL|SCB7_BASE|macro|SCB7_BASE
  DECL|SCB7|macro|SCB7
  DECL|SCB8_BASE|macro|SCB8_BASE
  DECL|SCB8|macro|SCB8
  DECL|SFLASH_BASE|macro|SFLASH_BASE
  DECL|SFLASH|macro|SFLASH
  DECL|SMARTIO_BASE|macro|SMARTIO_BASE
  DECL|SMARTIO_PRT8|macro|SMARTIO_PRT8
  DECL|SMARTIO_PRT9|macro|SMARTIO_PRT9
  DECL|SMARTIO|macro|SMARTIO
  DECL|SMIF0_BASE|macro|SMIF0_BASE
  DECL|SMIF0_DEVICE0|macro|SMIF0_DEVICE0
  DECL|SMIF0_DEVICE1|macro|SMIF0_DEVICE1
  DECL|SMIF0_DEVICE2|macro|SMIF0_DEVICE2
  DECL|SMIF0_DEVICE3|macro|SMIF0_DEVICE3
  DECL|SMIF0|macro|SMIF0
  DECL|SRSS_BASE|macro|SRSS_BASE
  DECL|SRSS|macro|SRSS
  DECL|SVCall_IRQn|enumerator|SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
  DECL|SysTick_IRQn|enumerator|SysTick_IRQn = -1, /*!< -1 System Tick Timer */
  DECL|TCPWM0_BASE|macro|TCPWM0_BASE
  DECL|TCPWM0_CNT0|macro|TCPWM0_CNT0
  DECL|TCPWM0_CNT1|macro|TCPWM0_CNT1
  DECL|TCPWM0_CNT2|macro|TCPWM0_CNT2
  DECL|TCPWM0_CNT3|macro|TCPWM0_CNT3
  DECL|TCPWM0_CNT4|macro|TCPWM0_CNT4
  DECL|TCPWM0_CNT5|macro|TCPWM0_CNT5
  DECL|TCPWM0_CNT6|macro|TCPWM0_CNT6
  DECL|TCPWM0_CNT7|macro|TCPWM0_CNT7
  DECL|TCPWM0|macro|TCPWM0
  DECL|TCPWM1_BASE|macro|TCPWM1_BASE
  DECL|TCPWM1_CNT0|macro|TCPWM1_CNT0
  DECL|TCPWM1_CNT10|macro|TCPWM1_CNT10
  DECL|TCPWM1_CNT11|macro|TCPWM1_CNT11
  DECL|TCPWM1_CNT12|macro|TCPWM1_CNT12
  DECL|TCPWM1_CNT13|macro|TCPWM1_CNT13
  DECL|TCPWM1_CNT14|macro|TCPWM1_CNT14
  DECL|TCPWM1_CNT15|macro|TCPWM1_CNT15
  DECL|TCPWM1_CNT16|macro|TCPWM1_CNT16
  DECL|TCPWM1_CNT17|macro|TCPWM1_CNT17
  DECL|TCPWM1_CNT18|macro|TCPWM1_CNT18
  DECL|TCPWM1_CNT19|macro|TCPWM1_CNT19
  DECL|TCPWM1_CNT1|macro|TCPWM1_CNT1
  DECL|TCPWM1_CNT20|macro|TCPWM1_CNT20
  DECL|TCPWM1_CNT21|macro|TCPWM1_CNT21
  DECL|TCPWM1_CNT22|macro|TCPWM1_CNT22
  DECL|TCPWM1_CNT23|macro|TCPWM1_CNT23
  DECL|TCPWM1_CNT2|macro|TCPWM1_CNT2
  DECL|TCPWM1_CNT3|macro|TCPWM1_CNT3
  DECL|TCPWM1_CNT4|macro|TCPWM1_CNT4
  DECL|TCPWM1_CNT5|macro|TCPWM1_CNT5
  DECL|TCPWM1_CNT6|macro|TCPWM1_CNT6
  DECL|TCPWM1_CNT7|macro|TCPWM1_CNT7
  DECL|TCPWM1_CNT8|macro|TCPWM1_CNT8
  DECL|TCPWM1_CNT9|macro|TCPWM1_CNT9
  DECL|TCPWM1|macro|TCPWM1
  DECL|USBFS0_BASE|macro|USBFS0_BASE
  DECL|USBFS0_USBDEV|macro|USBFS0_USBDEV
  DECL|USBFS0_USBHOST|macro|USBFS0_USBHOST
  DECL|USBFS0_USBLPM|macro|USBFS0_USBLPM
  DECL|USBFS0|macro|USBFS0
  DECL|_CY8C6336BZI_BUD13_H_|macro|_CY8C6336BZI_BUD13_H_
  DECL|__CM0PLUS_REV|macro|__CM0PLUS_REV
  DECL|__CM0P_PRESENT|macro|__CM0P_PRESENT
  DECL|__CM4_REV|macro|__CM4_REV
  DECL|__FPU_PRESENT|macro|__FPU_PRESENT
  DECL|__MPU_PRESENT|macro|__MPU_PRESENT
  DECL|__MPU_PRESENT|macro|__MPU_PRESENT
  DECL|__NVIC_PRIO_BITS|macro|__NVIC_PRIO_BITS
  DECL|__NVIC_PRIO_BITS|macro|__NVIC_PRIO_BITS
  DECL|__VTOR_PRESENT|macro|__VTOR_PRESENT
  DECL|__VTOR_PRESENT|macro|__VTOR_PRESENT
  DECL|__Vendor_SysTickConfig|macro|__Vendor_SysTickConfig
  DECL|__Vendor_SysTickConfig|macro|__Vendor_SysTickConfig
  DECL|audioss_interrupt_i2s_IRQn|enumerator|audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
  DECL|audioss_interrupt_pdm_IRQn|enumerator|audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
  DECL|bless_interrupt_IRQn|enumerator|bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
  DECL|cpuss_interrupt_crypto_IRQn|enumerator|cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
  DECL|cpuss_interrupt_fm_IRQn|enumerator|cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
  DECL|cpuss_interrupts_cm0_cti_0_IRQn|enumerator|cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
  DECL|cpuss_interrupts_cm0_cti_1_IRQn|enumerator|cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
  DECL|cpuss_interrupts_cm4_cti_0_IRQn|enumerator|cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
  DECL|cpuss_interrupts_cm4_cti_1_IRQn|enumerator|cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
  DECL|cpuss_interrupts_dw0_0_IRQn|enumerator|cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
  DECL|cpuss_interrupts_dw0_10_IRQn|enumerator|cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
  DECL|cpuss_interrupts_dw0_11_IRQn|enumerator|cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
  DECL|cpuss_interrupts_dw0_12_IRQn|enumerator|cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
  DECL|cpuss_interrupts_dw0_13_IRQn|enumerator|cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
  DECL|cpuss_interrupts_dw0_14_IRQn|enumerator|cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
  DECL|cpuss_interrupts_dw0_15_IRQn|enumerator|cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
  DECL|cpuss_interrupts_dw0_1_IRQn|enumerator|cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
  DECL|cpuss_interrupts_dw0_2_IRQn|enumerator|cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
  DECL|cpuss_interrupts_dw0_3_IRQn|enumerator|cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
  DECL|cpuss_interrupts_dw0_4_IRQn|enumerator|cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
  DECL|cpuss_interrupts_dw0_5_IRQn|enumerator|cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
  DECL|cpuss_interrupts_dw0_6_IRQn|enumerator|cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
  DECL|cpuss_interrupts_dw0_7_IRQn|enumerator|cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
  DECL|cpuss_interrupts_dw0_8_IRQn|enumerator|cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
  DECL|cpuss_interrupts_dw0_9_IRQn|enumerator|cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
  DECL|cpuss_interrupts_dw1_0_IRQn|enumerator|cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
  DECL|cpuss_interrupts_dw1_10_IRQn|enumerator|cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
  DECL|cpuss_interrupts_dw1_11_IRQn|enumerator|cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
  DECL|cpuss_interrupts_dw1_12_IRQn|enumerator|cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
  DECL|cpuss_interrupts_dw1_13_IRQn|enumerator|cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
  DECL|cpuss_interrupts_dw1_14_IRQn|enumerator|cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
  DECL|cpuss_interrupts_dw1_15_IRQn|enumerator|cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
  DECL|cpuss_interrupts_dw1_1_IRQn|enumerator|cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
  DECL|cpuss_interrupts_dw1_2_IRQn|enumerator|cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
  DECL|cpuss_interrupts_dw1_3_IRQn|enumerator|cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
  DECL|cpuss_interrupts_dw1_4_IRQn|enumerator|cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
  DECL|cpuss_interrupts_dw1_5_IRQn|enumerator|cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
  DECL|cpuss_interrupts_dw1_6_IRQn|enumerator|cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
  DECL|cpuss_interrupts_dw1_7_IRQn|enumerator|cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
  DECL|cpuss_interrupts_dw1_8_IRQn|enumerator|cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
  DECL|cpuss_interrupts_dw1_9_IRQn|enumerator|cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
  DECL|cpuss_interrupts_fault_0_IRQn|enumerator|cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
  DECL|cpuss_interrupts_fault_1_IRQn|enumerator|cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
  DECL|cpuss_interrupts_ipc_0_IRQn|enumerator|cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
  DECL|cpuss_interrupts_ipc_10_IRQn|enumerator|cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
  DECL|cpuss_interrupts_ipc_11_IRQn|enumerator|cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
  DECL|cpuss_interrupts_ipc_12_IRQn|enumerator|cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
  DECL|cpuss_interrupts_ipc_13_IRQn|enumerator|cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
  DECL|cpuss_interrupts_ipc_14_IRQn|enumerator|cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
  DECL|cpuss_interrupts_ipc_15_IRQn|enumerator|cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
  DECL|cpuss_interrupts_ipc_1_IRQn|enumerator|cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
  DECL|cpuss_interrupts_ipc_2_IRQn|enumerator|cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
  DECL|cpuss_interrupts_ipc_3_IRQn|enumerator|cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
  DECL|cpuss_interrupts_ipc_4_IRQn|enumerator|cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
  DECL|cpuss_interrupts_ipc_5_IRQn|enumerator|cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
  DECL|cpuss_interrupts_ipc_6_IRQn|enumerator|cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
  DECL|cpuss_interrupts_ipc_7_IRQn|enumerator|cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
  DECL|cpuss_interrupts_ipc_8_IRQn|enumerator|cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
  DECL|cpuss_interrupts_ipc_9_IRQn|enumerator|cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
  DECL|csd_interrupt_IRQn|enumerator|csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
  DECL|cy_en_intr_t|typedef|} cy_en_intr_t;
  DECL|disconnected_IRQn|enumerator|disconnected_IRQn = 240 /*!< 240 Disconnected */
  DECL|ioss_interrupt_gpio_IRQn|enumerator|ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
  DECL|ioss_interrupt_vdd_IRQn|enumerator|ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
  DECL|ioss_interrupts_gpio_0_IRQn|enumerator|ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
  DECL|ioss_interrupts_gpio_10_IRQn|enumerator|ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
  DECL|ioss_interrupts_gpio_11_IRQn|enumerator|ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
  DECL|ioss_interrupts_gpio_12_IRQn|enumerator|ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
  DECL|ioss_interrupts_gpio_13_IRQn|enumerator|ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
  DECL|ioss_interrupts_gpio_14_IRQn|enumerator|ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
  DECL|ioss_interrupts_gpio_1_IRQn|enumerator|ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
  DECL|ioss_interrupts_gpio_2_IRQn|enumerator|ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
  DECL|ioss_interrupts_gpio_3_IRQn|enumerator|ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
  DECL|ioss_interrupts_gpio_4_IRQn|enumerator|ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
  DECL|ioss_interrupts_gpio_5_IRQn|enumerator|ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
  DECL|ioss_interrupts_gpio_6_IRQn|enumerator|ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
  DECL|ioss_interrupts_gpio_7_IRQn|enumerator|ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
  DECL|ioss_interrupts_gpio_8_IRQn|enumerator|ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
  DECL|ioss_interrupts_gpio_9_IRQn|enumerator|ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
  DECL|lpcomp_interrupt_IRQn|enumerator|lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
  DECL|pass_interrupt_ctbs_IRQn|enumerator|pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
  DECL|pass_interrupt_dacs_IRQn|enumerator|pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
  DECL|pass_interrupt_sar_IRQn|enumerator|pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
  DECL|profile_interrupt_IRQn|enumerator|profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
  DECL|scb_0_interrupt_IRQn|enumerator|scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
  DECL|scb_1_interrupt_IRQn|enumerator|scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
  DECL|scb_2_interrupt_IRQn|enumerator|scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
  DECL|scb_3_interrupt_IRQn|enumerator|scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
  DECL|scb_4_interrupt_IRQn|enumerator|scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
  DECL|scb_5_interrupt_IRQn|enumerator|scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
  DECL|scb_6_interrupt_IRQn|enumerator|scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
  DECL|scb_7_interrupt_IRQn|enumerator|scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
  DECL|scb_8_interrupt_IRQn|enumerator|scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
  DECL|smif_interrupt_IRQn|enumerator|smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
  DECL|srss_interrupt_IRQn|enumerator|srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
  DECL|srss_interrupt_backup_IRQn|enumerator|srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
  DECL|srss_interrupt_mcwdt_0_IRQn|enumerator|srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
  DECL|srss_interrupt_mcwdt_1_IRQn|enumerator|srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
  DECL|tcpwm_0_interrupts_0_IRQn|enumerator|tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
  DECL|tcpwm_0_interrupts_1_IRQn|enumerator|tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
  DECL|tcpwm_0_interrupts_2_IRQn|enumerator|tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
  DECL|tcpwm_0_interrupts_3_IRQn|enumerator|tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
  DECL|tcpwm_0_interrupts_4_IRQn|enumerator|tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
  DECL|tcpwm_0_interrupts_5_IRQn|enumerator|tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
  DECL|tcpwm_0_interrupts_6_IRQn|enumerator|tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
  DECL|tcpwm_0_interrupts_7_IRQn|enumerator|tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
  DECL|tcpwm_1_interrupts_0_IRQn|enumerator|tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
  DECL|tcpwm_1_interrupts_10_IRQn|enumerator|tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
  DECL|tcpwm_1_interrupts_11_IRQn|enumerator|tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
  DECL|tcpwm_1_interrupts_12_IRQn|enumerator|tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
  DECL|tcpwm_1_interrupts_13_IRQn|enumerator|tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
  DECL|tcpwm_1_interrupts_14_IRQn|enumerator|tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
  DECL|tcpwm_1_interrupts_15_IRQn|enumerator|tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
  DECL|tcpwm_1_interrupts_16_IRQn|enumerator|tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
  DECL|tcpwm_1_interrupts_17_IRQn|enumerator|tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
  DECL|tcpwm_1_interrupts_18_IRQn|enumerator|tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
  DECL|tcpwm_1_interrupts_19_IRQn|enumerator|tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
  DECL|tcpwm_1_interrupts_1_IRQn|enumerator|tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
  DECL|tcpwm_1_interrupts_20_IRQn|enumerator|tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
  DECL|tcpwm_1_interrupts_21_IRQn|enumerator|tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
  DECL|tcpwm_1_interrupts_22_IRQn|enumerator|tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
  DECL|tcpwm_1_interrupts_23_IRQn|enumerator|tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
  DECL|tcpwm_1_interrupts_2_IRQn|enumerator|tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
  DECL|tcpwm_1_interrupts_3_IRQn|enumerator|tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
  DECL|tcpwm_1_interrupts_4_IRQn|enumerator|tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
  DECL|tcpwm_1_interrupts_5_IRQn|enumerator|tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
  DECL|tcpwm_1_interrupts_6_IRQn|enumerator|tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
  DECL|tcpwm_1_interrupts_7_IRQn|enumerator|tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
  DECL|tcpwm_1_interrupts_8_IRQn|enumerator|tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
  DECL|tcpwm_1_interrupts_9_IRQn|enumerator|tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
  DECL|udb_interrupts_0_IRQn|enumerator|udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
  DECL|udb_interrupts_10_IRQn|enumerator|udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
  DECL|udb_interrupts_11_IRQn|enumerator|udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
  DECL|udb_interrupts_12_IRQn|enumerator|udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
  DECL|udb_interrupts_13_IRQn|enumerator|udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
  DECL|udb_interrupts_14_IRQn|enumerator|udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
  DECL|udb_interrupts_15_IRQn|enumerator|udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
  DECL|udb_interrupts_1_IRQn|enumerator|udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
  DECL|udb_interrupts_2_IRQn|enumerator|udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
  DECL|udb_interrupts_3_IRQn|enumerator|udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
  DECL|udb_interrupts_4_IRQn|enumerator|udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
  DECL|udb_interrupts_5_IRQn|enumerator|udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
  DECL|udb_interrupts_6_IRQn|enumerator|udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
  DECL|udb_interrupts_7_IRQn|enumerator|udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
  DECL|udb_interrupts_8_IRQn|enumerator|udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
  DECL|udb_interrupts_9_IRQn|enumerator|udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
  DECL|unconnected_IRQn|enumerator|unconnected_IRQn = 240 /*!< 240 Unconnected */
  DECL|usb_interrupt_hi_IRQn|enumerator|usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
  DECL|usb_interrupt_lo_IRQn|enumerator|usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
  DECL|usb_interrupt_med_IRQn|enumerator|usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
  