text: // ==============================================================
  // File generated on Fri Dec 11 15:53:45 +0800 2020
  // Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.3 (64-bit)
  // SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
  // IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
  // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
  // ==============================================================
  #ifndef __lstm_i_state_H__
  #define __lstm_i_state_H__
  
  
  #include <systemc>
  using namespace sc_core;
  using namespace sc_dt;
  
  
  
  
  #include <iostream>
  #include <fstream>
  
  struct lstm_i_state_ram : public sc_core::sc_module {
  
    static const unsigned DataWidth = 32;
    static const unsigned AddressRange = 100;
    static const unsigned AddressWidth = 7;
  
  //latency = 1
  //input_reg = 1
  //output_reg = 0
  sc_core::sc_in <sc_lv<AddressWidth> > address0;
  sc_core::sc_in <sc_logic> ce0;
  sc_core::sc_out <sc_lv<DataWidth> > q0;
  sc_core::sc_in<sc_logic> we0;
  sc_core::sc_in<sc_lv<DataWidth> > d0;
  sc_core::sc_in <sc_lv<AddressWidth> > address1;
  sc_core::sc_in <sc_logic> ce1;
  sc_core::sc_out <sc_lv<DataWidth> > q1;
  sc_core::sc_in<sc_logic> we1;
  sc_core::sc_in<sc_lv<DataWidth> > d1;
  sc_core::sc_in<sc_logic> reset;
  sc_core::sc_in<bool> clk;
  
  
  sc_lv<DataWidth> ram[AddressRange];
  
  
     SC_CTOR(lstm_i_state_ram) {
  
  
  SC_METHOD(prc_write_0);
    sensitive<<clk.pos();
  
  
  SC_METHOD(prc_write_1);
    sensitive<<clk.pos();
     }
  
  
  void prc_write_0()
  {
      if (ce0.read() == sc_dt::Log_1) 
      {
          if (we0.read() == sc_dt::Log_1) 
          {
             if(address0.read().is_01() && address0.read().to_uint()<AddressRange)
             {
                ram[address0.read().to_uint()] = d0.read(); 
                q0 = d0.read();
             }
             else
                q0 = sc_lv<DataWidth>();
          }
          else {
              if(address0.read().is_01() && address0.read().to_uint()<AddressRange)
                q0 = ram[address0.read().to_uint()];
              else
                q0 = sc_lv<DataWidth>();
          }
      }
  }
  
  
  void prc_write_1()
  {
      if (ce1.read() == sc_dt::Log_1) 
      {
          if (we1.read() == sc_dt::Log_1) 
          {
             if(address1.read().is_01() && address1.read().to_uint()<AddressRange)
             {
                ram[address1.read().to_uint()] = d1.read(); 
                q1 = d1.read();
             }
             else
                q1 = sc_lv<DataWidth>();
          }
          else {
              if(address1.read().is_01() && address1.read().to_uint()<AddressRange)
                q1 = ram[address1.read().to_uint()];
              else
                q1 = sc_lv<DataWidth>();
          }
      }
  }
  
  
  }; //endmodule
  
  
  SC_MODULE(lstm_i_state) {
  
  
  static const unsigned DataWidth = 32;
  static const unsigned AddressRange = 100;
  static const unsigned AddressWidth = 7;
  
  sc_core::sc_in <sc_lv<AddressWidth> > address0;
  sc_core::sc_in<sc_logic> ce0;
  sc_core::sc_out <sc_lv<DataWidth> > q0;
  sc_core::sc_in<sc_logic> we0;
  sc_core::sc_in<sc_lv<DataWidth> > d0;
  sc_core::sc_in <sc_lv<AddressWidth> > address1;
  sc_core::sc_in<sc_logic> ce1;
  sc_core::sc_out <sc_lv<DataWidth> > q1;
  sc_core::sc_in<sc_logic> we1;
  sc_core::sc_in<sc_lv<DataWidth> > d1;
  sc_core::sc_in<sc_logic> reset;
  sc_core::sc_in<bool> clk;
  
  
  lstm_i_state_ram* meminst;
  
  
  SC_CTOR(lstm_i_state) {
  meminst = new lstm_i_state_ram("lstm_i_state_ram");
  meminst->address0(address0);
  meminst->ce0(ce0);
  meminst->q0(q0);
  meminst->we0(we0);
  meminst->d0(d0);
  
  meminst->address1(address1);
  meminst->ce1(ce1);
  meminst->q1(q1);
  meminst->we1(we1);
  meminst->d1(d1);
  
  meminst->reset(reset);
  meminst->clk(clk);
  }
  ~lstm_i_state() {
      delete meminst;
  }
  
  
  };//endmodule
  #endif
  