UTRAN TDD low chiprate
The work item "Low chip rate TDD Iub/Iur protocol aspects" is a Building Block which has been agreed at TSG RAN#8 as described in contribution [1]. Its parent feature is "Low chip rate TDD" which has been agreed at TSG-RAN#6 and updated at RAN#7. The purpose of the work item "Low chip rate TDD Iub/Iur protocol aspects" is to update the Iub/Iur interface protocol specifications and related overview specifications in RAN WG3 in support of the several aspects of the feature "Low chip rate TDD".
The purpose of the present document is to help the TSG RAN WG3 group to specify the changes to existing specifications, needed for the introduction of the low chip rate TDD option in the UTRAN for Rel.4. It is intended to gather all information in order to trace the history and the status of the Work Task in RAN WG3. It is not intended to replace contributions and Change Requests, but only to list conclusions and make reference to agreed contributions and CRs. When solutions are sufficiently stable, the CRs can be issued.
It describes agreed requirements related to the Work Task, and split the Work Task into "Study Areas" in order to group contributions in a consistent way.
It identifies the affected specifications with related Change Requests.
It also describes the schedule of the Work Task.
The present document is a "living" document, i.e. it is permanently updated and presented to all TSG-RAN meetings.