Show HN: Smelt — an open source test runner for chip developers
Hey everyone, James from Silogy here.<p>We’re excited to open-source our test runner, Smelt. Smelt is a simple and extensible test runner optimized for chip development workflows. Smelt enables developers to:<p>* Programmatically define numerous test variants<p>* Execute these tests in parallel<p>* Easily analyze test results<p>As chip designs get more complex, the state space that needs to be explored in design verification is exploding. In chip development, it&#x27;s common to run thousands of tests, each with multiple hyperparameters that result in even more variation. Smelt offers a straightforward approach to generating test variants and extracting valuable insights from your test runs. Smelt integrates seamlessly with most popular simulators and other chip design tools.<p>Key features:<p>* Procedural test generation: Programmatically generate tests with python<p>* Automatic rerun on failure: Describe the computation required re-run failing tests<p>* Analysis APIs: All of the data needed to track and reproduce tests<p>* Extensible: Define your tests with a simple python interface<p>Yves (<a href="https:&#x2F;&#x2F;github.com&#x2F;silogy-io&#x2F;yves">https:&#x2F;&#x2F;github.com&#x2F;silogy-io&#x2F;yves</a>) is a suite of directed performance tests that we brought up with smelt – check it out if you’d like to see smelt in action.<p>Repo: <a href="https:&#x2F;&#x2F;github.com&#x2F;silogy-io&#x2F;smelt">https:&#x2F;&#x2F;github.com&#x2F;silogy-io&#x2F;smelt</a><p>We built Smelt to streamline the testing process for chip developers. We&#x27;re eager to hear your feedback and see how it performs in your projects!