Google, HP, Oracle Join RISC-V
Google, HP, Oracle Join RISC-V

			

							

				
				

				
				

					
					

SAN JOSE, Calif. – RISC-V is on the march as an open source alternative to ARM and Mips. Fifteen sponsors, including a handful of high tech giants, are queuing up to be the first members of its new trade group which will host next week its third workshop for the processor core.
RISC V is the latest evolution of the original RISC core developed more than 25 years ago by Berkeley’s David Patterson and Stanford’s John Hennessey. In August 2014, Patterson and colleagues launched an open source effort around the core as an enabler for a new class of processors and SoCs with small teams and volumes that can’t afford licensed cores or get the attention of their vendors.

Google, Hewlett Packard Enterprise (HPE), Lattice, Microsemi and Oracle – which is hosting next week’s workshop — will be among the first members of RISC-V. Tool vendor Bluespec also is joining the group.


The group is still drafting the details of the open source license which will be part of its member agreement. The terms will specify a zero-royalty RAND license as well as verification suites licensees must run to use the RISC-V logo.
		
		
		
				
					
					
					
					
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Users will need to contribute as open source any changes they make to the core. Nevertheless, “there’s plenty of room for secret sauce and company-specific implementations,” said Rick O’Connor, executive director of the RISC-V Foundation.

Currently RISC-V runs Linux and NetBSD, but not Android, Windows or any major embedded RTOSes. Support for other operating systems is expected in 2016.
So far, a camera SoC is the only shipping chip said to use the open source core commercially. A handful of university projects use the core including a government-supported effort at IIT Madras in India to develop a homegrown processor family. The IIT chips and three or four other processors in the works use the Rapid IO interconnect as a front-side bus, said O’Connor who also manages the Rapid IO trade group.
At the workshop, two talks will describe boot environments for RISC-V in separate papers presented by engineers from Google and a team from HPE and Intel. A representative of military contractor BAE Systems will talk about building the software ecosystem for RISC-V.
Next page: FPGA accelerators tap RISC-V

		
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							Rick MerrittBased in San Jose, Rick writes news and analysis about the electronics industry and the engineering profession for EE Times. He is the editor of the Android, Internet of Things, Wireless/Networking, and Medical Designlines. He joined EE Times in 1992 as a Hong Kong based reporter and has served as editor in chief of EE Times and OEM Magazine.
																	
							
						
									
				
                

								


				





















                
			

		
			
			
			
			
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