Help me write some HLS source code to create a FPGA hardware accelerator for a streaming-based linear layer acclerator. Please use the Vitis HLS libaraies including `hls_math.h`, `hls_stream.h`, and `ap_fixed.h`. The inputs to the kernel is one stream for the input vector, and two fixed arrays for the weights and bias. Everything uses fixed point types of `ap_fixed<32,10>`.
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