def METHOD_NAME():
    name = f'ckt_{get_test_id()}'.upper()
    netlist = ota_six(name)
    constraints = [
        {"constraint": "PowerPorts", "ports": ["VCCX"]},
        {"constraint": "GroundPorts", "ports": ["VSSX"]},
        {"constraint": "DoNotUseLib", "libraries": ["DP_NMOS_B"]}
    ]
    example = build_example(name, netlist, constraints)
    ckt_lib, prim_lib = compiler_input(example, name, pdk_path, config_path)
    annotate_library(ckt_lib, prim_lib)
    all_modules = set(['CKT_DONT_USE_LIB', 'SCM_NMOS', 'SCM_PMOS', "NMOS_4T"])
    available_modules = set(
        ['_'.join(module.name.split('_')[:-1]) for module in ckt_lib if isinstance(module, SubCircuit)]
    )
    assert available_modules == all_modules, f"{available_modules}"
    clean_data(name)