### slides

```Logic and Computer Design Fundamentals
Chapter 3 – Combinational
Logic Design
Charles Kime & Thomas Kaminski
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Combinational Circuits
 A combinational logic circuit has:
• A set of m Boolean inputs,
• A set of n Boolean outputs, and
• n switching functions, each mapping the 2m input
combinations to an output such that the current output
depends only on the current input values
 A block diagram:
Combinatorial
Logic
Circuit
m Boolean Inputs
n Boolean Outputs
Design Procedure
1. Specification
•
Write a specification for the circuit if one is not
2. Formulation
•
•
Derive a truth table or initial Boolean equations
that define the required relationships between the
inputs and outputs, if not in the specification
Apply hierarchical design if appropriate
3. Optimization
•
•
Apply 2-level and multiple-level optimization
Draw a logic diagram or provide a netlist for the
resulting circuit using ANDs, ORs, and inverters
Design Procedure
4. Technology Mapping
•
Map the logic diagram or netlist to the
implementation technology selected
5. Verification
•
Verify the correctness of the final design
manually or using simulation
Design Example
1. Specification
• BCD to Excess-3 code converter
• Transforms BCD code for the decimal digits to
Excess-3 code for the decimal digits
• BCD code words for digits 0 through 9: 4-bit
patterns 0000 to 1001, respectively
• Excess-3 code words for digits 0 through 9: 4bit patterns consisting of 3 (binary 0011) added
to each BCD code word
• Implementation:
 multiple-level circuit
 NAND gates (including inverters)
Design Example (continued)
2. Formulation
•
•
•
•
Conversion of 4-bit codes can be most easily
formulated by a truth table
Variables
Input BCD
Output Excess-3
- BCD:
ABCD
WXYZ
A,B,C,D
0000
0011
0001
0100
Variables
0010
0101
- Excess-3
0011
0110
W,X,Y,Z
0100
0111
0101
1000
Don’t Cares
0110
1001
- BCD 1010
0111
1010
to 1111
1000
1011
1001
1011
Design Example (continued)
3.
Optimization z
a. 2-level using
K-maps
W = A + BC + BD
X = B C + B D + BC
Y = CD + C D
Z=D
C
1
1
0
1
3
4
5
7
1
X
X
13
9
1
4
5
X
A
X
13
9
1
1
2
0
4
5
7
6
4
1
1
X
13
X
X
14
10
1
5
1
1
X
13
6
X
9
14
X
11
D
B
X
15
1
8
2
7
X
12
A
X
11
D
B
X
15
9
10
3
1
8
X
11
C
3
1
14
w
1
A
B
X
D
0
12
6
X
8
C
X
7
15
1
10
x
X
2
X
D
1
3
1
12
X
11
D
B
14
X
8
1
0
1
X
15
1
1
6
X
12
C
2
1
A
y
10
Design Example (continued)
3. Optimization (continued)
b. Multiple-level using transformations
W = A + BC + BD
X = B C + B D + BC
Y = CD + C D
Z=D
•
D
G = 7 + 10 + 6 + 0 = 23
Perform extraction, finding factor:
T1 = C + D
W = A + BT1
X = B T1 + BC
Y = CD + C D
Z= D
D
G = 2 + 1 + 4 + 7 + 6 + 0 = 19
Design Example (continued)
3. Optimization (continued)
b. Multiple-level using transformations
T1 = C + D
W = A + BT1
X = B T1 + BC D
Y = CD + C D
Z =D
G = 19
• An additional extraction not shown in the text since it
uses a Boolean transformation: ( C D = C + D = T1 ):
W = A + BT1
X = B T1 + B T1
Y = CD + T1
Z= D
G = 2 +1 + 4 + 6 + 4 + 0 = 16!
Design Example (continued)
4. Technology Mapping
•
Mapping with a library containing inverters and 2-input
NAND, 2-input NOR, and 2-2 AOI gates
A
A
W
W
B
X
B
X
C
C
D
Y
D
Y
Z
Z
Beginning Hierarchical Design
 To control the complexity of the function mapping inputs to
outputs:
• Decompose the function into smaller pieces called blocks
• Decompose each block’s function into smaller blocks, repeating as
necessary until all blocks are small enough
• Any block not decomposed is called a primitive block
• The collection of all blocks including the decomposed ones is a
hierarchy
 Example: 9-input parity tree (see next slide)
•
•
•
•
•
Top Level: 9 inputs, one output
2nd Level: Four 3-bit odd parity trees in two levels
3rd Level: Two 2-bit exclusive-OR functions
Primitives: Four 2-input NAND gates
Design requires 4 X 2 X 4 = 32 2-input NAND gates
Hierarchy for Parity Tree Example
X
X
X
X
X
X
X
X
X
0
1
2
3
4
5
9-Input
odd
Z
O
function
X
6
0
A
0
3-Input
7
X
8
1
A
odd
1
B
O
function
(a) Symbol for circuit
X
X
X
2
3
4
A
A
A
2
0
A
3-Input
odd
1
B
O
A
0
1
function
X
X
X
5
6
7
A
A
A
A
2
3-Input
odd
1
B
O
function
X
8
A
2
(b) Circuit as interconnected 3-input odd
function blocks
A
A
A
0
B
1
odd
function
2
0
3-Input
O
2
(c) 3-input odd function circuit as
interconnected exclusive-OR
blocks
(d) Exclusive-OR block as interconnected
NANDs
B
O
Z
O
Reusable Functions
 Whenever possible, we try to decompose
function blocks
 These blocks are
• verified and well-documented
• placed in libraries for future use
Top-Down versus Bottom-Up
 A top-down design proceeds from an abstract, high-level
specification to a more and more detailed design by
decomposition and successive refinement
 A bottom-up design starts with detailed primitive blocks
and combines them into larger and more complex
functional blocks
 Design usually proceeds top-down to known building
blocks ranging from complete CPUs to primitive logic
gates or electronic components.
 Much of the material in this chapter is devoted to
learning about combinational blocks used in top-down
design.
Technology Mapping
 Mapping Procedures
• To NAND gates
• To NOR gates
• Mapping to multiple types of logic blocks in
Mapping to NAND gates
 Assumptions:
• Cell library contains an inverter and n-input NAND
gates, n = 2, 3, …
• An AND, OR, inverter schematic for the circuit is
available
 The mapping is accomplished by:
• Replacing AND and OR symbols,
• Pushing inverters through circuit fan-out points, and
• Canceling inverter pairs
NAND Mapping Algorithm
1. Replace ANDs and ORs:
.
.
.
.
.
.
.
.
.
.
.
.
2. Repeat the following pair of actions until there
is at most one inverter between :
a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.
.
.
.
.
.
.
NAND Mapping Example
Mapping to NOR gates
 Assumptions:
• Cell library contains an inverter and n-input NOR
gates, n = 2, 3, …
• An AND, OR, inverter schematic for the circuit is
available
 The mapping is accomplished by:
• Replacing AND and OR symbols,
• Pushing inverters through circuit fan-out points, and
• Canceling inverter pairs
NOR Mapping Algorithm
1. Replace ANDs and ORs:
.
.
.
.
.
.
.
.
.
.
.
.
2. Repeat the following pair of actions until there
is at most one inverter between :
a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.
.
.
.
.
.
.
NOR Mapping Example
A
A
B
B
2
1
F
C
X
F
C
D
3
D
E
(a)
A
E
(b)
B
C
F
D
E
(c)
Verification
 Verification - show that the final circuit
designed implements the original specification
 Simple specifications are:
• truth tables
• Boolean equations
• HDL code
 If the above result from formulation and are
not the original specification, it is critical that
the formulation process be flawless for the
verification to be valid!
Basic Verification Methods
 Manual Logic Analysis
• Find the truth table or Boolean equations for the final circuit
• Compare the final circuit truth table with the specified truth
table, or
• Show that the Boolean equations for the final circuit are equal
to the specified Boolean equations
 Simulation
• Simulate the final circuit (or its netlist, possibly written as an
HDL) and the specified truth table, equations, or HDL
description using test input values that fully validate
correctness.
• The obvious test for a combinational circuit is application of all
possible “care” input combinations from the specification
Verification Example: Simulation
 Simulation procedure:
• Use a schematic editor or text editor to enter
a gate level representation of the final circuit
• Use a waveform editor or text editor to enter
a test consisting of a sequence of input
combinations to be applied to the circuit
 This test should guarantee the correctness of the
circuit if the simulated responses to it are correct
 Short of applying all possible “care” input
combinations, generation of such a test can be
difficult
Verification Example: Simulation
 Enter BCD-to-Excess-3 Code Converter Circuit Schematic
AOI symbol
not available
Verification Example: Simulation
 Enter waveform that applies all possible input combinations:
INPUTS
A
B
C
D
0
50 ns
100 ns
 Are all BCD input combinations present? (Low is a 0 and high
is a one)
Verification Example: Simulation
 Run the simulation of the circuit for 120 ns
INPUTS
A
B
C
D
OUTPUTS
W
X
Y
Z
0
50 ns
100 ns
 Do the simulation output combinations match the original
truth table?
Functions and Functional Blocks
 The functions considered are those found to be
very useful in design
 Corresponding to each of the functions is a
combinational circuit implementation called a
functional block.
 In the past, functional blocks were packaged as
small-scale-integrated (SSI), medium-scale
integrated (MSI), and large-scale-integrated
(LSI) circuits.
 Today, they are often simply implemented within
a very-large-scale-integrated (VLSI) circuit.
Rudimentary Logic Functions
 Functions of a single variable X
TABLE 4-1
 Can be used on the
Functions of One Variable
inputs to functional
X
F=0 F=X F= X F=1
blocks to implement
other than the block’s
0
0
0
1
1
intended function
1
0
1
0
1
V CC or V DD
1
F5 1
F5 1
X
F5 X
(c)
0
F5 0
F5 0
X
(a)
(b)
F5 X
(d)
Multiple-bit Rudimentary Functions
 Multi-bit Examples:
A
1
0
A





F3 A
F2 1
F1 0
F0 A
2
1
3
0
4
F
4
2:1
2
F(2:1)
F
(c)
3
(a)
(b)
F(3), F(1:0)
4 3,1:0
A wide line is used to represent
F
a bus which is a vector signal
(d)
In (b) of the example, F = (F3, F2, F1, F0) is a bus.
The bus can be split into individual bits as shown in (b)
Sets of bits can be split from the bus as shown in (c)
for bits 2 and 1 of F.
The sets of bits need not be continuous as shown in (d) for bits 3, 1, and
0 of F.
Enabling Function
 Enabling permits an input signal to pass
through to an output
 Disabling blocks an input signal from passing
through to an output, replacing it with a fixed
value
 The value on the output when it is disable can
be Hi-Z (as for three-state buffers and
transmission gates), 0 , or 1 ENX
F
 When disabled, 0 output
 When disabled, 1 output
 See Enabling App in text
(a)
X
F
EN
(b)
3-7 Decoding
 A n-bit binary code can represent up to m=2n
elements:
encoding
m elements
n-bit binary code
(ex. 256 alpha-num. chars) decoding
(ex. 8-bit ASCII code)
 Decoding - the conversion of an n-bit input code
to an m-bit output code with
n ≤ m ≤ 2n such that each valid code word
produces a unique output code
n bits
A0
:
:
An-1
n-2n
decoder
D0
D1
:
:
Dm-1
m-elements
≤ 2n
 BCD to 7-segment decoder:
 Binary to ASCII.
 Address decoder in a memory:
Example: 4Mbit DRAM
222
No. of memory positions:
N row address bits (ex. 11)
M column addr bit (ex. 11)
into actual memory locations
Row
Decoder
1
BCD
code
decoder
Decoder examples
a
b
c
:
:
g
a
1
MATRIX OF
MEMORY
Row
CELLS
N
2
one cell
N
2 M
1
Column decoder
Write
Control
M
1
Out In
Data
b
2-to-4 line decoder
Table:
A0
A1
0
0
2-4 line 1
Decoder2
1 ?
3
D0
D1
D2
D3
A1 A0
0
0
1
1
0
1
0
1
D0 D1 D2 D3
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Logic expressions:
only one of the
inputs is active
D0 = A1 A0
D1 = A1 A0
D2 = A1 A0
D3 = A1 A0
minterms
2-to-4 Line Decoder circuit
A0
A1
D0 = A1 A0
D1 = A1 A0
D2 = A1 A0
D3 = A1 A0
Notice that the outputs of the decoder
correspond to the minterms: Di=mi
Decoder Expansion
 Larger decoders can be realized by
implementing each minterm using a single
AND gate:
• However for large decoders this requires
multiple input AND gates which is not always
feasible.
• Better to use a hierarchical approach: build
larger ones from smaller decoders.
 Approach:
• Output AND gates have only 2 inputs and
implement the minterms.
• The output AND gates are driven by two
decoders with their numbers of inputs either
equal or differing by 1.
Decoder Expansion - Example 1
 3-to-8-line decoder
• Number of output ANDs = 8
A0
• Number of inputs: 3
A1
A0
A1
2-4
Decoder
D0
A’1A’0
D1
A’1A0
D2 AA0’
D3 A1A0
A2
A’1A’0
A’1A0
2-4
Decoder
A2’A1’A0’
A2’A1’A0
A1’A0
A2’A1A0’
A 1 A0
A2’A1A0
A’2
A2
A2A1’A0’
1-to-2
decoder
3-to-8 decoder
A2A1A0
Further Decoder Expansion of
Example 1
Rule for building large decoders
 k-to-2k decoder:
• One needs 2k output AND gates
• If k can be divided by 2:
 use two k/2-to-2k/2 decoders
• If k cannot divided by 2:
 use a (k+1)/2 and
 use a (k-1)/2 decoder.
 Previous example: 3-to-8 decoder
(k=3):
• Use a 2-to-4 and a 1-to-2 decoder
Example : build a 4-to-16 decoder
 How many 2-input output AND gates?
 Which smaller decoders to use?
 Draw the circuit.
4-to-16 decoder
Use two 2-to-22 decoders
A0
A1
D0
A1’A0’
A1’A0
2-4 D1
Decoder A1A0’
D2
D3
A 1 A0
D0
D1
D2
D3
D4
A3’A2’A1’A0’
A3’A2’A1’A0
A3’A2’A1A0
A3’A2A1’A0’
:
A2
A3
D0 A3’A2’
2-4 D1
Decoder
D2
D3
:
A3’A2
A 3 A2
D14
D15
A3A2A1A0’
A3A2A1A0
Decoder Expansion - Exercise 2
 5-to-32-line decoder
• Number of output ANDs = ?
• Number of inputs to decoders driving output
ANDs = ?
• Which decoders to use to drive the output
ANDs?
• Block diagram:
5-to-32-line decoder
A0
A1
A2
A3
A4
D0
D1
D2
D3
A2’A1’A0’
A2’A1’A0
3-8
Decoder
D7
D3
A4’A3’A2’A1’A0’
A4’A3’A2’A1’A0
D7
D0 A4’A4’
2-4 D1
Decoder
D2
D0
D1
D2
D3
D4
A3’A2
:
A 4 A3
D30
D31
:
A4A3A2A1A0
Decoder Expansion - Example 2
 7-to-128-line decoder
• Number of output ANDs = ?
• Number of inputs to decoders driving
output ANDs = ?
• Closest possible split to equal
Decoder with Enable
 Extra input EN:
 If EN = 1: act as a regular decoder A
0
 If EN=0, all outputs are 0
A1
EN
 See truth table below for function
0
2-4
Decoder
1
D0
D1
D2
D3
Decoder with Enable: circuit
EN
A0
A1
EN
0
2-4
Decoder
1
Extra set
of ands
D0
D1
D2
D3
Regular decoder
If one considers EN an input, in that case the circuit can be viewed
as distributing value of signal EN(=IN) to 1 of 4 outputs: called a
0
demultiplexer:
D0
EN=IN Demux 1
2
1 0
3
A1 A0
D1
D2
D3
Example: Sprinkler System
 Design the sprinkler valve
controller
 Description:
• The system has 8 different zones
• Only one value is on at one time
(to maintain the pressure)
• A microcontroller is used to
control the valves:
 However the processor has
only 4 outputs
 Lets program the
microcontroller to indicate
which of the 8 valves should
be opened, using a binary
representation.
Sprinkler System
 We can use a 3-to-8 decoder with
enable input controlled by the
D0=A2’A1’A0’.EN
microprocessor
Microcontroller
a
A0
b
A1
c
A2
d
0
1
D0
D1
D2
D3
D1=A2’A1’A0.EN
2
3-8
Decoder
D7
EN
When EN=0, all valves are off
D7=A2A1A0.EN
Combinational Logic Implementation
- Decoder and OR Gates
 Implement m functions of n variables
with:
• Sum-of-minterms expressions
• One n-to-2n-line decoder
• m OR gates, one for each output
Example
 Design and implement a majority
function F(ABC) using a 3-to-8
decoder
Indicate MSB, LSB
ABC F
000 0
 Truth table:
0
 Minterms:
• F=m(3,5,6,7)
001
010
011
100
101
110
111
0
0
1
0
1
1
1
A
2
B
1
C
0
1
2
3
4
5
6
7
 Implementation using decoder:
F
Exercise
 Implement the functions using a 3-to-8 decoder:
• F2(ABC)=m (0,2,3,5,6,7)
• F3=AB’ + BC
• F4(ABC)= A + B + C’
• For F2(ABC)=m (0,2,3,5,6,7) implement
F2’=m(1,4): OR and INV= NOR gate with
m1 and m4 as inputs.
• F3= AB’+BC = AB’(C+C’)+BC (A+A’)
= m5 + m4 + m7 + m3
•F4=A+B+C’:
now F4’=A’B’C=m1 Thus F4=m1’ (needs an
inverter);otherwise:
F4=m0+m2+m3+m4+m5+m6+m7
Exercise
Implement the function F using a 2-to-4 decoder
and two tri-state buffers
F=C(AB+A’B’)
Exercise - solution
Implement the function F using a 2-to-4 decoder
and two tri-state buffers
F=C(AB+A’B’) = ABC + A’B’C
B
1
C
0
0
1
2
3
B’C
BC
A
F
Exercise
Can you also implement F using a 2-to-4 decoder
with enable input and an OR gate?
F=C(AB+A’B’)
Exercise - solution
1. Using a 2-to-4 decoder with enable input and
an OR gate:
F=C(AB+A’B’) = ABC + A’B’C
EN
A
1
B
0
0
1
2
3
EN
C
A’B’
F
AB
Exercise
Can you also implement F using a 2-to-4 decoder
with enable input and an NOR gate?
F=C(AB+A’B’)
3-8 Encoding
m-elements
≤ 2n
D0
D1
:
:
Dm-1
encoder
encoding
m elements
A0
n output
:
bits
:
An-1
n-bit binary code
decoding
n bits
A0
:
:
An-1
2-to-4
decoder
D0
D1
:
:
Dm-1
m-elements
≤ 2n
Encoding
 Typically, an encoder converts a code
containing exactly one bit that is 1 to a binary
code corresponding to the position in which the
1 appears: ex. D1=1  output 0001
D0
D1
:
:
Dm-1
0
1
2
3
m-1
0
encoder
0
1
0
0
0
1
2
n-1
A0
:
:
An-1
1
0
0
0
 Examples: Octal-to-Binary encoder
 Other examples?
Example: A decimal-to-BCD encoder
1
2
3
4
5
6
7
8
9
0
D9
D8
D7
3
A3
2
A2
encoder
A1
9
8
7
6
1
A0
D0
0
0
 A decimal-to-BCD encoder
• Inputs: 10 bits corresponding to decimal digits
0 through 9, (D0, …, D9)
• Outputs: 4 bits with BCD codes
• Function: If input bit Di is a 1, then the output
(A3, A2, A1, A0) is the BCD code for i,
Truth table of the decimal-to-BCD
encoder
D9
0
0
0
0
0
0
0
0
0
1
D8
0
0
0
0
0
0
0
0
1
0
D7
0
0
0
0
0
0
0
1
0
0
From table:
D6
0
0
0
0
0
0
1
0
0
0
D5
0
0
0
0
0
1
0
0
0
0
D4
0
0
0
0
1
0
0
0
0
0
D3
0
0
0
1
0
0
0
0
0
0
D2
0
0
1
0
0
0
0
0
0
0
D1
0
1
0
0
0
0
0
0
0
0
D0
1
0
0
0
0
0
0
0
0
0
A3 = D8 + D9
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7 + D9
A3 A2 A1 A0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
the fact that only
one input can be
“1” at one time
Priority Encoder
D0
0
1
D1
1
D2
2
?
0
D3
A1
A0
3
V
To
processor
 If more than one input value is 1, then the encoder
just designed does not work.
 An encoder that can accept all possible
combinations of input values and produce a
meaningful result is a priority encoder.
 Among the 1s that appear, it selects the most
significant input position (or the least significant
input position) containing a 1 and responds with
the corresponding binary code for that position.
Priority Encoder Example
 Priority encoder with 5 inputs (D4, D3, D2, D1, D0) - highest priority
is given to most significant 1 present - Code outputs A2, A1, A0
and V where V indicates at least one 1 present.
No. of Minterms/Row
1
1
2
4
8
16
Outputs
Inputs
D4
D3 D2
0 0
0 0
0 0
0 0
0 1
1 X
0
0
0
1
X
X
D1
D0
A2
A1
A0
V
0
0
1
X
X
X
0
1
X
0
0
0
0
1
X
0
0
1
1
0
X
0
1
0
1
0
0
1
1
1
1
1
0
X
0
1
1
X
X
X
Priority Encoder Example (continued)
One can use a K-map
to get equations, but
from table and
manually optimized if
careful:
A2 = D4
A1 = D4 D3 + D4D3 D2 = D4 F1, F1 = (D3 + D2)
A0 =
V=
Exercise: design a 4 input priority
encoder with active low inputs
Table:
D0
0
1
D1
1
D2
2
D3 D2 D1 D0 A1 A0 V
A0
1
1
1
1
0
?
0
D3
A1
3
V
1
1
1
0
x
1 1
1 0
0 x
x x
x x
Expressions:
A1 = D3.D2’ + D3’ = D2’ + D3’
A0 = D3D2D1’ + D3’ = D2.D1’ + D3’
V = (D3.D2.D1.D0)’
x
0
0
1
1
x 0
0 1
1 1
0 1
1 1
3-9 Selecting (multiplexers)
 Selecting of data or information is a critical
function in digital systems and computers
 Circuits that perform selecting have:
• A set of n information inputs from which the selection is
• A set of k control (select) lines for making the selection
I0
• A single output
0
n ≤ 2k inputs
I1
I2
I3
1
2
3
:
:
In-1
n-1
OUT
k-1 .. 1 0
Sk-1..S1 S0
k select lines
Multiplexer equivalent
I0
I1
I2
I3
0
1
2
3
Out
1 0
S1
S0
(Ref.: F. Vahid, “Digital Design”, J. Wiley, 2007)
Many uses of multiplexers
 In computers to select among signals
X
 To implement command:
Y
if A=0 then Z=XY
else Z=XY
0
Z
1
A
 Trip controller in a car to display mileage,
time, speed, etc.
clock
odometer
speed
mileage
0
1 4:1
2
3
1 0
S1
(F. Vahid)
Display
S0
Push button
Example of a 4-input MUX
 4 inputs mux requires 2 select lines:
I0
I1
I2
I3
0
1
2 4:1
3
1 0
S1
Out
S0
Table (condensed truth table):
I0
I1
I2
I3
0
1
2
3
S1 S0
S1 S0 OUT
0 0
I0
0 1
I1
1 0
I2
1 1
I3
Out
4:1 MUX realization
 Expression for OUT
OUT = S1S0 I0+ S1S0 I1+ S1S0 I2+ S1S0 I3
m0
m1
m2
m3
S1 S0 OUT
0 0
I0
0 1
I1
1 0
I2
1 1
I3
2k-1
or OUT = Σ mi Ii
i=0
 Circuit implementation: SOP
• 4 AND gates (4 product terms)
• 2-to-4 line decoder (to generate the
minterms)
Example: 4-to-1-line Multiplexer
 2-to-22-line decoder
 22 x 2 AND-OR
Decoder
Decoder
S1
S0
S1
S0
Decoder
4 3 2 AND-OR
m0
I0
m1
I1
m2
I2
m3
Gate input cost: 22
I3
Y
Y
 Quad refers to the fact that each
input consists of a 4-bit wide signal
(vector)
I0[3:0]
I1[3:0]
I2[3:0]
I3[3:0]
4
0
1
2 4:1
3
1 0
S1
4
Out [3:0]
S0
Single inputs for the select signals
Exercise
 Build a 8:1 MUX using two 4:1 and one 2:1 muxes
I0
I1
I2
I3
I4
I5
I6
I7
0
1
2 4:1
3
1 0
0
S1
1
S0
0
1
2 4:1
3
1 0
S1
S0
OUT
S2
Ex: S2S1S0=110 : select I6
Exercise
A student was working late and get confused. He designed the following 8-to-1
MUX but did not label the inputs. Can you do so?
S2S1S0
S1
S2
out
000
010
100
110
001
011
101
111
Next, rewire the circuit so that we have a regular 8-1 MUX whose
inputs corresponds to the selection code A2A1A0
Exercise
A student was working late and get confused. He designed the following 8-to-1
MUX but did not label the inputs. Can you do so?
S2S1S0
S1
1
3
5
7
S2
000
010
100
110
001
011
101
111
0
2
4
6
1
3
5
7
Accesses I0
Accesses I2
Accesses I1
Accesses I3
Accesses I0
Accesses I1
Accesses I2
Accesses I3
Next, rewire the circuit so that we have a regular 8-1 MUX whose
inputs corresponds to the selection code A2A1A0
Top 4-1 mux Bottom 4-1 mux
0
2
4
6
Multiplexer-based combinational circuits
realization- Approach 1
 A mux can be easily used to implement a
function defined by a truth table (lookup table)
 Indeed the output F of a mux is equal to:
2k-1
F = Σ mi Ii
Example
i=0
Give the input Ii the
value of 0 or 1
as shown in the truth table
0
1
1
0
0
1
2 4:1
3
1 0
A
B
F
A
0
0
1
1
B OUT =F
0
I0
0 m0
1
I1
1 m1
0
I2
1 m2
1
I3
0 m3
F= Σm(1,2)
Example: Gray to Binary Code
Gray
 Design a circuit to
ABC
convert a 3-bit Gray
000
code to a binary code
100
110
 The formulation gives
010
the truth table on the
011
111
right
101
 It is obvious from this
001
table that X = C and the
Y and Z are more complex
Binary
xyz
000
001
010
011
100
101
110
111
Gray to Binary (continued)
 Rearrange the table so
that the input combinations
are in counting order
 Functions y and z can
be implemented using
a dual 8-to-1-line
multiplexer by:
Gray
ABC
000
001
010
011
100
101
110
111
Binary
xyz
000
111
011
100
001
110
010
101
• connecting A, B, and C to the multiplexer select inputs
• placing y and z on the two multiplexer outputs
• connecting their respective truth table values to the inputs
Gray to Binary (continued)
Gray
ABC
000
001
010
011
100
101
110
111
Binary
xyz
000
111
011
100
001
110
010
101
0
1
1
0
0
1
1
0
A
B
C
D00
D01
D02
D03
D04
Out
D05
D06
D07
S2
8-to-1
S1
S0 MUX
0
1
1
0
1
0
0
1
Y
A
B
C
D10
D11
D12
D13
D14
Out
D15
D16
D17
S2 8-to-1
S1
S0 MUX
 Note that the multiplexer with fixed inputs is identical
to a ROM with 3-bit addresses and 2-bit data!
Z
Multiplexer-based combinational circuits
- Approach 2
 One can further simplify the
implementation:
 Previous example:
Example
A
0
0
1
1
B OUT F
0
I0
0
1
I1
1
0
I2
1
1
I3
0
B
B
B
0
B
1
F
A
Combinational Logic Implementation
- Multiplexer Approach 2
 Implement any m functions of n + 1
variables by using:
• An m-wide 2n-to-1-line multiplexer
 Design:
• Find the truth table for the functions.
• Based on the values of the first n variables,
separate the truth table rows into pairs
• For each pair and output, define a rudimentary
function of the final variable (0, 1, X, X )
Gray to Binary - Approach 2
 Rearranged the table so that the input combinations are
in counting order.
Gray
ABC
Binary
xyz
000
000
001
111
010
011
011
100
100
001
101
110
110
010
111
101
Rudimentary
Functions of
C for y
Rudimentary
Functions of
C for z
F=C
F=C
F=C
F=C
F=C
F=C
F=C
F=C
Gray to Binary (continued)
 Assign the variables and functions to the multiplexer inputs:
C
C
C
C
C
C
A
B
D00
D01
D02
D03
S1
S0
C
C
C
D10
D11
D12
D13
A
B
S1
S0
C
Out
8-to-1
MUX
Y
Out
Z
8-to-1
MUX
 Note that this approach (Approach 2) reduces the cost by almost
half compared to Approach 1.
Exercise 1 (cont)
 Implement the function
F(A,B,C)=Σm(0,1,2,5) using a 4:1 mux
A
0
0
0
0
1
1
1
0
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
1
1
1
0
0
1
0
0
1
C
C
0
1
C
C
0
0
1
2 4:1
3
1 0
A B
F
Exercise: Controller for rear lights of a
car
 Word description of the problem: Design a
circuit that controls the rear lights of a car:
Left and Right rear lights.
 Assume that is a single lamp in each of the
rear lights.
Example (continued): Specification
 The inputs to the controller are:
Name
LT
RT
EM
BR
BL
Description
Left turn signal: causes blinking of left side light
Right turn signal
Break is applied: both lights are on
Internal signal of 1Hz frequency
 Outputs signals:
Name
Left
Right
Description
Power control for the left rear light
Power control for the right rear light
Example (continued): Specification 2
 The break BR overrides the
emergency EM signal
 The Left turn LR and Right turn RT
overrides the break signals BR.
 Implement the two power control
signals as:
• Minimized SOP
• Decoder with NOR gates
• Multiplexer
Example (cont): Formulation
Left LT BR EM BL
Light 0 0 0 0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Left
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
Right
Light
RT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BR
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
EM
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BL
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Right
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
Example (cont): Mapping (SOP)
LT BR EM BL
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Left
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
K-map:
Left
LT
EM
0 0
1 0
1 1
1 1
0 1
0 1
1 0
1 0
BR
BL
Left= LT.BL + LT’.BR + EM.BL
Same for Right:
Right= RT.BL + RT’.BR + EM.BL
Example (cont): Encoder with NOR
 Left signal: implement the complement
Left’= m(0,1,2,8,10,12,14)
LT
BR
EM
BL
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Left
Example (cont) 8:1 Multiplexer
LT BR EM BL
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Left
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
BL
1
1
BL
BL
BL
BL
0
BL
1
0
1
2
3
4
5
6
7
2 1 0
LT BR EM
LR
Same for Right Signal
0
BL
1
0
1
2
3
4
5
6
7
2 1 0
RT BR EM
Right
```
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