text:
Solid-state read only memory (ROM)
Subclass of:
711 - Electrical computers and digital processing systems: memory
711101000 - Specific memory composition
Patent class list (only not empty are listed)
Deeper subclasses:
|Class / Patent application number
|Number of patent applications / Date published
|Programmable read only memory (PROM, EEPROM, etc.)
|SYSTEM AND METHOD FOR MANAGING ADDRESS MAPPING INFORMATION DUE TO ABNORMAL POWER EVENTS - A method and apparatus for managing address map information are disclosed. In one embodiment, an apparatus may comprise a processor configured to store address map changes to a first data storage medium, save the address map changes to a nonvolatile data storage medium when an abnormal power state is detected, and when the power state is no longer abnormal retrieve the last saved address map information and address map changes and update the address map information using the address map changes. The apparatus may be configured to retrieve the instructions for the processor operation over a network connection.
|ORDERING A PLURALITY OF WRITE COMMANDS ASSOCIATED WITH A STORAGE DEVICE - A system, method, and computer program product are provided for ordering a plurality of write commands associated with a storage device. In operation, a plurality of write commands associated with a storage device to be sent to a device are identified. Additionally, an order of the plurality of write commands is determined, the determined order being known by the device. Further, the plurality of write commands are ordered in the determined order.
|IMPLEMENTING ENHANCED PERFORMANCE WITH READ BEFORE WRITE TO PHASE CHANGE MEMORY TO AVOID WRITE CANCELLATIONS - A method, apparatus, and storage device are provided for implementing enhanced performance with read before write to phase-change-memory (PCM). Each write to PCM is preceded by a read to avoid write cancellations with urgent reads from nearby locations. For every write, a large block of data is read from PCM, such as an entire partition, prior to the write in PCM. The cache copy of the large block of data is kept in a controller for the duration of write. A read request from the pre-fetched region is provided from the cached copy thereby preventing read interrupt during write operation.
|SYSTEMS AND METHODS FOR SUPPORT OF NON-VOLATILE MEMORY ON A DDR MEMORY CHANNEL - Systems and methods are provided for supporting use of non-volatile memory (NVM) on a double data rate (DDR) memory channel for an information handling system so that non-volatile memory devices (e.g., such as Phase Change Memory "PCM" devices) may be employed for main memory usage. In one possible implementation, information handling system memory reads may be managed directly in hardware as memory semantics via use code, while memory writes may be separately handled, e.g., via an operating system (OS)/driver. In another possible implementation, both DRAM-based and NVM-based memory systems may be populated for an information handling system.
|LBA BLOCKING TABLE FOR SSD CONTROLLER - A host access instruction is received from one of a plurality of channels which are served in parallel. The host access instruction includes an address range of one or more addresses and a type of access. The address range and type of access are compared against a table of stored address ranges and stored types of access associated with any pending host access instructions. It is determined whether to execute the host access instruction based at least in part on the comparison. If it is decided to execute the host access instruction, the host access instruction is forwarded for execution and the address range and the type of access from the host access instruction are stored in the table.
|STORAGE SYSTEM, STORAGE MEDIUM, AND CACHE CONTROL METHOD - A storage system includes a storage that stores a file; and a plurality of access control devices that control access to the storage and include a cache memory in which the file is stored in blocks, wherein when receiving an update request of a prescribed block and latest data of the prescribed block is not stored in the cache memory of a first access control device, the first access control device among the plurality of access control devices obtains a version number added to the latest data from a second access control device, in which the latest data is stored, among the plurality of access control devices, and wherein the first access control device stores update data that updates the prescribed block in the cache memory of the first access control device and adds a new version number to the update data based on the version number.
|STORAGE ERROR MANAGEMENT - A storage controller identifies a storage division comprising unreadable data. In response, the storage controller relocates readable data (if any) from the identified storage division. The storage controller may be further configured to associate the unreadable data with a logical address, and to record persistent metadata to indicate that the logical address is mapped to unreadable, corrupt data. The storage controller may clear the corruption indicator from the logical address. The logical address may be cleared in response to determining that the unreadable data is invalid and/or available from another source.
|Method of Accessing On-Chip Read Only Memory and Computer System Thereof - A method of accessing an on-chip read only memory (ROM) includes dividing a frequency of a system clock by a specific divisor, in order to generate a ROM clock; combining a specific number of adjacent addresses into a combined address, wherein the specific number is determined according to the specific divisor; inserting a first stall signal into a real output data, wherein a length of the first stall signal is determined in order to meet a timing requirement for accessing the on-chip ROM; generating an output data of the on-chip ROM according to the combined address, wherein a width of the output data is extended by a specific multiple which is determined according to the specific number; and generating a first delay corresponding to the length of the first stall signal in the address.
|SYSTEMS AND METHODS FOR MANAGING DATA IN A COMPUTING ENVIRONMENT - Improved data management systems for managing and maintaining unstructured data in a computing system environment. Data content is associated with particular types of metadata to create data objects. In certain examples, the metadata is stored in various fields of the data objects, certain fields being designated as permanently read-only after their creation. Such fields can include, for instance, a unique identifier, a type of content and a classification governing copy permissions relating to the data object. Data objects, or didgets, can be grouped into logical containers referred to as chambers, which are further grouped by common control elements or attributes into domains. Chambers within a particular domain can generally freely share information therebetween, including copies of various types of didgets. A control program, or didget manager, in each domain manages the creation of didgets and subsequent operations directed thereto.
|KEY INJECTION TOOL - A method can include injecting key information from memory of a memory device into non-volatile memory of a hardware device via a data port of the hardware device; receiving via the data port identification information from the hardware device that identifies the hardware device; and associating the key information and the identification information in the memory of the memory device. Various other apparatuses, systems, methods, etc., are also disclosed.
|METHODS AND APPARATUS TO ACCESS DATA IN NON-VOLATILE MEMORY - Example methods, apparatus, and articles of manufacture to access data are disclosed. A disclosed example method involves generating a key-value association table in a non-volatile memory to store physical addresses of a data cache storing data previously retrieved from a data structure. The example method also involves storing recovery metadata in the non-volatile memory. The recovery metadata includes a first address of the key-value association table in the non-volatile memory. In addition, following a re-boot process, the locations of the key-value association table and the data cache are retrieved using the recovery metadata without needing to access the data structure to re-generate the key-value association table and the data cache.
|SYNCHRONOUS WIRED-OR ACK STATUS FOR MEMORY WITH VARIABLE WRITE LATENCY - A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.
|INTERFACE MANAGEMENT CONTROL SYSTEMS AND METHODS FOR NON-VOLATILE SEMICONDUCTOR MEMORY - A control system includes a control module configured to control data transfer events of blocks of data between an interface management module and a non-volatile semiconductor memory based on at least two descriptors for each one of the data transfer events. The non-volatile semiconductor memory is prepared for a read event or a program event of the data transfer event. The interface management module and the non-volatile semiconductor memory are configured to operate within a solid-state memory drive. A command management module is configured to generate a parameter signal based on the at least two descriptors. The interface management module is configured to generate instruction signals based on the parameter signal and transmit the instruction signals to the non-volatile semiconductor memory to perform the read event or the program event.
|MECHANICAL SHOCK MITIGATION FOR DATA STORAGE - A device adapted to capture vehicle data or surveillance data that includes a disk and a Non-Volatile Solid-State Memory (NVSM). The vehicle or surveillance data is received in a buffer of the device for storage on the disk, and an input is received indicating a level of mechanical shock. It is determined whether the input indicates the level of mechanical shock exceeds a first threshold indicative of an impact. If the input indicates the level of mechanical shock exceeds the first threshold, the vehicle or surveillance data is stored in the NVSM from the buffer and a status is determined for storing data on the disk.
|CONTACTLESS IC MEMORY ON REMOVEABLE MEDIA - Method, system, and computer program product embodiments for recording data on a contactless integrated circuit (IC) memory associated with a data storage cartridge are provided. In one exemplary embodiment, a consistency is verified between a TOC written to a contactless IC memory and an index, wherein if the TOC and the index are inconsistent, a TOC profile file is refreshed with data from the index. The TOC is written to the contactless IC memory.
|Accessing a Serial Number of a Removable Non-Volatile Memory Device - A removable non-volatile memory device durably stores a serial number or identifier, which is used to mark multimedia content legally stored on the removable non-volatile memory device. In order to retrieve the serial number, a host electronic system coupled to the removable non-volatile memory device sends a sequence of multiple file access commands to access a predefined target file stored on the removable non-volatile memory device. In accordance with the executed predefined sequence of multiple file access commands, a corresponding sequence of data access commands are received at the removable non-volatile memory device and are interpreted as a request by the host electronic device to read the serial number. The removable non-volatile memory device outputs the serial number in response to the sequence of data access commands.
|SYSTEM AND METHOD FOR MANAGING EXPANSION READ-ONLY MEMORY AND MANAGEMENT HOST THEREOF - A system and a method for managing an expansion read-only memory (ROM), and a management host thereof are provided. The management host is connected with a computer host through a bridge. The management host establishes an address lookup table to assign a virtual function and an expansion ROM corresponding to the virtual function. When a request is issued by the computer host to obtain a size of the expansion ROM, the management host provides data in a shadow register block corresponding to the expansion ROM to the computer host according to the address lookup table. The computer host assigns a memory block in the computer host to the expansion ROM according to the data in the shadow register block. When another request is issued by the computer host to obtain data of the expansion ROM, the management host provides the data of the expansion ROM to the computer host.
|MEMORY ACCESS CONTROL - An apparatus comprising: a memory having at least two sections; a security element associated with at least one of said at least two sections; and a processor for controlling access to at least one of the at least two sections of the memory in dependence on a value of the security element. The apparatus may be an integrated circuit and the memory may be a read-only-memory storing generic code in one of the sections and code specific to a mobile communication device provider in the second section. The security element may be a permanently programmed memory element programmed by the IC manufacturer.
|Semiconductor Device - Provided is a user-friendly information processing system which is capable of maintaining latency within a fixed range and ensuring the expandability of a memory capacity at high speed and low cost. The information processing system, including an information processing device, a volatile memory, and nonvolatile memories, is configured. The information processing device, the volatile memory, and the nonvolatile memories are connected in series with one another to reduce the number of connection signals, thereby realizing speeding-up while maintaining the expandability of the memory capacity. The information processing device manages response time zones and time zones where responses overlap one another, and performs a correction operation on the latency, thereby realizing fast data transfer while maintaining the latency within the fixed range. The information processing device performs an error correction to improve the reliability when transferring the data of the nonvolatile memories to the volatile memory. The information processing system composed of a plurality of chips is configured as an information processing system/module in which the respective chips are arranged in layers, and wired together by a through via.
|RECOVERABILITY WHILE ADDING STORAGE TO A REDIRECT-ON-WRITE STORAGE POOL - Embodiments include a method comprising detecting addition of a new nonvolatile machine-readable medium to a data storage pool of nonvolatile machine-readable media. The method includes preventing from being performed a first operation of a file system that requires a first parameter that identifies a logical indication of a location within the nonvolatile machine-readable media for the file system, until logical indications of locations within the new nonvolatile machine-readable medium for the file system have been stored in the data storage pool. The method includes allowing to be performed, prior to logical indications of locations within the new nonvolatile machine-readable medium being stored in the data storage pool, a second operation of the file system that does not require a second parameter that identifies a logical indication of a location within the nonvolatile machine-readable media, wherein the second operation causes data to be written into the new nonvolatile machine-readable medium.
|Data Storage Devices Including Multiple Host Interfaces and User Devices Including the Same - Disclosed is an information storing device which includes a first interface for connection with a host; a second interface for connection with the host; a first memory unit including a first controller controlling a first nonvolatile memory, the first controller communicating with the host via the first interface; and a second memory unit including a second controller controlling a second nonvolatile memory, the second controller communicating with the host via the second interface.
|SYSTEMS AND METHODS FOR OUT-OF-BAND BACKUP AND RESTORE OF HARDWARE PROFILE INFORMATION - Systems and methods are provided that may be implemented for out-of-band backup and/or restore of information handling system components. Such out-of-band backup and restore operations may be performed, in one embodiment, to backup and/or restore hardware profile information such as firmware images and corresponding system configuration information.
|MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME - A method for operating a memory controller is disclosed. The method includes receiving data output from a memory block of a non-volatile memory device and changing erase count of the memory block based on the received data.
|METHOD AND APPARATUS FOR PERFORMING MEMORY WEAR-LEVELING USING PASSIVE VARIABLE RESISTIVE MEMORY WRITE COUNTERS - Method and apparatus for performing wear-leveling using passive variable resistive memory (PVRM) based write counters are provided. In one example, a method for performing wear-leveling using passive PVRM based write counters is disclosed. The method includes associating a logical address of a memory array with a physical address of the memory array via at least one mapping table. Additionally, the method includes, in response to writing to the physical address of the memory array, incrementally updating at least one PVRM based write counter associated with the physical address of the memory array. The at least one PVRM based write counter may be incrementally updated by varying an amount of resistance stored in the at least one PVRM based write counter.
|SPI ROM WITH BUILT-IN MASK ROM FOR BIOS - A serial peripheral interface (SPI) includes a mask read only memory (ROM). The mask ROM stores a basic input/output system (BIOS) boot block so that the BIOS boot block is protected from being compromised.
|MEMORY SYSTEM INCLUDING NON-VOLATILE STORAGE MEDIA, COMPUTING SYSTEM INCLUDING MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM - In one aspect, meta data corresponding to a non-volatile storage media is read from the non-volatile storage media. Meta data to be updated is detected from the read meta data. Based on the read meta data and the detected meta data to be updated, storage areas of the non-volatile storage media are invalidated.
|Tamper-Resistant Memory Device With Variable Data Transmission Rate - A high capacity, secure and tamper-resistant computer data memory device. The device uses a plurality of dedicated memory controller elements in communication with an anti-tamper module that generates a tamper response when a predetermined tamper event occurs. The tamper response may be provided as the erasure or zeroization of the contents of a memory in the devices such as erasing one or more encryption keys. The elements of the device are preferably provided in a stacked configuration with rerouted I/O pads to obfuscate the I/O and function of the devices in the stack. In one embodiment, a data transfer governance means is provided. In a further embodiment, a current negotiation means is disclosed to permit the device to request a predetermined current from a host device. In a yet further embodiment, a portable safe house computing device is provided.
|CACHE MEMORY FOR HYBRID DISK DRIVES - A method for data storage in a data storage system, which includes a main storage device and a non-volatile memory, includes assessing quality levels of respective memory blocks of the non-volatile memory. One or more of the memory blocks whose assessed quality levels are lower than a predefined quality threshold are identified. The identified memory blocks are assigned to serve as read cache memory. Data is read from the main storage device via the read cache memory, including the assigned memory blocks.
|MEMORY MODULE VIRTUALIZATION - A memory system having a plurality of modules operated so that a group of memory modules may operation in a RAID configuration having an erase hiding property. The RAID groups are mapped to areas of memory in each of the memory modules of the RAID group. More than one RAID group may be mapped to a memory module and the erase operations of the RAID groups coordinated such that the erase operations do not overlap. This may improve the utilization of a bus over which the memory module communicates with the controller. Where a memory module is replaced by a memory module having an increased storage capacity, the additional storage capacity may be mapped to an expanded logical address space.
|PAGE REPLACEMENT METHOD AND MEMORY SYSTEM USING THE SAME - A memory system includes a central processing unit (CPU), a nonvolatile memory electrically coupled to the CPU and a main memory, which is configured to swap an incoming code page for a target code page therein, in response to a first command issued by the CPU. The main memory can be configured to swap the target code page in the main memory to the nonvolatile memory in the event a page capacity of the main memory is at a threshold capacity. The CPU may also be configured to perform a frequency of use analysis on the target code page to determine whether the target code page is to be swapped to the nonvolatile memory or discarded. The incoming code page may be provided by a disk drive storage device and the main memory may be a volatile memory.
|Secure Boot ROM Emulation - Secure boot ROM emulation with locking storage device. A locking storage device is provided by combining a nonvolatile memory device such as flash or EEPROM with one-shot locking logic which write enables at least a portion of the nonvolatile memory device upon power cycling of the overall digital device. This write enable is cleared during the stage 1 bootloader process, thus providing a protected update interval for updating a stage 2 bootloader once per power cycle.
|MULTIVERSIONED NONVOLATILE MEMORY HIERARCHY FOR PERSISTENT MEMORY - Example methods and systems to provide persistent memory are disclosed herein. An example system includes a nonvolatile cache to store data received from a volatile cache. The data is associated with a transaction and the data is to be identified as durable when the transaction is committed. The example system includes a nonvolatile memory to store the data received from the nonvolatile cache when the data is identified as durable.
|Storage Module and Method for Virtual Abort - A storage module and method for virtual abort are disclosed. In one embodiment, a virtual abort of a read command is provided. The read command triggers a read operation that comprises reading data from the storage module's memory, processing the data by at least one processing module as the data moves along a data path from the memory to the storage module's host interface module, and then providing the data to a host via the host interface module. When an abort command is received, the storage module allows the data that is read from the memory to be processed by the at least one processing module as the data moves along the data path to the host interface module but prevents the host interface module from providing the data to the host. In another embodiment, a virtual abort of a write command is provided.
|Method for field-programming a solid-state memory device with a digital media file - The preferred embodiments described herein provide a method for field-programming a solid-state memory device with a digital media file. In one preferred embodiment, a solid-state memory device is provided that comprises a memory array comprising a plurality of field-programmable memory cells. A digital media file is selected for storage in the memory device, and a digital media source field-programs the memory cells of the memory device with the selected digital media file. After the digital media file is stored in the memory device, the stored digital media file can be played using a digital playback device. In some embodiments, the memory array is a three-dimensional memory array, and the memory cells are write-once memory cells. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
|Managing the Write Performance of an Asymmetric Memory System - Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.
|WRITING MEMORY BLOCKS USING CODEWORDS - A generator matrix is provided to generate codewords from messages of write operations. Rather than generate a codeword using the entire generator matrix, some number of bits of the codeword are determined to be, or designated as, stuck bits. One or more submatrices of the generator matrix are determined based on the columns of the generator matrix that correspond to the stuck bits. The submatrices are used to generate the codeword from the message, and only the bits of the codeword that are not the stuck bits are written to a memory block. By designating one or more bits as stuck bits, the operating life of the bits is increased. Some of the submatrices of the generator matrix may be pre-computed for different stuck bit combinations. The pre-computed submatrices may be used to generate the codewords, thereby increasing the performance of write operations.
|OPTIMIZATION OF NON-VOLATILE MEMORY IN MESSAGE QUEUING - Embodiments of the invention provide for the optimization of utilization of non-volatile memory in message queuing. In an embodiment of the invention, a method for optimizing utilization of non-volatile memory in message queuing includes receiving a new message in a message queueing system implemented in a host computing system. The method also includes storing the new message as a master message in non-volatile memory of the host computing system. The method yet further includes subsequently receiving different messages that each share redundant information with the master message. The method even yet further includes delta encoding each of the different messages and storing the delta encoded different messages in the non-volatile memory. Finally, the method includes deleting the master message from the non-volatile memory only once each of the different messages and the master message have been acknowledged by at least one consumer subscribing to the message queuing system.
|Apparatus, System, and Method for Managing Contents of a Cache - Apparatuses, systems, and methods are disclosed for managing contents of a cache. A method includes receiving a read request for data stored in a non-volatile cache. A method includes determining whether a read request satisfies a frequent read threshold for a cache. A method includes writing data of a read request forward on a sequential log-based writing structure of a cache in response to determining that the read request satisfies a frequent read threshold.
|Devices, Systems and Methods for Time-Sensitive Data and Limited-Persistent Storage - Devices, systems, and methods are disclosed which relate to devices utilizing time-sensitive memory storage. The time-sensitive memory storage acts as normal device memory, allowing the user of the device to store files or other data to it; however the information stored on the time-sensitive memory storage is automatically erased, based on some storage time period. A limited amount of persistent storage is used for names and message headers.
|SYSTEM AND METHOD FOR UPDATING A BASIC INPUT/OUTPUT SYSTEM (BIOS) - There is provided a system and method for updating a basic input output system (BIOS). An exemplary method comprises obtaining a BIOS update package comprising a BIOS image update, a BIOS Signature, and a plurality of Public Key regions, wherein each Public Key region comprises a Public Key area and a signature area. The exemplary method also comprises updating a current Public Key with a new Public Key if the new Public Key is identified in one of the Public Key regions. The exemplary method additionally comprises validating the BIOS Signature using the current Public Key.
|SYSTEM AND METHOD FOR PROVIDING CONSISTENT, RELIABLE, AND PREDICTABLE PERFORMANCE IN A STORAGE DEVICE - The solution described here is a method to provide consistent performance in a storage device. A performance manager module is implemented to measure the time interval in which a command takes to be completed. In case the time interval is longer than a certain threshold, the difference is annotated and used on the consecutive commands within a programmable time window. This time window can be a regular time interval e.g. every second. In case the time interval is shorter than a threshold, the control module delays sending the command completion to the host until the threshold value is reached. The delay is adjusted based on the credit annotation due to commands that took longer than the time interval to be completed in order to compensate for commands that took longer than the threshold to complete, during a certain time window.
|REDUNDANCY FOR CODE IN ROM - A memory device capable of replacing code in read-only memory (ROM) by using a ROM redundancy register is disclosed. The memory device includes a controller that accesses code in ROM by use of a ROM address. The memory device further includes a ROM redundancy register capable of storing one or more ROM addresses and storing code corresponding to the one or more ROM addresses. The one or more ROM addresses may represent address locations in ROM that need code replacement. The ROM redundancy register may determine whether code corresponding to the ROM address should be replaced by code stored in the ROM redundancy register.
|Priority Based Backup in Nonvolatile Logic Arrays - A processing device selectively backups only certain data based on a priority or binning structure. In one approach, a non-volatile logic controller stores the machine state by storing in non-volatile logic element arrays a portion of data representing the machine state less than all the data of the machine state. Accordingly, the non-volatile logic controller stores the machine state in the plurality of non-volatile logic element arrays by storing a first set of program data of the machine state according to a first category for backup and restoration and storing a second set of program data of the machine state according to a second category for backup and restoration.
|FUZZY COUNTERS FOR NVS TO REDUCE LOCK CONTENTION - A system for data management in a computing storage environment includes a processor device, operable in the computing storage environment, that divides a plurality of counters tracking write and discard storage operations through Non Volatile Storage (NVS) space into first, accurate, and second, fuzzy, groups where the first, accurate, group is one of incremented and decremented per each write and discard storage operation, while the second, fuzzy, group is one of incremented and decremented on a more infrequent basis as compared to the first, accurate group.
|SWITCH MODULE BASED NON-VOLATILE MEMORY IN A SERVER - A switch module having shared memory that is allocated to other blade servers. A memory controller partitions and enables access to partitions of the shared memory by requesting blade servers.
|CACHING TECHNOLOGIES EMPLOYING DATA COMPRESSION - Caching technologies that employ data compression are described. The technologies of the present disclosure include cache systems, methods, and computer readable media in which data in a cache line is compressed prior to being written to cache memory. In some embodiments the technologies enable a caching controller to understand the degree to which data in a cache line is compressed, prior to writing the compressed data to cache memory. Consequently the cache controller may determine where the compressed data is to be stored in cache memory based at least in part on the size of the compressed data, a compression ratio attributable to the compressed data (or its corresponding input data), or a combination thereof.
|DOORBELL-LESS ENDPOINT-INITIATED PROTOCOL FOR STORAGE DEVICES - The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.
|METHOD OF IN-MEMORY MODIFICATION OF A DATA SET - The present invention relates to the field of the management of memory writes to an information processing device and more precisely to a method of writing a set of data in a unitary and coherent manner. The invention, although of more general scope, applies more particularly in the field of chip cards.
|INTEGRATED STORAGE DEVICE AND CONTROL METHOD THEREOF - An integrated storage device and a control method thereof are provided. The integrated storage device includes an interface controller, a microcontroller, a plurality of non-volatile storage devices, and a channel link controller. The interface controller retrieves a master control signal and a slave control signal sent by a motherboard. The microcontroller generates a selecting signal. The non-volatile storage devices have at least two storage types. The non-volatile storage devices are divided into a first group of storage device and a second group of storage device according to the selecting signal. The channel link controller respectively controls the first group of storage device and the second group of storage device according to the master control signal and the slave control signal. Thereby, the accessing efficiency of the integrated storage device is increased.
|MEMORY SYSTEM AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.
|System and Method for Providing Instant Video in an Information Handling System - Before initializing a memory of an information handling system, a method includes loading an image of a video option ROM code for a graphics interface device to a cache associated with a processor of the information handling system, and executing the video option ROM code to initialize the graphics interface device. The method also includes executing a memory reference code to initialize the memory, and while executing the memory reference code, providing status information from the graphics interface device.
|ADMINISTERING THERMAL DISTRIBUTION AMONG MEMORY MODULES OF A COMPUTING SYSTEM - A computing system includes a number of memory modules and temperature sensors. Each temperature sensor measures a temperature of a memory module. In such a computing system a garbage collector during garbage collection, determines whether a temperature measurement of a temperature sensor indicates that a memory module is overheated and, if a temperature measurement of a temperature sensor indicates a memory module is overheated, the garbage collector reallocates one or more active memory regions on the overheated memory module to a non-overheated memory module. Reallocating the active memory regions includes copying contents of the active memory regions from the overheated memory module to the non-overheated memory module.
|STORAGE DEVICE AND USER DEVICE INCLUDING THE SAME - A storage device includes a host interface, a buffer memory, a storage medium, and a controller. The host interface is configured to receive storage data and an invalidation command, where the invalidation command is indicative of invalid data among the storage data received by the host interface. The buffer memory is configured to temporarily store the storage data received by the host interface. The controller is configured to execute a transcribe operation in which the storage data temporarily stored in the buffer memory is selectively stored in the storage medium. Further, the controller is responsive to receipt of the invalidation command to execute a logging process when a memory capacity of the invalid data indicated by the invalidation command is equal to or greater than a reference capacity.
|COPY-PROTECTED SOFTWARE CARTRIDGE - A cartridge preferably for use with a game console. The cartridge comprises a ROM, a non-volatile memory, a processor and a dispatcher. An application running on the console may communicate with the dispatcher using predefined addresses, which enables the dispatcher to access the ROM, the non-volatile memory, or the processor, as the case may be. The invention improves on the prior art copy protection as no generic copy method may be found if the addresses are changed from one cartridge to another. In addition, to copy the software, the processor must be emulated.
|TECHNIQUES FOR SELECTING AMOUNTS OF OVER-PROVISIONING - A cost function is obtained where an amount of over-provisioning associated with solid state storage is an input of the cost function and a cost for a given amount of over-provisioning is an output of the cost function. An amount of over-provisioning is determined using the cost function and the amount of over-provisioning for the solid state storage is set to be the determined amount.
|TRANSFER OF OBJECT MEMORY REFERENCES IN A DATA STORAGE DEVICE - Herein are data storage devices to transfer a reference of a data object during a storage operation. These data storage devices include a host controller configured to obtain a reference of an object stored in a shared memory system for writing to a storage media controlled by a drive controller. To the drive controller, the host controller transfers the reference of the object in the memory system. The host controller transfers a storage command to the drive controller to write the object to the storage media. The drive controller may be configured to transfer a reference of an object read into the memory system.
|RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY - Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.
|STORAGE SYSTEM COMPRISING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, AND STORAGE CONTROL METHOD - A higher-level system of a nonvolatile semiconductor storage device (hereinafter, semiconductor device) displays a GUI (Graphical User Interface), which receives a parameter group (one or more parameters) for controlling the processing of the semiconductor device. The higher-level system stores at least one of the parameters of the parameter group inputted to the GUI, and sends a command comprising the parameter group to the semiconductor device. The semiconductor device stores at least one of the parameters of the parameter group included in this command. The higher-level system and the semiconductor device each execute processing in accordance with the stored parameter. The semiconductor device sends, to the higher-level system, information of a log related to the processing executed in accordance with the stored parameter. The higher-level system displays feedback information on the basis of multiple times of logs. A user can change a desired parameter on the basis of this feedback information.
|MEDIA WRITE OPERATION - A method or system comprises determining an end data track of a write operation in response to a request for the write operation in a media storage device, saving data from an adjacent track following the end data track to a cache, performing the write operation. In one implementation, performing the write operation is comprises writing data to a plurality of data tracks in a band.
|METHOD AND DEVICES FOR CONTROLLING POWER LOSS - Described herein are methods and devices for controlling power loss. For one embodiment, a method includes issuing a controlled power off command with a controller. The method includes determining whether a memory device is performing a background operation. The method includes safely suspending the background operation or completing the background operation if the memory device is performing the background operation. The method includes safely removing a supply power.
|MEMORY SYSTEM CAPABLE OF CONTROLLING WIRELESS COMMUNICATION FUNCTION - According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, controller, memory, wireless communication function section, and extension register. The controller controls the nonvolatile semiconductor memory device. The memory is serving as a work area of the controller. The wireless communication module has a wireless communication function. The extension register is provided in the memory. The controller processes a first command to read data from the extension register, and a second command to write data to the extension register. The extension register records, an information specifying the type of the wireless communication function in a specific page, and an address information indicating a region on the extension register to which the wireless communication function is assigned.
|COMPUTER SYSTEM HAVING NON-VOLATILE MEMORY AND METHOD OF OPERATING THE COMPUTER SYSTEM - A computer system includes a central processing unit (CPU), a main memory including a non-volatile memory, and a memory reset controller controlling the main memory. If a memory reset command is input from outside, while the computer system is powered on/off, the memory reset controller deletes data stored in the main memory.
|3D MEMORY WITH VERTICAL BIT LINES AND STAIRCASE WORD LINES AND VERTICAL SWITCHES AND METHODS THEREOF - A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.
|VARIABILITY AWARE WEAR LEVELING - Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products.
|MANAGEMENT OF SERVER CACHE STORAGE SPACE - An application server can be configured to access data stored on a networked storage server that is accessible over a network and that includes a cache device configured to store data received from the networked storage server. The application server can include a cache management module that is designed to monitor a data access requests transmitted over the network, the data access requests specifying a first page of data. In response to an indication that the requested data includes data stored in the cache device as an existing page of data, the first page of data can be mapped to a location corresponding to the existing page.
|CIRCUIT ARRANGEMENT AND METHOD FOR DATA PROCESSING - In order to further develop a circuit arrangement (
|MAINTAINING A SECURE PROCESSING ENVIRONMENT ACROSS POWER CYCLES - Embodiments of an invention for maintaining a secure processing environment across power cycles are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to evict a root version array page entry from a secure cache. The execution unit is to execute the instruction. Execution of the instruction includes generating a blob to contain information to maintain a secure processing environment across a power cycle and storing the blob in a non-volatile memory.
|OPTIMIZATION OF NON-VOLATILE MEMORY IN MESSAGE QUEUING - Embodiments of the invention provide for the optimization of utilization of non-volatile memory in message queuing. In an embodiment of the invention, a method for optimizing utilization of non-volatile memory in message queuing includes receiving a new message in a message queueing system implemented in a host computing system. The method also includes storing the new message as a master message in non-volatile memory of the host computing system. The method yet further includes subsequently receiving different messages that each share redundant information with the master message. The method even yet further includes delta encoding each of the different messages and storing the delta encoded different messages in the non-volatile memory. Finally, the method includes deleting the master message from the non-volatile memory only once each of the different messages and the master message have been acknowledged by at least one consumer subscribing to the message queuing system.
|IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH PARITY UPDATE FOOTPRINT MIRRORING - A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations.
|METHODS OF STORING DATA IN STORAGE MEDIA, DATA STORAGE DEVICES USING THE SAME, AND SYSTEMS INCLUDING THE SAME - A method of storing data in a storage media can include determining whether a size of data to be stored in the storage media satisfies a reference condition and compressing the data to provide compressed data for storage in the storage media upon determining that the size satisfies a reference condition.
|DYNAMIC ASSIGNMENT OF TRANSFERS OF BLOCKS OF DATA - A computer-program causing a computing device to transmit, from a data transfer thread of a multitude of data transfer threads executed within a data storage cluster and to a distribution thread at a network address on a network, a request for an assignment of an exchange of data with at least one computation thread of a multitude of computation threads executed within a data processing cluster; exchange a block of data with a single computation thread of the multitude of computation threads in response to receipt of an assignment to exchange the block of data with the single computation thread; and exchange multiple blocks of data with multiple computation threads of the multitude of computation threads in a round robin manner among the multiple computation threads in response to receipt of an assignment to exchange the multiple blocks of data with the multiple computation threads.
|MEMORY MANAGING DEVICE AND METHOD AND ELECTRONIC APPARATUS - A memory managing device and method and an electronic apparatus are provided. The memory managing device is applied to a memory having a plurality of storage regions capable of being separated physically, comprising: a storage detecting unit for detecting the current storage status of the memory; a block computing unit for computing the current active block in the memory; a discreteness deciding unit for deciding whether the discreteness of a segment in the memory is larger than a predetermined threshold; a segment arranging unit for arranging the segment when the discreteness is larger than the predetermined threshold to move the active block to a set of storage regions whose number of the storage regions is less than that before the movement; and a power consumption setting unit for setting the storage regions other than the set of the storage regions in the memory to a low power consumption status. With the memory managing device and method and electronic apparatus according to the embodiment of this application, all of the active blocks in the memory can be concentrated into less physical storage regions so that the power consumption of the memory can be reduced while the efficiency of the usage of the memory can be increased.
|METHOD OF STORING DATA IN STORAGE MEDIA, DATA STORAGE DEVICE USING THE SAME, AND SYSTEM INCLUDING THE SAME - A method of storing data in a storage media is provided which includes sequentially compressing data by a compression unit, and storing the compressed data in the storage media, the compression unit being varied according to a compression characteristic of data to be stored in the storage media.
|SYSTEMS AND METHODS FOR REFERENCING DATA ON A STORAGE MEDIUM - A storage layer is configured to store data at respective offsets within storage units of a storage device. Physical addresses of the data may be segmented into a first portion identifying the storage unit in which the data is stored, and a second portion that indicates the offset of the data within the identified storage unit. An index of the data offsets (e.g., second portions of the physical addresses) may be persisted on the storage device. The first portion of the address may be associated with logical addresses of the data in a forward index. The forward index may omit the second portion of the physical addresses, which may reduce the memory overhead of the index and/or allow the forward index to reference larger storage devices. Data of a particular logical address may be accessed using the first portion of the physical address maintained in the forward index, and the second portion of the media address stored on the storage device.
|SYSTEM AND METHOD FOR SECURE BOOTING AND DEBUGGING OF SOC DEVICES - Disclosed are systems, methods and computer program products for secure rebooting and debugging a peripheral subsystem of a system on a chip (SoC) device. According to one aspect of the method, when an application processor of the SoC device detects crash of the peripheral subsystem, the application processor loads a secure boot agent into SoC memory. The secure boot agent is configured to access a secure memory region of the peripheral subsystem containing memory dump data associated with the peripheral subsystem. The secure memory region is inaccessible to the application processor. The Secure boot agent encrypts the memory dump data in the secure memory region and opens the secure memory region for access to the application processor. The application processor accesses the secure memory region and collects the encrypted memory dump data. The application processor then forwards the encrypted memory dump data to a third party for debugging purposes.
|VIRTUAL MEMORY MANAGEMENT APPARATUS - A virtual memory management apparatus of an embodiment is embedded in a computing machine
|EXECUTING HOST DATA TRANSFER OPERATIONS DURING SETUP OF COPY SERVICES OPERATIONS - Host input/output (I/O) operations are performed via a file stored in a non-volatile storage coupled to a storage controller while data structures are being generated in the storage controller to copy data from source logical volumes to target logical volumes. The source logical volumes and the target logical volumes are logical representations of physical storage maintained in a plurality of direct access storage devices. The contents of the file are transferred from the non-volatile storage to one or more of the plurality of direct access storage devices, after the data structures have been generated, wherein the host I/O operations are performed via the file while the contents of the file are being transferred to the one or more of the plurality of direct access storage devices. The host I/O operations to the plurality of direct access storage devices are resumed, in response to transferring entire contents of the file to the one or more of the plurality of direct access storage devices.
|MICROPROCESSOR - According to an embodiment, the program memory stores application software in a ROM area. An address range of the application software targeted for restriction on use in the program memory is described in the application information memory. Yes-or-no information on the use of the application software targeted for restriction on use is written in the yes-or-no information memory. The switch switches between whether or not to apply an input signal to the processor core. The judgment unit judges whether or not a program counter value of the processor core is within the address range described in the application information memory and, when the program counter value is within the address range, the judgment unit controls the switching of the switch based on the yes-or-no information written in the yes-or-no information memory.
|ASSIGNING A WEIGHTING TO HOST QUALITY OF SERVICE INDICATORS - Quality of service indicators are provided from a host via a host interface. The quality of service indicators relate to data stored in a non-volatile data storage via the host. Workload indicators related to the quality of service indicators are measured, and a weighting is assigned to the host in response to a correlation between the quality of service indicators and the measured workload indicators. The weighting is applied to the quality of service indicators when responding to data access requests from the host.
|DATA WRITING METHOD FOR NON-VOLATILE MEMORY AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data writing method for a non-volatile memory and a storage system and a controller using the same are provided. The data writing method includes executing a non-volatile memory writing program pre-stored in the non-volatile memory on a host, managing data desired to be written through the non-volatile memory writing program, executing a write-enabling command to temporarily disable a write protection of the non-volatile memory and executing a write command through the non-volatile memory writing program to write the data in a writing unit not recorded with any data in the non-volatile memory, and re-enabling the write protection after completing the writing by executing a write-protecting command. Accordingly, it is possible to avoid damage to the non-volatile memory due to multiple writings which are not desired in the non-volatile memory.
|CONFIGURATION DATA BASED DIAGNOSTIC DATA CAPTURE - A data capture system includes a processor instructed by configuration data that indicates a trigger event and data identifiers, a volatile memory that stores data based upon the data identifiers, and a non-volatile memory that stores contents of the volatile memory based upon detection of the trigger event by the processor. The data identifiers indicate data elements to be stored.
|Dynamic Central Cache Memory - The specification and drawings present a new apparatus, method and software related product for using a cache/central cache module/device (instead of e.g., system DRAM) which can serve multiple memory modules/devices. Each memory/IO module/device connected to the same memory network (e.g., via hub, bus, etc.) may utilize memory resources of this cache module/device either in a fixed manner using pre-set allocation of resources per the memory module/device, or dynamically using run-time allocation of new resources to an existing module/device per its request or to a new module/device connecting to the memory network (e.g., comprised in a host device) and possibly requesting memory resources.
|IMAGE PROCESSING APPARATUS, ACCESS CONTROL METHOD, RECORDING MEDIUM - An image processing apparatus includes a nonvolatile memory device including a first storage area configured to store one or more predetermined information items; a secondary storage device including a second storage area configured to store the predetermined information items; and an access control unit configured to control access to the first storage area and the second storage area in response to an access request to access the predetermined information items.
|CONTROLLING METHOD FOR CONNECTOR, CONNECTOR AND MEMORY STORAGE DEVICE - A controlling method for connector is provided, which includes: receiving a first signal stream under a condition that a squelch detector is turned-off; determining whether the first signal stream contains a burst signal under a first operating frequency; if the first signal stream contains the burst signal, turning on the squelch detector and determining by the squelch detector under a second operating frequency whether a second signal stream is a waking signal, wherein the second signal stream is received after receiving the first signal stream and the second operating frequency is greater than the first operating frequency. The controlling method further includes: if the second signal stream is the waking signal, changing an operating state of the connector to an active state. In this way, the power consumption of the connector is reduced.
|MULTI-LEVEL MEMORY WITH DIRECT ACCESS - Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system.
|Storage System and Method for Operating Thereof - Storage system(s) for providing storing data in physical storage in a recurring manner, method(s) of operating thereof, and corresponding computer program product(s). For example, a possible method can include for each recurrence: generating a snapshot of at least one logical volume; destaging all data corresponding to the snapshot which was accommodated in the cache memory prior to a time of generating the snapshot and which was dirty at the time of generating said snapshot, thus giving rise to destaged data group; and after the destaged data group has been successfully destaged, registering an indication that the snapshot is associated with an order preservation consistency condition for the at least one logical volume, thus giving rise to a consistency snapshot.
|Preventing Out-Of-Space Errors For Legacy Option ROM In A Computing System - Preventing out of legacy option ROM space errors in a computing system, including: iteratively for each option ROM in the computing system: loading, into an option ROM memory, the option ROM; executing, from the option ROM memory, the option ROM; and removing, from the option ROM memory, the option ROM.
|Transparent Self-Hibernation of Non-Volatile Memory System - A memory system self-initiates hibernation mode and responds to host commands issued during hibernation within a host protocol timeout period. Hibernation mode is entered after controller state data has been stored and while no host command to the memory system is pending. Power to volatile data storage is diminished during hibernation mode. Upon receiving a host command during hibernation mode, power is restored and a reduced portion of the controller state data is read from non-volatile memory. A removable data storage device or a portable electronic device with embedded data storage may be constructed with such a self-hibernating memory system.
|MEMORY MANAGEMENT METHOD DURING POWER-ON SELF TEST - A memory management method during a power-on self test is used to perform an access management on an option ROM during a power-on self test after a personal computer is powered on. The memory management method includes the following steps. When a BIOS is booted, an option ROM is detected. A memory segment is designated in a conventional memory. It is determined whether the memory segment is empty or not. If the memory segment is not empty, a register segment with the same capacity as the memory segment is applied for from an extended memory, and data in the memory segment is moved to the register segment for being stored. If the memory segment is empty, data in the option ROM is moved to the memory segment. The option ROM in the memory segment is set.
|Preventing Out-Of-Space Errors For Legacy Option ROM In A Computing System - Preventing out of legacy option ROM space errors in a computing system, including: iteratively for each option ROM in the computing system: loading, into an option ROM memory, the option ROM; executing, from the option ROM memory, the option ROM; and removing, from the option ROM memory, the option ROM.
|DETERMINING WEIGHT VALUES FOR STORAGE DEVICES IN A STORAGE TIER TO USE TO SELECT ONE OF THE STORAGE DEVICES TO USE AS A TARGET STORAGE TO WHICH DATA FROM A SOURCE STORAGE IS MIGRATED - The present invention relates to a method, system, and computer program product for determining storage device weight values to use to select one of the storage devices to use as a target storage to which data from a source storage is migrated. A determination is made, for each of the storage devices, of static parameter values for static parameters comprising attributes of the storage device and dynamic parameter values for dynamic parameters providing device health information determined by accessing the storage device to determine operational conditions at the storage device. Storage device weight values are determined as a function of the static parameter values and the dynamic parameter values of the device. The determined storage device weight values are used to select one of the storage devices as the target storage to which data from the source storage is migrated.
|MULTI-CORE PROCESSOR AND CONTROL METHOD - According to an embodiment, a multi-core processor is capable of executing a plurality of tasks. The multi-core processor includes at least a first core and a second core. The first core and the second core are capable of accessing a shared memory area. The first core includes one or more memory layers in an access path to the shared memory area, the one or more memory layers including a local memory for the first core. The second core includes one or more memory layers in an access path to the shared memory area, the one or more memory layers including a local memory for the second core. The local memory for the first core and the local memory for the second core include memories with different unit cell configurations in at least one identical memory layer.
|BLOCK CONTROL DEVICE OF SEMICONDUCTOR MEMORY AND METHOD FOR CONTROLLING THE SAME - A block control device for a semiconductor memory and a method for controlling the same are disclosed, which relate to a technology for controlling a block operation state of a Low Power Double-Data-Rate 2 (LPDDR2) non-volatile memory device. A block control device for use in a semiconductor memory includes a block address comparator configured to compare a first block address with a last block address, and output a same pulse or unequal pulse according to the comparison result, a block address driver configured to output a lock state control signal for driving a block address in response to the same pulse, a block address counter configured to count block addresses from the first block address to the last block address in response to the unequal pulse, and generate a block data activation pulse, and a block address register configured to store a lock state of a corresponding block in response to the lock state control signal and the block data activation pulse.
|FLASH BACKED DRAM MODULE STORING PARAMETER INFORMATION OF THE DRAM MODULE IN THE FLASH - A device includes volatile memory; one or more non-volatile memory chips, each of which is for storing data moved from the volatile-memory; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from a primary power source; a controller in communication with the volatile memory and the non-volatile memory, wherein: the controller is programmed to move data from the volatile memory to the non-volatile memory chips upon a loss of power of the primary power source of the volatile memory; and parameters describing the volatile memory are stored in at least one of the non-volatile memory chips that store the data moved from the volatile memory. In some aspects the parameters include serial presence detect information.
|USE OF DIFFERING GRANULARITY HEAT MAPS FOR CACHING AND MIGRATION - For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, groups of data segments are migrated between the tiered levels of storage such that uniformly hot ones of the groups of data segments are migrated to utilize a Solid State Drive (SSD) portion of the tiered levels of storage, while sparsely hot ones of the groups of data segments are migrated to utilize the lower-speed cache.
|SYSTEMS AND METHODS FOR MANAGING READ-ONLY MEMORY - A first virtual memory address is mapped to a real memory in a memory device, and a second virtual memory address is mapped to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory.
|SOLID STATE DRIVE PACKAGES AND RELATED METHODS AND SYSTEMS - Solid state drive (SSD) packages are provided including a controller package and at least one non-volatile memory package. The controller package and the at least one non-volatile memory package are connected to each other using a package-on-package (PoP) technique. A data input/output of the at least one non-volatile memory package is controlled by using the controller package.
|MEMORY SYSTEM AND MEMORY - According to one embodiment, a memory system includes a memory and a controller configured to control the memory. The memory includes a semiconductor memory region in which data rewrite is executed by an instruction of the controller, a timing determination module configured to derive a command input timing to the memory, based on the instruction and a clock which are received from the controller, and a status register configured to store the command input timing to the memory, which is derived by the timing determination module.
|SYSTEM AND METHOD FOR MANAGING PERSISTENCE WITH A MULTI-LEVEL MEMORY HIERARCHY INCLUDING NON-VOLATILE MEMORY - An apparatus and method for implementing non-volatile store (nvstore) and non-volatile flush (nvflush) instructions. For example, a method according to one embodiment comprises: executing a set of non-volatile store instructions indicating data to be persisted to a non-volatile memory (NVM) of a multi-level system memory hierarchy; generating an entry in an NVM store queue prior to storing the data to the NVM, each entry indicating that the data associated therewith has not yet been persisted to non-volatile memory; executing a non-volatile flush instruction at a time when the data associated with each entry in the non-volatile store queue should be persisted to non-volatile memory; and removing the entries from the NVM store queue as the data associated with each entry is written to non-volatile memory
|Method and Apparatus for SSD Storage Access - A media management system including an application layer, a system layer, and a solid state drive (SSD) storage layer. The application layer includes a media data analytics application configured to assign a classification code to a data file. The system layer is in communication with the application layer. The system layer includes a file system configured to issue a write command to a SSD controller. The write command includes the classification code of the data file. The SSD storage layer includes the SSD controller and erasable blocks. The SSD controller is configured to write the data file to one of the erasable blocks based on the classification code of the data file in the write command. In an embodiment, the SSD controller is configured to write the data file to one of the erasable blocks storing other data files also having the classification code.
|MEMORY CONTROLLER USING CRISSCROSS ERROR-CORRECTING CODES - A method is provided to manage access to a memory array. The method includes encoding a bit string with a rank metric encoder to generate an encoded binary array, modifying the encoded binary array so each row has at most half of the row with a bit value and each column has at most half of the column with the bit value, and storing the modified binary array into corresponding memory devices of the memory array.
|SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR GENERATING CHRONOLOGICALLY ORDERED GLOBALLY UNIQUE IDENTIFIERS - A computer-based system, method and computer program product for generating chronologically based globally unique identifiers.
|MULTIPLE SUBARRAY MEMORY ACCESS - A multiple subarray-access memory system is disclosed. The system includes a plurality of memory chips, each including a plurality of subarrays and a memory controller in communication. with the memory chips, the memory controller to receive a memory fetch width ("MFW") instruction during an operating system start-up and responsive to the MFW instruction to fix a quantity of the subarrays that will be activated in response to memory access requests.
|BUFFER CACHE APPARATUS, JOURNALING FILE SYSTEM AND JOURNALING METHOD FOR INCORPORATING JOURNALING FEATURES WITHIN NON-VOLATILE BUFFER CACHE - Disclosed herein are a buffer cache apparatus, a journaling file system, and a journaling method capable of incorporating journaling features based on nonvolatile memory. The buffer cache apparatus provides a data buffering function between a central processing unit (CPU) and storage. The buffer cache apparatus includes a plurality of cache blocks and a journal management unit. The plurality of cache blocks are configured as volatile or nonvolatile memory devices. The journal management unit maintains states of freezing for write-protecting dirty up-to-date cache blocks among the plurality of cache blocks.
|Integrated circuits to control access to multiple layers of memory in a solid state drive - Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration.
|SYSTEMS AND METHODS FOR CACHE PROFILING - A cache module leverages a logical address space and storage metadata of a storage module (e.g., virtual storage module) to cache data of a backing store. The cache module maintains access metadata to track access characteristics of logical identifiers in the logical address space, including accesses pertaining to data that is not currently in the cache. The access metadata may be separate from the storage metadata maintained by the storage module. The cache module may calculate a performance metric of the cache based on profiling metadata, which may include portions of the access metadata. The cache module may determine predictive performance metrics of different cache configurations. An optimal cache configuration may be identified based on the predictive performance metrics.
|Managing Configuration Parameters for a Non-Volatile Medium - An apparatus, system, and method are disclosed for managing configuration parameters of a non-volatile storage device. The method includes storing a first set of configuration parameters for a non-volatile recording device. The first set of configuration parameters are configured for a storage operation on a storage element of the non-volatile recording device. The method also includes storing a second set of configuration parameters for the non-volatile recording device during execution of the storage operation on the storage element. The second set of configuration parameters are configured for a second storage operation on the storage element of the non-volatile recording device.
|CONTROL APPARATUS AND METHOD FOR CONTROLLING CONTROL APPARATUS - A control apparatus includes a signal processing module. The signal processing module includes a field programmable gate array and a volatile memory. The volatile memory is configured to store configuration information of the field programmable gate array. The field programmable gate array has access to the volatile memory after a configuration of the field programmable gate array.
|GENERATION OF FAR MEMORY ACCESS SIGNALS BASED ON USAGE STATISTIC TRACKING - A method is described that entails receiving an address for a read or write transaction to a non volatile system memory device. The method further involves determining a usage statistic of the memory device for a set of addresses of which the address is a member. The method further involves determining a characteristic of a signal to be applied to the memory device for the read or write transaction based on the usage statistic. The method further involves generating a signal having the characteristic to perform the read or write transaction.
|METHOD OF HANDLING I/O REQUEST AND SOLID STATE DRIVE USING THE SAME - A solid state drive (SSD) including a storage that includes a plurality of flash memories configured to be independently drivable and a controller to receive an input/output (I/O) request from a host, to split the I/O request into a plurality of sub-requests each having a size configured to be capable of being processed independently by each flash memory, and to process the I/O request based on the sub-requests.
|CACHING SCHEME SYNERGY FOR EXTENT MIGRATION BETWEEN TIERS OF A STORAGE SYSTEM - A method according to one embodiment includes determining to move an extent from a source-tier in a storage system to a destination-tier in the storage system, wherein a set of tracks of the extent is presently being accessed. In response to determining that a parameter of the extent exceeds a migration threshold, a destination-tier cache is populated with tracks as they are removed from a read-stack associated with the source-tier and/or a write-stack associated with the source-tier using a predetermined read-to-write ratio. The extent is migrated from the source-tier to the destination-tier.
|STORAGE SYSTEM HAVING VOLATILE MEMORY AND NON-VOLATILE MEMORY - A storage system including: a plurality of storage devices; a volatile memory which temporarily stores data; a nonvolatile memory; a battery saving power; a cache control unit which sets, according to battery charging rate of the battery, a part of the data stored in the volatile memory as save target data which are to be saved to the nonvolatile memory when power interruption occurs, and saves the part of the data, which is set as the save target data, to the nonvolatile memory by using power of the battery when power interruption occurs.
|CONTROLLER FOR CONTROLLING NON-VOLATILE MEMORY AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A controller controlling a non-volatile memory includes a first memory area suitable for storing a first address table, a second memory area suitable for storing a second address table, an address conversion block suitable for converting a sector address received from a host into a physical address corresponding to the non-volatile memory with reference to the first and second address tables, and one or more function blocks suitable for sharing the second memory area with the address conversion block. The address conversion block exclusively uses the first memory area.
|SEMICONDUCTOR MEMORY DEVICE, SYSTEMS AND METHODS IMPROVING REFRESH QUALITY FOR WEAK CELL - Disclosed is a semiconductor memory device which includes a normal memory cell array; a redundancy memory cell array; and a multi-row selection circuit configured to activate a defective normal memory cell or a defective normal word line of the normal memory cell array while activating a redundancy memory cell or a redundancy word line of the redundancy memory cell array.
|DETERMINING POLICY ACTIONS FOR THE HANDLING OF DATA READ/WRITE EXTENDED PAGE TABLE VIOLATIONS - Embodiments of systems, apparatuses, and methods for determining if an instruction of a virtual machine is allowed to modify a protected memory region are described. In some embodiments, a system detects an indication of an attempt by the instruction to write to the protected memory region. In addition, the system determines if the instruction is allowed to write to the protected memory region based on a starting address and data length of the instruction. Furthermore, if the instruction is allowed to write to the protected memory region, the system updates the protected memory region with the instruction results.
|APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY - A system and method are described for intelligently flushing data from a processor cache. For example, a system according to one embodiment of the invention comprises: a processor having a cache from which data is flushed, the data associated with a particular system address range; and a PCM memory controller for managing access to data stored in a PCM memory device corresponding to the particular system address range; the processor determining whether memory flush hints are enabled for the specified system address range, wherein if memory flush hints are enabled for the specified system address range then the processor sending a memory flush hint to a PCM memory controller of the PCM memory device and wherein the PCM memory controller uses the memory flush hint to determine whether to save the flushed data to the PCM memory device.
|DELAYED AUTOMATION TO MAXIMIZE THE UTILIZATION OF READ AND WRITE CACHE - A storage module may include a non-volatile memory module and a controller that communicates with the non-volatile memory module using a communications bus. In response to receipt of a host command, the controller may generate one or more sets of context commands for communication of data on the communications bus between the controller and an area of memory. The controller may execute the sets of context commands in a cache sequence. During execution of the context commands in the cache sequence, the controller may determine an opportunity window that occurs after execution of a context command of a prior set and before execution of a context command of a current set, during which the controller may utilize the communications bus.
|UTILIZING UNMAPPED AND UNKNOWN STATES IN A REPLICATED STORAGE SYSTEM - A system and method for utilizing unmapped and unknown states in a storage system. When a first portion of a first medium is determined to be unreachable from any other mediums, the first portion of the first medium may be put into an unmapped state, and its data may be discarded and the corresponding storage locations may be freed. During replication of the first medium to a replica storage array, the state of the first portion of the first medium may be translated from the unmapped state into an unknown state on the replica storage array. If another storage array has the data of the first portion of the first medium, this data may be used to overwrite the first portion of the first medium on the replica storage array, converting the first portion of the first medium from the unknown state into the mapped state.
|APPARATUSES AND METHODS FOR IDENTIFYING AN EXTREMUM VALUE STORED IN AN ARRAY OF MEMORY CELLS - The present disclosure includes apparatuses and methods related to identifying an extremum value using sensing circuitry. An example method can include determining a location of an extremum value of a set of N data values stored as vectors in a memory array. A number of operations to determine the location of the extremum value can remain constant with respect to a value of N.
|Processing Device With Restricted Power Domain Wakeup Restore From Nonvolatile Logic Array - A processing device handles two or more operating threads. A non-volatile logic controller stores first program data from a first program in a first set of non-volatile logic element arrays and second program data from a second program in a second set of non-volatile logic element arrays. The first program and the second program can correspond to distinct executing threads, and the storage can be completed in response to receiving a stimulus regarding an interrupt for the computing device apparatus or in response to a power supply quality problem for the computing device apparatus. When the device needs to switch between processing threads, the non-volatile logic controller restores the first program data or the second program data from the non-volatile logic element arrays in response to receiving a stimulus regarding whether the first program or the second program is to be executed by the computing device apparatus.
|DURABLE TRANSACTIONS WITH STORAGE-CLASS MEMORY - A method for conducting memory transactions includes receiving a transaction. The steps of the received transaction are performed in a memory buffer. A state of the memory buffer cache lines is set as pending and unstored while the transaction is in progress. After all steps have been successfully performed, the state of the memory buffer cache lines are changed to complete and unstored. When it is determined that the memory buffer cache lines are to be written to the non-volatile main memory, the contents is written to the non-volatile main memory. The state of the memory buffer cache lines are then changed to complete and stored. When the memory buffer cache lines are in the complete and unstored state, access to modify their content is restricted.
|COMPUTER SYSTEM, MEMORY MANAGEMENT METHOD AND PROGRAM THEREOF - A computer system, having a non-volatile storage unit (
|ADJUSTING ALLOCATION OF STORAGE DEVICES - Embodiments of the present invention provide methods, computer systems, and computer program products for adjusting allocation of a storage device. In one embodiment, a first part of the storage device is allocated to tiering storage, and a second part of the storage device is allocated to cache storage. Operating statuses of the first part and second part are collected. A performance measure of the first part is obtained based on the operating status of the first part, and a performance measure of the second part is obtained based on the operating status of the second part. Allocation of a capacity of the storage devices is adjusted between the first part and the second part based on the performance measures of the first part and the second part.
|Storage Medium with Data Memory and Charging Station - There is provided a storage medium for use as a source of energy for vehicles. An exemplary storage medium comprises a data memory that stores information about the charge status of the storage medium. The exemplary storage medium also comprises a SIM card.
|Device and Method for Managing Die Groups - The embodiments described herein methods and devices that enhance the endurance of a non-volatile memory (e.g., flash memory). The method includes obtaining, for each of the plurality of die, an endurance metric. The method also includes sorting the plurality of die into a plurality of die groups based on their corresponding endurance metrics, where each die group includes one or more die and each die group is associated with a range of endurance metrics. In response to a write command specifying a set of write data, the method further includes writing the write data to the non-volatile memory by writing in parallel subsets of the write data to the one or more die assigned to a single die group of the plurality of die groups.
|STORING CACHED DATA IN OVER-PROVISIONED MEMORY IN RESPONSE TO POWER LOSS - A power loss condition is detected that affects volatile data that is cached in preparation for storage in a non-volatile, solid-state memory device. The volatile cached data is stored in an over-provisioned portion of the non-volatile, solid-state memory device in response to the power loss condition.
|SYSTEM AND METHOD TO UPDATE READ VOLTAGES IN A NON-VOLATILE MEMORY IN RESPONSE TO TRACKING DATA - A method includes reading a representation of tracking data from at least a portion of a non-volatile memory. The method further includes adjusting a read voltage based on a comparison between a number of bits in tracking data as compared to a count of bits in the representation of the tracking data.
|MULTI-CORE DEVICE WITH OPTIMIZED MEMORY CONFIGURATION - A multi-core device for a piece of electronic equipment includes at least two cores arranged to execute different software portions stored on a memory means. At least one of these cores is associated with a primary RAM that is part of the memory means and arranged for persistent storage without power consumption.
|METHOD AND APPARATUS FOR IMPROVING SMALL WRITE PERFORMANCE IN A NON-VOLATILE MEMORY - An invention is provided for improving performance in block based non-volatile memory when performing random small write operations. When requests for small page updates are received for a memory page currently storing data, the updated page data is written to a reserve memory page. The reserve memory page can be in the same memory block as the target memory page, or in an associated reserve memory block. In addition, the associated logical page address is temporarily remapped to the reserve page. Later, when time permits, the page data for the block can be reorganized into continuous pages in a new block.
|SYSTEM AND METHOD FOR DATA-PROCESSING - Disclosed is a data processing system and method. The data processing system may include a plurality of servers to process data, and a controller to shut off a power supplied to a server, among the plurality of servers, having data throughput less than a predetermined data throughput.
|INFORMATION PROCESSING SYSTEM AND DATA PROCESSING METHOD - The information processing apparatus includes a preprocessing unit that allocates the identifier to one or more collected groups, the main storage unit including a buffer having a size of the predetermined unit installed for each group, the storage unit that stores the data written in the buffer for each predetermined unit and each group, a write processing unit that acquires the data allocated to the group for each group and writes the acquired data in the buffer, determines whether or not the data of the predetermined unit has been written in the buffer, and causes the storage unit to store the data written in the buffer when the data of the predetermined unit is determined to have been written in the buffer, and a read processing unit that reads the stored data out to the main storage unit for each group, extracts the read data, and executes the process.
|Multiprocessor system with booting function using memory link architecture - The multiprocessor system includes first and second multiport semiconductor memory devices, first, second and third processors individually storing a first boot loader, the first and second processors being configured to access the first multiport semiconductor memory device, and the second and third processors being configured to access the second multiport semiconductor memory device, and a memory link architecture including the second multiport semiconductor memory device, the third processor, and a nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device includes a plurality of storage areas storing a second boot loader and software for the first, second and third processors. The third processor is configured to access the nonvolatile semiconductor memory device and configured to apply the second boot loader to the first and second processors through a serial communication to perform a portion of booting the system.
|SELF RECOVERY IN A SOLID STATE DRIVE - An apparatus having a nonvolatile memory and a controller. The memory stores information in multiple pages. The information includes data units and headers. Each data unit is associated with a respective identifier in an address space of the apparatus and a respective location in the memory, has a respective header having the respective identifier, and is associated with a respective time stamp. Multiple headers include ones of the time stamps. The controller is configured to (i) read information stored in the pages, (ii) determine an order in which the data units were written based on the time stamps, (iii) locate based on the order (a) each last-written occurrence of the respective identifiers and (b) the respective locations of the data units associated with the last-written occurrences, and (iv) rebuild a map of the controller according to the respective locations of each last-written occurrence of each respective identifier.
|INFORMATION PROCESSING DEVICE, MEMORY ORDER GUARANTEE METHOD, AND RECORDING MEDIUM STORING PROGRAM - An information processing device includes a plurality of processors including an Acquire side processor and a Release side processor, and a shared memory. The Acquire side processor and the Release side processor includes a cache, a memory access control unit in the Release side processor configured to issue a StoreFence instruction for requesting a guarantee of completing the cache invalidation by the Acquire side processor, a memory access control unit in the Acquire side processor configured to issue a LoadFence instruction in response to the StoreFence instruction for guaranteeing completion of the cache invalidation in accordance with the invalidation request from the shared memory after completing a process for the cache invalidation, and an invalidation request control unit configured to perform a process for invalidating the cache in accordance with the invalidation request from the shared memory.
|SELECTIVELY PLACING DATA IN THERMALLY CONSTRAINED MEMORY SYSTEMS TO DYNAMICALLY ADAPT TO CHANGING ENVIRONMENTAL CONDITIONS - A method for selectively placing cache data, comprising the steps of (A) determining a line temperature for a plurality of devices, (B) determining a device temperature for the plurality of devices, (C) calculating an entry temperature for the plurality of devices in response to the cache line temperature and the device temperature and (D) distributing a plurality of write operations across the plurality of devices such that thermal energy is distributed evenly over the plurality of devices.
|MEMORY SYSTEM IN WHICH EXTENDED FUNCTION CAN EASILY BE SET - According to one embodiment, a memory system, such as a SDIO card, includes a nonvolatile semiconductor memory device, a control section, a memory, an extended function section, and an extension register. The extended function section is controlled by the control section. A first command reads data from the extension register in units of given data lengths. A second command writes data to the extension register in units of given data lengths. A extension register includes a first area, and second area different from the first area, information configured to specify a type of the extended function and controllable driver, and address information indicating a place to which the extended function is assigned, the place being on the extension register, are recorded in the first area, and the second area includes the extended function.
|EFFICIENT IMPLEMENTATIONS FOR MAPREDUCE SYSTEMS - Techniques for use with a processor configured to function as at least a Mapper in a MapReduce system include generating a set of [key, value] pairs by executing a Map function on input data. The set of [key, value] pairs may be stored in a storage system implemented on at least one data storage medium, the storage system being organized into a plurality of divisions with different divisions of the storage system storing [key, value] pairs corresponding to different keys. A first [key, value] pair corresponding to a first key handled by a first Reducer in the MapReduce system and a second [key, value] pair corresponding to a second key handled by a second Reducer in the MapReduce system may both be stored in a first division of the plurality of divisions.
|METHOD AND DEVICE FOR STORING DATA - The invention discloses a method for storing data and a device of implementing the same. The method comprises receiving a request for storing data sent by a user and storing the data to an SSD according to the received request. The device comprises a request receiving module used to receive the request storing data and an SSD storage module used to store the data to an SSD according to the received request. The invention ensures consistency of data storage by storing data to an SSD according to the received request, thereby reducing data redundancy caused by using a cache layer to cache the data in the prior art. Additionally, the use of a single layer of an SSD to store data avoids the need of reloading data in the cache layer once a machine is power-down, thereby reducing the complexity of system design and the cost of operation and maintenance.
|INFORMATION RECORDING DEVICE, INFORMATION RECORDING SYSTEM, AND INFORMATION COMMUNICATION METHOD - An information recording device comprises a memory component configured to hold data, a first file system controller configured to manage data held in the memory component on the basis of a first file name formed by a first code, and a wireless component configured to send and receive wireless signals. The first file system controller receives, from an access device connected to the information recording device, the first file name and a second file name that corresponds to the first file name and is formed by a second code that is different from the first code, identifies specific data having the first file name out of the data held in the memory component, and sends the second file name and the specific data to another information recording device connected via the wireless component.
|FILE SYSTEM AND CONTROL METHOD THEREOF - A file system including a first memory unit which is non-volatile and has a plurality of blocks, a control unit configured to select one of the plurality of blocks of the first memory unit, determine whether the selected block is a valid block, control a data write with respect to the selected block if the selected block is a valid block, divide the plurality of blocks into valid blocks and bad blocks by checking the plurality of blocks of the first memory unit, generate an address table by mapping the valid blocks and the bad blocks to addresses and control a loading of the address table generated, and a second memory unit which is volatile and stores the address table for the plurality of blocks of the first memory unit. An address table of a flash memory, which is a non-volatile memory, is stored in another memory
|STORAGE CACHING ACCELERATION THROUGH USAGE OF R5 PROTECTED FAST TIER - A data storage system with redundant SSD cache includes an SSD cache organized into logical stripes, each logical stripe having several logical blocks. The logical blocks of each stripe are organized into logical data blocks and one logical parity block. Data may be written to the SSD cache by performing an exclusive disjunction operation on the logical parity block, the new data and the existing data in logical stripe to update the parity block, then writing the new data over the existing data in a logical data block in the same logical stripe.
|CONFIGURABLE MEMORY SYSTEM - An interface circuit that emulates a memory circuit having a first organization using a memory circuit having a second organization, wherein the second organization includes a number of banks, a number of rows, a number of columns, and a number of bits per column.
|EFFICIENT TWO WRITE WOM CODES, CODING METHODS AND DEVICES - The invention provides a family of 2-write WOM-codes, preferred embodiments of which provide improved WOM-rates. Embodiments of the invention provide constructs for linear codes C having a 2-write WOM-code. Embodiments of the invention provide 2-write WOM-codes that improve the best known WOM-rates known to the present inventors at the time of filing with two writes. Preferred WOM-codes are proved to be capacity achieving when the parity check matrix of the linear code C is chosen uniformly at random. Preferred embodiments of the invention provide an electronic device utilizing an efficient coding scheme of WOM-codes with two write capability. The coding) method is based on linear binary codes and allows the electronic device to write information to the memory twice before erasing it This method can be applied for any kind of memory systems, and in particular for flash memories. The method is shown to outperform all well-known codes.
|SYSTEM AND METHOD FOR OPTIMIZING THERMAL MANAGEMENT FOR A STORAGE CONTROLLER CACHE - The present invention is directed to a method for optimizing thermal management for a storage controller cache of a data storage system. The method allows for pending writes of a storage controller to be selectively provided to solid-state device (SSD) module(s) of the controller in a manner which allows operating temperatures of the SSD module(s) to be maintained within a thermal envelope.
|APPARATUS, SYSTEM, AND METHOD FOR DETERMINING A CONFIGURATION PARAMETER FOR SOLID-STATE STORAGE MEDIA - An apparatus, system, and method are disclosed to improve the utility of solid-state storage media by determining one or more configuration parameters for the solid-state storage media. A media characteristic module references one or more storage media characteristics for a set of storage cells of solid-state storage media. A configuration parameter module determines a configuration parameter for the set of storage cells based on the one or more storage media characteristics. A storage cell configuration module configures the set of storage cells to use the determined configuration parameter.
|INFORMATION PROCESSING APPARATUS - According to one embodiment, if a nonvolatile memory which stores format information of an HDD, a CD/DVD, an FDD and a USB storage device, and the USB storage device are connected, the drive letter of the USB storage device is virtually assigned as FDD or HDD on the basis of the format information.
|Conditional Iteration for a Non-Volatile Device - Apparatuses, systems, methods, and computer program products are disclosed for conditional iteration. A method includes receiving a request comprising a condition. A method includes checking an address mapping structure for entries satisfying a condition for a request. A method includes providing a result for a request based on one or more entries satisfying a condition for a request.
|Write Mechanism for Storage Class Memory
|MEMORY STORAGE DEVICE, MEMORY CONTROLLER, AND TEMPERATURE MANAGEMENT METHOD - A temperature management method suitable for a memory storage device having a rewritable non-volatile memory module and a memory controller used for controlling the rewritable non-volatile memory module are provided. The temperature management method includes detecting and determining whether the hot-spot temperature of the memory storage device is higher than a predetermined temperature; and when affirmative, making the memory controller execute a cooling process, so as to reduce the hot-spot temperature of the memory storage device. Accordingly, the problem of heat buildup of the (rewritable non-volatile) memory storage device can be mitigated, as well as the problems of data loss and device aging of the (rewritable non-volatile) memory storage device.
|Write Once Read Many Media Methods - A method for providing for write once read many (WORM) times from at least some addresses of a storage drive that is otherwise manufactured for multiple writes to individual addresses. In at least one embodiment, a WORM area(s) is defined by a START_LBA and an END_LBA and the method uses a HWM_LBA to determine whether a LBA in the WORM area has been written to previously and to prevent previously written to LBA(s) in the WORM area from being rewritten. In at least one embodiment where there are multiple WORM areas, each WORM area has its own respective START_LBA, END_LBA and HWM_LBA.
|ISOLATION SWITCHING FOR BACKUP MEMORY - Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.
|SOLID STATE DRIVE INTERFACE CONTROLLER AND METHOD OF CONTROLLING SOLID STATE DRIVE INTERFACE - A solid state drive (SSD) interface controller includes a host interface, first and second command interfaces, and an interface storage unit. The host interface is configured to communicate data with a host device. The first command interface is configured to communicate data between the host interface and an SSD, and the second command interface is configured to communicate data between the host interface and the SSD independently of the first command interface. The interface information storage unit is configured to store information for determining activation or deactivation of each of the first and second command interfaces, and a capacity allocated to each of the first and second command interfaces.
|RECOVERY FROM CACHE AND NVS OUT OF SYNC - For cache/data management in a computing storage environment, incoming data segments into a Non Volatile Storage (NVS) device of the computing storage environment are validated against a bitmap to determine if the incoming data segments are currently in use. Those of the incoming data segments determined to be currently in use are designated to the computing storage environment to protect data integrity.
|SOLID STATE DRIVE DATA STORAGE SYSTEM & METHOD - The present disclosure relates to a data storage system and method that includes at least two solid state devices that can be classified in at least two different efficiency levels, wherein data progression is used to allocate data to the most cost-appropriate device according to the nature of the data.
|Method And Apparatus For Dynamically Allocating Memory Address Space Between Physical Memories - A memory address space for each of a plurality of physical memories in a microprocessor-based system is allocated prior to knowing the desired logical size of at least one of the physical memories. At least two of the allocated memory address spaces overlap at least a portion of each other. After the system is fabricated, a pointer value set that corresponds to an address boundary between at least two physical memories of the fabricated system is set during boot time and/or during run time when the size of the physical memories are known. The technique provides a faster time-to-market for microprocessor-based systems by allowing, for example, Application Specific Integrated Circuits (ASICs) comprising microprocessor systems on-chip be manufactured prior to the final firmware and software being fully developed. Additionally, the subject matter disclosed herein permits changes in memory-space allocation for finalized ASIC designs.
|INFORMATION PROCESSING APPARATUS AND METHOD OF RECORDING USING START DATE THEREOF - According to an aspect of the present invention, there is provided an information processing apparatus including: a date generating module configured to generate date information in a real time; a nonvolatile recording module configured to record the date information in a given area; and a recording control module configured to access to the given area when specific software is started, wherein the recording control module is configured to record present date information generated by the date generating module in the given area when the date information is not recorded in the given area.
|MEMORY CONTROL APPARATUS, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM, AND MEMORY CONTROL METHOD - A memory control apparatus includes a temperature obtaining unit, a priority determination unit, and a write processing unit. The temperature obtaining unit is configured to obtain, in a memory having a plurality of measurement areas each including a plurality of unit areas, temperatures measured in the plurality of measurement areas. The priority determination unit is configured to determine a priority for each unit area in accordance with a degree of consumption and the temperature of the measurement area including the unit areas, the degree of consumption being a degree of consumption of the unit area which is caused by a write process performed. The write processing unit is configured to preferentially perform the write process with respect to the unit area having a higher priority as a data write destination.
|Method and System for Preventing Unreliable Data Operations at Cold Temperatures - Systems and methods for reducing problems and disadvantages associated with protecting data during cold excursions are provided. A method for preventing unreliable data operations at cold temperatures may include determining whether a first temperature of a solid state drive (SSD) is below a threshold temperature. The method may also include initiating an artificial read/write operation if the first temperature is below the threshold temperature.
|RECOVERY FROM CACHE AND NVS OUT OF SYNC - For cache/data management in a computing storage environment, incoming data segments into a Non Volatile Storage (NVS) device of the computing storage environment are validated against a bitmap to determine if the incoming data segments are currently in use. Those of the incoming data segments determined to be currently in use are designated to the computing storage environment to protect data integrity.
|INTER-SET WEAR-LEVELING FOR CACHES WITH LIMITED WRITE ENDURANCE - A cache controller includes a first register that updates after every memory location swap operation on a number of cache sets in a cache memory and resets every N−1 memory location swap operations. N is a number of the cache sets in the cache memory. The memory controller also has a second register that updates after every N−1 memory location swap operations, and resets every (N
|STORAGE SUB-SYSTEM FOR A COMPUTER COMPRISING WRITE-ONCE MEMORY DEVICES AND WRITE-MANY MEMORY DEVICES AND RELATED METHOD - Methods and apparatus for a solid state non-volatile storage sub-system of a computer is provided. The storage sub-system may include a write-many storage sub-system memory device including write-many memory cells, a write-once storage sub-system memory device including write-once memory cells, and a page-based interface that is adapted to read and write the write-once and write-many storage sub-system memory devices. Numerous other aspects are provided.
|APPARATUS AND METHOD FOR SEGMENTED CACHE UTILIZATION - In some embodiments, a non-volatile cache memory may include a segmented non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the segmented non-volatile cache memory, wherein the controller is configured to control utilization of the segmented non-volatile cache memory. The segmented non-volatile cache memory may include a file cache segment, the file cache segment to store complete files in accordance with a file cache policy, and a block cache segment, the block cache segment to store one or more blocks of one or more files in accordance with a block cache policy, wherein the block cache policy is different from the file cache policy.
|NETMORY - An apparatus, method, and system are provided for optimizing computer operation. An embodiment of the apparatus includes a device that interconnects the core of the computer through the memory interface. The apparatus provides a communication path from the computer core to the world wide network. Computing communication and storage functions of the conventional computer are incorporated in the apparatus. Thus this improved computer architecture can operate with superior performance without disk and without operating system. This novel architecture permits to application software designers to develop software applications targeting this novel computer architecture rather than various the operating systems.
|AUTOMATICALLY RECONFIGURING A STORAGE MEMORY TOPOLOGY - A storage cluster is provided. The storage cluster includes a plurality of storage nodes within a single chassis. Each of the plurality of storage nodes has nonvolatile solid-state memory for storage of user data. The plurality of storage nodes are configured to distribute the user data and metadata throughout the plurality of storage nodes with erasure coding of the user data such that the plurality of storage nodes can access the user data, via the erasure coding, with a failure of two of the plurality of storage nodes. The plurality of storage nodes are configured to employ the erasure coding to reconfigure redundancy of the user data responsive to one of adding or removing a storage node
|Processing Device With Nonvolatile Logic Array Backup - A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.
|SHARED MEMORY ACCESS TECHNIQUES - Memory access techniques, in accordance with embodiments of the present technology, redirect memory access requests received from a baseband processor to shared memory coupled to an application processor. The techniques enable substantially real time read and write accesses by the application and baseband processors to the shared memory coupled to the application processor.
|DATA PROCESSING AND ADDRESSING METHODS FOR USE IN AN ELECTRONIC APPARATUS - An electronic apparatus is disclosed. The electronic apparatus comprises a random access memory (RAM), a read-only memory (ROM) and a processing unit. The RAM stores a call transfer table, wherein the code transfer table comprising at least one transferred address in the RAM. The ROM stores at least one code to call one address of the code transfer table. The processing unit executes the code in the ROM and reads the transfer table accordingly, then transfers to run the data in the transferred address of the RAM.
|METHOD FOR STORING DATA AND ELECTRONIC APPARATUS USING THE SAME - A method for storing data and an electronic apparatus using the same are provided. Only data is written to a memory card when the electronic apparatus wants to store the data to the memory card. And file information and location information corresponding to the data stored in the memory card are recorded into a buffer block of the electronic apparatus. After a file closing action is executed, the file information and the location information recorded in the buffer block are written to the memory card.
|LOGIC DEVICE HAVING A COMPRESSED CONFIGURATION IMAGE STORED ON AN INTERNAL READ ONLY MEMORY - Systems and methods for using an internal read only memory (ROM) to configure a logic device are described. The ROM and the logic device may be located on a single chip. The ROM may be adapted to store highly compressed configuration images and be non-reprogrammable. The logic device may be configured based on the compressed configuration image.
|ACCESSING DIFFERENT TYPES OF MEMORY BY RESPECTIVE COMMANDS WITH DIFFERENT TIMING REQUIREMENTS - A system is provided that includes a remote device and bus controller coupled to the remote device via a digital network bus. The remote device includes one or more data channels for respective one or more peripherals, and includes volatile channel-based memory for each data channel and non-volatile device-based memory for the remote device. The bus controller is and configured to send a command across the network bus to the remote device, and in response thereto, the remote device is configured to acquire data from a designated data channel or command the designated data channel to perform a conversion. The command is from a communication protocol with which the remote device is compatible, and includes a set of channel commands for accessing the channel-based memory, and a different, distinct set of device-memory commands for accessing the device-based memory. The channel commands and device-memory commands have different timing requirements.
|MEMORY SYSTEM, MEMORY DEVICE AND MEMORY INTERFACE DEVICE - In memory system in which the processing unit (
|MAINTAINING AT LEAST ONE JOURNAL AND/OR AT LEAST ONE DATA STRUCTURE BY CIRCUITRY - An embodiment may include circuitry to perform option (a) and/or option (b). In option (a), the circuitry may maintain a journal to record information that is related to a transaction that may result in writing to at least one logical address and at least one physical address of the storage. The information may be recorded in the journal via an atomic operation that may be executed prior to recording, at least in part, the information in a data structure that correlates the at least one logical address to the at least one physical address. In option (b), the circuitry may maintain another data structure that indicates a correlation between at least one other physical address and the at least one logical address. The correlation may be valid prior to completion of the transaction, but the correlation may no longer be valid after the completion.
|DATA SECURITY IN SOLID STATE MEMORY - The invention concerns data security in solid state memory. The solid state memory contains at least one specific area directed to storing sensitive information. The invention is for handling security relevant data in solid state memories and to protect the data from unauthorized access. According to the invention, the solid state memory includes a security element for deleting the specific memory area at start up.
|DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device may include: a data storage unit comprising a plurality of channels each having a plurality of nonvolatile memory devices; and a control unit configured to control a garbage collection operation of selecting a first block included in a first channel as a victim block and copying first data included in the first block into a second block included in a second channel that is selected.
|SECURE DATA STORAGE IN RAID MEMORY DEVICES - A redundant array of independent disk (RAID) memory storage system comprising data storage blocks arranged in a first plurality of data rows and a second plurality of data columns, wherein parity data is stored in additionally defined parity blocks, and wherein numbers of data blocks in respective columns are different, to accommodate the additional diagonal parity data block that the geometry of the system requires. The system is suitable for an SSD array in which sequential disk readout is not required.
|STORAGE SYSTEM LOGICAL BLOCK ADDRESS DE-ALLOCATION MANAGEMENT AND DATA HARDENING - A bridge receives a power down command and in response converts the power down command to a data hardening command. The bridge issues the data hardening command to a solid state disk. In response to the data hardening command, data stored on the solid state disk is hardened. The hardening comprises writing data in volatile memory to non-volatile memory. The data that is hardened comprises user data and protected data. The data hardening command optionally comprises one or more of a flush cache command, a sleep command, and a standby immediate command.
|HYBRID STORAGE DEVICE AND METHOD OF OPERATING THE SAME - The inventive concept herein relates to data storage devices, and more particularly, to a hybrid storage device including a plurality of storage media. The hybrid storage device may include first and second storage media storing a plurality of data blocks according to a data type and a hybrid controller configured to copy a data block having a change type to the first storage medium if a data type of the data block stored in the second storage medium is changed.
|METHOD OF MASSIVE PARALLEL PATTERN MATCHING AGAINST A PROGRESSIVELY-EXHAUSTIVE KNOWLEDGE BASE OF PATTERNS - A method of pattern and image recognition and identification includes building a data store of known patterns or images having known attributes and comparing those patterns to unknown patterns. The data store and comparison processing may be distributed across processors. A digital pattern recognition engine on each of the processors has the ability to compare a known pattern from the data store and an unknown pattern and compare the two patterns to determine whether the patterns constitute a match based on match criteria. If the comparison indicates a match, the match may be communicated to the data store and added as a known pattern with detected attributes to the data store. If the comparison does not indicate a match, the pattern may be flagged, transmitted to manual recognition, or further processed using character thresholding or cutting or slicing the pattern.
|FIRMWARE CLEANUP DEVICE - A firmware cleanup device includes a solid state disk (SSD) and an operation member. The SSD includes two pads and a connection portion, the connection portion defines two contacting pins respectively and electronically connected to the two pads. The operation member is detachably connected to the connection portion, the operation member includes two interconnected connection lines, and the two connection lines are respectively and electronically connected to the two contacting pins.
|APPARATUS, SYSTEM, AND METHOD FOR WEAR MANAGEMENT - A storage module is configured to determine a health metric of a storage division of a solid-state storage medium. The health metric may comprise a combination of factors, including, but not limited to: wear level, performance (e.g., program time, erase time, and the like), error rate, and the like. A wear level module may configure storage operations to reduce the wear rate of storage divisions having poor health metrics and/or heath metrics that are degrading more quickly than other storage divisions. Reducing wear rate may include deferring grooming operations, delaying use for storage operations, temporarily retiring the storage division, or the like. Storage divisions may be brought back into service at normal use rates in response determining that other portions of the storage media have been worn to the point that they exhibit similar health and/or reliability characteristics.
|SYSTEM AND METHOD FOR IMPLEMENTING TRANSACTIONS USING STORAGE DEVICE SUPPORT FOR ATOMIC UPDATES AND FLEXIBLE INTERFACE FOR MANAGING DATA LOGGING - Systems and methods provide an efficient method for executing transactions on a storage device (e.g., a disk or solid-state disk) by using special support in the storage device for making a set of updates atomic and durable. The storage device guarantees that these updates complete as a single indivisible operation and that if they succeed, they will survive permanently despite power loss, system failure, etc. The storage device performs transaction (e.g., read/write) operations directly at storage device controllers. As a result, transactions execute with lower latency and consume less communication bandwidth between the host and the storage device. Additionally, a unique interface is provided which allows the application to manage the logs used by the hardware.
|SYSTEM AND METHOD OF MANAGING MEMORY - The disclosure is related to systems and methods of management of memory. In a particular embodiment, a system is disclosed that comprises a control circuit adapted to compare a second data set to a first data set and to selectively replace the first data set with the second data set without performing an erase operation based on the comparison, wherein the erase operation is not performed when the first data set and the second data set differ only when locations of the second data set include a first logic value corresponding to one or more locations of the first data set that include a second logic value.
|CONTROL CIRCUIT OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A control circuit includes a ROM suitable for generating ROM data based on a ROM address corresponding to a predetermined operation, a command analyzing unit suitable for outputting the ROM address corresponding to the predetermined operation, generating an address storing signal in response to an operation suspension command for suspending the predetermined operation, and generating an address output signal in response to an operation resumption command for resuming the predetermined operation, an address storing unit suitable for storing a ROM address, which corresponds to the ROM address at a time point where the predetermined operation is suspended, in response to the address storing signal, and an address output unit suitable for outputting the ROM address corresponding to said time point in response to the address output signal, wherein the ROM generates ROM data for resuming the predetermined operation based on the ROM address corresponding to said time point.
|Mask-Programmed Read-Only Memory with Reserved Space - The present invention discloses a mask-ROM with reserved space (mask-ROM
|NONVOLATILE MEMORY APPARATUS AND WRITE CONTROL METHOD THEREOF - A nonvolatile memory apparatus includes a memory cell array, and a write operation controller configured to verify a write operation by comparing input data to the write operation controller with cell data written into the memory cell array, measure a resistance value after a first time is elapsed, and determine whether or not to re-perform the write operation according to the measured resistance value.
|INTEGRATED ARCHIVAL SYSTEM - Embodiments are disclosed for presenting a digital content item comprising a plurality of content portions. One example embodiment includes a computing device comprising a primary content storage machine, where the primary content storage machine is configured to selectively store one or more content portions of a digital content item. The computing device is configured to determine a dynamically changing content access window including one or more content portions useable to provide an above-threshold user experience based on a current access position of the digital content item. The computing device is configured to dynamically load the primary content storage machine with the content portions of the digital content item corresponding to the content access window and dynamically unload the content portions of the digital content item outside of the content access window from the primary content storage machine.
|SYSTEMS, METHODS, AND DEVICES FOR RUNNING MULTIPLE CACHE PROCESSES IN PARALLEL - Certain embodiments of the present disclosure related to systems, methods, and devices for increasing data access speeds.
|NONVOLATILE MEMORY SYSTEMS CONFIGURED TO USE DEDUPLICATION AND METHODS OF CONTROLLING THE SAME - At least one example embodiment discloses a method of determining a similarity in a nonvolatile memory. The method includes obtaining first data and second data units, the first data unit divided into a first plurality of non-overlapping chunks of data and the second data unit divided into a second plurality of non-overlapping chunks of data, determining a first plurality of values associated with the first plurality of chunks and a second plurality of values associated with the second plurality of chunks and determining a similarity between the first data unit and the second data unit based on whether any of the first plurality of values equals any of the second plurality of values.
|STORAGE DEVICE CONTROLLER - Provided is an apparatus including a first storage device having a first write speed and a second storage device having a second write speed. The apparatus also includes a controller configured to manage a transfer of data to the first storage device or the second storage device. The amount of data stored on each of the first and second storage devices is based on the first write speed and the second write speed.
|APPARATUS, SYSTEM, AND METHOD FOR ATOMIC STORAGE OPERATIONS - A virtual storage layer (VSL) for a non-volatile storage device presents a logical address space of a non-volatile storage device to storage clients. Storage metadata assigns logical identifiers in the logical address space to physical storage locations on the non-volatile storage device. Data is stored on the non-volatile storage device in a sequential log-based format. Data on the non-volatile storage device comprises an event log of the storage operations performed on the non-volatile storage device. The VSL presents an interface for requesting atomic storage operations. Previous versions of data overwritten by the atomic storage device are maintained until the atomic storage operation is successfully completed. Data pertaining to a failed atomic storage operation may be identified using a persistent metadata flag stored with the data on the non-volatile storage device. Data pertaining to failed or incomplete atomic storage requests may be invalidated and removed from the non-volatile storage device.
|Memory controllers to output data signals of a number of bits and to receive data signals of a different number of bits - A memory controller has a digital signal processor. The digital signal processor is configured to output a digital data signal of M+N bits of program data intended for programming a memory cell of a memory device. The digital signal processor is configured to receive a digital data signal of M+L bits read from the memory cell of the memory device and to retrieve from the received digital data signal M bits of data that were stored in the memory cell.
|MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device includes an interface unit and a memory unit. The interface unit receives a clock signal, a command signal and a data signal, internally adjusts input impedance based upon at least one of the command signal and the clock signal, and generates internal control signal of the memory device based upon the command signal and data signal. The memory unit performs read/write operations based upon the internal control signal.
|ON-THE-FLY PERFORMANCE ADJUSTMENT FOR SOLID STATE STORAGE DEVICES - Methods and apparatus related to on-the-fly performance adjustment techniques for solid state storage devices are described. In one embodiment, a controller logic controls access to one or more non-volatile memory devices. The controller logic causes a change in an operational frequency of one or more of: the controller logic, a bus that couples the one or more non-volatile memory devices to the controller logic, and one or more of the one or more non-volatile memory devices. Also, the controller logic is capable of causing the change in the operational frequency in response to a command. Furthermore, changing power limits is made possible to scale solid state storage device performance based on system capabilities. Other embodiments are also disclosed and claimed.
|Inexpensive Solid-State Storage Through Write Throttling - Many of the benefits of solid-state-based storage devices can be obtained, while minimizing the costs associated therewith, by write-throttling solid-state storage media in accordance with empirically derived capabilities. Untested solid-state storage media can be obtained inexpensively due to the lack of waste that is otherwise been inherent in the testing and subsequent discarding of solid-state storage media whose capabilities do not meet stringent manufacturer standards. The untested solid-state storage media is initialized through a testing procedure that empirically identifies capabilities of individual solid-state blocks, or groupings of blocks, within such solid-state storage media. Such empirically obtained capability information is then utilized to throttle the speed at which data is written to the solid-state storage media. Additionally, it can enable binning of individual solid-state blocks, or individual groupings of blocks, into bins that can comprise different performance thresholds.
|NVS THRESHOLDING FOR EFFICIENT DATA MANAGEMENT - For data management by a processor device in a computing storage environment, a threshold for an amount of Non Volatile Storage (NVS) space to be consumed by any particular logically contiguous storage space in the computing storage environment is established based on at least one of a Redundant Array of Independent Disks (RAID) type, a number of point-in-time copy source data segments in the logically contiguous storage space, and a storage classification.
|METHOD AND APPARATUS FOR COMPRESSING DATA SECTORS IN STORAGE DRIVE - A storage drive includes a non-volatile semiconductor memory, and interface, a compression module, a sector module, and a control module. The interface is configured to receive first data sectors transmitted from a host to the storage drive. The compression module is configured to compress the first data sectors to generate second data sectors. Lengths of the second data sectors vary. The first sector module is configured to generate third data sectors by adding nuisance data to (i) the second data sectors, or (ii) an encrypted version of the second data sectors, wherein lengths of the third data sectors do not vary. The control module is configured to store the third data sectors in the non-volatile semiconductor memory.
|CONTENT ADDRESSABLE MEMORY EARLY-PREDICT LATE-CORRECT SINGLE ENDED SENSING - Circuits and methods for performing search operations in a content addressable memory (CAM) array are provided. A system for searching a CAM includes a circuit that selectively activates a main-search of a two stage CAM search while a pre-search of the two stage CAM search is still active.
|DATA MANAGEMENT METHOD, MEMORY CONTROLLER AND EMBEDDED MEMORY STORAGE APPARATUS USING THE SAME - A data management method, a memory controller and an embedded memory storage apparatus are provided. The embedded memory storage apparatus has a plurality of physical blocks and each of the physical blocks has fast physical pages and slow physical pages. The method includes detecting a status of a state indication unit. The method further includes automatically reading data stored in the embedded memory storage apparatus, using the fast and slow physical pages of the embedded memory storage apparatus to re-store the data and marking status of the state indication unit as a second status when the status of the state indication unit is a first status. Accordingly, the storage space of the embedded memory storage apparatus can be efficiently used.
|ADAPTIVE RECORD CACHING FOR SOLID STATE DISKS - A storage controller receives a request that corresponds to an access of a track. A determination is made as to whether the track corresponds to data stored in a solid state disk. Record staging to a cache from the solid state disk is performed, in response to determining that the track corresponds to data stored in the solid state disk, wherein each track is comprised of a plurality of records.
|SEMICONDUCTOR STORAGE DEVICE - According to the embodiments, a first management table, which is included in a nonvolatile second semiconductor memory and manages data included in a second storage area by a first management unit, is stored in the second semiconductor memory and a second management table for managing data in the second storage area by a second management unit larger than the first management unit is stored in a first semiconductor memory capable of random access.
|Systems and Methods for User Configuration of Device Names - A system includes a device, a BIOS, and a processor. The BIOS includes a storage operable to store predefined identifier/user defined name pairs. The processor is operable to, detect the device, determine a predefined identifier for the device, and access the storage to locate a predefined identifier/user defined name pair corresponding to the predefined identifier. The processor is further operable to provide a user defined name of the predefined identifier/user defined name pair when the predefined identifier/user defined name pair is present, and provide the predefined identifier of the predefined identifier/user defined name pair when the predefined identifier/user defined name pair is not present.
|APPARATUS, SYSTEM, AND METHOD FOR ATOMIC STORAGE OPERATIONS - A virtual storage layer (VSL) for a non-volatile storage device presents a logical address space of a non-volatile storage device to storage clients. Storage metadata assigns logical identifiers in the logical address space to physical storage locations on the non-volatile storage device. Data is stored on the non-volatile storage device in a sequential log-based format. Data on the non-volatile storage device comprises an event log of the storage operations performed on the non-volatile storage device. The VSL presents an interface for requesting atomic storage operations. Previous versions of data overwritten by the atomic storage device are maintained until the atomic storage operation is successfully completed. Data pertaining to a failed atomic storage operation may be identified using a persistent metadata flag stored with the data on the non-volatile storage device. Data pertaining to failed or incomplete atomic storage requests may be invalidated and removed from the non-volatile storage device.
|ADAPTIVE RECORD CACHING FOR SOLID STATE DISKS - A storage controller receives a request that corresponds to an access of a track. A determination is made as to whether the track corresponds to data stored in a solid state disk. Record staging to a cache from the solid state disk is performed, in response to determining that the track corresponds to data stored in the solid state disk, wherein each track is comprised of a plurality of records.
|Memory system and method of accessing a semiconductor memory device - A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.
|Storage Device with Health Status Check Feature - A storage device with a health status check feature is disclosed. In one embodiment, the storage device keeps track of the number of erase cycles performed on the memory of the storage device. The storage device also stores a value of the predicted limit on the number of times that erase cycles can be performed on the memory. In response to a request from a host device for the health status of the memory, the storage device can provide the host device with information about how many erase cycles have been performed on the memory as compared to the predicted limit.
|Low Latency Memory Access Control for Non-Volatile Memories - A memory is provided that comprises a bank of non-volatile memory cells configured into a plurality of banklets. Each banklet in the plurality of banklets can be enabled separately and independently of the other banklets in the bank of non-volatile memory cells. The memory further comprises peripheral banklet circuitry, coupled to the bank of a non-volatile memory array, that is configured to enable selected subsets of bit lines within a selected banklet within the plurality of banklets. Moreover, the memory comprises banklet select circuitry, coupled to the peripheral banklet circuitry, that is configured to select data associated with a selected banklet for reading out from the banklet or writing to the banklet.
|Information processing system, resynchronization method and storage medium storing firmware program - An information processing system includes sets of multiple processors performing processing synchronously. The system includes: a ROM storing a firmware program activating the processors to a synchronized state; a RAM defined by one address map; a firmware copying section copying the firmware program in the ROM to the RAM, on system boot; and a RAM address register storing an address of the RAM and of a copy destination of the firmware program. The system further includes: a RAM address storing section storing the address of the RAM and of the copy destination of the firmware program; a loss-of-synchronism detection section detecting loss of synchronism of the processors; and an address replacing section referring to the RAM address register upon detection of the loss of synchronism, thereby replacing an address for reading the stored firmware program, with the address of the RAM and of the copy destination of the firmware program.
|SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM - A semiconductor memory device and a memory system are disclosed. The semiconductor memory device includes: a memory bank configured to include a first section and a second section, each of which is comprised of a plurality of memory cells; an LIO line switching circuit configured to generate first and second selection signals on the basis of page-size information; and an input/output (I/O) circuit configured to access the first section, the second section, or the first and second sections on the basis of the first and second selection signals, wherein the page-size information includes first and second information. If the page-size information is the first information, the LIO line switching circuit generates the first and second selection signals using a row address, and if the page-size information is the second information, the LIO line switching circuit generates the first and second selection signals using a column address.
|LEVERAGING A HYBRID INFRASTRUCTURE FOR DYNAMIC MEMORY ALLOCATION AND PERSISTENT FILE STORAGE - Dynamic allocation of memory in a hybrid system is provided. In particularly, a method and system is provided to leverage a hybrid infrastructure for dynamic memory allocation and persistent file storage. The method includes a method comprises dynamically allocating a file or its part or to cache a file or its part between different storage technologies and respective memory technologies in a hybrid infrastructure.
|VIRTUAL MEMORY SYSTEM, VIRTUAL MEMORY CONTROLLING METHOD, AND PROGRAM - Disclosed herein is a virtual memory system including a nonvolatile memory allowing random access, having an upper limit to a number of times of rewriting, and including a physical address space accessed via a virtual address; and a virtual memory control section configured to manage the physical address space of the nonvolatile memory in page units, map the physical address space and a virtual address space, and convert an accessed virtual address into a physical address; wherein the virtual memory control section is configured to expand a physical memory capacity allocated to a virtual page in which rewriting occurs.
|EVENT PROCESSING IN A FLASH MEMORY-BASED OBJECT STORE - Approaches for processing an event in an objects store, such as an MySQL database management system or a memcached caching system, that are maintained on one or more solid state devices. A plurality of threads may be instantiated. Each of the threads may be configured to retrieve items from a queue of items. Each item in the queue of items may be associated with a particular event occurring within the object store. Each event is a message that indicates an activity requiring work has occurred within the object store. When a particular thread retrieves an item from the queue of items, the particular thread processes the particular event associated with the item retrieved by the particular thread. In this way, event handling in object stores such as MySQL and memcached may be performed more efficiently on a solid state device.
|NONVOLATILE MEMORY SYSTEM AND METHOD OF PERFORMING OPERATION OF THE NONVOLATILE MEMORY SYSTEM - According to example embodiments, a nonvolatile memory system includes a nonvolatile memory device includes a nonvolatile memory cell array, a temperature sensor configured to measure a temperature of the nonvolatile memory device, and a memory controller configured to adjust an execution frequency of a memory management operation based on a desired (and/or alternatively predetermined) temperature range and the measured temperature.
|METHOD AND SYSTEM FOR VM-GRANULAR I/O CACHING - Methods are presented for caching I/O data in a solid state drive (SSD) locally attached to a host computer supporting the running of a virtual machine (VM). Portions of the SSD are allocated as cache storage for VMs running on the host computer. A mapping relationship is maintained between unique identifiers for VMs running on the host computer and one or more process identifiers (PIDs) associated with processes running in the host computer that correspond to each of the VM's execution on the host computer. When an I/O request is received, a PID associated with I/O request is determined and a unique identifier for the VM is extracted from the mapping relationship based on the determined PID. A portion of the SSD corresponding to the unique identifier of the VM that is used as a cache for the VM can then be accessed in order to handle the I/O request.
|SYSTEM AND METHOD FOR RECORDING NUMBER OF POWER ON TIMES OF MOTHERBOARD - A powering on times recording system records powering on times of a motherboard, and includes a Basic Input/Output System (BIOS) Read Only Memory (ROM) chip installed on the motherboard. The BIOS ROM chip includes a first storage area storing a recording module and a second storage area storing a first variable data. When the motherboard is powered on, the recording module acquires the first variable data from the second storage area and increments the first variable data by one. The changed first variable data is recorded in the second storage area.
|INFORMATION STORAGE SYSTEM, SNAPSHOT ACQUISITION METHOD, AND DATA STORAGE MEDIUM - The information storage system of an aspect of the present invention includes a first differential data storage area which stores differential data of a higher volume from a first point of time to a second point of time, a lower snapshot manager which provides a lower snapshot at the second point of time of the higher volume, and a second differential data storage area which stores differential data of the higher volume after the second point of time. The higher snapshot manager acquires a plurality of generations of higher snapshots from the lower snapshot and the data in the first differential data storage area and acquires a plurality of generations of higher snapshots from the data of the higher volume and the data in the second differential data storage area.
|USB CONTROLLER AND EXECUTION METHOD THEREOF - A universal serial bus (USB) controller and an execution method thereof are presented. The USB controller stores settings of different sensors in an external memory, or stores modified program codes when an originally stored program has bugs. With the execution of the set configurations, the program section to be execute is dynamically loaded into the random access memory (RAM) of the USB controller, so as to reduce the size of the RAM, thereby providing a large program modification space and avoiding the entire chip (the USB controller) from being stretched by an excessive large RAM.
|MEMORY ERASING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A memory erasing method and a memory controller and a memory storage apparatus using the same are provided. The memory erasing method includes following steps. Physical blocks of a rewritable non-volatile memory module of the memory storage apparatus are logically grouped into at least a data area and a spare area. After the memory storage apparatus is powered on, an erase mark is configured for each of the physical blocks in the spare area, and each of the erase marks is initially set to an unerased state. After the memory storage apparatus enters a standby state, whether an erase command is executed on the physical blocks in the spare area is determined according to the erase marks. Thereby, the memory erasing method can effectively shorten the time for the memory storage apparatus to enter the standby state after the memory storage apparatus is powered on.
|COMPUTING DEVICE AND OPERATING METHOD OF COMPUTING DEVICE - Exemplary embodiments may provide a computing device which includes a first random access memory; a second random access memory; a memory controller which is configured to control the first random access memory and second random access memory; and a processor which is configured to use the first random access memory and second random access memory, as a working memory, through the memory controller, wherein the memory controller is configured to access one memory, selected by a transferred command from the processor, from among the first random access memory and second random access memory.
|MEMORY CONTROL DEVICE, NON-VOLATILE MEMORY, AND MEMORY CONTROL METHOD - Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not the read data matches the write data for each of a plurality of memory cells, a retry inhibiting unit that inhibits a retry process from being performed in a memory cell in which the read data matches the write data among the plurality of memory cells, and a retry control unit that designates at least some memory blocks among the plurality of memory blocks and simultaneously executes the retry process when the read data does not match the write data in any one of the plurality of memory cells in which all the write data is written.
|RECORDING DEVICE, ACCESS DEVICE, RECORDING SYSTEM, AND RECORDING METHOD - A recording device operates in accordance with an instruction from an access device. The recording device comprising a nonvolatile memory that stores data, a communication unit that receives an instruction issued by the access device, and a memory controller that controls the nonvolatile memory. When a recording instruction for recording data into the nonvolatile memory is received from the access device, the memory controller starts recording of data into the nonvolatile memory. When the memory controller receives from the access device a suspension instruction for suspending the recording of data, the memory controller stores suspension information into the nonvolatile memory, the suspension information indicating a suspended position as a position in a recording area of the nonvolatile memory at which the data is being recorded upon reception of the suspension instruction.
|SYSTEMS AND METHODS FOR REVISING PERMANENT ROM-BASED PROGRAMMING - An application program stored in a ROM includes a function lookup data structure in which functions called by the application program have identifiers and memory addresses at which the function is located and can be executed. Upon startup, the function lookup data structure is copied to a RAM as a revised lookup data structure and is compared to a revision lookup data structure also written to that RAM or elsewhere. If the revision lookup data structure contains replacement functions having the same function identifiers but new memory addresses, these new memory addresses are written over the existing addresses in the revised lookup data structure for those replacement functions. The application program refers to the revised lookup data structure to find and execute the functions; thus the original application program on the ROM can continue to be used with revised functions.
|ELECTRONIC DEVICE AND METHOD OF MANAGING MEMORY OF ELECTRONIC DEVICE - A method of managing a memory by an electronic device is provided. The method includes configuring a swap data amount per unit time, identifying an actual use amount of swap data, and comparing the identified actual use amount of the swap data with the configured swap data amount per unit time.
|METHOD OF CONTROLLING MEMORY, MEMORY CONTROL CIRCUIT, STORAGE DEVICE AND ELECTRONIC DEVICE - A method of controlling a memory including a first storage area and a second storage area. The method includes determining, in response to a request for writing a write data string, whether the write data string changes a logical value stored in the memory from a first logical value to a second logical value, writing, to the first storage area, a logical value that is located in a position of the write data string and does not change an existing logical value of the memory from the first logical value to the second logical value, and writing the second logical value that is located in a position of the write data string and changes an existing logical value of the memory from the first logical value to the second logical value to the second storage area which is different from the first storage area.
|System and Method for Providing Personality Switching in a Solid State Drive Device - A solid state drive (SSD) device includes a Peripheral Component Interconnect-Express (PCIe) interface, a non-volatile storage media, and a memory that stores code, the code including an Advanced Host Controller Interface (AHCI) controller, and a Non-Volatile Memory-Express (NVMe) controller. The SSD device is operable to select one of the AHCI controller and the NVMe controller to process data storage commands between the PCIe interface and the non-volatile storage media.
|Memory Reclamation Method and Apparatus - A memory reclamation method and apparatus are disclosed. The memory reclamation method is performed by a processor for reclaiming memory pages of a non-volatile memory (NVM) in a terminal device. In the method, the processor receives a memory reclamation request message including a reclamation identifier which is used to indicate a quantity of memory pages requested to be reclaimed. Then, the processor reclaims inactive memory pages of the NVM according to the reclamation identifier in ascending order of the write times of inactive memory pages of the NVM. According to the memory reclamation method, a page having a relatively small quantity of inactive memory page write times of the NVM is reclaimed first, and a page having a relatively large quantity of inactive memory page write times of the NVM is reclaimed later.
|ELECTRONIC APPARATUS AND CONTROL METHOD THEREOF - An electronic includes a read-only memory (ROM), a random access memory (RAM), a processing module, a demand paging module and a decompression module. The ROM stores multiple sets of compressed data corresponding to a plurality of sets of uncompressed data. The plurality of sets of uncompressed data are divided from one same set of original data. According to a request associated with the set of original data and from the processing module, the demand paging module selects one or more sets from the multiple sets of compressed data. The decompression module decompresses and stores the selected one or more sets of compressed data to the RAM for use of the processing module.
|ELECTRONIC DEVICE - An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction intersecting the first direction, and a plurality of variable resistance patterns that is positioned at intersections of the first lines and the second lines and disposed between the first lines and the second lines in a vertical direction. Each of the variable resistance patterns has an elongated shape in a plan view and a portion of each of the variable resistance patterns is disposed outside a region in which a corresponding first line and a corresponding second line overlap with each other.
|APPARATUS, SYSTEM, AND METHOD FOR MANAGING DATA IN A STORAGE DEVICE WITH AN EMPTY DATA TOKEN DIRECTIVE - An apparatus, system, and method are disclosed for managing data with an empty data segment directive at the storage device. The apparatus, system, and method for managing data include a write request receiver module and a data segment token storage module. The write request receiver module receives a storage request from a requesting device. The storage request includes a request to store a data segment in a storage device. The data segment includes a series of repeated, identical characters or a series of repeated, identical character strings. The data segment token storage module stores a data segment token in the storage device. The data segment token includes at least a data segment identifier and a data segment length. The data segment token is substantially free of data from the data segment.
|DRIFT MANAGEMENT IN A PHASE CHANGE MEMORY AND SWITCH (PCMS) MEMORY DEVICE - The present disclosure relates to the drift management for a memory device. In at least one embodiment, the memory device of the present disclosure may include a phase change memory and switch (hereinafter "PCMS") memory cell and a memory controller that is capable of implementing drift management to control drift. Other embodiments are described and claimed.
|System and Method to Create a Non-Volatile Bootable RAM Disk - A manufacturing testing system includes an information handling system, a RAM memory device including a reserved physical RAM address space, non-volatile bootable disk, and a header for the reserved physical RAM address space. The head may include a non-volatile bootable disk signature, a start physical address, a length of reserved space, and a processor.
|NON-VOLATILE MEMORY INTERFACE - Apparatuses, systems, methods, and computer program products are disclosed for a memory controller. An apparatus includes a volatile memory medium located on a memory module. An apparatus includes a non-volatile memory medium located on a memory module. A memory controller is located on a memory module. A memory controller may be configured to provide access to at least a non-volatile memory medium over a direct wire interface with a processor.
|System And Method For Storing Manufacturing Information And Lifetime Usage History Of A Power Module For A Memory System - A memory system is described. The memory system includes a plurality of memory subsystems. Further, the memory system includes a controller coupled with the plurality of memory subsystems. The memory system also includes a power module including a storage device configured to store information and the power module is detachably coupled with the controller.
|EXTERNAL MEMORY DEVICE - An external memory device configured to communicate with an external electronic device includes: a semiconductor substrate including a first edge and a second edge perpendicular to the first edge; a semiconductor integrated circuit device provided on the semiconductor substrate, the semiconductor integrated circuit device including a memory device configured to store data provided from the external electronic device, an input/output interface configured to interface with the external electronic device, and a controller configured to control the memory device in response to a signal transmitted through the input/output interface; an insulating layer covering the semiconductor integrated circuit device; and external input/output pins provided adjacent to the first edge on the insulating layer and configured to establish an electrical connection between the external electronic device and the semiconductor integrated circuit device.
|NON-VOLATILE HYBRID MEMORY - Memory units and computer systems are provided. The computer systems include a memory unit. The memory unit includes a stable storage unit, an unstable storage unit, and a controller. The unstable storage unit stores pending write operations for the stable storage unit. The controller is configured to determine the locations in the unstable storage that store the pending write information and to selectively write the pending write operations to the stable storage unit when power to the memory unit is interrupted.
|Configuration Bit Sequencing Control of Nonvolatile Domain and Array Wakeup and Backup - A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to store
|Nonvolatile Logic Array With Retention Flip Flops To Reduce Switching Power During Wakeup - A processing device is operated using a plurality of volatile storage elements. Data in the plurality of volatile storage elements is stored in a plurality of non-volatile logic element arrays. A primary logic circuit portion of individual ones of the plurality of volatile storage elements is powered by a first power domain, and a slave stage circuit portion of individual ones of the plurality of volatile storage elements is powered by a second power domain. During a write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements, the first power domain is powered down and the second power domain is maintained. In a further approach, the plurality of non-volatile logic element arrays is powered by a third power domain, which is powered down during regular operation of the processing device.
|APPARATUS, SYSTEM AND METHOD FOR ADAPTIVE CACHE REPLACEMENT IN A NON-VOLATILE MAIN MEMORY SYSTEM - Techniques and mechanisms for adaptively changing between replacement policies for selecting lines of a cache for eviction. In an embodiment, evaluation logic determines a value of a performance metric which is for writes to a non-volatile memory. Based on the determined value of the performance metric, a parameter value of a replacement policy is determined. In another embodiment, cache replacement logic performs a selection of a line of cache for data eviction, where the selection is in response to the policy unit providing an indication of the determined parameter value.
|DYNAMIC REDUNDANCY MAPPING OF CACHE DATA IN FLASH-BASED CACHING SYSTEMS - A method for managing redundancy of data in a solid-state cache system including at least three solid-state storage modules. The method may include designating one or more extents of each dirty mirror pair to be of a particular priority order of at least two priority orders. The at least two priority orders can include at least a highest priority order. The highest priority order can have a higher relative priority than the other priority orders. The method may also include performing at least one redundancy conversion iteration. Each redundancy conversion iteration includes converting extents of at least two dirty mirror pairs into at least one RAID 5 group and at least one unconverted extent. The extents of the at least two dirty mirror pairs can include extents designated to be of a highest remaining priority order. Each redundancy conversion iteration can also include deallocating the at least one unconverted extent.
|METHOD AND DESIGN FOR HIGH PERFORMANCE NON-VOLATILE MEMORY - A non-volatile memory (NVM) system compatible with double data rate, single data rate, or other high speed serial burst operation. The NVM system includes input and output circuits adapted to synchronously send or receive back-to-back continuous bursts of serial data at twice the frequency of any clock input. Each burst is J bits in length. The NVM system includes read and write circuits that are adapted to read or write J bits of data at a time and in parallel, for each of a multitude of parallel data paths. Data is latched such that write time is similar for each bit and is extended to the time it takes to transmit an entire burst. Consequently, the need for small and fast sensing circuits on every column of a memory array, and fast write time at twice the frequency of the fastest clock input, are relieved.
|APPARATUS, SYSTEM, AND METHOD FOR BIASING DATA IN A SOLID-STATE STORAGE DEVICE - An apparatus, system, and method are disclosed for improving performance in a non-volatile solid-state storage device. Non-volatile solid-state storage media includes a plurality of storage cells. The plurality of storage cells is configured such that storage cells in an empty state store initial binary values that satisfy a bias. An input module receives source data for storage in the plurality of storage cells of the non-volatile solid-state storage media. Bits of the source data have a source bias that is different from the bias of the plurality of storage cells. A bit biasing module biases the bits of the source data toward the bias of the plurality of storage cells. A write module writes the biased source data to the plurality of storage cells of the non-volatile solid-state storage media.
|Method and Controller for Identifying a Unit in a Solid State Memory Device for Writing Data To - In a method for identifying a unit in a solid state memory device for writing data to a tier structure is maintained the tier structure comprising at least two tiers for assigning units available for writing data to. In response to receiving a request for writing data it is determined if a unit for writing data to is available in a first tier of the at least two tiers. In response to determining that a unit is available for writing data to in the first tier this unit is identified for writing data to, and in response to determining that no unit is available for writing the data to in the first tier it is determined if a unit is available for writing data to in a second tier of the at least two tiers subject to a priority of the write request.
|PROGRAM, CONTROL METHOD, AND CONTROL DEVICE - Provided are a program, a control method, and a control device by which an activation time can be shortened. In a computer system which is equipped with a Memory Management Unit (MMU), with respect to a table of the MMU, page table entries are rewritten so that page faults occur at each page necessary for operation of software. At the time of activating, stored memory images are read page by page for the page faults which occurred in the RAM to be accessed. By reading as described above, reading of unnecessary pages is not performed, and thus, the activation time can be shortened. The present invention can be applied to a personal computer and an electronic device provided with an embedded computer.
|METHOD TO ENHANCE PROGRAMMING PERFORMANCE IN MULTILEVEL NVM DEVICES - An apparatus includes an interface and a processor. The interface is configured to communicate with a memory device. The processor is configured to send to the memory device, via the interface, a sequence of write commands that program multiple types of memory pages that incur respective different programming durations in the memory device, while inserting in the sequence suspension periods for permitting execution of storage commands that are not part of the sequence, such that at least some of the suspension periods are followed by write commands of types that do not have a shortest programming duration among the programming durations.
|NON-VOLATILE HARD DISK DRIVE CACHE SYSTEM AND METHOD - A non-volatile hard disk drive cache system is coupled between a processor and a hard disk drive. The cache system includes a control circuit, a non-volatile memory and a volatile memory. The control circuit causes a subset of the data stored in the hard disk drive to be written to the non-volatile memory. In response to a request to read data from the hard disk drive, the control circuit first determines if the requested read data are stored in the non-volatile memory. If so, the requested read data are provided from the non-volatile memory. Otherwise, the requested read data are provided from the hard disk drive. The volatile memory is used as a write buffer and to store disk access statistics, such as the disk drive locations that are most frequently read, which are used by the control circuit to determine which data to store in the non-volatile memory.
|ELECTRONIC DEVICE FOR STORING DATA ON PRAM AND MEMORY CONTROL METHOD THEREOF - The present disclosure relates to an electronic device for storing data on PRAM and a memory control method thereof The electronic device of the present disclosure comprises: a nonvolatile memory in which data is stored; a volatile memory in which an address conversion table of a nonvolatile memory is stored; and a controller that stores data on a nonvolatile memory by referencing an address conversion table of a nonvolatile memory stored on a volatile memory. Due to this, a nonvolatile memory having limitative number of write and read such as PRAM can be operated more effectively.
|System and Method for Sharing a Solid-State Non-Volatile Memory Resource - A computing device and methods for exposing a solid-state non-volatile memory element to multiple masters in a computing device are disclosed. A portion of a solid-state non-volatile memory element includes code and data for use by a non-boot processing resource. A host controller in communication with the solid-state non-volatile memory element is modified to receive and respond to a resource identifier unique to the processing resource that is requesting read access to the solid-state non-volatile memory element. Logic executed by a boot master and logic executed by a non-boot processing resource are synchronized in response to a set of indicators.
|USING EXTERNAL MEMORY DEVICES TO IMPROVE SYSTEM PERFORMANCE - The invention is directed towards a system and method that utilizes external memory devices to cache sectors from a rotating storage device (e.g., a hard drive) to improve system performance. When an external memory device (EMD) is plugged into the computing device or onto a network in which the computing device is connected, the system recognizes the EMD and populates the EMD with disk sectors. The system routes I/O read requests directed to the disk sector to the EMD cache instead of the actual disk sector. The use of EMDs increases performance and productivity on the computing device systems for a fraction of the cost of adding memory to the computing device.
|STORAGE SUBSYSTEM AND ITS DATA PROCESSING METHOD - The amount of data to be stored in a semiconductor nonvolatile memory can be reduced and overhead associated with data processing can be reduced. When a microprocessor
|Method and Apparatus for Detecting the Presence of Subblocks in a Reduced-Redundancy Storage System - Method and apparatus for rapidly determining whether a particular subblock of data is present in a reduced-redundancy storage system. An aspect of the invention achieves this by hashing each subblock in the storage system into a bitfilter that contains a '1' bit for each position to which at least one subblock hashes. This bitfilter provides an extremely fast way to determine whether a subblock is in the storage system. In a further aspect of the invention, index entries for new subblocks may be buffered in a subblock index write buffer so as to convert a large number of random access read and write operations into a single sequential read and a single sequential write operation. The combination of the bitfilter and the write buffer yields a reduced-redundancy storage system that uses significantly less high speed random access memory than is used by systems that store the entire subblock index in memory.
|Wear Leveling For Erasable Memories - In accordance with some embodiments, wear leveling may be done based on the difference in age of discarded blocks and engaged blocks. Data is moved to an older discarded block from a younger engaged block. Two wear leveling bits may be used for each logical block, such that the wear leveling bits are used in alternating cycles.
|ACCESS DEVICE AND MEMORY CONTROLLER - Refresh to be performed together with normal processing may fail to be performed for a sufficiently long period of time due to the specification requirements. In this case, data loss can occur in an area that has not been refreshed for a sufficiently long period of time. An access module (
|METHOD AND APPARATUS FOR INCREASING FILE COPY PERFORMANCE ON SOLID STATE MASS STORAGE DEVICES - A mass storage device and method that utilize storage memory and a shadow memory capable of increasing the speed associated with copying data from one location to another location within the storage memory without the need to access a host computer for the copy transaction. A controller of the mass storage device receives a file copy request for a file to be copied between first and second locations within the storage memory. Data from the first location within the storage memory is then loaded into a shadow memory means of the mass storage device, and then the data is written from the shadow memory means to the second location within the storage memory.
|Characterizing Multiple Resource Utilization Using a Relationship Model to Optimize Memory Utilization in a Virtual Machine Environment - An approach is provided that uses a hypervisor to allocate a shared memory pool amongst a set of partitions (e.g., guest operating systems) being managed by the hypervisor. The hypervisor retrieves memory related metrics from shared data structures stored in a memory, with each of the shared data structures corresponding to a different one of the partitions. The memory related metrics correspond to a usage of the shared memory pool allocated to the corresponding partition. The hypervisor identifies a memory stress associated with each of the partitions with this identification based in part on the memory related metrics retrieved from the shared data structures. The hypervisor then reallocates the shared memory pool amongst the plurality of partitions based on the identified memory stress of the plurality of partitions.
|DEVICE AND METHOD FOR RELIABLE DATA STORAGE - A data storage device comprising at least one non-volatile storage medium having a plurality of data blocks, and a controller configured to allocate at least one of the data blocks for a writing operation based at least in part on data integrities of the data blocks.
|Selectively utilizing a plurality of disparate solid state storage locations - A method for selectively utilizing a plurality of disparate solid state storage locations is disclosed. The technology initially receives class types for a plurality of disparate solid state storage locations. The characteristics of the received data are determined. The received data is then allocated to one of the plurality of disparate solid state storage locations based upon the determined characteristics of the received data.
|Hybrid nonvolatile RAM - A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.
|Method and apparatus for writing data to and reading data from phase-change random access memory - A method and apparatus for writing data to and reading data from a phase-change random access memory (PRAM) include encoding original data using a predetermined encoding function, selecting data, from among the original data and the encoded data, which require less power when being written to the PRAM, writing the selected data to the PRAM, generating marking information related to the selected data, and writing the marking information to the PRAM. Therefore, power consumption can be reduced when data are written to the PRAM.
|EMULATION OF READ-ONCE MEMORIES IN VIRTUALIZED SYSTEMS - The subject matter herein relates to computer systems and, more particularly, to emulation of read-once memories in virtualized systems. Various embodiments described herein provide systems, methods, and software that leverage the value of read-once memory for purposes such as keeping data or instructions secret and protected from unauthorized viewers, applications, hackers, and other processes. Some such embodiments include a virtual machine manager that emulates hardware memories in a system memory to facilitate virtual access to the hardware memories.
|SECURITY STORAGE OF ELECTRONIC KEYS WITHIIN VOLATILE MEMORIES - It is described a method for providing an electronic key within an integrated circuit (
|Method and device for reorganizing data in a memory system, in particular for control devices in motor vehicles - A method for reorganizing performance quantity data in a segment of a non-volatile memory. The method encompasses the tasks or operations of generating a cohesive data block at an address space of a working memory, of performance quantity data from a first segment of the non-volatile memory and/or from the working memory, and of copying the data block to a predefined address space of the first or a second segment of the non-volatile memory in a block write operation, the performance quantity data of the data block in essence being written to the predefined address space simultaneously in the block write process.
|Memory Module, Memory Controller, Nonvolatile Storage, Nonvolatile Storage System, and Memory Read/Write Method - In a storage having a nonvolatile RAM of destructive read type, the number of restorations attributed to data read from the nonvolatile RAM is decreased, and the overall life of the storage is prolonged. In a storage having a nonvolatile RAM of destructive read type and a volatile RAM and holding the same data in the nonvolatile and volatile RAMs, data is read out of the volatile RAM in reading and data is written in both volatile and nonvolatile RAMs in writing.
|DATA STORAGE DEVICE, MEMORY SYSTEM, AND COMPUTING SYSTEM USING NONVOLATILE MEMORY DEVICE - Provided is a data storage device including two or more data storage areas including may have two or more (heterogeneous) types of nonvolatile memory cells. At least one of the data storage areas includes a plurality of memory blocks that are sequentially selected, and metadata are stored in the currently selected memory block. The memory blocks can be sequentially used and metadata can be stored in a uniformly-distributed manner throughout the data storage device. Therefore, separate merging and wear-leveling operations are unnecessary. Thus, it is possible to improve the lifetime and writing performance of a data storage device having two or more heterogeneous nonvolatile memories.
|MEMORY APPARATUS, MEMORY CONTROL METHOD, AND PROGRAM - Disclosed herein is a memory apparatus comprising: a nonvolatile memory configured to allow data to be written thereto and read therefrom in units of a cluster and to permit data to be deleted therefrom in units of a block made up of a plurality of sectors; a control circuit configured to control access operations to said nonvolatile memory; a management area; a user data area; and a cache area; said management area includes a logical/physical table, and the addresses of physical blocks in said cache area.
|Semiconductor Memory Device and Its Control Method - A card information storage part (
|DIRECT INTERCONNECTION BETWEEN PROCESSOR AND MEMORY COMPONENT - Conventional processor and memory configurations place holes into silicon or use expensive multi-layer-laminates/substrates to connect the processor with memory. Using a direct contact between the memory and processor allows for signaling between the two units. By judicious arrangement of the contact areas as well as employing other structures such as carriers and redistributors, adequate power and ground supply can be maintained for the processor. Therefore, there is little-to-no damage done to the silicon and expensive multi-layer-laminates/substrates can be avoided. Furthermore, there can be faster processing speeds since the memory and processor are close together.
|NON-VOLATILE MEMORY STORAGE SYSTEM AND METHOD FOR READING AN EXPANSION READ ONLY MEMORY IMAGE THEREOF - A non-volatile memory storage system including a connecting interface, a non-volatile memory, a buffer memory, a microcontroller, and a virtual host module is provided. The connecting interface is used for connecting to a host. The non-volatile memory is used for storing user data, wherein the non-volatile memory further stores an expansion read only memory (ROM) image to be read by the host. The buffer memory is used for temporarily storing the expansion ROM image. The microcontroller controls the operation between the connecting interface, the buffer memory, and the non-volatile memory. The virtual host module provides an activation code in the expansion ROM image to the host through the microcontroller. Thereby, both the size and the fabrication cost of the non-volatile memory storage system can be effectively reduced.
|Multimedia Platform - A device comprising a multimedia platform with a plurality of memories and a method of sharing a non-volatile memory. The multimedia platform in accordance with an embodiment of the present invention can have a non-volatile memory, a multimedia processor setting a route in accordance with a route selection signal received from the main processor such that the main processor accesses the non-volatile memory or the display unit, a first volatile memory which is a temporary memory device of the main processor, and a second volatile memory which is a temporary memory of the multimedia processor. With the present invention, the portable terminal can be made smaller by putting a memory chip and a multimedia platform in a single chip by use of the POP (package on package) technology.
|Partially storing software functions that are not expected to change over time in ROM instead of RAM - A technique to identify portions of software that does not change over time, in order to store that portion in ROM, instead of RAM, to reduce RAM size. The smaller RAM conserves space on a chip and consumes less power. The technique allows wireless devices, such as cell phones, to use less RAM.
|SEMICONDUCTOR DEVICE CONNECTABLE TO MEMORY CARD AND MEMORY CARD INITIALIZATION METHOD - A semiconductor device includes first and second interfaces, and a control unit. The first interface is capable of being connected to a memory card and communicating with the memory card. The memory card has a nonvolatile semiconductor memory and has an unlock state and a lock state. The memory card in the unlock state permits an access to the nonvolatile semiconductor memory. The memory card in the lock state prohibits the access. The second interface is capable of being connected to a host device and communicating with the host device. The host device generates an access command to access the memory card. The control unit operates based on the access command sent from the host device through the second interface so as to release the lock state of the memory card, when the memory card is connected to the first interface.
|ARCHITECTURE FOR VERY LARGE CAPACITY SOLID STATE MEMORY SYSTEMS - To provide a feasible means to connect many non-volatile memory modules into a very large capacity solid-state memory, a group modules may be connected in a serial manner to form a unidirectional loop with the memory controller. In some embodiments the same serial connection may be used to communicate commands, write data, and/or configuration data from the memory controller to each memory module, and to communicate read data and/or configuration status from each memory module to the memory controller. Some memory controllers may have capacity to handle multiple such loops.
|NONVOLATILE MEMORY APPARATUS - The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.
|LONG-TERM DIGITAL DATA STORAGE - Embodiments are directed to recording digital data on an optically ablatable digital storage media. In one embodiment, a device configured to ablate portions of ablatable material on an optically ablatable digital storage media receives digital data that is to be recorded on a recording layer of an optically ablatable digital storage media. The recording layer is formed on a substrate with zero or more intervening layers between the recording layer and the substrate. The recording layer includes ablatable material capable of storing digital data. The device ablates the ablatable material in the recording layer according to a sequence defined by the received digital data such that the ablated portions correspond to data points of the received digital data.
|Solid memory module structure with extensible capacity - A solid memory module structure with extensible capacity includes at least a non-volatile memory module, each of which has at least a memory chip, a first connector, and a control unit. And A Solid memory module includes at least a second connector, which electrically connects the first connector of the volatile memory module, and a system interfac
Patent applications in class Solid-state read only memory (ROM)
Patent applications in all subclasses Solid-state read only memory (ROM)